Single Event Upsets (SEUs) – Soft Errors
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Transcript of Single Event Upsets (SEUs) – Soft Errors
Single Event Upsets Single Event Upsets (SEUs) – Soft Errors(SEUs) – Soft Errors
By:By:Rajesh GargRajesh Garg
Sunil P. KhatriSunil P. KhatriDepartment of Electrical and Computer Engineering,Department of Electrical and Computer Engineering,
Texas A&M University, College Station, TXTexas A&M University, College Station, TX
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BackgroundBackground
pnpn junction behavior junction behavior Electric fieldElectric field Depletion regionDepletion region
Energy band diagram of SiEnergy band diagram of Si Energy transferred to Si may Energy transferred to Si may excite an excite an
electronelectron from valence band to conduction from valence band to conduction bandband
e-h pairs can be generatede-h pairs can be generated2
n+
S
n+
p-substrate
G
D
VDD
Depletion Region
Radiation Particle
_ ++_
_ +_
+_
+ _+_+
E_+VDD - Vjn
E
Charge Deposition by a Radiation Charge Deposition by a Radiation Particle – Drift and DiffusionParticle – Drift and Diffusion
Radiation particles - protons, neutrons, alpha particles and heavy Radiation particles - protons, neutrons, alpha particles and heavy ionsions
Reverse biased Reverse biased p-np-n junctions are most sensitive to particle strikes junctions are most sensitive to particle strikes Charge is collected at the Charge is collected at the
drain nodedrain node throughthrough drift drift and diffusionand diffusion
Results in a voltage glitch Results in a voltage glitch at the drain node at the drain node
System state may change System state may change if this voltage glitch is if this voltage glitch is capturedcaptured by at least one by at least one memory elementmemory element This is called This is called SEUSEU May causeMay cause system failure system failure
B 3
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Charge Deposited by a Radiation Particle
Linear Energy Transfer (LET) is a common measure of the energy transferred by a radiation particle when it strikes a material
Relationship between Q, LET and t
Charge of 1 electron
Therefore the charge deposited by a unit LET (for a track length of 1µm)
So the charge deposited by a radiation strike (in terms of LET and track length) is
Other Charge Collection Other Charge Collection MechanismsMechanisms
Bipolar EffectBipolar Effect Parasitic bipolar transistor exists in MOSFETsParasitic bipolar transistor exists in MOSFETs
For example, n-p-n (S–B–D) in an NMOS transistorFor example, n-p-n (S–B–D) in an NMOS transistor Holes accumulation in an NMOS transistor may Holes accumulation in an NMOS transistor may
turn on this bipolar transistorturn on this bipolar transistor Alpha-particle Source-drain Penetration Alpha-particle Source-drain Penetration
(ALPEN)(ALPEN) A radiation particle penetrates through both A radiation particle penetrates through both
source and drain diffusionssource and drain diffusions
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Modeling a Radiation Particle Modeling a Radiation Particle StrikeStrike
A radiation particle strike is modeled by a current A radiation particle strike is modeled by a current pulse aspulse as
wherewhere: : is the collection time constantis the collection time constant
is the ion track establishment constantis the ion track establishment constant
The radiation induced The radiation induced current always flows current always flows from from nn-diffusion to -diffusion to pp-diffusion-diffusion
For an accurate analysis, For an accurate analysis, device level simulationdevice level simulationshould be performedshould be performed
)()( //
tt
seu eeQ
ti
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Single Event UpsetsSingle Event Upsets Single Event Upsets Single Event Upsets (SEUs) or Soft Errors(SEUs) or Soft Errors
Troublesome for both Troublesome for both memoriesmemories and and combinational logiccombinational logic Becoming increasingly problematic even for terrestrial Becoming increasingly problematic even for terrestrial
designsdesigns A particle strike at the output A particle strike at the output
of a combinational gateof a combinational gateresults in a results in a Single Event Single Event Transient (SET)Transient (SET) If a memory latches wrongIf a memory latches wrong
value -> SEUvalue -> SEU A particle strike in a memory A particle strike in a memory
element may directly lead to an SEU eventelement may directly lead to an SEU event
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Radiation Hardening Radiation Hardening ApproachesApproaches
Can be classified into three categoriesCan be classified into three categories Device levelDevice level Circuit levelCircuit level System levelSystem level
Device level – Fault avoidanceDevice level – Fault avoidance SOI devices are inherently SOI devices are inherently less susceptibleless susceptible to radiation to radiation
strikesstrikes Low collection volumesLow collection volumes
Still needs other hardening techniques to achieve SEU Still needs other hardening techniques to achieve SEU tolerancetolerance
Bipolar effect significantly increases the amount of charge Bipolar effect significantly increases the amount of charge collected at the drain nodecollected at the drain node
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System Level Radiation System Level Radiation Hardening ApproachesHardening Approaches
Fault detection and fault correction approachesFault detection and fault correction approaches
SEU events are detected using built in current SEU events are detected using built in current sensors (BICS) (Gill et al.)sensors (BICS) (Gill et al.)
Error correction codes (Gambles et al.)Error correction codes (Gambles et al.)
Triple modulo redundancy based approaches Triple modulo redundancy based approaches (Neumann et. al)(Neumann et. al) Classical way of radiation hardeningClassical way of radiation hardening Area and power overheads are ~200% !!!!Area and power overheads are ~200% !!!!
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Circuit Level HardeningCircuit Level Hardening Fault avoidance approachFault avoidance approach
Gate sizingGate sizing is done to improve is done to improve the radiation tolerance of a the radiation tolerance of a design (Zhou et al.)design (Zhou et al.)
Radiation tolerance improvesRadiation tolerance improves Higher drive capability Higher drive capability Higher node capacitanceHigher node capacitance
Area, delay and power Area, delay and power overheads can be largeoverheads can be large Selectively harden critical gatesSelectively harden critical gates
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Diode Clamping based Diode Clamping based Hardening ApproachHardening Approach
Approach A - PN Junction Diode based SEU Approach A - PN Junction Diode based SEU Clamping CircuitsClamping Circuits
G
GP
in
1V
0V
1.4V
-0.4V
outP
out
D2 D1
Higher VT
device
Radiation Strike
V (out)
time0
0.2
0.4
0.6
0.8
V (outP)
time0
0.2
0.4
0.6
0.8
-0.4
Shadow Gate
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Our Radiation Hardening Our Radiation Hardening ApproachApproach
Approach B - Diode-connected Device based SEU Approach B - Diode-connected Device based SEU Clamping CircuitsClamping Circuits
G
GP
in
1V
0V
1.4V
-0.4V
outP
out
D2 D1
Higher VT
device
Radiation Strike
V (out)
time0
0.2
0.4
0.6
0.8
V (outP)
time0
0.2
0.4
0.6
0.8
-0.4
Ids
Performance of approach A is slightly better Performance of approach A is slightly better than B but with a higher area penalty than B. than B but with a higher area penalty than B. Therefore, we selected approach BTherefore, we selected approach B
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Protection Performance - Protection Performance - ExampleExample
Circuit simulation is performed in SPICECircuit simulation is performed in SPICE 65nm BPTM model card is used65nm BPTM model card is used
VVDD DD = 1V= 1V
VVTTNN = = | V| VTTPP| = | = 0.22V0.22V
Radiation strike at Radiation strike at output of 2X INVoutput of 2X INV Q Q = 24 fC= 24 fC 145ps145ps 45ps45ps
Approach B is usedApproach B is used
Our Split-output Approach
Phase 1Phase 1 Gate level hardeningGate level hardening
Phase 2Phase 2 Block level hardeningBlock level hardening Selectively harden critical gates in a circuitSelectively harden critical gates in a circuit
To keep area and delay overheads lowTo keep area and delay overheads low Reduce SER by 10XReduce SER by 10X
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Gate Level Hardening ApproachGate Level Hardening Approach
in out2out1
Radiation Particle
Radiation Particle
out2
out1n
inn
inp
out1p inp & inn
out1n
out1p
out2
|VTP|
VDD - VTN
Static Leakage Paths
A radiation particle strike at a reverse biased p-n junction A radiation particle strike at a reverse biased p-n junction results in a current flow from n-type diffusion to p-type diffusionresults in a current flow from n-type diffusion to p-type diffusion A gate constructed using only PMOS (NMOS) transistors cannot A gate constructed using only PMOS (NMOS) transistors cannot
experience 1 to 0 (0 to 1) upsetexperience 1 to 0 (0 to 1) upset
INV1 INV2
INV2INV1
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Our Gate Level Hardening Our Gate Level Hardening ApproachApproach
out1n
inn
out1p
out2
out1ninn
out1p
out2
inp
X
X
inp & inn
out1n
out1p
out2
|VTP|
VDD - VTN
Low VT transistors
Radiation Tolerant Inverter
Leakage currents are lower by ~100X
Modified Inverter
inp
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Radiation Tolerant InverterRadiation Tolerant Inverter
out1n
inn
out1p
out2
inp
inp & inn
out1n
out1p
out2
X
Radiation Particle Strike
M1
M2
M3
M4
M5
M6
M7
M8
The voltage at out2 is unaffected
X
A radiation particle strike at any node of the first inverter (radiation tolerant inverter) does not affect the voltage at out2
Radiation Particle Strike
X
X
X
X
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Radiation Tolerant InverterRadiation Tolerant Inverter
Radiation particle strike at the outputs of INV1Radiation particle strike at the outputs of INV1 Implemented using 65nm PTM with VDD=1VImplemented using 65nm PTM with VDD=1V Radiation strike: Radiation strike: QQ=150fC, =150fC, =150ps & =150ps & =38ps=38ps
out1ninn
out1p
inp
out2
INV118
Block Level Radiation HardeningBlock Level Radiation Hardening 100% SEU tolerance can be achieved by hardening all 100% SEU tolerance can be achieved by hardening all
gates in a circuit but this will be very costlygates in a circuit but this will be very costly Protect only sensitive gates in a circuit to achieve good Protect only sensitive gates in a circuit to achieve good
SEU tolerance or coverageSEU tolerance or coverage We obtain these sensitive gates using We obtain these sensitive gates using Logical MaskingLogical Masking PPLM LM (G)(G) is the probability that the voltage glitch due to a radiation is the probability that the voltage glitch due to a radiation
particle strike gets logically maskedparticle strike gets logically masked PPSenSen(G) (G) = 1 – = 1 – PPLMLM(G)(G)
If we want to protect only 2 gates then we should to protect If we want to protect only 2 gates then we should to protect Gates 1 and 3 to maximize SEU toleranceGates 1 and 3 to maximize SEU tolerance
Gate 3 is the most sensitiveGate 3 is the most sensitive
3
1
2
01
1→ 1
0
1
Radiation Particle
0
P1 = 0.25 P0 = 0.75
P1 = 0.5 P0 = 0.5
For all inputs P1 = 0.5 P0 = 0.5
GateGate PPLMLM PPSenSen
11 0.50.5 0.50.5
22 0.750.75 0.250.25
33 00 11
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Block Level Radiation HardeningBlock Level Radiation Hardening Obtained Obtained PPSenSen for all gates in a circuit using a fault simulator for all gates in a circuit using a fault simulator
Sort these gates in decreasing order of their Sort these gates in decreasing order of their PPSen Sen
Harden gates until the required Harden gates until the required coveragecoverage is achieved is achieved
Coverage is a Coverage is a good estimate for SER reductiongood estimate for SER reduction (Zhou et al.) (Zhou et al.)
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__
__ *
GgatesAll
GSen
GhardenedAll
GSen
P
P
Coverage
Gates at the primary output of a Gates at the primary output of a circuit need to be hardened since circuit need to be hardened since PPSenSen = 1 for these gates = 1 for these gates
The dual outputs of the hardened The dual outputs of the hardened gates at the primary outputs drive gates at the primary outputs drive the dual inputs of an SEU tolerant the dual inputs of an SEU tolerant flip-flip (such as the flip-flop flip-flip (such as the flip-flop proposed by Liu et al.)proposed by Liu et al.)
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Critical Charge (Qcri)
Minimum amount of Minimum amount of charge which can result in charge which can result in an SEU eventan SEU event
Our hardened gates can Our hardened gates can tolerate a large amount of tolerate a large amount of charge dumped by a charge dumped by a radiation particleradiation particle Operating frequency of Operating frequency of
circuit determines circuit determines QcriQcri
QQcricri is the amount of charge is the amount of charge
which results in a which results in a voltage voltage glitch of pulse width glitch of pulse width TT
in
out1n
out1p
out2
CLK
t1 T + t1 2T + t121
Experimental ResultsExperimental Results
We implemented a standard cell library We implemented a standard cell library LL using a using a 65nm PTM model card with VDD = 1.0V65nm PTM model card with VDD = 1.0V Implemented both regular and hardened versions of all cell Implemented both regular and hardened versions of all cell
types types
Applied our approach to several ISCAS and MCNC Applied our approach to several ISCAS and MCNC benchmark circuitsbenchmark circuits
We implemented We implemented A tool in A tool in SISSIS to find the sensitive gates in a circuit to find the sensitive gates in a circuit An STA tool to evaluate the delay of a hardened circuit An STA tool to evaluate the delay of a hardened circuit
obtained using our approachobtained using our approach Layouts were created for all gates in our library for both Layouts were created for all gates in our library for both
regular and hardened versionsregular and hardened versions
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Experimental ResultsExperimental Results
Our SEU immune gates can tolerate high energy radiation Our SEU immune gates can tolerate high energy radiation particle strikesparticle strikes
Critical chargeCritical charge is is extremely high (>520fC)extremely high (>520fC) for all benchmark for all benchmark circuitscircuits Suitable for space and military application because of the presence of Suitable for space and military application because of the presence of
large number of high energy radiation particleslarge number of high energy radiation particles
Avg. ResultsAvg. Results CoverageCoverage % Area Ovh% Area Ovh % Delay Ovh% Delay Ovh
Area MappedArea Mapped90%90% 62.462.4 28.928.9
100%100% 97.797.7 44.344.3
Delay MappedDelay Mapped90%90% 58.1558.15 27.927.9
100%100% 96.596.5 47.647.6
Average results over several benchmark circuits mapped Average results over several benchmark circuits mapped for area and delay optimalityfor area and delay optimality
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Comparison Our Hardening Comparison Our Hardening ApproachApproach
Our approachOur approach is suitable for radiation is suitable for radiation environments with high energy particlesenvironments with high energy particles
Zhou et al.Zhou et al. Our ApproachOur Approach
90% Coverage90% Coverage
Area Ovh.Area Ovh. 90%90% 58%58%
Delay Ovh.Delay Ovh. 8%8% 28%28%
Critical ChargeCritical Charge ~150fC~150fC >520fC>520fC
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SRAM HardeningSRAM Hardening
Decrease recovery Decrease recovery timetime
Slow down feedback Slow down feedback pathpath Insert resistors in the Insert resistors in the
feedback pathsfeedback paths ResistorResistor
PolysiliconPolysilicon GatedGated
Increases write delayIncreases write delay
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ConclusionsConclusions SEUs SEUs are troublesome for both memories and are troublesome for both memories and
combinational logiccombinational logic Becoming increasingly problematic even for terrestrial Becoming increasingly problematic even for terrestrial
designsdesigns
Applications demand reliable systemsApplications demand reliable systems Need to Need to efficientlyefficiently design design radiation hardening radiation hardening
approaches for approaches for both combinational and sequential both combinational and sequential elements elements
Also need efficient Also need efficient analysis techniques analysis techniques to estimate to estimate SER of complex circuitsSER of complex circuits
SEU susceptibility can be checked during design SEU susceptibility can be checked during design phasephase
Reduce the number of design iterationsReduce the number of design iterations
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THANK YOUTHANK YOU
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