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SINGLE ELECTRON TRANSISTOR

PREPARED FOR

Technical Report Writing & Language Lab

Practice

HU 481

APPROVED BY

Head Of Department, Electronics

Mr. A.K. Dutta

Techno India, Salt lake

March 2012

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CERTIFICATE

This is to certify that Ishika Biswas, a student of

ECE–‘B’, 2nd Year from Techno India, Salt Lake has

prepared the report furnished hereforth.

The report entitled “Single Electron Transistor” has

been done under my careful supervision and

embodies a genuine work with the statistics and

information provided having been verified to the best

of ability . The content has been sought and

received from various sources which have been duly

credited.

Date: /03/2012

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LETTER OF TRANSMITTALTo

Ms. Rituparna Ganguly

Humanities Department

Techno India, Salt Lake

Kolkata-91

Subject: Submission of report

Date: /03/12

Respected Ma’am

This is to present the final draft of the report as expected of me.

The topic of ‘Single Electron Transistor’ was chosen owing to its relevance as well as the personal interest I have in it. The field of Nanotechnology is one of the greatest challenges that modern science has set for mankind and the topic’s understanding requires years of study. However, an attempt has been made by me to details some basic and other concepts of Single Electron Transistor. The findings as obtained in this endeavour have been highly intriguing as I have mentioned in the report. I have made an effort to do justice to the subject covering its detail history, idea of generation, application, problem, future prospect etc. I also tried to ensure all norms and guidelines were maintained. I must thank you for your guidance in this regard.

As always, your suggestions are expected and wholly appreciated.

Thanking You

Yours Sincerely

Ishika Biswas

ECE-‘B’

Roll no.- 13000310109

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ACKNOWLEDGEMENTI would like to articulate our deep gratitude to our project guide Prof. Rituparna Ganguly for her guidance, advice and constant support in the project work. We would like to thank him for being our advisor here at Techno India,Salt lake. A special thanks also goes towards Ms. Rupa Mukherjee, Head of the Department Of Humanities, whose inputs and encouragement are an integral part of this report. I would like to thank all faculty members and staff of the Department of Electronics and Communication Engineering, TISL for their generous help in various ways for this project.

The most pleasant point of presenting a thesis is the opportunity to thank those who have contributed to it. Unfortunately, the list of expressions of thank no matter how extensive is always incomplete and inadequate. Indeed this page of acknowledgment shall never be able to touch the horizon of generosity of those who tendered their help to me.

This opportunity must also be taken to show appreciation for all friends, classmates and family who contributed in their own significant way towards making this report an enjoyable experience.

Ishika Biswas

Roll number: 13000310109

Dept. of Electronics and Communication Engineering

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CONTENTS1. Introduction 10

2. Moore’s law 11

3. Nanotechnology

13

4. CMOS in nano-era

a. Si Breakthrough: High-K/Metal-Gate Stacks

14

for High-Performance Si CMOS

b. Si Innovations: Uniaxial and Biaxial Strains 17

to enhance Si CMOS Transistor Performance

c. Transistor Architecture Innovation: 19

Non-planar Tri-gate CMOS to Improve Device

Electrostatics

5. What’s next?

a. 22 nanometer technology 21

b. Nanotechnology and?? 25

6. Approach

a. Top down approach 26

b. Bottom up approach 26

c. Top down vs bottom up 27

7. The physics behind 29

8. The history behind 35

9. Type

39

10. Fabrication on silicon 41

11. Applications 43

12. Problems

45

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LIST OF ILLUSTRATIONS

Pic no. Title Page no.

1. William Shockley (seated at Brattain's laboratory bench), John Bardeen (left) and Walter Brattain (right). The picture on the left above shows the first point contact transistor built by Walter Brattain.

10

2. In 1965 Moore sketched out his prediction of the pace of silicon technology.

11

3. Moore’s Law update 124. Richard Feynman 135. Scaling of transistor size (physical gate length Lg) to sustain Moore’s

Law.14

6. TEM cross-section of (a) SiO2 gate oxide withphysical thickness of only 0.8 nm and (b) 15 nm Lg transistor.

15

7. Id-Vg characteristics of Si NMOS transistor withphysical gate length Lg of 15 nm and physical SiO2 of 0.8 nm.

15

8. The use of metal gates is effective in screening the remote phonon-channel charge interaction and improves the transistor channel mobility

16

9. N-type (n+) metal gate electrode on high-K for NMOS and p-type (p+) metal gate electrode on high-K for PMOS have been engineered. Metal electrodes with the right work functions are necessary for CMOS transistors to achieve correct threshold voltages.

16

10. Id-Vg characteristics of the high-K/metal-gate CMOS transistors with Lg = 80 nm, EOT = 1.0 nm, “correct” threshold voltages, and negligible gate oxide leakage

16

11. (a) A strained epitaxial SiGe film in the S/D region toinduce compressive strain in the PMOS channel region.(b) NMOS device capped with a high tensile stress silicon nitride layer to induce tensile channel strain in NMOS

17

12. Biaxially tensile-strained silicon on relaxed SiGe substrate for NMOS application.

17

13. Channel mobility of biaxially tensile-strained NMOS transistor increases with increasing Ge% in the SiGe layer. The transistors have high-K/metal gate stacks.

18

14. Biaxially compressive-strained SiGe layer formed on top of a Si substrate upon which surface-channel PMOS transistors can be made.

18

15. PMOS mobility gain induced by the biaxially compressive strain in SiGe increases with increasing Ge% in the SiGe layer. This mobility

18

Pic no. Title Page no.

16. a) planar single-gate DST, (b) non-planar double-gate FINFET, and (c) non-planar Tri-gate transistor.

19

17. Simulation results showing the silicon geometry requirements for planar single-gate DST, double-gate FINFET, and Tri-gate devices. Tri-gate requirements are the most relaxed allowing for improved manufacturability.

19

18. Top-down SEM image of a Tri-gate transistor with multiple Si legs. 2019. Sub threshold slope versus transistor physical gate length. The non-planar

Tri-gate shows significant improvement over the conventional planar Si MOSFETs.

20

20. road map of processer size 2121. 22 nanometer trigate transistor(a) 2222. 22 nm trigate transistor (b) 2223. 22 nm Tri-Gate transistors can operate at lower voltage with good

performance, reducing active power by >50%23

24. Manufacturing fabs of 22nm technology 2425. An electron in motion, as captured by a quantum stroboscope. 2526. approach to new invention 2627. top down vs. bottom up in nano tech 2728. Schematic drawing of a SET. Wires are connected to source and drain

contacts to pass current through the 2DEG at the GaAs/AlGaAs interface. Wires are also connected to the confining electrodes to bias them negatively and to the gate electrode that controls the electrostatic energy of the confined electrons.

29

29. Sketch of the electrostatic potential energy experienced by an electron moving at the interface between GaAs and AlGaAs in Pic 28.

30

30. Electron micrograph of the top surface of the SET used in the experiments of Goldhaber-Gordon

30

31. Conductance of a SET as a function of the gate voltage. The spacing between the peaks is the voltage necessary to add one electron to the artificial atom.

31

32. Differential conductance on a gray scale as a function of both gate and drain-source voltage. The dark diamonds correspond to regions in which there is a gap to current flow. For a SET made of metal all diamonds would have identical size and there would be no variations of conductance outside the diamonds. Semiconductor SETs have diamonds of different sizes and peaks in differential conductance outside the diamonds, corresponding to excited states. These results are from Kouwenhoven who have made SETs so perfect that shell structure gives more stability (larger diamonds) for the electron numbers indicated.

34

33. An atomic-scale depiction of the Sketch SET shows three wires (green bars) converging on the central island (center green area), which can house up to two electrons. Electrons tunnel from one wire to another through the island. Conditions on the third wire can result in distinct conductive properties.

36

34. Jeremy Levy 3735. Initial device structure of the SET before oxidation. 4136. Schematic plane view of the device and potential diagram along the Si wire 42

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37. Current oscillations as a function of the gate voltage measured for the same device at 40 K at a drain voltage of 1 mV.

42

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ABSTRACT

Scaling down of electronic device sizes has been the fundamental strategy for improving the performance of ultra-large-scale integrated circuits (ULSIs). Metal-oxide-semiconductor field-effect transistors (MOSFETs) have been the most prevalent electron devices for ULSI applications, and thus the scaling down of the sizes of MOSFETs has been the basis of the development of the semiconductor industry for the last 30 years. However, in the early years of the 21st century, the scaling of CMOSFETs is entering the deep sub-50 nm regime. In this deep-nanoscaled regime, fundamental limits of CMOSFETs and technological challenges with regard to the scaling of CMOSFETs are encountered. On the other hand, quantum-mechanical effects are expected to be effective in these small structured devices. Therefore, in order to extend the prodigious progress of LSI performance, it is essential to introduce a new device having an operation principle that is effective in smaller dimensions and which may utilize the quantum- mechanical effects, and thus provide a new functionality beyond that attainable with CMOSFETs. Single-electron devices are promising as new nanoscaled devices because single-electron devices retain their scalability even on an atomic scale and, moreover, they can control the motion of even a single electron. Therefore, if the single-electron devices are used as ULSI elements, the ULSI will have the attributes of extremely high integration and extremely low power consumption. In this respect, scalability means that the performance of electronic devices increases with a decrease of the device dimensions. Power consumption is roughly proportional to the electron number transferred from voltage source to the ground in logic operations. Therefore, the utilization of single- electron devices in ULSIs is expected to reduce the power consumption of ULSIs. The goal of this paper is to review in brief the basic physics of single-electron devices, as well as their current and prospective applications. These devices, based on the controllable transfer of single electrons between small conducting "islands", have already enabled several important scientific experiments. Several other applications of analog single-electron devices in unique scientific instrumentation and metrology seem quite feasible. On the other hand, the prospect of silicon transistors being replaced by single-electron devices in integrated digital circuits faces tough challenges and remains uncertain. Nevertheless, even if this replacement does not happen, single-electronics will continue to play an important role by shedding light on the fundamental size limitations of new electronic devices. Moreover, recent research in this field has generated some exciting by-product ideas which may revolutionize random-access-memory and digital-data-storage technologies. Then, the advantages and disadvantages of single-electron devices over conventional MOSFETs are discussed. Next, the analytical device model of a single-electron transistor, which is a typical functional single-electron device, for circuit simulation is derived and the methodology of designing logic circuits with single-electron transistors is discussed.

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COPYRIGHT NOTICE

Copyright © 2012 Ishika Biswas. All rights reserved.

Any redistribution or reproduction of part or all of the contents in any form is prohibited other than the following:

personal and non-commercial use is permitted . the contents may be shared with any third parties for

their personal use but only upon written acknowledgement of the author and/or inclusion of this copyright notice.

Redistribution or commertial exploitation of the content is prohibited unless express written permission in provided by the author, The same condition applies to any storage or transmittal through any form of print media or electronic retrieval system. Any infringement will be considered as a punishable offence.

1.INTRODUCTION

Almost every piece of equipment that stores, transmits, displays, or manipulates information has at its core silicon chips filled with electronic circuitry. These chips each house many thousands or even millions of transistors. The history of the transistor begins with the dramatic scientific discoveries of the 1800's scientists like Maxwell, Hertz, Faraday, and Edison made it possible to harness electricity for human uses. Inventors like Braun, Marconi, Fleming, and DeForest applied this knowledge in the development of useful electrical devices like radio. Their work set the stage for the Bell Labs scientists whose challenge was to use this knowledge to make practical and useful electronic devices for communications. Teams of Bell Labs scientists, such as Shockley, Brattain, Bardeen, and many others met the challenge.--and invented the information age. They stood on the shoulders of the great inventors of the 19th century to produce the greatest invention of our time: the transistor. When it was placed in computers, however, the transistor became an integral part of the technology boom. They are also capable of being mass-produced by the millions on a sliver of silicon—the semiconductor chip. It is this almost boundless ability to integrate transistors onto chips that has fueled the information age. Today these chips are not just a part of computers. They are also important in devices as diverse as video cameras, cellular phones, copy machines, jumbo jets, modern automobiles, manufacturing equipment, electronic scoreboards, and video games. Without the transistor there would be no Internet and no space travel. In the years following its creation, the transistor gradually replaced the bulky, fragile vacuum tubes that had been used to amplify and switch signals. The transistor became the building block for all modern electronics and the foundation for microchip and computer technology.

Pic 1: William Shockley (seated at Brattain's laboratory bench), John Bardeen (left) and Walter Brattain (right). The picture on the left above shows the first point contact transistor built by Walter Brattain.

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2. MOORES LAW:

Pic 2: In 1965 Moore sketched out his prediction of the pace of silicon technology.

Near 40 years ago, Intel co-founder Gordon Moore forecasted the rapid pace of technology innovation. His prediction, popularly known as “Moore’s law” states that transistor density on integrated circuit doubles at every two years.

His prediction has proved to be uncannily accurate, in part because the law is now used in the semiconductor industry to guide long-term planning and to set targets for research and development.

This trend has continued for more than half a century. 2005 sources expected it to continue until at least 2015 or 2020. However, the 2010 update to the International Technology Roadmap for Semiconductors has growth slowing at the end of 2013, after which time transistor counts and densities are to double only every 3 years.

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Pic 3: Moore’s Law update

However Moore’s law will be valid no longer than 2019 when transistor will be composed of not more than few atoms. At this point laws of classical physics lose its relevance and rules of quantum mechanics become new engine of computing. In other words we will embrace the world of nanotechnology which promises to extend Moore’s law beyond 2019.

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3.NANOTECHNOLOGY:

Now the next question that peeps in is what is NANOTECHNOLOGY? And why is it so important? Nanotechnology is the creation of materials, components, devices, and systems at the near-atomic, or nanometer, level. “Nano” means one-billionth. Thus nanotechnology draws its name from the scale at which the technology operates—at nanometers, or 1/1,000,000,000 (one billionth) of a meter. This almost inconceivably small dimension is 100,000 times thinner than a strand of human hair. Individual atoms, the fundamental building blocks of all matter, are of this size. For example, the DNA molecule, the blueprint of life and the basis of the genome, is a twisted double-strand of molecules approximately two nanometers (2nm) across.

Nanotechnology is creating a wealth of new materials and manufacturing possibilities, which in turn will profoundly I impact our economy, our environment, and our society. Using nanotechnology, researchers and manufacturers can fabricate materials literally molecule-by-molecule. They can harness previously inaccessible properties of matter and “custom design” ultra-precise new structures, devices, and systems with new, unique, and often remarkable properties—such as materials with vastly increased strength, vastly decreased weight, vastly greater electrical connectivity, or the ability to change shape or color on demand.

Pic 4: Richard Feynman

Now Nanoelectronics refer to the use of nanotechnology on electronic components, especially transistors. The field of nanoelectronics aims to enable the continued realization of Moore’s law by using new methods and materials to build electronic devices with feature sizes on the Nano scale.

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I want to build a billion tiny factories, models of each

other, which are manufacturing

simultaneously. . . The principles of physics, as far as I can see, do not speak against the possibility of

maneuvering things atom by atom. It is not an

attempt to violate any laws; it is something, in

principle, that can be done; but in practice, it has not

4. CMOS IN NANO-ERA:

In order to sustain Moore’s Law, the physical gate length (Lg) of the transistor has been scaled by ~30% every generation, as shown in Pic 5. Previously 90 nm generation technology node used to produce CMOS devices with Lg of ~50 nm. It was projected that the Lg of the transistor will reach ~10 nm in 2011. Through silicon technology innovations and breakthroughs such as metal-gate/high-K stacks uniaxially strained Si channels , biaxially strained Si and SiGe channels, and the non-planar fully-depleted Tri-gate CMOS transistor architecture, CMOS transistor scaling and Moore’s Law will continue at least through early this decade. Recently, tremendous progress has been made in the research of novel Nano electronic devices such as carbon nanotube FETs, Si-nanowire FETs, and III-V compound semiconductor FETs These novel devices present both challenges and opportunities for future Nano electronics applications.

Pic 5: Scaling of transistor size (physical gate length Lg) tosustain Moore’s Law.

By combining Si innovations with the novel nanotechnologies onto the same Si platform, it is expected that circuit functionality can be greatly enhanced and Moore’s Law will be extended well into the next decade.

Si Breakthrough: High-K/Metal-Gate Stacks for High-Performance Si CMOS

For more than 15 years the physical thickness of SiO2 has been aggressively scaled for high-performance, low-power CMOS applications. Recently SiO2 with physical thickness of 1.2 nm has been successfully implemented in the 90 nm logic technology node. In addition, SiO2 with physical thickness of 0.8 nm [Pic: 6(a)] has been demonstrated in the laboratory, and has been integrated into 15 nm Lg Si research transistor, whose TEM cross-section is shown in Pic: 6(b) and drain current vs. gate voltage (Id-Vg) characteristics shown in Pic: 7. Continual gate oxide scaling, however, will require high-K materials since gate oxide leakage is increasing with decreasing SiO2 thickness and

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since SiO2 is running out of atoms for further scaling. So far, the most common high-K dielectric materials investigated are Hf-based and Zr-based.

Pic: 6 TEM cross-section of (a) SiO2 gate oxide withphysical thickness of only 0.8 nm and (b) 15 nm Lg transistor.

Pic: 7 Id-Vg characteristics of Si NMOS transistor withphysical gate length Lg of 15 nm and physical SiO2 of 0.8 nm.

There are two fundamental problems in replacing poly-Si/SiO2 with poly-Si/high-K dielectric stack for high-performance CMOS applications. First, high-K dielectrics and poly-Si gates are incompatible due to Fermi level pinning at the poly-Si/high-K interface, which causes high threshold voltages in MOSFETs. Fermi level pinning is most likely caused by defect formation at the poly-Si/high-K dielectric interface. Second, poly-Si/high-K transistors exhibit severely degraded channel mobility due to the coupling of low-energy surface optical (SO) phonon modes arising from the polarization of the high-K dielectric to the inversion channel charge carriers. The above fundamental poly-Si/high-K problems can be solved by replacing the conventional poly-Si gate with metal gate electrodes with “correct” work functions. The use of metal gates is effective in screening the remote phonon-channel charge interaction and improves the transistor channel mobility, as shown in Pic: 8. To achieve the correct CMOS transistor threshold voltages, a n-type (n+) metal is needed for NMOS while a p-type (p+) metal is needed for PMOS, as shown in Pic: 9.Pic: 10 shows the Id-Vg characteristics of the resulting high-K/metal-gate CMOS transistors with Lg = 80 nm, equivalent oxide thickness (EOT) of 1.0 nm, electrical oxide thickness of 1.45 nm at inversion, and negligible gate oxide leakage. The NMOS transistor achieves record-setting Ion = 1.66 mA/μm with Ioff = 37 nA/μm, while the PMOS transistor achieves record-setting Ion = 0.71 mA/μm with Ioff = 45 nA/μm at Vd = 1.3 V

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Pic 8: The use of metal gates is effective in screening the remote phonon-channel charge interaction and improves the transistor channel mobility

Pic: 9 N-type (n+) metal gate electrode on high-K for NMOS and p-type (p+) metal gate electrode on high-K for

PMOS have been engineered. Metal electrodes with the right work functions are necessary for CMOS transistors to achieve correct threshold voltages.

Pic 10: Id-Vg characteristics of the high-K/metal-gate CMOS transistors with Lg = 80 nm, EOT = 1.0

nm, “correct” threshold voltages, and negligible gate oxide leakage

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Si Innovations: Uniaxial and Biaxial Strains to enhance Si CMOS Transistor Performance

Pic 11: (a) A strained epitaxial SiGe film in the S/D region toinduce compressive strain in the PMOS

channel region.(b) NMOS device capped with a high tensile stress silicon nitride layer to induce tensile channel strain in NMOS

Pic 12: Biaxially tensile-strained silicon on relaxed SiGe substrate for NMOS application.

Strain improves transistor performance by enhancing the channel mobility through reduced electron effectivemass and intervalley scattering rate for NMOS, and reduced hole effective mass and interband scattering ratefor PMOS. There are two types of strain: uniaxial and biaxial strain. In the case of uniaxial strain, epi-SiGe isused to form the transistor source/drain regions to induce uniaxial compressive strain in the channel of the PMOS transistor as shown in Pic. 11(a), while a high tensile-stress silicon nitride cap is used to induce uniaxial tensile strain in the channel of the NMOS transistor as shown in Pic 11(b). Uniaxial strain has been successfully implemented in production CMOS transistors in the 90 nm technology node. In the case of biaxial strain, a layer of biaxially tensile-strained Si is formed on top of a relaxed SiGe substrate for both NMOS [7] and PMOS, as shown in Pic 12. Pic 13 shows the channel mobility of the biaxially tensile-strained NMOS transistor increases with increasing Ge% in the SiGe layer. However, the use of biaxially tensile-strained Si is not as effective as the uniaxially compressive-strained Si in enhancing the PMOS mobility because the mobility gain induced by the former reduces at high transverse channel electric fields. There is, however, another way of applying biaxial strain to the PMOS and not having the problem of losing the mobility gain at high transverse channel electric fields.

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Pic 14 shows a biaxially compressive-strained SiGe layer formed on top of a Si substrate, upon which surface-channel PMOS transistors can be made. Pic 15 shows the PMOS mobility gain induced by the biaxial compressive strain in SiGe increases with increasing Ge% in the SiGe layer, and that this mobility gain does not reduce at high transverse channel electric fields as in the case of the biaxial tensile strain in Si.

Pic 13: Channel mobility of biaxially tensile-strained NMOS transistor increases with increasing Ge%

in the SiGe layer. The transistors have high-K/metal gate stacks.

Pic 14: Biaxially compressive-strained SiGe layer formed on top of a Si substrate upon which surface-channel PMOS transistors can be made.

Pic 15: PMOS mobility gain induced by the biaxially compressive strain in SiGe increases with increasing Ge% in the SiGe layer. This mobility gain does not reduce at high transverse channel

electric fields like in the case of the biaxially tensile strain in Si.

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Transistor Architecture Innovation: Non-planar Tri-gate CMOS to Improve Device ElectrostaticsAs the Lg of the transistor scales, its electrostatics and short channel performance become harder to control, and the transistor Ioff increases. Several promising device architectures have been proposed to improve the electrostatics and Ioff of the transistor in upcoming logic generations, including the planar depleted-substrate transistor (DST), the non-planar double-gate FINFET, and the non-planar Tri-gate transistor, as shown in Pic 16. All three devices utilize a fully-depleted body and can be used to improve short-channel performance. Of the three device architectures shown in Pic 16, the Tri-gate transistor has the least stringent silicon body thickness (Tsi) and width (Wsi) requirement, as illustrated in Pic 17. Hence, Tri-gate is the easiest to fabricate and is the most manufacturable. Figure 18 shows a top-down SEM image a Tri-gate transistor with multiple legs. Pic 19 compares the subthreshold slope of Tri-gate transistors versus conventional planar Si transistors with respect to Lg scaling. The data shows that non-planar Tri-gate transistors have much improved electrostatics over the conventional planar Si transistors.

Pic 16: a) planar single-gate DST, (b) non-planar double-gate FINFET, and (c) non-planar Tri-gate transistor.

Pic 17: Simulation results showing the silicon geometry requirements for planar single-gate DST,

double-gate FINFET, and Tri-gate devices. Tri-gate requirements are the most relaxed allowing for improved manufacturability.

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Pic 18: Top-down SEM image of a Tri-gate transistor with multiple Si legs.

Pic 19: Subthreshold slope versus transistor physical gate length. The non-planar Tri-gate shows significant improvement over the conventional planar Si MOSFETs.

Therefore through Si breakthroughs and innovations, CMOS transistor scaling and Moore’s Law will continue at least through this decade.

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5. WHAT’S NEXT?

FinFETs are a promising substitute for bulk CMOS for meeting the challenges being posed by the scaling of conventional MOSFETs. Now Intel has declared it is putting Finfet transistors into production on a 22nm process later this year. Nearly a decade ago, TSMC demo-ed a 0.25 micron Finfet - what Intel calls a Tri-Gate - transistor. Apart from FinFets, other exploratory concepts being pursued in transistor design are: Quantum Well devices; Tunnel FET; Graphene FET; and Carbon Nanotubes. GloFo is in a bit of a fog about it all, rambling: "We and our development partners have longstanding programs to evaluate options for next-generation transistors, including non-planar structures, and we don't see the need for these technologies until beyond the 22/20nm generation." Over two years ago, IBM, Applied Materials and the College of Nanoscale Science and Engineering (CNSE) of the University at Albany announced an agreement to co-develop Finfet technology for manufacturing 22-nm logic and memory chips. At that time it was said that Finfets were considered a potential successor to planar transistors for 22-nm chips. But FinFETs are not our point of concern. Here we are more interested about 22nm technology.

22 nanometer technology

Intel will use this novel 22nm technology to manufacture its Ivy Bridge processors, which should be in volume production in the second half of this year and available in PCs and servers starting in early 2012. It was first introduced in 2011.but was not implemented practically.

Pic 20: road map of processer size

To demonstrate that Ivy Bridge is real, Intel showed several working systems including a server with a dual-core processor, a desktop running a driving game and a laptop playing a 1080p video. Intel said that the 22nm tri-gate transistor will deliver 37% better performance than the 32nm planar transistors used in Sandy Bridge chips–already the fastest by a wide margin. Alternatively, Intel can tune the tri-gate transistors to provide the same level of performance while using half the power of Sandy Bridge. The 22nm technology will increase the CPU performance in Ivy Bridge, but Dadi Perlmutter, a vice president and General Manager of the Intel Architecture Group, also hinted it will make a big difference in the graphics and media processing capabilities of Ivy Bridge.This transition will occur as the rest of the industry is shifting from 45nm/40nm to 32nm/28nm. Like the introduction of high-k materials and metal gates (HKMG)–where competitors are still playing catch-up three years later–the shift to tri-gates could propel Intel years ahead of AMD.

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Pic 21:22 nanometer trigate transistor(a)

And because the 22nm technology with tri-gates is not only denser, but also uses less power, it should work well in mobile devices giving Intel a fresh chance to challenge companies that design ARM-based application processors such as Qualcomm, Samsung, Texas Instruments and Nvidia. While SOCs (System-On-Chip) using Intel’s 22nm process technology will come later, Atom is on an accelerated schedule and will be released around the same time as new PC processors in future generations.The vast majority of today’s integrated circuits are built using planar transistors, meaning ones in which the silicon channels that conduct the flow of electrons when the switch (the gate electrode) is turned on and off lie flat on a silicon base or substrate.

Pic 22: 22 nm trigate transistor (b)

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It’s possible to build 32nm/28nm chips using conventional polysilicon oxynitride gates–most semiconductor foundries will offer this–but the benefits of HKMG are so significant that the rest of the industry is following suit. AMD’s Llano processor which is now shipping and should appear in desktops and laptops starting in June, is manufactured by GlobalFoundries using a 32nm HKMG process. TSMC, the world’s largest semiconductor foundry, will start volume production of chips using a 28nm HKMG process later this year, followed by GlobalFoundries on that node in early 2012.

As chip designers scale transistors beyond 32nm, however, the features start to become so small that it creates more electrostatic problems. In other words, it is difficult to properly control the switching of the transistors. One solution to this is a 3-D or non-planar transistor structure. Most of the industry refers to this as a FinFET (Field-Effect Transistor) because the conducting channel sticks up from the substrate like a fin with a gate on either side–or a double-gate–to better control switching. The problem with FinFETs is that they require a relatively thin and tall fin, which is difficult to manufacture. Think of it like building a skyscraper versus a small office building (although you could fit perhaps 5,000 of these “skyscrapers” in the width of a human hair). Intel has a different twist on the FinFET. The tri-gate surrounds the channel on three sides so that it can effectively control a shorter and wider fin that should be easier to build, though it is still more challenging than the tried-and-true planar transistor. (The ideal transistor would have a gate that wrapped all the way around a tiny silicon nanowire, but this is impossible to manufacture using today’s technology.)

Pic 23: 22 nm Tri-Gate transistors can operate at lower voltage with good performance, reducing active power by >50%

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Therefore 22 nanometer tri-gate shows dramatic performance gain at low operating voltage, better than Bulk, PDSOI or FDSOI. Shows 37% performance increase at low voltage, >50% power reduction at constant performance Improved switching characteristics (On current vs. Off current) , higher drive current for a given transistor footprint and only 2-3% cost adder. The introduction of tri-gate transistors will enable Moore’s Law to continue. Intel said the tri-gate structure will work not only at 22nm, but also on the 14nm technology scheduled for production in late 2013. More important, it should allow Intel’s customers to build not only laptops but a whole range of devices from smartphones to servers in large data centers that have significantly better performance and use less power.

And here are some Fantabulous manufacturing fabs of 22 nanometer technology.

Pic 24: Manufacturing fabs of 22 nanometer technology

Nanotechnology and??

The lust of people for smaller smaller and smaller technology are taking technology at single atomic level. A University of Pittsburgh-led team has created a single-electron transistor that provides a building block for new, more powerful computer memories, advanced electronic materials, and the basic components of quantum computers. The researchers report in Nature Nanotechnology that the transistor's central component—an island only 1.5 nanometers in diameter—operates with the

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addition of only one or two electrons. That capability would make the transistor important to a range of computational applications, from ultradense memories to quantum processors, powerful devices that promise to solve problems so complex that all of the world's computers working together for billions of years could not crack them. In addition, the tiny central island could be used as an artificial atom for developing new classes of artificial electronic materials, such as exotic superconductors with properties not found in natural materials, explained lead researcher Jeremy Levy, a professor of physics and astronomy in Pitt's School of Arts and Sciences. Levy worked with lead author and Pitt physics and astronomy graduate student Guanglei Cheng, as well as with Pitt physics and astronomy researchers Feng Bi, Daniela Bogorin, and Cheng Cen. The Pitt researchers worked with a team from the University of Wisconsin at Madison led by materials science and engineering professor Chang-Beom Eom, including research associates Chung Wun Bark, Jae-Wan Park, and Chad Folkman. Also part of the team were Gilberto Medeiros-Ribeiro, of HP Labs, and Pablo F. Siles, a doctoral student at the State University of Campinas in Brazil.

This single electron transistor is our topic which is to be covered in this report.

But before going into the detail of this technology we need to discuss some other terms and situation.

Pic 25: An electron in motion, as captured by a quantum stroboscope.

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6. APPROACH:

Now that we know what size nanomaterials are, how do we go about making them. There are two main approaches - one is called the top-down approach, the other is the bottom-up approach.

Pic 26: approach to new invention

Top down approach

A top-down approach (also known as stepwise design) is essentially the breaking down of a system to gain insight into its compositional sub-systems. In a top-down approach an overview of the system is formulated, specifying but not detailing any first-level subsystems. Each subsystem is then refined in yet greater detail, sometimes in many additional subsystem levels, until the entire specification is reduced to base elements. The top-down approach is a physics/engineering approach. It involves taking bulk material and carving out the nanomaterials, much like a sculptor would carve out a statue, only on a much smaller scale. The advantage of this technique is that you can create very precise shapes and structures using lasers or atomic sized needles. The disadvantage is that there is an enormous cost in the precision instruments that are required to make nanoscale materials. Computer chip companies like Intel would use an approach like this in generating nanoscale computer chips - you can find out more by looking up techniques such as "photolitography".

Bottom up approach

A bottom-up approach is the piecing together of systems to give rise to grander systems, thus making the original systems sub-systems of the emergent system. In a bottom-up approach the individual base elements of the system are first specified in great detail. These elements are then linked together to form larger subsystems, which then in turn are linked, sometimes in many levels, until a complete top-level system is formed. This strategy often resembles a "seed" model, whereby the beginnings are small but eventually grow in complexity and completeness.

In nanotechnology the bottom-up approach is a chemistry approach and involves making nanomaterials from simple molecules, assembling them together into the shape you want. A key feature of this is what's called molecular self assembly - where molecules are arranged together and mixed in sequence so they add together and "self-assemble" into the desired arrangement. As an

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example, imagine we wanted to make a protein sensor discussed above. We would have some sort of surface, a platform that is going to hold our device - with a metal strip onto it. the first step would be to dip this into a solution containing long alkane chains - maybe 15 carbons, that have an alcohol (-OH) or thiol (-SH) group on the end. These are like velcro to the metal, and stick on. At the other end, there would be a group that we could easily replace in a simple chemical reaction - so all we have to do is put out platform with alkane chains into a beaker and add in what ever we wanted to stick on the end - after it reacts, we can use the combined device as a sensor. For example, the group at the end might give off light when there is no protein attached, but not give off light when there is - so we could see very easily it there was protein present in the sample we were analysing. Self-assembley is very cheap, and can make large quantities.

Top down vs bottom up

The biggest problem with top down approach is the imperfection of surface structure and significant crystallographic damage to the processed patterns. These imperfections which in turn leads to extra challenges in the device design and fabrication . But this approach leads to the bulk production of nano material. Regardless of the defects produced by top down approach, they will continue to play an important role in the synthesis of nano structures.

Pic 27: top down vs bottom up in nano tech

Though the bottom up approach oftenly referred in nanotechnology, it is not a newer concept. All the living beings in nature observe growth by this approach only and also it has been in industrial use for over a century. Examples include the production of salt and nitrate in chemical industry. Although the bottom up approach is nothing new, it plays an important role in the fabrication and processing of nano structures. There are several reasons for this and explained as below.When structures fall into a nanometer scale, there is a little chance for top down approach. All the tools we have possessed are too big to deal with such tiny subjects. Bottom up approach also promises a better chance to obtain nano structures with less defects, more homogeneous chemical composition.On the

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contrary, top down approach most likely introduces internal stress, in addition to surface defects and contaminations.And remarkably single electron transistor is also a outcome of this bottom up approach.

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7. THE PHYSICS BEHIND:

A conventional field-effect transistor, the kind that makes all modern electronics work, is a switch that turns on when electrons are added to a semiconductor and turns off when they are removed. These on and off states give the ones and zeros that digital computers need for calculation. Interestingly, these transistors are almost completely classical in their physics. Only a few numbers that characterize their behavior are affected by quantum mechanics. However, if one makes a new kind of transistor, in which the electrons are confined within a small volume and communicate with the electrical leads by tunneling, all this changes. One then has a transistor that turns on and off again every time one electron is added to it; we call it a single electron transistor (SET). Furthermore, the behavior of the device is entirely quantum mechanical. It is very appropriate, therefore, to discuss this device on the 100th anniversary of Planck’s constant. Various structures have been made in the past two decades, in which electrons are confined to small volumes in metals or semiconductors. Perhaps not surprisingly, there is a deep analogy between such confined electrons and atoms. Whereas natural atoms are studied by adding, removing or exciting electrons with light, these artificial atoms typically have such small energy scales that they are best studied by measuring the voltage and current resulting from tunneling between the artificial atom and nearby electrodes

Pic 28. Schematic drawing of a SET. Wires are connected to source and drain contacts to pass current through the 2DEG at the GaAs/AlGaAs interface. Wires are also connected to the confining

electrodes to bias them negatively and to the gate electrode that controls the electrostatic energy of the confined electrons.

A schematic of one kind of SET is shown in Pic 28. It consists of a semiconductor, in this case GaAs, separated from metal electrodes by an insulator, in this case AlGaAs. The AlGaAs is doped with Si, which donates electrons. These fall into the GaAs, because their energy is lower in the latter material. The resulting positive charge on the Si atoms creates a potential that holds the electrons at the GaAs/AlGaAs interface, creating a two dimensional electron gas (2DEG). The source and drain contacts allow one to drive electrons from an external circuit through the 2DEG. The 2DEG is confined perpendicular to the GaAs/AlGaAs interface, and the confinement in the other two directions is accomplished with electric fields imposed by very small confinement electrodes. A

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negative voltage on these electrodes creates a potential similar to the one sketched in Pic 29 ; the negative voltage repels electrons from underneath the confinement electrodes and creates saddle point potential barriers under the constrictions. For the remainder of our discussion, we assume that the voltage on these constriction electrodes is fixed, resulting in a fixed confinement potential. However, the voltage on an additional electrode, the gate, is varied to adjust the potential of the electrons confined in the potential well.Pic 30 shows an electron micrograph of such constriction and gate electrodes for one of the

Pic 29. Sketch of the electrostatic potential energy experienced by an electron moving at the interface between GaAs and AlGaAs in Pic 28.

Pic 30. Electronmicrograph of the top surface of the SET used in the experiments of Goldhaber-Gordon

smallest SETs made in this way so far. The region surrounded by electrodes appears to be a few hundred nanometers in diameter. However, the droplet of electrons confined in it is considerably smaller. We estimate that these SETs have about 50 electrons confined to a droplet about 100 nm in

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diameter. The GaAs/AlGaAs structure is grown with molecular beam epitaxy. The electrodes are fabricated using electron beam lithography. When the voltage on the gate electrode is increased, the potential minimum, in which the electrons are trapped, becomes deeper. This causes the number of trapped electrons to increase. However, unlike a conventional transistor, in which the charge increases continuously, the charge in the trap increases in discrete steps, and this is reflected in the conductance between source and drain.

Pic 31 shows the conductance as a function of gate voltage Vg for a SET made b y U. Meirav , larger than the one in Fig. 30. The conductance is measured by applying a very small voltage Vds between drain and source, small enough that the current is proportional to Vds. As seen in the figure, the conductance increases and decreases by several orders of magnitude almost periodically in Vg. A calculation of the capacitance between the gate electrode and the droplet of confined electrons shows that the voltage between two peaks or two valleys is just that necessary to add one electron to the droplet. The name “single electron transistor” comes from the observation that the transistor turns on and off again every time a single electron is added to it.

Pic 31. Conductance of a SET as a function of the gate voltage. The spacing between the peaks is the voltage necessary to add one electron to the artificial atom.

For current to flow the number of electrons on the droplet must fluctuate, say between N and N +1. Thus the Nth peak in the conductance occurs when the state of the droplet containing N electrons is in equilibrium with the state containing N +1 electrons. Were the gate the only electrode contributing to the electrostatic energy of the droplet, the gate voltage at which the Nth peak occured multiplied by the charge of the electron e would be the energy difference between the two states. Since there are several electrodes near the droplet, the energy change caused by Vg is αeVg where α = Cg/C is the ratio of the gate capacitance to the total capacitance. Therefore, a conductance peak occurs when

αeVg(N) = E(N + 1) − E(N)………………………………………….(1)

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apart from a constant, where E(N) is the total energy of the droplet with N electrons. Thus, predicting the position of the Nth peak in Pic 31 requires a model for the total energy of an artificial atom with N electrons. There are several levels of sophistication with which such models have been developed. The simplest is called the Coulombb lockade model, and treats the droplet of confined electrons as a metal particle. Think about how an electron tunnels from one lead onto the metal particle and then onto the other lead. Suppose the particle is neutral to begin with. To add a charge Q to the particle requires energy Q2/2C, where C is the total capacitance between the particle and the rest of the system. Setting Q =−Ne in Eq. 1 gives values of the peak positions that are equally spaced in gate voltage with separation ΔVg=e/Cg. This result is a direct consequence of the charge quantization. Taking E(Q) =Q2/2C means that the energy as a function of Q is a parabola with minimum at Q0.By varying Vg we can choose any value of Q0, the charge that would minimize the energy, were not the charge quantized. However, because the real charge is quantized only discrete values of the energy E are possible. When Q0 = −Ne, for which an integer number N of electrons minimizes E, the Coulombi nteraction results in an energy difference U = e2/2C for increasing or decreasing N by one. There is thus an energy gap that suppresses charge fluctuations. For all values of Q0 except Q0 =−(N + 1/2)e there is a smaller, but non-zero, energy gap for adding or subtracting an electron. Under these circumstances no current can flow at temperature T = 0. However, when Q0 =−(N + 1/2)e the state with Q =−Ne and that with Q =−(N + 1)e are degenerate; the charge fluctuates between the two values even at zero temperature. Consequently, the energy gap disappears and current can flow. The peaks in conductance are, therefore, periodic, occurring whenever the average charge on the artificial atom is Q0 = −(N + 1/2)e. Thus the approximately equally spaced peaks in conductance of the SET results from quantization of charge. But under what conditions is charge quantized? This may seem like a silly question. Since the discovery of the electron we have known that its charge is quantized. However, because the wave functions of electrons in conductors are extended over macroscopic distances, the charge in any small volume is not quantized. It is the localization of electrons to a small region of space that quantizes their charge. However, the degree of localization depends on the transmission of the tunnel barriers. A very elegant argument tells us how resistive the tunnel barriers must be for charge quantization. One simply demands that the RC time constant for an electron to tunnel off the droplet into the leads be great enough that the energy uncertainty is less than the charging energy. If the tunneling resistance is R, this condition is RC > h/U or approximatelyR > h/e2, the fundamental unit of resistance that enters, for example, in the quantum Hall effect. Thus, while the calculation of the charging energy is entirely classical, Planck’s constant determines whether the charging energy is present or not. This condition is valid at T = 0, independent of C and therefore of the size of the artificial atom. Of course, thermal charge fluctuations can overcome this localization, so charge quantization is observable only at temperatures kT < U, which means that it is easier to see the effects in smaller artificial atoms, which have larger U. In addition to charge quantization, energy quantization is important when electrons are confined to small volumes. Interestingly, the criterion for charge and energy quantization at T = 0 are exactly the same. Whereas U is the energy to add an extra electron to the artificial atom, there is a typical level spacing Δ∈ necessary to excite the artificial atom with fixed number of electrons. Furthermore, the levels of the artificial atom are not perfectly sharp, but rather have typical width Γ. The level width is caused by lifetime broadening, because an electron in a level on the artificialatom can tunnel into the leads. Alternatively, one can say that the eigenstates of thesystem are mixtures of localized states on the artificial atom and extended states in the leads. Clearly, energy quantizationmeans that Δ∈> Γ. FollowingThouless the current through the SET for a single quantum level is the charge of the electron divided by the time t for an electron in a single quantum state to

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traverse the artificial atom while in that level. If (dN/d∈) is the density of states in the artificial atom, then (dN/d∈)eVds is the number of current-carrying channels between the Fermi energy in the source and that in the drain. Thus, the current is given by

I=e etdNd∈

eV ds………………………………….. (2)

The width gives the traversal time, t = h/Γ and (dN/d∈) = 1/Δ∈, so the condition for energy quantization is R = Vds/I > h/e2, the same as for charge quantization. However,while the conditions for charge and energy quantization at zero temperature are the same, charge quantization often survives to higher temperatures. The charge quantization can be observed whenkT < U, but energy quantization requires kT <Δ∈.Since U > Δ∈ for most SETs made to date, energy quantization is more difficult to observe than charge quantization. Energy quantization can be observed by measuring the variations between peak positions for data like those in Pic 31. Alternatively, the energy level spectrum can be measured directly by observing the tunneling current at fixed Vg as a function of Vds

.Suppose we adjust Vg so that Q0 = −Ne and then begin to increase Vds. The Fermi level in the source rises in proportion to Vds relative to the drain, so it also rises relative to the energy levels of the artificial atom. Current begins to flow when the Fermi energy of the source is raised just above the first quantized energy level of the atom. As the Fermi energy is raised further, higher energy levels in the atom fall below the Fermi energy, and more current flows because there are additional channels for the electron to use for tunneling onto the artificial atom. One measures the energies by measuring the voltage at which the current increases, or, equivalently, the voltage at which there is a peak in the derivative of the current dI/dVds. One of the most beautiful experiments of this kind is shown in Pic. 32.This is for an SET made in a very different way from that in Pic 29, such that the confining potential is almost perfectly circular. The diamonds with very low differential conductance are regions where only one charge state is stable. Data like those in pic 31 would be obtained by moving along the vertical axis at Vds = 0. The boundary of the diamonds corresponds to the threshold for changing the charge of the artificial atom. One can overcome the charging energy by changing the source-drain voltage as well as by changing Vg. The diagonal lines outside the diamonds correspond to excited energy levels of the artificial atom. In this case, the artifical atom is so small that Δ∈∼ U so the peak spacings at Vds = 0 are far from constant and reflect the shell structure of the artificial atoms. One can even see the effects of exchange, that is, the filling follows Hund’s rule, making certain values of N more stable than others.

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Pic 32: Differential conductance on a gray scale as a function of both gate and drain-source voltage. The dark diamonds correspond to regions in which there is a gap to current flow. For a SET made of

metal all diamonds would have identical size and there would be no variations of conductance outside the diamonds. Semiconductor SETs have diamonds of different sizes and peaks in differential

conductance outside the diamonds, corresponding to excited states. These results are from Kouwenhoven who have made SETs so perfect that shell structure gives more stability (larger

diamonds) for the electron numbers indicated.

So far we have identified three different energy scales that are important in understanding SETs: U, Δ∈ and Γ. These are the typical energies, respectively, to add an electron to the artificial atom, to excite the artificial atom with a fixed number of electrons and the broadening of the artifical atom’s energy levels by quantum mechanical tunneling to the leads. Although the Coulomb blockade model is often adequate to estimate U, we know that it, like Δ∈ and Γ has a quantum mechanical origin. There is one last energy scale that is even smaller than these three. The tunneling results in a kind of chemical bond between the artificial atom and the leads when the artificial atom has a spin. This is the origin of the Kondo effect, usually associated with magnetic impurities in metals. The Kondo “bond” is very weak in SETs, and was not observed for nearly a decade after theorists predicted it. However, it has now been identified in a number of experiments and is the subject of intense experimental and theoretical research.

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8. THE HISTORY BEHIND:

The effects of charge quantization were first observed in tunnel junctions containing metal particles as early as 1968. Later, the idea that the Coulomb blockade can be overcome with a gate electrode was proposed by a number of authors ,and Kulik and Shekhter [20] developed the theory of Coulomb-blockade oscillations, the periodic variation of conductance as a function of gate voltage. Their theory was classical, including charge quantization but not energy quantization. However, it was not until 1987 that Fulton and Dolan made the first SET, entirely out of metals, and observed the predicted oscillations. They made a metal particle connected to two metal leads by tunnel junctions, all on top of an insulator with a gate electrode underneath. Since then, the capacitances of such metal SETs have been reduced to produce very precise charge quantization. The first semiconductor SET was fabricated accidentally in 1989 by Scott-Thomas narrow Si field effect transistors. In this case the tunnel barriers were produced by interface charges. Shortly thereafter Meirav et al. [8] made controlled devices of the kind depicted in pic 28, albeit with an unusual heterostructure with AlGaAs on the bottom instead of the top. In these and similar devices the effects of energy quantization were easily observed. Only in the past few years have metal SETs been made small enough to observe energy quantization. Foxman also measured the level width Γ and showed how the energy and charge quantization are lost as the resistance decreases toward h/e2. In most cases the potential confining the electrons in a SET is of sufficiently low symmetry that one is in the regime of quantum chaos: the only quantity that is quantized is the energy. In this case there is a very sophisticated approach, based in part on random matrix theory, for predicting the distributions of peak spacings and peak heights for data like those in Pic 31. There are challenging problems in this arena that are still unsolved. In particular, there is great interest in how the interplay of exchange and level spacing determines the spin of a small metal SET. As already mentioned, the data of Pic 32 are for an SET of sufficiently high symmetry that angular momentum in the plane of the 2DEG is conserved, so shell structure is apparent. Another way to eliminate the scattering that destroys angular momentum conservation is to apply a magnetic field perpendicular to the 2DEG. At sufficientlyhigh fields elegant patterns are seen in the single-electron-peak positions as a function of field. The evolution of Coulomb charging peaks with magnetic field have been interpretedwith various degrees of sophistication, imitating the development of the theory ofn atoms. First one tries the “constant interaction model” in which electrons are treated as independent except for a constant Coulomb charging energy. This gives only a qualitative picture of the physics. In order to be quantitative, one needs to at least treat the electron-electron interactions self-consistently (analogous to the Thomas-Fermi model), and for some cases one needs to include exchange and correlations. In particular, it is found that electrons in an SET undergo a series of phase transitions at high magnetic field. One of these is well described by Hartree-Fock theory, but others appear to require additional correlations. The future of research on SETs looks very bright. There are strong efforts around the world to make the artificial atoms in SETs smaller, in order to raise the temperature at which charge quantization can be observed. These involve self-assembly techniques and novel lithographic and oxidation methods whereby artificial atoms can be made nearly as small as natural ones. This is, of course, driven by an interest in using SETs for practical applications. However, as SETs get smaller, all of their energy scales can be larger, so it is very likely that new phenomena will emerge.

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Recently A University of Pittsburgh-led team has created a single-electron transistor that provides a building block for new, more powerful computer memories, advanced electronic materials, and the basic components of quantum computers.

The researchers report in Nature Nanotechnology that the transistor’s central component—an island only 1.5 nanometers in diameter—operates with the addition of only one or two electrons. That capability would make the transistor important to a range of computational applications, from ultradense memories to quantum processors, powerful devices that promise to solve problems so complex that all of the world’s computers working together for billions of years could not crack them.

Pic 33. An atomic-scale depiction of the SketchSET shows three wires (green bars) converging on the central island (center green area), which can house up to two electrons. Electrons tunnel from one

wire to another through the island. Conditions on the third wire can result in distinct conductive properties.

In addition, the tiny central island could be used as an artificial atom for developing new classes of artificial electronic materials, such as exotic superconductors with properties not found in natural materials, explained lead researcher Jeremy Levy, a professor of physics and astronomy in Pitt’s School of Arts and Sciences. Levy worked with lead author and Pitt physics and astronomy graduate student Guanglei Cheng, as well as with Pitt physics and astronomy researchers Feng Bi, Daniela Bogorin, and Cheng Cen. The Pitt researchers worked with a team from the University of Wisconsin at Madison led by materials science and engineering professor Chang-Beom Eom, including research associates Chung Wun Bark, Jae-Wan Park, and Chad Folkman. Also part of the team were Gilberto Medeiros-Ribeiro, of HP Labs, and Pablo F. Siles, a doctoral student at the State University of Campinas in Brazil.

Levy and his colleagues named their device SketchSET, or sketch-based single-electron transistor, after a technique developed in Levy’s lab in 2008 that works like a microscopic Etch A SketchTM, the

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drawing toy that inspired the idea. Using the sharp conducting probe of an atomic force microscope, Levy can create such electronic devices as wires and transistors of nanometer dimensions at the interface of a crystal of strontium titanate and a 1.2 nanometer thick layer of lanthanum aluminate. The electronic devices can then be erased and the interface used anew.

The SketchSET—which is the first single-electron transistor made entirely of oxide-based materials—consists of an island formation that can house up to two electrons. The number of electrons on the island—which can be only zero, one, or two—results in distinct conductive properties. Wires extending from the transistor carry additional electrons across the island.

Pic 34: Jeremy Levy

One virtue of a single-electron transistor is its extreme sensitivity to an electric charge, Levy explained. Another property of these oxide materials is ferroelectricity, which allows the transistor to act as a solid-state memory. The ferroelectric state can, in the absence of external power, control the number of electrons on the island, which in turn can be used to represent the 1 or 0 state of a memory element. A computer memory based on this property would be able to retain information even when the processor itself is powered down, Levy said. The ferroelectric state also is expected to

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be sensitive to small pressure changes at nanometer scales, making this device potentially useful as a nanoscale charge and force sensor.

Since August 2010, Levy has led a $7.5 million, multi-institutional project to construct a semiconductor with properties similar to SketchSET, he said. Funded by the U.S. Air Force Office of Scientific Research’s Multi-University Research Initiative (MURI) program, the five-year effort is intended to overcome some of the most significant challenges related to the development of quantum information technology. Levy works on that project with researchers from Cornell, Stanford, the University of California at Santa Barbara, the University of Michigan, and UW-Madison.

The research in Nature Nanotechnology also was supported in part by grants from the U.S. Defense Advanced Research Projects Agency (DARPA), the U.S. Army Research Office, the National Science Foundation, and the Fine Foundation.

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9. TYPES:

Single-electron transistors can be made using metals, semiconductors, carbon nanotubes, or single molecules. Aluminum SET's made with Al/AlOx/Al tunnel junctions are the SET's that have been used most often in applications. This kind of SET is used in metrology to measure currents, capacitance, and charge. They are used in astronomical measurements and they have been used to make primary thermometers. However, many fundamental single-electron measurements have been made using GaAs heterostructures. The island of this kind of SET is often called a quantum dot. Quantum dots have been very important in contributing to our understanding of single-electron effects because it is possible to have just one or a few conduction electrons on a quantum dot. The quantum states that the electrons occupy are similar to electron states in an atom and quantum dots are therefore sometimes called artificial atoms. The energy necessary to add an electron to a quantum dot

depends not just on the electrostatic energy of Eq. ∫0

−e

Vdq=−eV (n )+ e2

2C Σ ……….(3)

(Where n is the number of electrons on the island, e is the positive elementary charge, and CΣ is the total capacitance of the island CΣ = C1 + C2 + Cg1 + Cg2 + C0. The energy it takes to move an

infinitesimally small charge dq from ground at a potential V = 0 to the island is Vdq. )

But also on the quantum confinement energy and the magnetic energy associated with the spin of the electron states. By measuring the current that flows thorough a quantum dot as a function of the gate voltage, magnetic field, and temperature allows one understand the quantum states of the dot in quite some detail.

The SET's described so far are all relatively large and have to be measured at low temperature, typically below 100 mK. For higher temperature operation, the SET's have to be made smaller. Ono used a technique called pattern dependent oxidation (PADOX) to make small silicon SET's. These SET's had junction capacitances of about 1 aF and a charging energy of 20 meV. The silicon SET's have the distinction of being the smallest SET's that have been incorporated into circuits involving more than one transistor. Specifically, Ono et al. constructed an inverter that operated at 27 K. Postma made a SET that operates at room temperature by using an AFM to buckle a metallic carbon nanotube in two places. The tube buckles much the same way as a drinking straw buckles when it is bent too far. Using this technique, a 25 nm section of the nanotube between the buckles was used as the island of the SET and a conducting substrate was used as the gate. The total capacitance achievable in this case is also about 1 aF. Pashkin used e-beam lithography to fabricate a SET with an aluminum island that had a diameter of only 2 nm. This SET had junction capacitances of 0.7 aF, a charging energy of 115 meV, and operated at room temperature. SET's have also been made by placing just a single molecule between closely spaced electrodes. Park built a SET by placing a C 60

molecule between electrodes spaced 1.4 nm apart. The total capacitance of the C60 molecule in this configuration was about 0.3 aF. Individual molecules containing a Co ion bonded to polypyridyl ligands were also placed between electrodes only 1-2 nm apart to fabricate a SET. In similar work, Liang placed a single divanadium molecule between closely spaced electrodes to make a SET. In the last two experiments, the Kondo effect was observed as well as the Coulomb blockade. The charging energy in the molecular devices was above 100 meV.

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One of the conclusions that can be drawn from this review of SET devices is that small SET's can be made out a of variety of materials. Single electron transistors with a total capacitance of about 1 aF were made with aluminum, silicon, carbon nanotubes and individual molecules. It seems unlikely that SET's with capacitances smaller than the capacitances of the molecular devices can be made. This sets a lower limit on the smallest capacitances that can be achieved at about 0.1 aF. Achieving small capacitances such as this has been a goal of many groups working on SET's. However, while some of the device characteristics improve as a SET is made smaller, some of the device characteristics get worse as SET's are made smaller. For some applications, the single molecule SET's are too small to be useful. As SET's are made smaller, there is an increase in the operating temperature, the operating frequency, and the device packing density. These are desirable consequences of the shrinking of SET devices. The undesirable consequences of the shrinking of SET's are that the electric fields increase, the current densities increase, the operating voltage increases, the energy dissipated per switching event increases, and the power dissipated per unit area increases, the voltage gain decreases, the charge gain decreases, and the number of Coulomb oscillations that can be observed decrease.

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10. FABRICATION ON SILICON:

For SET operation at finite temperature T, the island should be small to maintain the Coulomb blockade condition, i.e., e2/2Ctotal > kT, where Ctotal is the total capacitance of the SET island. It is necessary that theSET island be smaller than 10 nm for operation at room temperature. The most difficult issue in fabricating such a SET has been how to attach the two tunnel capacitors to the nanometer-scale island. We have already developed a controllable fabrication method called pattern-dependent oxidation (PADOX) that converts a small Si wire pattern on a SOI (silicon on insulator) wafer to a single-electron island with a tunnel capacitor at each end . The initial structure of the SET contains a narrow and short one-dimensional Si wire oriented to the [110] direction on a thin (001) SOI wafer as shown in Pic 35. Typical wire width is about 30 nm.

Pic 35: Initial device structure of the SET before oxidation.

The wire height, which is the thickness of the SOI layer, is also about 20 nm. The wire length varies from 30 to 200 nm. When a narrow Si wire is thermally oxidized in dry oxygen ambient, the oxidation is suppressed due to the huge amount of compressive stress accumulated in the newly grown SiO2, which surrounds the wire completely. It is reported that a compressive stress larger than 20 000 atm accumulates in newly grown SiO2

when a 10-nmdiameter Si wire is formed by oxidizing a 30-nmdiameter Si wire. When the Si wire structure shown in Pic 35 is subjected to thermal oxidation, the compressive stress is exerted on the middle part of the wire. Oxidation proceeds relatively faster in the wire regions around the end than at the middle because of the shear stress caused by the oxidation from the back in the wide two-dimensional layer. We estimated by using the first-principles calculation that a bandgap reduction of about 150 meV occurs when the compressive stress on the middle of the Si wire is 20000 atm. This reduction cancels out the effective bandgap increase of about 50 meV due to the quantum size effect in a 5-10 nm Si wire. As a result, a potential profile is formed as schematically shown in Pic 36.

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Pic 36: Schematic plane view of the device and potential diagram along the Si wire

The two potential hills serve as tunnel barriers: a tunnel capacitor is formed between the Si island and the wider Si layer. This mechanism provides a SET in a self-aligned manner. Another great advantage of the method is that an island becomes smaller than the initial size defined by lithography. Another important feature of Si SETs fabricated by PADOX is stability of the electrical characteristics. In conventional SETs, offset charges moving around the SET island sometime changes the characteristics. However, devices fabricated by PADOX are definitely stable for long-term drift, which is indispensable for actual usage of SETs. Pic 37 shows the conductance vs. gate-voltage characteristics of the same SET, where the two measurements were carried out at seven-years interval. During the seven years, the SET was kept at room temperature although the device was cooled down twice to 40 K for measurements. The two curves are the same within the accuracy of our measurement system. This indicates that there is no effective movable offset charge in the SET fabricated by PADOX, probably due to the very high stability of the Si/SiO2 system.

Pic 37: Current oscillations as a function of the gate voltage measured for the same device at 40 K at a drain voltage of 1 mV.

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11. APPLICATIONS:

10.1. Supersensitive Electrometer

The high sensitivity of single-electron transistors have enabled them as electrometers in unique physical experiments. For example, they have made possible unambiguous observations of the parity effects in superconductors. Absolute measurements of extremely low dc currents (~10-20 A) have been demonstrated. The transistors have also been used in the first measurements of single-electron effects in single-electron boxes and traps A modified version of the transistor has been used for the first proof of the existence of fractional-charge excitations in the fractional quantum hall effect.

10.2. Single-Electron Spectroscopy

One of the most important application of single-electron electrometry is the possibility of measuring the electron addition energies (and hence the energy level distribution) in quantum dots and other nanoscale objects.

10.3. DC Current Standards

One of the possible applications of single-electron tunneling is fundamental standards of dc current for such a standard a phase lock SET oscillations or Bloch oscillations in a simple oscillator with an external RF source of a well characterized frequency f. The phase locking would provide the transfer of a certain number m of electrons per period of external RF signal and thus generate dc current which is fundamentally related to frequency as I= mef. This arrangement have limitation of coherent oscillation that are Later overcome by the use of such a stable RF source to drive devices such as single-electron turnstiles and pumps , which do not exhibit coherent oscillations in the autonomous mode.

10.4. Temperature Standards

One new avenue toward a new standard of absolute temperature can be developed by the use of 1D single-electron arrays. At low temperatures, arrays with N>>1 islands exhibit dc I-V curves generally similar to those of single-electron transistors with a clear Coulomb blockade of tunneling at low voltages (|V|<Vt) and approaching the linear asymptote V = NRI + constant at (|V|≫Vt ). If the temperature is raised above Ec/kB, thermal fluctuations smear out the Coulomb blockade, and the I-V curve is almost linear at all voltages: G =dI⁄dV ~Gn=1⁄NR The only remaining artifact of the Coulomb blockade is a small dip in the differential conductance around V=0.

10.5. Detection of Infrared Radiation

The calculations of the photo response of single-electron systems to electromagnetic radiation with frequency ~Ec ⁄h have shown that generally the response differs from that the well-known Tien-Gordon theory of photon-assisted tunneling. In fact, this is based on the assumption of independent (uncorrelated) tunneling events, while in single-electron systems the electron transfer is typically correlated. This fact implies that single-electron devices, especially 1D multi-junction array with their low co-tunneling rate, may be used for ultra-sensitive video- and heterodyne detection of high frequency electromagnetic radiation, similar to the superconductor-insulator-superconductor (SIS) junctions and arrays. The Single electron array have advantages over their SIS counterparts: Firstly

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lower shot noise and secondly convenient adjustment of the threshold voltage. This opportunity is especially promising for detection in then few-terahertz frequency region, where no background-radiation-limited detectors are yet available.

10.6. Voltage State Logics

The single-electron transistors can be used in the "voltage state" mode. In this mode, the inputgate voltage U controls the source-drain current of the transistor which is used in digital logic circuits, similarly to the usual field-effect transistors (FETs). This means that the single-electron charging effects are confined to the interior of the transistor, while externally it looks like the usual electronic device switching multi-electron currents, with binary unity/zero presented with high/low dc voltage levels (physically not quantized). This concept simplifies the circuit design which may ignore all the single-electron physics particulars. One substantial disadvantage of voltage state circuits is that neither of the transistors in each complementary pair is closed too well, so that the static leakage current in these circuits is fairly substantial, of the order of 10 -4e/RC. The corresponding static power consumption is negligible for relatively large devices operating at helium temperatures. However, at the prospective room-temperature operation this power becomes on the order of 10-7 Watt per transistor. Though apparently low, this number gives an unacceptable static power dissipation density (>10 kW/cm2) for the hypothetical circuits which would be dense enough (>1011 transistors per cm2) to present a real challenge for the prospective CMOS technology.

10.7. Charge State Logics

The problem of leakage current is solved by the use of another logic device name charge state logic in which single bits of information are presented by the presence/absence of single electrons at certain conducting islands throughout the whole circuit. In these circuits the static currents and power vanish, since there is no dc current in any static state.

10.8 Programmable Single Electron Transistor Logic

An SET having non volatile memory function is a key for the programmable SET logic. The half period phase shift makes the function of SET complimentary to the conventional SETs. As a result SETs having non-volatile memory function have the functionality of both the conventional (n-MOS like) SETs and the complementary (p-MOS like) SETs. By utilising this fact the function of SET circuit can be programmed, on the basis of function stored by the memory function. The charged around the QD of the SET namely an SET island shift the phase of coulomb oscillation, the writing/erasing operation of memory function which inject/eject charge to/from the memory node near the SET island , makes it possible to tune the phase of coulomb oscillation. If the injected charge is adequate the phase shift is half period of the coulomb oscillation.

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12. PROBLEMS:

12.1 Lithography TechniquesThe first biggest problem with all single-electron logic devices is the requirement Ec~100kBT, which in practice means sub-nanometer island size for room temperature operation. In VLSI circuits, this fabrication technology level is very difficult. Moreover, even if these islands are fabricated by any sort of nanolithography, their shape will hardly be absolutely regular. Since in such small conductors the quantum kinetic energy gives a dominant contribution to the electron addition energy (Ek >> Ec,), even small variations in island shape will lead to unpredictable and rather substantial variations in the spectrum of energy levels and hence in the device switching thresholds.12.2. Background ChargeThe second major problem with single-electron logic circuits is the infamous randomness of the background charge. A single charged impurity trapped in the insulating environment polarizes the island, creating on its surface an image charge Q0 of the order of e. This charge is effectively subtracted from the external charge Qe

12.3 CotunnelingThe essence of the effect is that the tunneling of several (N>1) electrons through different barriers at the same time is possible as a single coherent quantum-mechanical process. The rate of this process is crudely (RQ/R)N-1 times less than that for the single-electron tunneling described by Equation of the orthodox theoryG(DW) = (1/e) I(DW/e) [1 - exp{-DW/kBT}]-1 …………………….(4)If the condition expressed by equation (4) is satisfied this ratio is rather small; cotunneling can nevertheless be clearly observed within the Coulomb blockade range where orthodox tunneling is suppressed.12.4 Room Temperature OperationThe first big problem with all the known types of single-electron logic devices is the requirement Ec ~ 100 kBT, which in practice means sub-nanometer island size for room temperature operation. in such small conductors the quantum kinetic energy gives a dominant contribution to the electron addition energy even small variations in island shape will lead to unpredictable and rather substantial variations in the spectrum of energy levels and hence in the device switching thresholds.12.5 Linking SETs with the Outside EnvironmentThe individual structures patterns which function as logic circuits must be arranged into larger 2D patterns. There are two ideas. The first is to integrating SET as well as related equipments with the existed MOSFET, this is attractive because it can increase the integrating density. The second option is to give up linking by wire, instead utilizing the static electronic force between the basic clusters to form a circuit linked by clusters, which is called quantum cellular automata (QCA). The advantage of QCA is its fast information transfer velocity between cells (almost near optic velocity) via electrostatic interactions only, no wire is needed between arrays and the size of each cell can be as small as 2.5nm, this made them very suitable for high density memory and the next generation quantum computer.

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13. CONCLUSION:

Single Electronic Transistor (SET) has proved their value as tool in scientific research. Resistance of SET is determined by the electron tunneling and the capacitance depends on the size of the nanoparticle. The current starts to flow through the junction when applied voltage is just sufficient to raise the energy of electron above the coulomb blocked, this is called threshold voltage Vth and the flat zero current persist for 2Vth. Several applications of nanoscale devices in metrology, including the fundamental standards of current, resistance and temperature also seem quite promising. Another potential application is terahertz radiation detection. The situation is much more complex with digital single electronics. The concept of single electron logic suggested so far face sturdy challenges: either removing background charge or providing continuous charge transfer in nanoscale. The main problem in nanometer era is the fabrication of nanoscale devices. SET provide the potential for low-power, intelligent LSI chips, appropriate for ubiquitous application.

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APPENDIXGLOSSARY

TEM: Transmission electron microscopy (TEM) is a microscopy technique whereby a beam of electrons is transmitted through an ultra thin specimen, interacting with the specimen as it passes through. An image is formed from the interaction of the electrons transmitted through the specimen; the image is magnified and focused onto an imaging device, such as a fluorescent screen, on a layer of photographic film, or to be detected by a sensor such as a CCD camera.

Tri gate: Tri-gate or 3-D are terms used by Intel Corporation to describe the nonplanar transistor architecture planned for use in future microprocessors. These transistors employ a single gate stacked on top of two vertical gates allowing for essentially three times the surface area for electrons to travel. Intel reports that their tri-gate transistors reduce leakage and consume far less power than current transistors. This allows up to 37% higher speed, or a power consumption at under 50% of the previous type of transistors used by Intel.

Hkmg High K Metal Gate (HKMG) is one of the most significant innovations in CMOS fabrication since the inception of silicon VLSI. HKMG enables a revival in transistor scaling that had stalled with polySiON gate technology.

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Quantum computers: A quantum computer is a device for computation that makes direct use of quantum mechanical phenomena, such as superposition and entanglement, to perform operations on data. Quantum computers are different from digital computers based on transistors. Whereas digital computers require data to be encoded into binary digits (bits), quantum computation utilizes quantum properties to represent data and perform operations on these data.

Pdsoi: Partially Depleted Silicon-On-Insulator (MOSFET type)

Fdsoi: Fully Depleted Silicon-On-Insulator (MOSFET type)

Qualcomm: Designer and supplier of CDMA chipsets, system software, network base stations, handsets, modems, kid trackers, camera phones, MP3 players, game players

Nvidia: The world leader in visual computing technologies and the inventor of the GPU, which generates interactive graphics on desktop computers,

Soc(system on chip): an integrated circuit (IC) that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate. A typical application is in the area of embedded systems.

2DEG: A two-dimensional electron gas (2DEG) is a gas of electrons free to move in two dimensions, but tightly confined in the third. This tight confinement leads to quantized energy levels for motion in that direction, which can then be ignored for most problems. Thus the electrons appear to be a 2D sheet embedded in a 3D world. The analogous construct of holes is called a two-dimensional hole gas (2DHG), and such systems have many useful and interesting properties.

Quantum chaos: a branch of physics which studies how chaotic classical dynamical systems can be described in terms of quantum theory.

Matrix theory: Matrix theory is a branch of mathematics which is focused on study of matrices. Initially, it was a sub-branch of linear algebra, but soon it grew to cover subjects related to graph theory, algebra, combinatorics and statistics as well.

Hertee fock theory: Hartree Fock theory is one the simplest approximate theories for solving the many-body Hamiltonian. It is based on a simple approximation to the true many-body wavefunction: that the wavefunction is given by a single Slater determinant of spin-orbitals

where the variables include the coordinates of space and spin.

E beam lithography: Electron beam lithography (often abbreviated as e-beam lithography) is the practice of emitting a beam of electrons in a patterned fashion across a surface covered with a film (called the resist)

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Quantum dot: a portion of matter (e.g., semiconductor) whose excitons are confined in all three spatial dimensions. Consequently, such materials have electronic properties intermediate between those of bulk semiconductors and those of discrete molecules

STM: A scanning tunneling microscope (STM) is an instrument for imaging surfaces at the atomic level.

Coulomb blockade: n physics, a Coulomb blockade (abbreviated CB), named after Charles-Augustin de Coulomb's electrical force, is the increased resistance at small bias voltages of an electronic device comprising at least one low-capacitance tunnel junction. Because of the CB, the resistances of devices are not constant at low bias voltages, but increase to infinity for zero bias (i.e. no current flows).

Kondo effect: It describes the scattering of conduction electrons in a metal due to magnetic impurities. It is a measure of how electrical resistivity changes with temperature.

QCA: a proposed physical implementation of "classical" cellular automata by exploiting quantum mechanical phenomena.

Cotunneling: The simultaneous tunneling of two or more electrons

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MEDIA QUOTES

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BIBLIOGRAPHY1) E. F. Schubert “Scaling of MOSFETs” Rensselaer Polytechnic Institute, 20032) Tsu-Jae King “FinFETs for Nanoscale CMOS Digital Integrated Circuits” 0-7803-9254-X/05/$20.00 ©2005 IEEE.3) Robert L.Boylestad and Louis Nashelsky “Electronics Devices and Circuit Theory”Pg.131-132, 8th Edition.4) http://ecee.colorado.edu/~bart/book/book/chapter7/ch7_7.htm5) Adel S. Sedra “Microelectronic Circuits” Pg-321, Fifth Edition.6) Q Zhang, Journal of “FinFET”, EE 666, 20057) A. Burenkov, J. Lorenz “On the Role of Corner Effect in FinFET”. Fraunhofer Institute Integrierte Systeme and Bauelementetechnologie.8) PRATEEK MISHRA, ANISH MUTTREJA, and NIRAJ K. JHA “Low-Power FinFET Circuit Synthesis Using Multiple Supply and Threshold Voltages” Vol. 5, No.2,Article 7, Publication date: July 2009.9) Hiroshi IWAI” Future of Nano-CMOS Technology” Tokyo Institute of Technology,Japan, June 2007.10) ITRS “Modelling and Simulation” 2007.11) Hesham F. A. Hamed, Savas Kaya, Janusz A. Starzyk ” Use of nano-scale double gate MOSFETs in low-power tunable current mode analog circuits” Springer Science+Business Media, LLC 200812) Daniel Minoli “Nanotechnology applications to telecommunications and networking” A john wiley & sons inc., Publications.13) Dhruva Ghai, Saraj P. Mohanty, Elias Kougianos “A process and Supply Variation Tolerant Nano-CMOS Low Voltage, High Speed, A/D Converter for System-on-Chip” GLSVLSI, May 2008, Orlando, Florida, USA.14) M. A. Kastner, “The single electron transistor and artificial atoms”, Ann. Phy. (Leipzig), vol. 9,pp. 885-895, 2000.15) S. Bednarek, B. Szafran, and J. Adamowski, “Solution of the Poisson Schrodinger problem for asingle-electron transistor”, Phys. Rev. B, Vol. 61, pp. 4461-4464, 2000.16) Songphol Kanjanachuchai and Somsak Panyakeow, “Beyond CMOS: Single-ElectronTransistors”, IEEE International Conference on Industrial Technology, Bangkok, Thailand,2002.17) www.nanowerk.com/news/newsid=6258.php

18) www.webopedia.com/TERM/S/single_electron_transistor.html

19) luciano.stanford.edu/~shimbo/set.html

20) link.aps.org › Journals › Rev. Mod. Phys. › Volume 64 › Issue 3

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