Silicon Wafers

Silicon WafersProduction

Specifications

Si and SiO2 Etching

Our Portfolio

2012

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Dear Reader,

Two years ago, we expanded our portfolio of chemicals for micro-structuringto include silicon wafers. A steadily growing network of wafer manufacturersand service providers allows us to fulfil special wafer requests as well as tooffer big volume prices even to our customers with small and mediumdemand.

Therefore, we decided this was a perfect opportunity to create this brochurecontaining technical information related to silicon wafers.

With the help of illustrations we would like to show the way from quartz sandto finished and structured silicon wafers, how wafers are specified and theassortment we can offer.

Wishing you much success,

Your MicroChemicals Team

Content

From Quartz to High-Purity Silicon 7

Silicon Crystal Growth Techniques 8

From Single Crystals to Polished Wafers 11

Further Wafer Process Steps 14

Silicon Wafer Specifications 17

Wet Etching of Si and SiO2 20

Our Silicon Wafers 25

MicroChemicals® – Silicon Wafers

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From Quartz to High-Purity Silicon

Silicon in the Universe and on EarthHydrogen and heliumdominate the visible mat-ter of the universe, themass fraction of silicon isless than 0.1 %. This ele-ment mainly arises fromthe fusion of two oxygennuclei (2 16O 28 Si +4He) at temperatures > 109

K inside stars with morethan eight solar masses.

The entire planet Earthcontains approx. 17 % sili-con, the third most abun-dant element after ironand oxygen, closely fol-lowed by magnesium.

In the earth’s iron-basedcore, silicon (≈ 7 mass %)is the second most abundant element.

The earth’s approx. 40 km thick crust contains silicon (in the form of silicates andSiO2) with a mass fraction of 28 % as the second most abundant element after oxy-gen. Quartz = crystalline SiO2 is the raw material for silicon production.

Metallurgical-Grade Silicon ProductionQuartz sand is reduced with carbon in an elec-tric arc furnace at temperatures > 1900°C tometallurgical grade silicon (> 98 % pure). Themajor part of the world production (2008:approx. 6 million tons) is used for manufactur-ing alloys with aluminium and steel, and as rawmaterial for polysiloxane production.

In 2010, Si wafer production consumed approx.200 kilotons purified silicon. Approx. 90 % ofthis volume was used for mono- and polycrys-talline solar cells, the remaining 10 % (corre-sponding to a wafer area of ≈ 5 km2) went intothe semiconductor industry.

Purification of SiliconThe impurity concentration in metallurgical-grade silicon is many orders of magnitudetoo high for an application in photovoltaics and microclectronics, and therefore has tobe purified.

For this reason, silicon intended for wafer production is converted into trichlorosilanegas (HSiCl3) at 300°C using hydrochloric acid via

Si + 3 HCl HSiCl3 + H2

which already removes many impurities which don’t form volatile chlorine compoundsat the applied process temperature.

Trichlorosilane (boiling point 32°C) mixed with other gaseous chlorine compounds un-dergoes multiple distillation thereby improving the purity up to 99,9999999 %. („9N“)and is subsequently thermally decomposed to polycrystalline silicon.

SiO2 + 2 C Si + 2 CO

Reduction of SiO2 with carbon to metal-lurgical grade silicon in an electric arcfurnace

< 0.1 %

28 %

17 %

The abundance (in mass %) of silicon in the universe, theplanet Earth, the earth’s core and the earth crust.

7 %


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The polycrystalline silicon formation is per-formed in the so-called Siemens-Process (fig.left): The purified trichlorosilane mixed in hy-drogen is thermally decomposed on the sur-face of a heated (approx. 1100°C) silicon rodvia

HSiCl3 + H2 Si + 3 HCl

to polycrystalline silicon and HCl, which corre-sponds to the reverse reaction of thetrichlorosilane formation.

This “electronic-grade“ (purity concentration <1014 cm-3) poly-silicon is the raw material forsilicon single crystals which are grown by twodifferent processes as described in the follow-ing sections.

Growth Techniques for Monocrystalline Silicon Ingots

Czochralski-TechniqueBasics

The Czochralski-technique is a method to pull a monocrystal with the same crystallo-graphic orientation of a small monocrystalline seed crystal out of melted silicon.

First, electronic-grade polysilicon nuggets (e. g. from the Siemens-process) optionallytogether with dopants are melted in a quartz crucible at a temperature > 1400°C inan inert gas atmosphere (e. g. argon). The quartz crucible sits inside a graphite con-tainer which homogeneously transfers the heat from the surrounding heater to thequartz crucible.

The silicon melt temperature is kept constant roughly above the silicon melting point.A monocrystalline silicon seed crystal with the desired crystal orientation (e. g.<100>, <110> or <111>) is immersed into the melt and acts as a starting point forthe crystal formation supported by the heat transfer from the melt to the alreadygrown crystal.

The seed crystal is slowly (few cm/hour) pulled out of the melt, where the pull speeddetermines the crystal diameter. During crystal growth, the crystal as well as the cru-cible counter-rotate in order to improve the homogeneity of the crystal and its dopantconcentration.

Before the crystal growth is finished, a continuous increase of the pull speed reducesthe crystal diameter towards zero. This helps prevent thermal stress in the ingotwhich could happen by an abrupt lifting out of the melt and could destroy the crystal.

Advantages and Disadvantages

The Czochralski-technique allows big crystal diameters (state of the art: 18 inch = 46cm) and – compared to the float-zone technique described in the following section –lower production cost per wafer.

One disadvantage of the Czochralski-technique is impurities such as oxygen (typ.

Thermal conversion of trichlorosilane to polycrystal-line silicon on the surface of a heated silicon rod in theso-called Siemens-process.


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The different process steps of Czochralski crystal growth: Melting of polysilicon with dopants, im-mersion of the seed crystal, crystal growth.

1018 cm-3) and carbon (typ. 1017 cm-3) from the quartz and graphite crucible whichlower the minority carrier diffusion length in the final silicon wafer.

Another disadvantage is a comparably low homogeneity of the axial and radial do-pant concentration in the crystal caused by oscillations in the melt during crystalgrowth. This makes it difficult to attain high-ohmic CZ-wafers with a resistivity ex-ceeding ≈ 100 Ohm cm). A magnetic field (“Magnetic Czochralski”, MCZ) can retardthese oscillations and improve the dopant homogeneity in the ingot.



Schema of the float-zone technique: A seedcrystal is attached to the end of apolysilicon ingot (left) which is the startingpoint for the crystallization of the entire in-got (right).

Float-Zone TechniqueA monocrystalline silicon seed crystal is brought into contact with one end of a poly-crystalline silicon ingot. Starting from here, an RF coil melts a small region of thepolysilicon which, after cooling down, forms monocrystalline silicon with the crystallo-graphic orientation of the seed crystal (e. g. <100>, <110> or <111>).

The RF coil and the melted zone move along the entire ingot. Since most impuritiesare less soluble in crystal than in the melted silicon, the molten zone carries the im-purities away with it. The impurities concentrate near the end of the crystal where fi-nally they can simply be cut away. The procedure can be repeated one or more timesin order to further reduce the remaining impurity concentration.

Doping is realized during crystal growth by adding dopant gases such as phosphine(PH3), arsine (AsH3) or diborane (B2H6) to the inertgas atmosphere.

Advantages and Disadvantages

The main advantage of the float-zonetechnique is the very low impurityconcentration in the silicon crystal. Inparticular the oxygen and carbon con-centration are much lower as com-pared to CZ silicon, since the meltdoes not come into contact with aquartz crucible, and no hot graphitecontainer is used.

Additionally, the dopant concentrationin the final crystal is rather homoge-neous and manageable which allowsvery high-ohmic (1 - 10 KOhm cm)wafers as well as wafers with a nar-row specified electrical resistivity.

However, FZ silicon is more expensivethan CZ silicon, and the crystal diam-eter is limited to eight inches (state ofthe art).


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n-type<111>

p-type<100>

p-type<111>

n-type<100>

Si cylinder

Inside hole saw

From Single Crystals to Polished Wafers

LappingThe ingots grown with the Czochralski or float-zone technique are cut into shorterworkable cylinders with e. g. a band saw and ground to a certain diameter.

An orientation flatis added to indi-cate the crystalo r i e n t a t i o n(schema right),while wafers withan 8 inch diam-eter and aboveuse a single notchto convey wafer orientation, independent from the doping type.

DicingTwo common techniques are applied for wafer dicing: Inside hole saw and wire saw,both explained in the following sections.

Inside Hole Saw (Annular Saw)

The wafers are sawed inside a circular bladewhose cutting edge is filled with diamond splin-ters (schema right).

After sawing, the wafer surfaces are relativelyflat and smooth, so the subsequent lapping ofthe surfaces takes less time and effort.

However, only one wafer per annular saw canbe cut at the same time, so this technique has acomparably low throughput which makes thewafers more expensive compared to wafers cutby a wire saw.

Wire Saw

In order to increase throughput, wire saws withmany parallel wires are used which cut manywafers at once.

8 inch



Feed reel

Wire moving direction

Wire guides

Silicon ingot

Take-up reel

Diamond-coated wire

Ingot and wiresapprox. drawn to

scale

Bottom: Schema of the wire saw technique. The two detailed enlargements above show the propor-tions of the wire, the gaps between the wire lines, and the ingot approx. to scale.

A long (up to 100 km) high-grade steel wire with a diameter of ≈ 100 - 200 µm iswrapped around rotating rollers with hundreds of equidistant grooves at a speed oftypically 10 m/s. The mounted silicon cylinder is drained into the wire grid and thuscut into single wafers.

The wire is either coated with diamond splinters or wetted with a suspension of abra-sive particles such as diamonds or silicon carbide grains, and a carrier (glycol or oil).

The main advantage of this sawing method is that hundreds of wafers can be cut at atime with one wire. However, the attained wafer surface is less smooth and morebumpy as compared to wafers cut by an annular saw, so the subsequent lappingtakes more time.

LappingAfter dicing, the wafers are lapped on both sides in order to i) remove the surfacesilicon which has been cracked or otherwise damaged by the slicing process (e. g.grooves by the wire saw) and ii) thinned to the desired wafer thickness.


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Several wafers at a time are lapped in between two counter-rotating pads by a slurryconsisting of e. g. Al2O3 or SiC abrasive grains with a defined size distribution.

EtchingWafer dicing and lapping degrade the silicon surface crystal structure, so subse-quently the wafers are etched in either KOH- or HNO3/HF based etchants in order toremove the damaged surface.

PolishingAfter etching, both wafer surfaces appear like the rear side of finished single-sidepolished wafer. In order to attain the super-flat, mirrored surface with a remainingroughness on atomic scale, the wafers have to be polished.

Wafer polishing is a multi-step process using an ultra-fine slurry with 10 - 100 nmsized grains consisting of e. g. Al2O3, SiO2 or CeO2 which, combined with pressure,erode and smoothen the wafer surface between the two rotating pads similar to lap-ping.

CleaningFinally, the wafers are cleaned with ultra-pure chemicals in order to remove the pol-ishing agents thereby making them residual-free.

Schema of a WaferLapping Machine



The attained film thicknesses of wet and dry (dashed) SiO2as a function of the growth time and temperature.

Schema of an oxidationfurnace for Si wafers

Heating coils

Wafers

O2 a

nd H

2O

inle

t

Quartz tube

Further Process Steps

Thermal Oxidation of SiliconFields of Application

The electronic (resistivity 1014 ... 1016 Ohm.cm, breakthrough field 106 ... 107 V/cm,barrier for electrons and holes from crystalline Si > 3 eV), mechanical (melting pointapprox. 1700°C) and optical (transparent in the visible as well as near infrared andultraviolet spectral range) properties of SiO2 make it a suitable material for the di-electric film in transistors, capacitors (DRAM) or flash-memories; and as a hard maskfor diffusion, implantation, wet or dry chemical etching; and generally as an isolatorbetween integrated devices, or as an antireflection layer on e. g. solar cells.

Required SiO2 film thicknesses range from a few nm (gate-oxide of state-of-the-artCMOS transistors) up to sev-eral µm for electrical insula-tion. Compared to sputteredor CVD SiO2, thermal SiO2 re-veals a better and more re-producible electrical insula-tion.

Oxidation Technique

Compared to (crystalline)quartz, native (= few nmgrown at room temperaturein air) and thermal (growthtemperature 800 - 1200°C)silicon dioxide (schema of anoxidation furnace right) isamorphous (= without long-term atomic lattice order).The silicon in native or ther-mally grown SiO2 evolvesfrom the Si substrate, whichis partially consumed duringSiO2 growth: 100 nm SiO2 re-quires approx. 46 nm Si,while the wafer thickness si-multaneously increases byapprox. 54 nm.

One has to distinguish be-tween dry oxide (Si + O2 SiO2), and – with H2O as pro-cess gas – wet oxide (Si + 2H2O SiO2 + 2 H2).

At the same process param-eters, due to the highergrowth rate, wet oxide re-veals a higher porosity andHF etch rate.

0.01

0.10

1.00

10.00

0 120 240 360 480 600 720 840 960

Time (minutes)

SiO

2-t

hic

kn

ess (

µm

)_

800°C900°C1000°C1100°C800°C900°C1000°C1100°C

wet

dry


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Density(g/cm3)

Refractiveindex

@ 400 - 800 nm

BOE 7:1 etch rate12.5 % HF, 21°C

(nm/min)

KOH etch rate44 %, 80°C(nm/min)

Dielectricstrength

(kV/cm @ 20°C)

SiO2 2.2 1.4 - 1.5 50 - 100 5 - 10 250 - 400

SiNx 2.5 - 3.1 1.9 - 2.1 10 - 100 < 1 > 1000

Oxidation Rate and Attainable SiO2 Film Thickness

At the beginning of thermal SiO2 growth, the chemical reactions on the surface/inter-face limit the film thickness which increases linearly with time.

With the SiO2 thickness increasing, the more and more dominating oxygen diffusionthrough the already-grown film towards the Si/SiO2-interface limits the growth rate.The SiO2 thickness now increases with the square-root of growth time.

Besides the process gas composition (O2/H2O), their partial pressure as well as thesubstrate temperature (activation energy of oxygen diffusion and chemical reactionat the Si/SiO2-interface), the SiO2 growth rate also depends on the Si substrate crys-tal orientation, mechanical strain of the substrate (e. g. in case of already processeddevice layers), as well as on substrate doping (e. g. faster oxide growth on phospho-rous doped silicon).

Silicon Nitride CoatingIn the field of tool-making, stoichiometric trisilicon tetranitride (Si3N4) with its veryhigh mechanical and thermal stability is used for tools such as roller bearings usedunder harsh conditions.

For semiconductor devices, the chemical and electrical properties of amorphous hy-drogenated silicon nitride (SiNx) make this material well-suited for different applica-tions, such as for

passivation or insulating layers in integrated circuits

masking or etch stop material in wet and plasma etching processes due to its highchemical stability

masking material in silicon oxidation processes due to the very low oxygen diffu-sion coefficient in SiNx

anti-reflective coating in photovoltaics due to its matched refractive index

SiNx layers realized by the chemical vapour deposition (CVD) technique from SiH4and NH3 typically – depending on the deposition temperature and gas composition –contain 5 - 20 atom% hydrogen which saturates dangling bonds and thus chemicallyand mechanically stabilized the SiNx lattice.

SiNx can be etched via photoresist masks either with buffered or unbuffered HF or(selectively to SiO2) with concentrated phosphoric acid. The HF etch rate of SiNx de-pends on the SiNx deposition temperature and its refractive index. A hydrogen-richSiNx film deposited at 100°C with a refractive index of n = 1.9 shows an etch rate ofseveral 100 nm/min in buffered HF (12.5 % HF). The etch rate drops to less than 10nm/min for SiNx films deposited at 400°C with a refractive index of n = 2.

Properties of Amorphous SiO2 and SiNx FilmsThe table below lists “typical” values for selected amorphous SiO2 and SiNx film prop-erties. Dependant on the deposition conditions, measured values can deviate fromthese values.



Si substrate

O-implantation

Si + O

Thermal annealing

Si substrate

SiO2

Silicon EpitaxyMechanism

In wafer fabrication, silicon epitaxy refers to the growth of a thin layer of single-crys-talline silicon onto a single-crystalline silicon substrate, usually via chemical vapourdeposition.

Commonly used process gases are silicon tetrachloride (SiCl4), trichlorosilane(SiHCl3), dichlorosilane (SiH2Cl2) or silane (SiH4) which are thermally decomposed tosilicon on the surface of wafers heated up to typically 600 - 1000°C. The Si atoms re-leased from the gaseous compounds form crystalline silicon monolayer by monol-ayer.

Fields of Application

The addition of dopants such as phosphine, arsine or diborane to the process gas al-lows the realization of certain doping profiles in the epitaxial film which is required fore. g. box-shaped doped structures or a low-doped layer on top of highly doped siliconwhich can not be realized by diffusion.

Already realized films such as areas doped via ion implantation, or microelectronicdevices can be buried under an epitaxial layer.

Since the oxygen and carbon concentrations in epitaxial layers are very low, the(electronic) quality of this film is better than for the silicon substrate underneath,which can be important for integrated devices.

SOI-WafersBasics

„Silicon on Insulator“-wafers are wafers with a crystalline silicon film or devices litho-graphically made from this film located on an electrical insulator such as SiO2. Thereare two main fields of application for SOI wafers:

Fields of Application

Transistors located on an electrically insulating film have a lower capacity and smallerelectrical current leakage as compared to transistors directly sitting on the siliconsubstrate. Therefore, the transistors can be packed more densely, their energy con-sumption is lower, and the switching speed increased which allows higher clock ratesand lower power demand.

In micro-optics, the insulating film allows integrated optical components includingwaveguides in which µm-waves can be guided in SiO2 (refractive index = 1.5) em-bedded in silicon (refractive index = 3.5) by total reflection.

Realization

One technique for producing SOI wafers is the SIMOXTM-process (Separation by IMplantation of OXygen, seeschema right) starting with oxygen implantation in siliconwafers, which allows an accurate control of the depth pro-file of the implanted O-atoms.

Subsequently, a high temperature step forms the SiO2layer where the O-atoms have been captured in the siliconlattice, and thermally anneals the crystal structure of thesilicon beyond distorted by the implantation process.

The Smart-CutTM-technique (top of next page) combineshydrogen ion implantation and wafer bonding. Hydrogenions are implanted in an oxidized silicon wafer. This waferis bonded with another wafer without SiO2. A baking step(> 500°C) splits the oxidized wafer along the depth of theimplanted hydrogen atoms induced by mechanical stress.


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SiO2

Si wafer

H-implantation

Si wafer

Si + H

SiO2

Waferbonding

Si substrate

Si + H

SiO2

Si wafer

Thermallyinducedsplitting

Silicon Wafer Specifications

Diameter, Orientation and SurfaceDiameter

The wafer diameter is specified in mm or – most commonly – an integer number ofinches (one inch = 25.4 mm) and the diameter tolerance (typ. < 1 mm).

Orientation

The wafer orientation denotes the crystallographic plane parallel to the wafer surface.The tilt angle defines the maximum extent to which the wafer surface and crystallo-graphic plane are inclined to each other.

Surface

Usually both sides of silicon wafers are at least lapped and etched. Surface polishingis performed either on one (SSP = Single-Side Polished) or both sides (DSP = Dou-ble-Side Polished).

Doping and ResistivityThe dopant atoms incorporated during silicon crystal growth increase the electricalconductivity via an increase in the free electron (in the case of phosphor or arsenicdopants) or hole (boron as dopant) concentration by up to many orders of magnitudebeyond the value of undoped silicon.

Below a doping concentration of approx. c = 1016 cm-3 the resistivity drops recipro-cally with c, towards a higher doping concentration the free carrier mobility dropswhich flattens the R(c) dependency.

Since the dopingconcentration is notperfectly homoge-neous but axiallyand radially variesin the silicon crystal,the wafers arespecified to a cer-tain range (for CZwafers typically oneorder of magnitude,such as 1 - 10 ohmcm, for FZ wafersoften more narrow)in the electrical re-sistivity.

The dependency of the electrical resistivity from the doping concen-tration of boron and phosphor / arsenic in crystalline silicon

0.001

0.01

0.1

1

10

100

1000

10000

100000

1.E+12 1.E+13 1.E+14 1.E+15 1.E+16 1.E+17 1.E+18 1.E+19

Dopant concentration (1/cm3)

El.

re

sist

ivit

y (

Oh

m c

m)_ Boron

Phosphor / Arsenic



[001]

[100]

[110]

[010]

[111]

{111}

{100}anisotropic

etching

{111}

[100] [110]

{110}

The crystal structure of silicon with the high stability of the{111}-surfaces allows the realisation of pyramids and

trenches via anisotropically etching of different orientatedsubstrates.


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d

Different median surfacesof bowed wafers

Referenceplane

Wafer surface

Wafer

d5

d6

d3

d4

d1

d2

Thickness, Thickness Variation and SurfaceThe thickness usually measured in the centre of a wafer gives no information onhow strong the shape of the wafer deviates from an ideal (very flat) cylinder.

TTV

The Total Thickness Variati-on TTV specifies the differ-ence d1 - d2 (left) betweenthe minimum and maximumthickness of a wafer meas-ured at typically five differ-ent locations.

Bow

The bow is defined by d3 +d4 (left) corresponding tothe maximum deviation ofthe median surface to a ref-erence plane.

Warp

The value d5 + d6 (left) cor-responds to the deviation ofthe median surface of thewafer from a referenceplane which is already cor-rected by the bow of the en-tire wafer.

Micro-Roughness

The Root Mean Square (“RMS“) denotesthe standard height deviation of a sur-face scan on a wafer.

The RMS values are typically < 1 nmwhich corresponds to a smoothness onatomic scale!



Wet Etching of Silicon and SiO2

Anisotropic Silicon EtchingStrong alkaline substances (pH > 12) such as aqueous KOH, NaOH or TMAH solutions,etch silicon via Si + 4 OH- Si(OH)4 + 4 e-.

Since the bonding energy of Si atoms is different for each crystal plane and KOH/TMAH Si etching is not diffusion- but etch rate limited, the Si etching is highly aniso-tropic: While the {100}- and {110}-crystal planes are being etched, the stable {111}planes act as an etch stop allowing interesting applications (illustrated on page 18):

(111)-Wafers are almost never attacked by the etch.

(100)-Wafers form square-based pyramids with {111} surfaces. These pyramidsare realised on c-Si solar cells for the purpose of reflection minimization.

(110)-Wafers form perpendicular trenches with {111} sidewalls, used as e. g. mi-cro-channels in micromechanics and microfluidics.

The degree of anisotropy (= etch rate selectivity between different crystal planes),the etch rates and etching homogeneity (plots and figures on pages 20 - 24) dependon the etching temperature, atomic defects in the silicon crystal, intrinsic impurities ofthe Si crystal, impurities (metal ions) by the etchant and the concentration of Si-at-oms already etched.

The doping concentration of the Si to be etched also has a strong impact on the etch-ing: During etching, Boron doped Si forms borosilicate glass on the surface whichacts as an etch stop if the boron doping concentration exceeds 1019 cm-3.

We supply 44 % KOH as well as 25 % TMAH in VLSI-quality in 2.5 L sales units.

The following two pages show plots depicting the temperature- and concentration-de-pendant etch rates of (100)- and (110)-Si in KOH and TMAH, as well as the selectivityto SiO2 which is commonly used as etch mask.

(100)/(111)-Selectivity

13

48

41

41 37

50

159 67 60

290

50

70

90

110

130

150

0 10 20 30 40 50

KOH- or TMAH-Concentration (%)

Te

mp

era

ture

(°C

)

KOH

TMAH

The circular surfaces (the inserted values) refer to the (100) : (111) etch rate ratio in TMAH (yellow) and KOH (blue).

The (100) : (111) etch rate ratio of crystalline Silicon in TMAH (gold circular areas) and KOH(turquoise) as a function of the concentration and temperature

(100) : (111) - Selectivity


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The etch rate of (100)- and (110)-Silicon surfaces in KOH as a function of the KOH concentrationand temperature. The alkaline etching of Si requires OH--ions as well as free water molecules.Thus the etch rate (as well as the surface roughness) drops towards higher concentrations.

The (100)-Si : SiO2 etch rate selectivity in KOH as a function of the KOH-concentration and tem-perature.

0.01

0.1

1

10

20 30 40 50 60

KOH-Concentration (%)

Etc

h R

ate

in

µm

/m

in__

40°C (100)

60°C (100)

80°C (100)

100°C (100)

40°C (110)

60°C (110)

80°C (110)

100°C (110)

0.01

0.1

1

10

0 10 20 30 40

TMAH-Concentration (%)

Etc

h R

ate

in

µm

/m

in__

60°C (100)

70°C (100)

80°C (100)

90°C (100)



0

250

500

750

1000

1250

1500

1750

2000

20 25 30 35 40 45 50

KOH-Concentration (%)

(10

0)-

Si

/ S

iO 2

Etc

h R

ate

Ra

tio

20°C

40°C

60°C

80°C

100°C

Etch Temperature:

3000

4000

5000

6000

7000

8000

9000

10000

5 10 15 20 25 30 35 40

TMAH-Concentration (%)

(10

0)-

Si

/ S

iO 2

Etc

h R

ate

Ra

tio

70°C

80°C

90°C

Etch Temperature:

The (100)-Si : SiO2 etch rate selectivity in KOH as a function of the KOH-concentration and tem-perature.

The (100)-Si : SiO2 etch rate selectivity in TMAH as a function of the TMAH-concentration andtemperature. The Si and SiO2 etch rates in TMAH have their maxima at different temperatures, sotheir ratio shows an S-shape.


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Isotropic Etching of Silicon with HF/HNO3

Etch Mechanism

The following chemical reactions summarize the basic etch mechanism for isotropicsilicon etching (steps 1 - 4) and SiO2 (only step 4) using a HF/HNO3 etching mixture:

(1) NO2 formation (HNO2 always in traces in HNO3): HNO2 + HNO3 2 NO2 + H2O(2) Oxidation of silicon by NO2: 2 NO2 + Si Si2+ + 2 NO2

-

(3) Formation of SiO2: Si2+ + 2 (OH)- SiO2 + H2(4) Etching of SiO2: SiO2 + 6 HF H2SiF6 + 2 H2O

In conclusion,HNO3 oxidises Si,and HF etches theSiO2 formed.

Silicon Etch Rate

The plot rightshows the etchrate of crystallineSi for different HF :HNO3 mixtures.

The etch ratedrops towards zerowhen either the HFor HNO3 concentra-tion becomes verylow, since in pureHF no SiO2 formswhich can beetched in HF, andHNO3 only oxidizesthe Si withoutetching it.

An accurate con-trol of the etchrate requires atemperature rangewithin ± 0.5°C. Adilution with acetic acid improves the wet-ting of the hydrophobic Si-surface and thusincreases and homogenizes the etch rate.

Doped (n- and p-type) silicon as well asphosphorus-doped SiO2 etches faster thanundoped Si or SiO2.

Si : SiO2 Etch Selectivity

As the etch triangle (Fig. right) shows, highHF : HNO3 ratios promote rate-limited etch-ing (strong temperature dependency of theetch rate) of Si via the oxidation (1) - (3),while low HF : HNO3 ratios promote diffu-sion-limited etching (lower temperature de-pendency of the etch rate) via step (4).HNO3-free HF etches do not attack Si.

The SiO2 etch rate is determined by the HF-concentration, since the oxidation (1) - (3)does not apply.

[H2O]+[CH3COOH] [HNO3]

[HF]

Si etch

rate in

creases

Increasing etchrate tempera-ture depend-ency

I n c r e a s -ing selec-tivity Si/SiO2

The etch triangle of silicon depicts the de-pendency of the etch rate and selectivity be-tween Si and SiO2 on the etch composition.

1 3 5 7 9 1216

2229

3850

6688

59

1629

10

100

1000

10000

100000

1000000

Etc

h R

ate

(n

m/

min

)

[HF (49%)]

[HNO3 (70%)]



Compared to thermal oxide, deposited (e. g. CVD) SiO2 has a higher etch rate due toits porosity; wet oxide a slightly higher etch rate than dry (thermal) oxide for thesame reason.

Isotropic Etching of SiO2 with HF or BHFHydrofluoric acid is the one and only chemical able to isotropically etch SiO2. Due tothe high toxicity of concentrated HF, one has to consider the maximum concentrationthat is really required. 1 % HF is sufficient for removing native SiO2 in a so-called“HF-Dip”, and even 200 - 300 nm oxide can be etched in 10 % HF or buffered HF in areasonable amount of time. We supply 1 %, 10 %, 50 % HF and buffered HF (BOE 7 :1 = AF 87.5 - 12.5) in VLSI-quality.

Unbuffered and Buffered Hydrofluoric AcidEtching of Si and SiO2 with HF consumes F--ions via the reaction

SiO2 + 4 HF SiF4 + 2 H2O

HF buffered with ammonia fluoride (NH4F + H2O + HF = ‘BHF’) maintains the free F--ion concentration via NH4F HF + NH3, allowing

a constant and controllable etch rate as well as spatial homogeneous etchingan increase in the etch rate (factor 1.5 - 5.0) by highly reactive HF2

--ions andan increase of the pH-value ( minor resist underetching and resist lifting.

Despite the increased reactivity, strongly buffered hydrofluoric acid has a pH-value ofclose to seven and therefore may not be detected by chemical indicators!

10

100

1000

3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

NH4OH : HF - Ratio

Etc

h R

ate

in

nm

/m

in__

25°C

30°C

35°C

40°C

45°C

55°C

Etch Temperature:

Our BOE 7 : 1

The SiO2 etch rate in buffered HF (BOE) as a function of the ammonia : HF concentration


phone: +49 (0)731/36080-409 fax: +49 (0)731/36080-908-25-

Our Silicon Wafers

Available Specifications

Growth Method: Czochralski and float-zone

Diameter: 2, 3, 4, 5, 6 and 8 inch

Thickness: 280 µm (2“), 380 µm (3“), 525 µm (4“), 675 µm (6“) etc., otherthicknesses on request

Orientation: (100) and (111), (110) on request

Doping: Boron, phosphor and arsenic

Surface: Single- and double-side polished

Quality: “Prime”, “Test” and “Dummy”

Services

Oxidation: Dry and wet, up to 3 µm

Silicon Nitride

Metallization: Material and thickness on request

Silicon Epitaxy

Wafer cutting: On request

Sales Units and Lead Time

We supply our wafers in units of 25 (one carrier) or single wafers in single-waferboxes. For wafers with special specifications, a minimum order quantity of 25, 50 or100 wafers is possible.

A daily revised list of stock wafers which can be shipped in few working days can befound here:

http://www.microchemicals.eu/various/wafer_list.html

For wafers we produce according your requirements, the typical lead time is 3 - 4weeks.

Your Contact Persons

Dr.-Ing. Christian Koch

Tel.: +49 (0) 731 36080-409Mobile: +49 (0) 178 7825198Fax: +49 (0) 731 36080-908E-mail: [email protected]

Dr.-Ing. Titus J. Rinke

Tel.: +49 (0) 731 36080-409Mobile: +49 (0) 177 3332453Fax: +49 (0) 731 36080-908E-mail: [email protected]

Imprint

AddressMicroChemicals GmbHNicolaus-Otto-Strasse 39Ulm, Germany 89079Tel.: +49 (0) 731/36080 409Fax.: +49 (0) 731/36080 908E-mail: [email protected]

Managing DirectorsDr.-Ing. Titus J. Rinke, Dr.-Ing. Christian Koch

Place of Business VAT-IDUlm HRB 4271 DE813168639

Bank AccountSparkasse: Acct. No. 21090628, Code: 63050000(Germany) SWIFT Code (= BIC): SOLADES1ULM

IBAN: DE19630500000021090628

Ulmer Volksbank: Acct. No. 6069002, Code: 63090100(Germany) SWIFT Code (=BIC): ULMVDE66

IBAN: DE59630901000006069002

Switzerland: BS Bank Schaffhausen, SchleitheimBC 6858, account: 164.008.476.00

AZ and the AZ logo are registered trademarks of AZ Electronic Materials(Germany) GmbH.

Silicon Wafers

Documents

Transcript of Silicon Wafers