(Silicon Carbide Inverter)
Transcript of (Silicon Carbide Inverter)
SiCverter (Silicon Carbide Inverter)
ECE 445 Design Document
Chaitanya Sindagi, Conner Bone,
and Joshua Powell
Team 4
TA: Dean Biskup
10/1/2020
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1 Introduction
1.1 Objective
This project is being done in collaboration and as a part of the Illini Formula Electric
team which builds an electric race car every year. This year, the race car being built is
using 4 permanent magnet (PM) motors, one for each wheel of the car. These motors
are driven by 3-phase AC power, so the vehicle’s 600V battery pack’s DC output must
be converted to 3-phase AC by a motor controller/inverter. One inverter for each motor.
Moreover, to achieve the maximum performance possible, each inverter must be
capable of outputting 35kW and 62Arms to each of the motors.
The problem is that all commercially available motor controllers capable of driving 35kW
motors at 600V are too expensive and/or too heavy to be useful in our electric race car.
Therefore, the objective of this project is to create a motor controller that meets the
specifications required for the car while being lightweight, efficient, compact, and
affordable. To limit the scope of the project, a single inverter for a single motor will be
developed over the course of the semester and tested at low voltages and currents to
validate its functionality.
Our solution involves a design that will use high efficiency silicon carbide MOSFETs,
high energy density film capacitors and a high-performance microcontroller from TI
designed to function well in motor drive applications. It will be designed as a standard
voltage source inverter with 3 phase legs and current sensing for all 3 legs for
redundancy and noise immunity. A Field-Oriented Control Algorithm will be used to
modulate the phase currents and maximize motor efficiency and performance. A motor
resolver using a BiSS (Bidirectional/Serial/Synchronous)1 interface along with a dual
CAN (Controller Area Network)2 communication network will be used for noise immune
communications on the vehicle. Four of these inverters will be placed on a single large
heatsink instead of the industry standard method of using a complex liquid-cooled cold
plate. However, this will require ~99% efficiency from the inverter which we believe to
be possible. Once achieved, we will have created a compact, lightweight- solution with
very high efficiency that will cost much less and have more than double the power
density of the best commercially available motor drives.
1.2 Background
The Illini Formula Electric organization at UIUC participates in the Electric category of
the Formula SAE competition and over the past few years has been gradually getting
more competitive. In the competition year of 2021, the team aims to progress their
design to a 4-wheel drive design to maximize the performance of the vehicle within the
1 Described in Section 2.3.2 2 Described in Section 2.3.3
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constraints of the competition rulebook. This is accompanied by numerous engineering
challenges, one of which is the design of a motor controller that has a high enough
performance to be usable on a race car of this caliber.
1.3 Visual Aid
As seen in Figure 1, a Texas Instruments control card will be attached to a control board
which sits above the power stage and the entirety of this represents a single motor
controller. Four such identical motor controllers will be placed within a single heat-sink
enclosure.
Figure 1: Texas Instrument Control Board connection to the main PCB
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1.4 High-Level Requirements
Our first high-level requirement is that our drive inverter has a maximum power
dissipation of less than 400W per module at peak output power of 35kW. Competitors
and commercial solutions generally used in our competition have motor inverters that
dissipate 1000W or more, which requires water cooling. To minimize weight and
complexity, our design aims to be air cooled and use a heatsink which can dissipate up
to 120W. From simulating the vehicle driving a lap of the racetrack, we know the
approximate operational duty cycle is around 30%. Hence, the restriction on dissipation
at 400W or less.
Second, the inverter must have a small volume occupied. Our electric race car has very
little space designated for the inverter; thus, we require the inverter to fit in a 200mm x
100mm x 40mm volume. Since the vehicle is primarily limited in vertical space, the goal
is to minimize the vertical height of the design to 40mm or less while keeping the
footprint as small as possible.
Our final high-level requirement is that the weight of our 4 inverters combined is less
than 6 kilograms. Most competitor’s drive inverters and commercial designs typically
have a dry weight of more than 8 kilograms and potentially over 10kg all included.
Weight is an important factor when it comes to designing an electric race car, and even
small reductions in weight help efficiency and performance.
2 Design
The overall vehicle design block diagram is seen in Figure 2. The 600V battery pack
supplies the 4 motor controllers with DC power through its protection relays. This power
is converted into 4 sets of 3-phase power for each motor on the wheel. Each of these
motors are rated for 40kW but will only be operated at 35kW at most.
Figure 2: Overall vehicle diagram representation
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2.1 Motor Controller Block Diagram (Figure 3)
The motor controller takes 600Vdc from the vehicle’s battery and converts it to a 3-phase
AC output for the motor at up to 62Arms. It contains 2 primary components, the power
stage, and the control board, these are seen in the block diagram in Figure 3. The
control board takes its control inputs from the vehicle’s Controller Area Network (CAN)
bus and sense signals from the motor encoder which measures shaft angle and the
voltage/current signals from the power stage. It uses these to compute Pulse Width
Modulation (PWM) signals that control the power stage. These PWM signals are
converted into a switching high voltage output by the power stage which can source the
3-phase 62Arms currents necessary to drive the motor. The details on how this is done
is explained below.
Figure 3: Single Motor Controller block diagram representation
2.2 Power Stage Block Diagram (Figure 4)
The power stage contains all high voltage and high current paths of the inverter. It is
composed of 3 phase legs each drive one phase of the motor. It also contains a sensing
circuit for the DC voltage of the battery, connectors for the battery input power and
connectors to plug the control board into. Each phase leg consists of DC link capacitors,
a Silicon Carbide (SiC) MOSFET half-bridge, gate drivers, isolated gate drive, isolated
power supplies, phase current sensing and module temperature sensing.
2.2.1 DC Link Capacitors
Since capacitor inductance and layout loop inductance is hard to estimate even if using
simplified methods as described in [5], capacitors similar to those used in [2] were
selected and placed in an approximately similar layout. A total bus capacitance of all 3
phases of 45uF was chosen to provide sufficient decoupling at 50kHz PWM frequency
while minimizing volume. If switching losses are higher than expected, there is enough
capacitance margin to allow the PWM frequency to be reduced to 30kHz.
Figure 5 Figure 4
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Requirement Verification
DC bus ripple is under 10% of 440V, the
minimum operational voltage of the vehicle
battery.
This measurement will be done at a lower
current and the resulting data will be
extrapolated to 62Arms operation. When the
complete power stage is connected as
described in Appendix A, the inverter is
operated at 15.5Arms, and the DC bus voltage
is measured with the oscilloscope. The peak-
to-peak voltage is measured and must stay
within 11V.
Operating temperature does not exceed
105°C, the datasheet specified maximum
operating temperature. This is 70K above the
assumed case internal temp of 45°C.
While operating the complete power stage as
described above at 1/4th of peak power,
capacitor case temperature rise over ambient
is monitored with an IR thermometer. The
temperature rise in these conditions must not
exceed 17.5 Kelvin.
2.2.2 Isolated Gate Driver and Isolated Power Supply x6
MOSFETs need to be turned on and off rapidly to minimize switching losses during the
transition. This is done using powerful isolated gate drivers. Each of the 6 MOSFETs in
the inverter, 2 per module, are driven by the same gate driver IC (UCC21750). It
supports important features like desaturation detection which detects accidental shorts
and interlocked PWM inputs which prevent MOSFET damage in failure situations as
described in [1]. Further, a miller clamp reduces the chance of the MOSFET turning on
during fast switching events and an analog to PWM converter which allows for isolated
module temperature sensing without any additional components. The power supply is a
2W isolated module optimized for SiC gate drives (MGJ2 series from Murata) which is
has a very high common-mode transient immunity(CMTI), just like the gate driver so
there are no false transmissions across the isolation barrier during fast voltage
transitions(>150V/ns) across it.
Requirement Verification
Supply output regulation within 0.5V at operational voltage transients of up to 50V/ns to maintain a stable gate drive supply
During double pulse testing as described in Appendix B, the power supply rails of the high side FET are monitored with a differential oscilloscope probe to ensure they stay within the 0.5V requirement even during the fast voltage transitions when switching.
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2.2.3 Half Bridges x3
To maximize thermal performance and minimize the work to be done, a module
containing 2 MOSFETs in a half-bridge configuration is preferred. A low inductance
Infineon half-bridge module (FF11MR12W1M1P_B11) is used to implement the phase
legs. It strikes the right balance between switching losses, conduction losses and cost.
It also allows for compact temperature sensing which is very hard to achieve with a
discrete solution.
Requirement Verification
Switch node voltage overshoot is under 300V to stay within MOSFET operating limits
During double pulse tests as described in Appendix B, switch node voltage is measured with high bandwidth and overshoot voltage is measured. The layout inductance, capacitor inductance and gate resistor must all be tuned to ensure this stays under 300V with a 100V DC voltage. This does not scale predictably to 600Vdc operation, so this step will have to be repeated when testing at 600V later.
Thermal resistance to the heatsink is under 0.7K/W
While a known amount of heat is being dissipated by the module using a power supply across the drain and source and function generator on the gate input, the module temperature is measured using its built in sensor and the heatsink temperature is measured with an IR thermometer. The difference is used to compute the thermal resistance and compared with the maximum allowable value. If this is too high, better thermal compounds and mounting methods must be investigated.
2.2.4 Bus Voltage Sense
For the motor controller’s algorithm to function effectively at a wide range of battery
voltages, the voltage of the DC bus must be known. A resistor divider circuit and
isolated sigma delta converter (AMC1336) is used to scale down the voltage and
convert it to a 1-bit stream. This allows for compact and noise free measurement of the
DC bus. The input to the modulator has an analog filter which is configured to greatly
attenuate switching noise. The isolated 5V supply for the modulator is provided by a
low-noise linear regulator connected to the low-side gate driver power supply.
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Requirement Verification
Voltage measurement must have 10-bit accuracy at 600V (0.6V)
The power supply voltage is set to various values between 0 and 100V and the measured voltage is compared to a measurement taken with a multimeter at no load so there are no resistive voltage drops in the measurement.
Figure 4: Power Stage block diagram representation
2.3 Control Board Block Diagram
The control board as described earlier takes in all sensed inputs and throttle commands
and outputs the necessary control signals to the power stage to ensure the output is
what is required to generate the torque requested. The software being used to do this is
described in a later section. It uses a Bidirectional/Serial/Synchronous interface to
communicate with the motor resolver and get the motor shaft angle. It also uses a
Controller Area Network (CAN) bus to get the throttle input from the driver pedal. Based
on those inputs as well as sensed signals from the power stage, it executes a Field
Oriented Control (FOC) algorithm on a microcontroller at 50kHz and ensures that all of
this occurs safely. It also generates all the necessary voltage busses for the proper
operation of the board. It will also log all important parameters during operation and in
fault conditions to the CAN bus.
2.3.1 Power Supplies
We require 12V, 3.3V and 5V busses for the different ICs on the board such as our gate
drivers, isolated power supplies and interface controllers. However, we will only have a
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12V supply to the board from the vehicle’s battery. Hence, the power supply section
generates these additional 2 rails for low power components.
Requirement Verification
3.3V bus and 5V bus have at least 5% output
regulation and less than 100mV ripple to
ensure proper functioning of all components
on the bus.
During full power stage operation (See
Appendix A), both bus voltages are
measured with a multimeter to measure
output regulation and an oscilloscope in AC
coupling mode to measure output ripple
under load.
2.3.2 BiSS (Bidirectional/Serial/Synchronous) Interface IC
BiSS is a RS485 based signaling protocol designed for high speed motor resolvers that
is very noise immune and accurate. An RM44x resolver is placed on the motor shaft
that interacts with the control board over this protocol. An RS485 Tx/Rx interface is
used for this and will be implemented on the board using a circuit similar to [7].
Requirement Verification
Communication protocol library is functional. The control card is wired to the RM44
resolver and angle measurements at the
necessary update rate are performed and
verified to approximately match with the
motor shaft angle. The accuracy of this
measurement is not verified since the product
is rated to meet a certain specification with no
additional steps or verification.
2.3.3 CAN (Controller Area Network) Interface IC x2
The entire vehicle uses multiple CAN busses to communicate various signals. The
inverter will be connected to 2 CAN busses. Each CAN BUS will have a transceiver to
handle data transmission from the CAN bus that is accessed by other components on
the car. One CAN bus will take in torque commands sent by the driver’s foot pedal and
communicate them to the microcontroller. The other bus will be used to output data for
the vehicle’s external datalogger to store critical parameters, status history, potential
error codes and crashes.
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Requirement Verification
Both CAN busses operate up to 1Mbaud
stably
CAN bus output through the IC is connected
to a laptop using a USB-to-CAN adapter
(PCAN-USB) and bidirectional
communication is verified with a loopback
program and a CAN bus viewer software
(PCAN-View)
2.3.4 Texas Instruments TMDSCNCD280049C Control Card
To implement the FOC algorithm on a microcontroller, a control card from Texas
Instruments will be used. The algorithm will operate with at 100kHz to update a 50kHz
PWM signal to each of the 6 MOSFETs twice every cycle. It takes in motor shaft
position from the BiSS interface and current and voltage data from the power stage.
Using the torque command from the CAN bus, the algorithm will generate six pulse-
width modulation signals that are sent to the power stage to drive each MOSFET.
Requirement Verification
All communication pins are correctly mapped
in software.
Each pin group is tested while testing each
peripheral (CAN, BiSS, PWM etc.). As a
result, no independent testing is necessary.
Figure 5: Control Board block diagram representation, which includes Texas
Instruments’ Control Card featured in Figure 1
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2.4 Schematics
Below are schematics for the parts of the design currently completed. This only includes
one phase leg of the power stage so far. The control card and other boards are
currently in development. Yellow notes boxes indicate design decisions, notes for layout
or part choices. Green notes are notes made about component pricing or other Bill of
Materials (BOM) related optimization. Orange notes are design errors that have been
noticed and will be fixed in future board revisions. Compile blankets are used to define
net classes (HV+, HV-, Phase) so that appropriate PCB spacing can be used.
Figure 6: Power supply circuit and connectors to the control board
Figure 7: HV DC connections and Phase output connection
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Figure 8: Capacitor discharge resistors and module temperature sensing bias circuit
Figure 9: Module half bridge connections and phase current sensing
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Figure 10: High side and Low side gate driver circuitry
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Figure 11: DC bus voltage sensing
2.5 Board Layout
Currently, the board layout that has been designed is a single-phase leg design to be
used for double pulse testing. The layout images for this is shown in Figures 12, Figure
13, Figure 14, and Figure 15. The full power stage and control board layout will be
completed in the future.
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Figure 12: Top/Layer 1 of PCB
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Figure 13: Mid 1/Layer 2 of PCB
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Figure 14: Mid 2/Layer 3 of PCB
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Figure 15: Bottom/Layer 4 of PCB
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2.6 Software
The software running on the control card from Texas Instruments will be the only
software programmed/used in our motor inverter. The control card as seen in 2.3.4 will
execute a Field Oriented Control algorithm. Demo source code from Texas Instruments’
libraries of which implement this algorithm will be used as the basis for our software.
The demo code has multiple build levels to it, and we will only need to use the first three
levels of said algorithm.
2.6.1 BUILDLEVEL 1
As seen in Figure 16 below, Level 1 will verify our target independent modules along
with the duty cycles and pulse-width modulation updates. In this level, the motor is
disconnected. Here we want each PWM signal to be exactly 120° apart from each other.
Specifically, the Tb waveform will lag the Ta waveform by 120° and the Tc waveform will
lead the Ta waveform by 120°.
Figure 16: Block Diagram of system built in Level 1 [10]
2.6.2 BUILDLEVEL 2
In Figure 17 below, Level 2 is added to Level 1 and Level 2 of our BUILDLEVEL
consists of verifying our analog-to-digital conversions, offset compensation, and the
Clarke and Park transformations. The Clarke transformation is used to convert our
balanced three-phases into balanced two-phase quadratures. Furthermore, Clarke
transformation then uses this two-phase reference frame and converts it into a rotating
reference frame. Here we can assume Level 1 is fully functional because we completely
tested it and started with Level 2. Now is when we can run the motor in an open loop to
test and verify the functionality of the various current sense using different methods.
Another test we will conduct in this level is the functionality of our BiSS position
encoder.
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Figure 17: Block Diagram of system build Level 2 added to Level 1 [10]
2.6.3 BUILDLEVEL 3
Lastly, we reach our Level 3 in BUILDLEVEL as seen in Figure 18 below. Here is when
we verify our dq-axis current regulation, which is performed by PI (Proportional-Integral)
macros and speed measurement modules. The direct (d) axis is the axis where flux is
produced from the field winding and the quadrature (q) axis is the axis that torque is
produced on. In Level 3, we manually compute transformations based on the reference
angle that is generated rather than our actual rotor position. It is tested this way so that
a big load is not necessary to be used on the motor, which allows for easy Iq loop
testing.
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Figure 18: Block Diagram of system build Level 3 added to Level 2 and Level 1 [10]
2.7 Tolerance Analysis
One of the biggest constraints and challenges with this revision of the design is thermal
management. Our high-level requirement for heat dissipation is less than 400W when
running at 35kW. This is to ensure the average power dissipated is under 120W over
the period of a lap. Any higher and the heatsink temperature will rise more than
allowable. This operational duty ratio is computed using the team’s lap simulator.
We have gone through the theoretical analysis of the power that will be lost and
dissipated by the largest heat producing part of the design, the half bridges containing
the MOSFETs responsible for outputting AC to our motors. We will consider two forms
of power loss for our half bridge packages: conduction losses and switching losses.
𝑃𝑐𝑜𝑛𝑑 = 𝑅𝐷𝑆(𝑜𝑛)(125∘𝐶) ∗ 𝐼𝑟𝑚𝑠
2
Eq. 1: Half Bridge Conduction Losses
𝑃𝑠𝑤 = 2 ∗ (𝐸𝑠𝑤(𝐼𝑜 = 88𝐴 ) ∗ (𝑓𝑠𝑤) ∗ 0.637 ∗ 0.5)
Eq. 2: Half Bridge Switching Losses
When considering a specific package, our goal was to minimize losses such that we can
operate in our desired conditions of less than 400W of power dissipated. For the
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FF11MR12W1M1P_B11 half bridge package, we will need 3 for each inverter, so the
total losses for each half bridge can be no greater than 400W / 3. Below, specifications
from the datasheet for our chosen half bridge package have been inserted into
equations to see if our thermal target is feasible.
𝑃𝑐𝑜𝑛𝑑 = 14.8𝑚Ω ∗ (62𝐴𝑟𝑚𝑠)2 = 56.9𝑊
Eq. 3: Solved Half Bridge Conduction Losses
𝐸𝑠𝑤 = 𝐸𝑜𝑛 + 𝐸𝑜𝑓𝑓 | 𝐸𝑜𝑛 = 1.317𝑚𝐽, 𝐸𝑜𝑓𝑓 = 0.535𝑚𝐽 (𝐼𝑜 = 88𝐴)
Eq. 4: Energy Lost from Switching
𝑃𝑠𝑤 = 1.852𝑚𝐽(@𝐼𝑜 = 88𝐴) ∗ (50 ∗ 103) ∗ 0.637 ∗ 0.5 = 29.5𝑊
Eq. 5: Solved Half Bridge Switching Losses
As our inverters will have 3 half-bridges, we will multiply the power losses by 3 to obtain
the total power loss per inverter.
3 ∗ (𝑃𝑐𝑜𝑛𝑑 + 𝑃𝑠𝑤) = 347.7𝑊
Eq. 6: Total Losses from Half Bridges
As shown above, we will be within our power dissipation limits by a comfortable 50W.
The numbers above are calculated at ideal operating conditions. The main source of
any tolerance error would come from temperature. The two package specific variables
𝑅𝐷𝑆(𝑜𝑛) and 𝐸𝑠𝑤 will increase if temperatures rise, with the max operating temperature of
the package being at 150°C. There, the maximum variance we might see in power
dissipation would be +/- 10% (313W – 382.5W), which still leaves us below our 400W
target.
2.8 COVID-19 Contingency Planning
When it comes to COVID-19, if we can no longer have access to the lab, we will be able
to continue our work at home. All testing and manufacturing needed to complete this
board is possible with equipment owned by Illini Formula Electric.
Social distancing guidelines can be followed as any testing requiring two people can be
conducted 6 feet apart at minimum, and board soldering can be done by a single
person.
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3 Cost and Schedule
3.1 Cost Analysis
3.1.1 Labor Costs
Our labor costs are estimated using the fact that there are 3 people on our team, each
person works about 12 hours a week on the assignment, and about 70% of the project
will be completed by the end of the semester.
3 ∗16 𝑤𝑒𝑒𝑘𝑠
0.7∗
$30
ℎ𝑟∗
12ℎ𝑟
𝑤𝑒𝑒𝑘∗ 2.5 = $61,715
Eq. 6: Fixed labor costs computation
3.1.2 Parts Costs
For bulk pricing, a production run volume of 1000pcs is assumed as this is a product for
very high-performance vehicles and will not see high demand like a regular consumer
product.
Part Cost (prototype) Cost (bulk) DC Link Capacitors (Mouser; B32774D8305K000)
$37.80 $19.35
Isolated Gate Driver and Isolated Power Supply x6
$28.68 $24.30
Bus Voltage Sense (Texas Instruments; AMC1336DWVR)
$6.69 $4.07
Current Sensor x 2 (AKM Semiconductor Inc; CZ3706)
$17.10 $9.00
Power Supply $10.20 $6.40
BiSS Interface ICs $10.00 $5.00
CAN Interface ICs $5.00 $2.00
Half Bridge x 3 (Infineon; FF11MR12W1M1B11BOMA1)
$428.67 $362.28
Texas Instruments Control Card
$99.00 $99.00
PCB $300.00 $100.00
Miscellaneous Passives $50.00 $20.00
Total $993.14 $651.40
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3.1.3 Grand Total
When adding together the costs of our prototypes along with labor costs we receive a
total cost of
$61715 + $993.14 = $62708.14
Eq. 7: R&D and Prototype
$61715
1000+ $651.40 = $713.12
Eq. 8: Components purchased in bulk total cost
3.2 Schedule
Week Chaitanya Sindagi Conner Bone Joshua Powell
9/28/2020 Order single phase board & parts
Order single phase board & parts
Read through [10] Documentation
10/5/2020 Assemble single phase board and
incrementally test
Assemble single phase board and
incrementally test
Assist with testing PCB
10/12/2020 Continue testing and revise schematics
Continue testing and revise schematics
BUILDLEVEL 1 Complete
10/19/2020 Complete layout design for full power
stage
Finish testing single phase leg board
Work on BUILDLEVEL 2 and 3
10/26/2020 Assemble test bench for complete power
stage
Assemble test bench for complete power
stage
BUILDLEVEL 2 Complete
11/2/2020 Assemble power stage and incrementally test
Assemble power stage and incrementally test
BUILDLEVEL 3 Complete
11/9/2020 Test power stage with RL load
Test power stage with RL load
Proceed with Final Testing
11/16/2020 Test power stage with motor
Test power stage with motor
Test power stage with motor
11/23/2020 Plan final paper and presentation layout
Plan final paper and presentation layout
Plan final paper and presentation layout
11/30/2020 Present and continue final paper
Present and continue final paper
Present and continue final paper
12/7/2020 Final paper Final paper Final paper
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4 Ethics and Safety
In following IEEE’s 7.8 Code of Ethics, Section I Policy 1 “To hold paramount the safety,
health, and welfare of the public... “, there are two concerns our group shall address.
As of Fall 2020, the University of Illinois @ Urbana-Champaign has provided guidelines
for preventing the spread of COVID-19. All members of this project group will follow
CDC recommended safety guidelines to prevent the spread of COVID-19, and receive
testing for the virus twice a week, per the Student guidelines provided by the University
[8]. In-person work will be limited to “as necessary”. All other work will be completed
remotely in order to maximize social distancing.
As this project will involve working with high voltage electronics, our project members
will follow best practices as outlined in IEEE STD 4-2013 “IEEE Standard for High-
Voltage Testing Techniques”. Any work done with active power electronics will be done
with at minimum 2 people present for testing for safety purposes. [9]
As work on this project corresponds to progress on a component of a vehicle owned
and operated by Illini Formula Electric, all work contributed by parties outside of the
three listed in this project proposal will be properly attributed. This will be in accordance
to IEEE’s 7.8 Code of Ethics Section I Policy 5 “... and to credit properly the
contributions of others; “
Finally, in accordance with Section I Policy 6, “... to undertake technological tasks for
others only if qualified by training or experience, … “, all tests will be conducted in the
Electrical and Computer Engineering Building labs in which project members are
certified and trained to work in. Members will make every effort to be familiar with any
power electronic testing equipment and its operation before conducting testing.
Appendix
Appendix A Power Stage Testing
Full power stage testing is an important and critical aspect of the testing process. Using
the BUILDLEVEL1 of the FOC algorithm described in 2.6.1, 6 sine wave modulated
PWM outputs will be generated by the control board for the power stage. The power
stage will be connected to a 100V power supply that can deliver the necessary current
for the test. Depending on the test, either a resistor-inductor (RL) load or a small motor
will be connected to the power stage. The RL load will be used to simulate a motor by
using the inductor to be approximately equal to the motor winding inductance and
resistor to simulate the power conversion. This resistor will have to be sized depending
on the current to be tested at. If 15.5Arms is required for testing the capacitors for
example, then the chosen resistor will be –
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𝑅 =100
15.5 × √2= 4.5Ω
Eq. 9: Resistor value calculation for simulated RL load
The power dissipated in these resistors will be large, therefore, they must be
appropriately heatsinked.
Appendix B Double Pulse Testing
Double pulse testing is a method used to determine switching performance of a half
bridge module at different levels of current. By using a large inductor connected
between the switch node and DC+, a precise value of current can be conducted through
the lower MOSFET in the half bridge by turning on the MOSFET for a fixed period of
time. Then, the MOSFET is switched on and off rapidly, before the inductor current
decays, resulting in a measurement of a variety of parameters during the turn-on and
turn-off events at a specified current.
This test will be conducted by connecting the largest inductor available in the lab that
can operate at the current levels necessary without saturating. The high side MOSFET
is held low while the low side MOSFET is turned on for a fixed period of time to raise the
current to the necessary value. It is then turned off and back on within 1μs and then
turned back off to allow the inductor to discharge. These timings will be generated using
a function generator to allow for precise control.
Appendix C Lap Simulation
The Illini Formula Electric team uses a series of programs developed in MATLAB to
simulate the performance of every component of the electric race car as it drives a
virtual lap of the racetrack at the competition. The details of this simulator are beyond
the scope of this document, however, details such as the torque and speed of the motor
over a lap can be extracted as seen in Figure 19.
Figure 19: Motor torque(left) and Motor rpm(right) vs time over a lap
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This data can be used to analyze various design requirements of components. For
example, using the following code to approximate losses in the inverter, the power
dissipation graph is generated. The value does not fall to 0 due to the imperfect
assumptions made in the simulator and calculations.
Figure 20: Inverter power loss estimation and simulated losses over a lap
The average power dissipation over a lap from Figure 20 is calculated as 110W, leaving
some margin to the 120W limit imposed by the heatsink.
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References
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