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SiC Power Semiconductors in HEVs: Influence of Junction Temperature on Power

Density, Chip Utilization and Efficiency

Benjamin Wrzecionko, Jürgen Biela and Johann W. Kolar Power Electronic Systems Laboratory

ETH Zurich Zurich, Switzerland

Email: wrzecionko@lem.ee.ethz.ch

SiC Power Semiconductors in HEVs:Influence of Junction Temperature on Power

Density, Chip Utilization and EfficiencyBenjamin Wrzecionko, Jurgen Biela and Johann W. Kolar

Power Electronic Systems LaboratoryETH Zurich

Zurich, SwitzerlandEmail: wrzecionko@lem.ee.ethz.ch

Abstract—With SiC, junction temperatures of power semicon-ductors of more than 700 ◦C are theoretically possible due tothe low intrinsic charge carrier concentration of SiC. Hence, a lotof research on package configurations for power semiconductoroperation above 175 ◦C is currently carried out, especiallywithin the automotive industry due to the possible high ambienttemperatures occurring in hybrid electric vehicles (HEVs). Thispaper shows, that a higher junction temperature though doesnot necessarily guarantee a higher utilization of the SiC chipswith respect to the current that the device can conduct withoutoverheating. The reason is, that for most power devices the powerlosses start to increase very rapidly at high junction temperatureswhile the power that can be dissipated always increases linearlywith the junction temperature.

The junction temperature, where the device current starts todecrease at, is derived for different SiC chips using measured on-state conduction and switching losses in this paper. This paperfurthermore analyzes in detail, how the junction temperature onthe one hand is influenced by boundary conditions and on theother hand influences itself the core parameters of a convertersuch as efficiency, the required chip area (i. e. cost) as well as thevolumetric power density and thus forms an additional degreeof freedom in the design of a power electronic converter. Whilecalculating the optimum junction temperature and analyzing itsimpact on the system performance, it is demonstrated, how theseresults can help to find the best suited power semiconductordevice for the particular application.

The performance of the calculations is shown on a designapplied to a drive inverter for hybrid electric vehicles withnormally-off SiC JFETs. Operated close to the optimum junctiontemperature of the SiC JFETs, it reaches a power density of51 kW/l for the power modules and the air-cooling system, whichis shown to be doubled by increasing chip size and using anadvanced power semiconductor package with a lower thermalresistance from junction to ambient than the for this caseassumed 1 K/W.

I. INTRODUCTION

An increasing trend towards more compact power electronicconverters for high ambient temperatures can be observed inthe development of hybrid electric vehicles (HEVs). Often,existing car concepts are enhanced by a model with a hybridpower train. There, small converters for hot surroundings(e. g. close to the internal combustion engine or the gearbox)can help to simplify packaging and manufacturing issues ofthe vehicle [1], [2]. Fig. 1 shows the topology of a typical

CDC

T4

T1T7

T8

T3 T5

T2T6

+

-

VDCVBattery

Scope of Analysis

M

LB

Fig. 1. Topology of a typical drive inverter with DC-DC converter used inHEVs. The impact of the power semiconductor junction temperature is carriedout for a six-switch air-cooled inverter system. A power density of 51 kW/l atan ambient temperature of 120 ◦C and an efficiency of 97.8% can be reachedwhen operated close to the optimum junction temperature.

converter used in HEVs to drive the electrical machine of thevehicle from the a high voltage traction battery.

To achieve the goals of small size and high temperaturecapability, the power semiconductors employed in these con-verters must exhibit a low on-resistance and low switchingenergies in order to reduce the power losses. With the reducedlosses, the amount of heat that needs to be removed by thecooling system is minimized.

To minimize the volume of a particular cooling system,the temperature difference between the ambient temperatureand the junction temperature of the power semiconductorchip should be high. Hence, at high ambient temperatures,the semiconductor must be able to operate at higher junctiontemperatures. The maximum operation temperature of mostpower semiconductors made of Silicon (Si) is 175 ◦C.

The group III-V compound semiconductor Silicon Carbide(SiC) features physical properties superior to those of thewidespread elemental semiconductor Si when manufacturingpower semiconductor devices for high power density convert-

© IEEE 2009 3870 Preprint of IECON 2009 Proceedings

1E+08

1E+10

1E+12

1E+14rie

r Co

ncen

trat

ion

(cm

-3)

Si

4H-SiC

1E+00

1E+02

1E+04

1E+06

1E+08

1E+10

1E+12

1E+14

0 100 200 300 400 500 600 700

Intr

insi

c Ch

arge

Car

rier

Conc

entr

atio

n (c

m-3

)

Temperature (°C)

Si

4H-SiC

Fig. 2. Intrinsic charge carrier concentration ni of Si and SiC vs. temperature.The comparably low ni is the reason for the high temperature capability ofSiC power semiconductors.

ers in (hybrid) electric vehicles [3]. Therefore, automotivepower electronic converters start to feature switches made ofSiC [4].

The for the objective of this paper most important favorablephysical property of SiC compared to Si is its low intrinsiccharge carrier concentration ni. Fig. 2 shows, that for a largetemperature range ni of 4H-SiC stays below 1015 cm−3, wherethe intrinsic conduction of the semiconductor starts and itbehaves as a bulk resistor [5] — at 700 ◦C, ni of 4H-SiCis equal to that of Si at 100 ◦C. This is the reason, why SiCpower semiconductors can be operated at much higher junctiontemperatures than power semiconductors made of Si.

Further superior properties include a three times higherband-gap leading to an order of magnitude higher breakdownelectrical field (328 MV/m for 4H-SiC, the most common SiCcrystal structure for SiC power semiconductors, compared to29 MV/m for Si) while having a comparable electron mobility[6]–[11]. These characteristics allow SiC devices to blockhigher voltages while having a lower on-resistance. Hence,unipolar devices with low switching losses (due to the absenceof carrier injection), are feasible and competitive even forhigh operating junction temperatures and voltages exceeding1000 V with SiC [12].

It arises the question, whether it is desirable to operate theSiC device up to its maximum temperature limit. On the onehand, the higher the junction temperature, the more powercan be dissipated for the same cooling system. On the otherhand, very advanced packaging technologies are needed andreliability issues need to be solved [13] for temperatures con-siderably above 175 ◦C. A third aspect concerns the losses: Formost SiC power semiconductors, the losses increase more thanlinearly with device temperature while the power, that can bedissipated by the package, increases linearly with temperature.That is, at a certain temperature, the device current cannot be

Package

Information

On-Resistance

Measurements

Switching Loss

Measurements

Rth,JA(A)TA VDC Ron(TJ, A)

PS(fS, TJ, A, VDC, IDS)

PS(TJ, A, IDS) + PC(Ron(TJ, A), IDS) = (TJ – TA) / Rth,JA(A)

fS

IDS = f(TJ, A)TJ,opt(A)

IDS,submax(A)TJ,subopt(A)

Specifications

Solve for IDS

Include Safety Margin

Fig. 3. Flow chart illustrating the way of determining the optimum junctiontemperature of SiC power semiconductors: Input parameters (specificationsand device characteristics) are used to derive an equation for the thermallystable operation of the converter. This equation is solved for the devicecurrent in order to calculate the junction temperature that maximizes thedevice current. For a safe operation of the converter, the maximum current isreduced by a safety margin. This usually provides a huge additional benefitwith respect to reliability issues of the package as it is shown in Section II-Cthat the junction temperature can be decreased by more than 100 ◦C whilestill conducting 90% of the maximum possible drain current.

risen any more even though the junction temperature increasesbut must be decreased in order to prevent the device from athermal runaway [14]. This point, where the device currentstarts to decrease with increasing temperature, is the optimumjunction temperature with respect to the utilization of thepower semiconductor switch because this is the point, wherethe device current reaches its maximum for a given coolingsystem.

In contrast to [14], this paper derives the optimum junctiontemperature using real measurements of on-resistances andswitching energies of different SiC power semiconductors(cf. Section II). As the switching losses are now includedin the calculations, the dependencies become more complex.The influence of the device characteristics as well as ofthe operating conditions such as switching frequency fS,ambient temperature TA and the thermal resistance Rth,JA onthe optimum junction temperature is exemplarily analyzed indetail for a 1200 V normally-off JFET (cf. Section III).

The impact of the junction temperature on the core per-formance parameters of a power electronic converter such asefficiency η, the volumetric power density p and the requiredchip area A is shown in Section IV. The performance of thecalculations is demonstrated for an inverter in hybrid electricvehicles (cf. Fig. 1). This reference design reaches a powerdensity of 51 kW/l for the power modules and the air-coolingsystem including heat sinks and fans.

II. OPTIMUM JUNCTION TEMPERATURES

The flow chart in Fig. 3 illustrates how the optimum junctiontemperature TJ,opt for SiC power semiconductors is derivedin this paper. First, the input parameters have to be obtained.

© IEEE 2009 3871 Preprint of IECON 2009 Proceedings

A. Specifications

The input parameters consist of predefined specifications:

• The ambient temperature TA is around 120 ◦C for powerelectronic converters placed under the engine hood ofhybrid electric vehicle regardless of the cooling fluid(water-glycol mixture or air).

• The DC link voltage VDC is usually chosen as high aspossible in order to minimize the current for a certainpower level so that the I2R losses in the switches, supplylines and the electrical machine(s) are minimal. The DClink voltage is directly given by the maximum voltagethat can be applied to the machine in the power train.Due to partial discharge issues in the machine, VDC

stays usually below 800 V for electrical machines usedin hybrid electric vehicles and is assumed to be 700 V inthis case.

• The switching frequency fS is specified depending onEMI filtering requirements and the desired rotationalspeed of the electrical machine and thus the requiredfrequency of the output current in the case of an inverter.For a DC/DC converter, the size of the passive elementsinfluences the choice of the switching frequency. Here, fSis chosen to be 50 kHz in order to be able to drive highspeed electrical machines that can provide power densitybenefits [15].

• The thermal resistance Rth,JA from the power semi-conductor junction to the ambient is determined by theparticular package configuration. It will not stay constantfor different chip sizes as the heat spreading of a largerchip or several small chips is better than that of a singlesmall chip. Hence, a correlation between Rth,JA andthe chip area A is required for precise results. Thiscan be obtained by measuring or simulating the packageconfiguration with different chip sizes. A curve fittingalgorithm using the correlation

Rth,JA(A) =aRth

A+ bRth (1)

usually gives good fitting results because for very smallchip sizes, the thermal resistance approaches infinity, andfor chip sizes close to the maximum (i. e. the surfacewhere the chips are soldered onto and that is feeding theheat into the cooling system is fully covered with chips) ithas got a value close to its minimum bRth. The constantsaRth and bRth are positive real values. For the exemplarycalculations in this paper, a very conservative estimate ofRth,JA(0.16 cm2) = 1 K/W is used.

B. Device Characteristics

In addition to these predefined parameters, the device char-acteristics of the considered power semiconductors need tobe identified, as the temperature behavior of the on-resistanceand the switching energies determine the optimum junctiontemperature with respect to a maximum utilization of thesemiconductor area.

Fig. 4. Measured and curve fitted temperature dependency of the on-stateresistance of the latest normally-on and normally-off 1200 V SiC JFETs. Thechip area is 17.3mm2 for the normally-on JFET and 4mm2 for the normally-off JFET.

1) On-Resistance: Most power semiconductors feature apositive temperature coefficient of their on-state resistance,i. e. the on-resistance increases with rising device temperature.This can be advantageous as it ensures an even currentdistribution among different dies if several chips are connectedin parallel. The on-resistances Ron of the latest normally-onand normally-off SiC vertical junction field effect transistors(VJFETs) are shown in Fig. 4.

The change in on-resistance is mainly influenced by thechange in charge carrier mobility, which is for unipolar devicesthe mobility of the majority charge carriers (electrons for n-type semiconductors). The decrease in mobility can be par-tially compensated though: Depending on the doping densityof the semiconductor material, not all dopants are ionizedat low temperatures. With rising temperature, the ionizationdegree increases, i. e. new charge carriers are generated,especially in the channel and substrate region [16]. This effectcan clearly be seen for the normally-on JFET, whose slope inon-resistance is lower than that of the normally-off JFET.

For the following calculations, analytic expressions of theon-resistances need to be derived with curve fitting algorithms.Polynomial functions of second order give better fittingsthan power functions due to the mentioned side effects thatsuperimpose the change in charge carrier mobility.

2) Switching Energies: As for the on-resistance, an ana-lytic expression must be derived for the measured switchingenergies in order to be able to analytically calculate theoptimum junction temperature. When measuring the switchingenergies, the turn-off and turn-on energies can be summated.The load conditions should be as close as possible to the laterapplication especially with respect to the parasitic capacitance

© IEEE 2009 3872 Preprint of IECON 2009 Proceedings

Fig. 5. Measured and curve fitted switching energies (turn-on and turn-off)for different temperatures and drain currents of the latest normally-off 1200 VSiC JFETs with an antiparallel SiC diode (Cree C2D10120) on an inductiveload. The normally-on JFET has got a four times larger chip area than thenormally-off JFET. The switched voltage is 700 V for both devices.

of the load that needs to be charged during every switchingtransition.

Fig. 5 shows the measured switching energies and thecurve fitting results. At high junction temperatures, the devicecurrent has to be decreased in order not to go beyond thecurrent carrying limit of the device. The measurement resultsof the switching energies show that as a good approxima-tion, the temperature behavior of the switching energies isindependent of the drain-source current and correspondinglythe dependency of the switching energy on the drain-sourcecurrent is equal for all measured temperatures. Hence, theimpact of drain-source current and the impact of temperatureon the switching energy can be calculated independently andthe resulting function describing the switching energy is aproduct of two independent functions.

ES(IDS, TJ) = kE · gE(IDS) · hE(TJ) (2)

The constant kE is a proportionality factor. The functiongE(IDS) represents the normalized dependency of the switch-ing energy on the drain current and can be derived using themeasured switching energies at a constant temperature, e. g.25 ◦C for the normally-off JFET as it is the only temperaturewhere measured values up to 10 A are available. The functionhE(TJ) forms the normalized temperature behavior whichcan be determined using the measured switching energies atconstant drain current level. Both functions, hE and gE , aresecond-order-polynomials of the form

gE(IDS) = aE + bE · IDS + cE · I2DS (3)

TJ,subopt

10%

TJ,opt

Fig. 6. Drain currents of the normally-on and normally-off JFET (eachwith four single devices in parallel) as functions of the junction temperaturefor the values of Section II-A and Section II-B. Optimum and suboptimumjunction temperature are shown on the example of the normally-off JFET.The differences in maximum drain current and optimum junction temperaturebetween the two devices are mainly due to the differences in the temperaturebehavior of the on-resistance. For very small drain currents, the junctiontemperature does not exactly equal the ambient temperature due to the (atlow currents high) portion of switching losses, which are not close to zerofor drain currents close to zero, especially for the normally-on JFET with afour times larger chip area compared to the normally-off device.

and

hE(TJ) = dE + eE · TJ + fE · T 2J . (4)

The switching energies depicted in Fig. 5 are measuredwith a single JFET, i. e. not multiple devices in parallel. Iflarger currents than measured are conducted through severalchips connected in parallel, an ideal current distribution canbe assumed for a symmetrical module structure due to theabove mentioned positive temperature coefficient of the on-resistance of the JFETs. That is, for i paralleled switches,the switching losses can be calculated for one switch withone ith of the overall current. These switching losses are thenmultiplied by i to obtain the switching losses for all chips.For the following calculations, four devices (four normally-onand four normally-off JFETs, respectively) are assumed to beconnected in parallel, which gives a factor of i = 4.

C. Calculation of the Optimum Junction Temperature

Having derived all input parameters according to Fig. 3, thecalculation of the optimum junction temperature can now bestarted by equalizing the power losses and the power, that canbe dissipated by the package. The losses in the off-state dueto leakage currents (< 100µA per chip at 700 V and 250 ◦Cfor both devices) and the losses arising at the gate (< 1 W perchip) can be neglected. Hence, the power losses consist only

© IEEE 2009 3873 Preprint of IECON 2009 Proceedings

(a) (b) (c)

Fig. 7. Drain current as a function of the junction temperature as well as (a) ambient temperature, (b) switching frequency and (c) thermal resistance forfour 1200 V normally-off SiC JFET connected in parallel.

of the conduction and switching losses, which leads to

I2DSRon + fS · ES =

TJ − TA

Rth,JA(5)

for the thermal equilibrium.Using (2), the junction temperature, where the drain cur-

rent reaches its maximum, can be calculated by deriving anequation for IDS from (5) first,

IDS =1

2(Ron(TJ) − cEfShE(TJ))· (−bEfShE(TJ)

+

√b2Ef

2Sh

2E − 4(Ron − cEfShE)(aEfShE −

(TJ − TA

Rth,JA

)),

(6)

where aE , bE , cE denote the zeroth, first and second ordercoefficients respectively of the drain current for gE(IDS) in(2). Fig. 6 shows a plot of (6) for both the normally-on andnormally-off JFET.

It can clearly be seen from Fig. 6, that there is a junctiontemperature TJ,opt which maximizes the drain current foreach device. This maximum IDS,max can be calculated bydifferentiating (6) with respect to TJ and setting the derivativeto zero. For the conditions of Section II-A and Section II-B,the optimum junction temperature for the normally-off JFETis

TJ,opt,n-off = 361 ◦C, (7)

assuming that the extrapolation of the on-resistance is valid inthis temperature range.

If the junction temperature stays below this value, the JFETis not fully utilized. This is disadvantageous with respect tothe material cost of the converter as more chip area wasused than it was needed but is advantageous in terms of thereliability of the power module and the achievable efficiencyas at a higher temperature the conduction and switching losseswill be higher. If the junction temperature rises above itsoptimum, the semiconductor switch is operated with far lower

efficiency and lower utilization due to lower current that canbe conducted. If the current is not decreased quickly enoughat temperatures above TJ,opt, it can start a positive feedbackmechanism leading to a thermal runaway which results finallyin a thermal destruction of the device.

In order to prevent the chip from heating up higher thanTJ,opt, a safety margin for the drain-source current can bechosen so that IDS is not allowed to rise to more than 90%of its maximum value, which in this case leads to a current of22.5 A. Then, the suboptimum junction temperature is in thiscase

TJ,subopt,n-off = 234 ◦C, (8)

which is significantly below the optimum junction temperaturebecause the slope in IDS is very small around its maximum.This small slope becomes particularly interesting when thetrade-off between current utilization of the chip and reliabilityis considered. By reducing the junction temperature by 127 ◦Cthe reliability rises by orders of magnitude while the maximumcurrent is decreased by 10% only.

For the normally-on JFET, the effect of the slower increasein on-resistance with junction temperature can be seen: Theoptimum junction temperature

TJ,opt,n-on = 428 ◦C, (9)

is reached significantly later, and thus the drain current at thesuboptimum junction temperature

TJ,subopt,n-on = 293 ◦C, (10)

can be larger with 28.4 A.Due to the larger chip area of the normally-on JFET, its

switching losses are higher compared to the normally-offJFET (cf. Fig. 5). Considering the fact, that the switchingenergies are not negligible for negligible drain current currents,Fig. 6 shows, that the switching losses account for a highportion of the overall losses at small drain currents, leadingto a temperature difference between the ambient and junctiontemperature for zero drain current.

© IEEE 2009 3874 Preprint of IECON 2009 Proceedings

T‘A = TA - 40 °C

Baseline

f‘S = 2/3 fS

R‘th,JA = 2/3 Rth,JA

Fig. 8. Drain-source current as a function of junction temperature withvariations in the ambient temperature, the switching frequency and thethermal resistance for the normally-off 1200 V SiC JFET with a chip areaof 0.16mm2.

III. SENSITIVITY OF THE OPTIMUM JUNCTIONTEMPERATURE

Equation (6) shows, that IDS and thus the optimum junctiontemperature depend on• the on-resistance and the switching energies of the power

semiconductor, i. e. the respective absolute value and therespective temperature behavior

• the DC link voltage• the chip size• the switching frequency• the ambient temperature• the thermal resistance from the junction to the ambient.

Most of these parameters become fixed at a certain point in thedesign process of a power electronic converter. The resultingvalue is the consequence of a trade-off consideration betweendifferent impacts on the converter properties of a particularparameter. This section presents the impact of three parameterson the optimum junction temperature and the maximum devicecurrent for the example of the normally-off JFET.

Fig. 7 shows, that the switching frequency fS exhibits thelowest impact on TJ,opt and IDS,max. A change in fS changesthe portion of switching and conduction losses in the overalllosses. As the switching losses increase slightly less withtemperature compared to the conduction losses (cf. Fig. 4 andFig. 5), TJ,opt increases slightly with an increasing portion ofswitching losses. Due to the overall higher losses at higher fS,IDS,max decreases with rising fS.

With the switching losses considered in (5), the thermalresistance Rth,JA from the semiconductor junction to theambient does not cancel out, if (6) is differentiated and setto zero. Therefore, an increased Rth,JA shifts TJ,opt slightly

Normalized Losses atConstant Chip Area

Power Density atConstant Chip Area

Chip Area atConstant Power

Fig. 9. Impact of the junction temperature on the system performanceparameters chip area, power density and losses for a SiC normally-off JFETemployed as a switch in an inverter for hybrid electric vehicles at an ambienttemperature of 120 ◦C and a switching frequency of 50 kHz.

towards higher values and drastically decreases the maximumdevice current.

The ambient temperature TA has by far the biggest influenceon the optimum junction temperature TJ,opt. The lower TA, thelower TJ,opt and the higher IDS,max because at lower junctiontemperatures, the on-resistance and switching losses are lower.Hence, more current can be conducted at constant losses. Thecorrelation between TA and TJ,opt is linear with a slope ofapproximately 1, i. e. every degree reduction in TA reducesTJ,opt likewise.

Precise values of the change in device current and optimumjunction temperature due to the change in parameters can beread of Fig. 8 by comparing the respective curves with thebaseline curve.

IV. IMPACT ON SYSTEM PERFORMANCE OF A DRIVEINVERTER FOR HEVS

In Section II, the impact of the power semiconductor junc-tion temperature on the device current is investigated and thusthe optimum junction temperature with respect to a maximumcurrent is determined.

The junction temperature influences also other system pa-rameters: The chip area that is needed to conduct a certainamount of current at different junction temperatures can becalculated by solving (6) for the chip area A. In Fig. 9, thecurrent is the suboptimum current of 22.5 A for a switch with achip size of 0.16 cm2 out of Section II-C. For junction temper-atures close to the ambient temperature, the required chip areaapproaches infinity because the low temperature differencebetween the junction and the ambient means according to (5),that only very few losses can be dissipated. Hence, the chiparea must be large to adequately minimize the on-resistanceof the switch.

The power density and the normalized losses also depictedin Fig. 9 apply to a six-switch three-phase inverter that can

© IEEE 2009 3875 Preprint of IECON 2009 Proceedings

be used to drive the electrical machine of a (hybrid) electricvehicle. For deriving both parameters, the correlation betweenthe rms value of the drain current of a single switch, IDS, andthe input power of the complete inverter is required.

The input power can be calculated using the the DC linkvoltage VDC and the DC current IDC drawn from the DC linkcapacitor or a high voltage battery,

Pin = VDC · IDC = 3 · VDC · iDS. (11)

IDC is the sum of the three average currents iDS flowingthrough each inverter leg and thus through each switch.

With unipolar devices, the channel can be turned on duringthe conduction period of the freewheeling diode. That is, eachswitch conducts the equivalent of a sine half wave. Then, theratio of IDS upon iDS is π/2 yielding with (11)

Pin =6π· VDC · IDS. (12)

It is assumed, that the losses during the freewheeling statesof the inverter (i. e. either all high-side or all low-side switchesare turned on) are negligible, that the switching frequency iswith 50 kHz much higher than the electrical output frequencyof the inverter and that the converter is PWM controlled, whichprovides an upper estimation of the losses as they will decreasewith space vector control compared to PWM control.

Together with the volume of the package for the powersemiconductors and cooling system including heat sinks andfans, VC = 0.5934 l, the power density p can be plotted (cf.Fig. 9) with

p =Pout

VC=Pin − PD

VC. (13)

For operation at the suboptimum junction temperature of234 ◦C, the drain-source current IDS = 22.5 A of Section II-Cleads to a power density of

psubopt = 50.7 kW/l (14)

at a power level of

Psubopt = 30.1 kW. (15)

Both the power and the power density can be significantlyincreased by simply increasing the die area by a certainamount as this will reduce the conduction losses by the sameamount. Reduced losses lead to increased power that can betransferred at a constant efficiency as the amount of lossesthat can be dissipated by the cooling system remains constant.Increased chip area also leads to a lower thermal resistancefrom junction to ambient; this can be further enhanced byadvanced packaging methods as double-sided cooling. If thecalculations of Section II-C are conducted with eight insteadof four chips leading to a chip area of 32 mm2 for each of thesix switches and the thermal resistance is cut in half, whichis a realistic assumption for double sided cooling as thermalsimulations show, the power density can be doubled to morethan 100 kW/l.

The efficiency decreases with temperature according toFig. 9 due to the increasing losses, which can be calculated

with the suboptimum junction temperature (cf. (8)) and thesuboptimum drain current of 22.5 A (cf. Fig. 6) using (5). Atthe suboptimum junction temperature, the efficiency is

ηsubopt = 97.8% (16)

for the inverter depicted in Fig. 1.

V. CONCLUSION

The latest SiC JFETs can make a significant contributionto the development of ultra compact and efficient powerelectronic converters for hot surroundings in HEVs. In thispaper, the influence of the junction temperature of SiC powersemiconductor devices on the device current is calculated.This calculation is based on theoretical considerations andmeasurements of the temperature behavior of on-resistance andswitching energies for real SiC switches. It is shown, that a1200 V normally-off JFET with a chip area of 0.16 cm2 andrealistic boundary conditions for automotive use, is utilized to90% with respect to the maximum device current at a junctiontemperature of 234 ◦C.

The sensitivity of the optimum junction temperature is alsoinvestigated: A lower optimum junction temperature can beachieved by decreasing the ambient temperature. 1 ◦C lowerambient temperature means 1 ◦C lower optimum junctiontemperature as a good approximation. The most effectiveway to increase the device current, is to reduce the thermalresistance of the package and cooling system. Cutting thethermal resistance in half corresponds to a 50% higher devicecurrent.

The calculations are applied to an inverter for hybridelectric vehicles which is operated close to the optimumjunction temperature at an ambient temperature of 120 ◦C.Then, the employed power semiconductor chips are utilizedwith 141 A/cm2 and the inverter reaches a power density of51 kW/l at a power level of 30 kW and an efficiency of 97.8%,assuming a high thermal resistance of Rth,JA = 1 K/W,which is shown to be doubled by increasing chip size andusing an advanced power semiconductor package with a lowerthermal resistance from junction to ambient than the for thiscase assumed 1 K/W.

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© IEEE 2009 3876 Preprint of IECON 2009 Proceedings

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