SiC MOSFET Reliabilityneil/SiC_Workshop... · SiC power device technology: the industry’s first...
Transcript of SiC MOSFET Reliabilityneil/SiC_Workshop... · SiC power device technology: the industry’s first...
© 2015 Cree, Inc. All rights reserved© 2015 Cree, Inc. All rights reservedA CREE COMPANY
SiC MOSFET Reliability
- Oxide lifetime / breakdown
- High-energy Neutron radiation ruggedness
Daniel J Lichtenwalner, Edward Van Brunt, Shadi Sabri, Jim Richmond, Brett Hull, David
Grider, Scott Allen, John Palmour Wolfspeed, a Cree company
Radiation testing support from Akin Akturk, Brendan Cusak, Jim McGarrity (CoolCad Electronics, LLC )
ARL MOS Workshop - August 17, 2017
© 2015 Cree, Inc. All rights reserved
2WOLFSPEED PRODUCT OVERVIEW: POWER, RF, MATERIALS
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• SiC power devices demonstrate performance & efficiency advantages, that lower system costs
• Die, Discrete devices, and Power Modules (Diodes, MOSFETs)
Applications: Transportation, EnergyIndustrial
SiC POWER MOSFETS: devices & applications
CREE POWER PRODUCTS brochure (2015).
solar
wind
EV chargers
Power supplies
Motor drives
Electric trains
LED drivers
Power Modules
DieDiscrete devices
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4WOLFSPEED POWER MOSFET (Z-FETTM) PORTFOLIO
R&D Demonstrations of MOSFETs to 15 kV, IGBTs to 27 kV, & GTO Thyristors to 20 kV
New!Silicon Carbide Power MOSFET
C3M Planar MOSFET Technology
N-Channel Enhancement Mode Wolfspeed introduces its latest breakthrough in
SiC power device technology:
the industry’s first 900-V MOSFET platform.
Optimized for high-frequency power
electronics applications, including renewable-
energy inverters, electric-vehicle
charging systems, and three-phase industrial
power supplies, the new 900-V platform
enables smaller and higher-efficiency next-
generation power conversion systems at
cost parity with silicon-based solutions.
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Key reliability tests related to SiC MOS devices
Gate Field (~VGS) dominated failure:
1. Time-dependent dielectric breakdown (TDDB)Accelerated gate oxide lifetime testing under constant or ramped VGS bias
Extrapolation to use gate field for lifetime prediction
Drain Field (~VDS) dominated failure:
1. High-Accelerated blocking tests with VDS bias near avalanche
Extrapolation to use drift field for lifetime prediction
2. Cosmic radiation single-event burnout (SEB)Accelerated lifetime test under high-flux N bombardment
Measured at device use fields, no field extrapolation needed!
OUTLINE: Lifetime/reliability tests for MOS devices
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• TDDB = f(VGS)
• HTRB = f(VDS)
• Neutron-SEB
= f(VDS, VGS, h, T)
• Device design, oxide quality & oxide thickness affect slopes of HTRB & TDDB lifetime curves
DEVICE LIFETIME SCHEMATIC: HTRB, TDDB, NEUTRON SEB
Log
(Fai
lure
Rat
e)
Log (operation time)
General effects of HTRB, TDDB, and Neutron Radiation
SEBf(VDS, VGS, h, T)
HTRBf(VDS)
TDDBf(VGS)
‘Random fail’ region ‘Wear-out’ region
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Gate-Related Device Lifetime:
TDDB: Constant VGS, or Ramped VGS
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Many devices need to be taken to breakdown for evaluation of failure distributions
• Constant voltage TDDB (or HTGB) can be used to determine oxide lifetime; typically many packaged devices are stressed simultaneously in an oven at moderate VGS levels
• Ramped TDDB is more amenable to on-wafer testing on a probe station, and allows testing of many devices in hours instead of days
Can test Ncaps with gate area similar to MOSFETs. Results are of practical significance only if large areas are tested!
1.1 TIME-DEPENDENT DIELECTRIC BREAKDOWN (TDDB)
Large-area N-cap (2mmx2mm)
1200V 80mohm MOSFET wafer
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91.2 RAMPED TDDB: Gen2 1200V MOSFETS (20 VGS use), ~100 parts, 150°C
IG-VG, 100 parts, VGS ramp 2 V/s Weibull failure plot
1E-12
1E-10
1E-08
1E-06
1E-04
1E-02
1E+00
10 20 30 40 50 60
Gat
e C
urr
ent
(A
)
Gate Voltage (V)
Ramped TDDB - G2 1200V MOSFET
-6
-5
-4
-3
-2
-1
0
1
2
25 30 35 40 45 50 55 60ln
(-ln
(1-F
))
Failure Voltage (V)
G2 MOSFET R-TDDB
Gen2 oxide 150C
99.9%99%90%
50%
10%
1%
On-Wafer testing, results obtained in a few hoursSharp Weibull indicates good oxide quality for all devices
F-N tunneling
Oxide breakdown
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101.2 RAMPED TDDB: Gen3 oxide, Ncaps (15 VGS use), ~250 parts, 150°C
IG-VG, 250 parts, VGS ramp 2 V/s Weibull failure plot
1E-12
1E-10
1E-08
1E-06
1E-04
1E-02
1E+00
0 10 20 30 40 50
Gat
e Le
akag
e (A
)
Gate Voltage (V)
250 Ncaps - G3 oxide 150°C
-7
-6
-5
-4
-3
-2
-1
0
1
2
20 25 30 35 40 45 50 55Ln
(-Ln
(1-F
))Breakdown Voltage (V)
Weibull: G3 oxide, 250 Ncaps, 150°C
99.9%99%90%
50%
10%
1%
0.1%
Gen3 oxide, for 15 VGS use: similar breakdown field & Weibull as Gen2 oxide
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• Varied sweep rates allows calculation
of field acceleration factor, g~38 nm/V
1Fail time = t(0)*exp(g*(Efail-Euse))
t(0) = dt/(1-exp(-g*dE)
dt, dE = ramp step time & field
• Ramped TDDB extrapolation (solid blue line) & constant-V TDDB (points) lifetime extrapolations agree
1.2 Ramped TDDB lifetime extrapolation: 2x2mm2 Ncaps (750 devices)
1 H.C. Cramer et al., CS MANTECH, p.91 (2006)
1E+01
1E+02
1E+03
1E+04
1E+05
1E+06
1E+07
1E+08
1E+09
15 20 25 30 35 40 45Ti
me
(hrs
)Gate Voltage (V)
TDDB & lifetime extrapolation109
107
105
103
101
constant-V TDDB (points)
Ramped TDDB extrapolation
-7-6-5-4-3-2-10123
42 44 46 48 50 52 54 56
ln(-
ln(1
-F))
Failure Voltage (V)
3296CJX99 Ramped TDDB
Rrate (V/s) 2.00
Rrate (V/s) 0.67
Rrate (V/s) 0.20
Extrapolated TDDB mean fail time at 20 VGS >108 hrs
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What about oxides on thicker, rougher SiC epi, for higher V
devices?
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Confocal/DIC Image of 10 µm thick SiC Epi
250 µm
50 µm
5 µm
1.3 3.3kV SiC MOSFETS
12 nm5 µm
250 µm
Confocal/DIC Image of 30 µm thick SiC Epi
AFM Image of “pit” AFM Depth Profile
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• Each capacitor: 4.31 mm2; Total area tested: 334 capacitors, 14.4 cm2
• Ramped TDDB shows tight failure distribution, similar to that on thinner/smoother SiC epi
1.3 3.3kV SiC EPITAXIAL WAFERS: LARGE Ncap R-TDDB, 150°C
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R-TDDB Weibull plots with varied ramp rates
Linear field accel. factor g~40nm/V
Lifetime extrapolation using measured field acceleration factor
1.3 3.3kV SiC EPITAXIAL WAFERS: R-TDDB LIFETIME EXTRAPOLATION
• 1% failure time >108 hrs• No early failures observed within experimental population
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161.3 3.3kV SiC EPI: R-TDDB LIFETIME & SiC MORPHOLOGY
• Two earliest failures do have large macroscopic defects • MOSFETs fabricated on these defects will fail routine parametric electrical tests
T1%: > 2∙108 hours
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171.4 10kV SiC epi (~100um thick SiC): LARGE Ncap R-TDDB, 150°C
2.3 mm
2.3
mm
• 250 MOS Capacitors• Total gate area = ~10 cm2
Ramped Breakdown IV curves
• Tight failure distribution
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181.4 10kV SiC epi: Failure voltage independent of surface texture
Extracted capacitor failure voltages
Inset: examples of epi surface texture
• Tight failure distribution despite SiC surface roughness
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• Breakdown extrapolations show that expected oxide lifetime is high (>1×108
hrs) at use voltage (20 VGS Gen2, 15 VGS Gen3)
• Even rough, thicker SiC epi does not impact oxide breakdown significantly
• Thus, oxide trap states or SiC epi defects do not observably impact oxide lifetime
TDDB SUMMARY
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Drain-Field-Related Device Lifetime:
1) High-temperature reverse-bias (HTRB)2) Neutron-induced Single-Event Burnout (SEB)
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212.1 HIGH TEMPERATURE REVERSE BIAS (HTRB)
• JEDEC HTRB Qualification
– 150°C, VDS = 80% of rated voltage (960V for 1200V part)
– 3 Lots x 25 Packaged Devices per Lot, testing for 1000hrs with no fails
– Guarantees part quality, but does not predict ultimate lifetime
• Accelerated tests (VDS >1400V) are needed to determine device lifetime
– Avalanche sets limit to VDS acceleration
0
2
4
6
8
10
12
0 500 1000 1500 2000
Cu
rre
nt
(mA
)
Drain Bias (V)
VGS = 0V Avalanche ~1650V
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• 1200V 20A G2 MOSFETs, VGS= 0 V
• Devices stressed at VDS @ 1460V, 1540V, or 1620V
• Extrapolation line gives predicted mean failure time at given VDS (each data point is a mean
failure time)
2.1 HIGH-TEMPERATURE REVERSE-BIAS (HTRB) ACCELERATED TESTING
1E+01
1E+02
1E+03
1E+04
1E+05
1E+06
1E+07
1E+08
1E+09
600 1,000 1,400 1,800
Tim
e (
hrs
)
Drain Voltage (V)
109
107
105
103
101
Extrapolated HTRB mean failure time at 800 VDS ~3x107 hrs (~3,400 yrsLifetime at lower VDS cannot be directly measured (time too long)
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What about impact of neutron single-event burnout (SEB)?
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• The high energy flux of neutrons from Cosmic radiation (terrestrial neutrons) can cause burnout in devices with high drain fields
Failure Mechanisms in Literature
• Parasitic NPN turn-on, single-event burnout (SEB) if impact is near source
• Single-event gate rupture (SEGR) if impact is near gate and gate field is high
• Either failure results in a localized device thermal runaway
• If testing is not accelerated, would need thousands of parts monitored in blocking for many years
3.1 Single-Event Effects (SEE) due to terrestrial Neutrons
P.C. Adell, L.Z. Scheick, IEEE TNS 60, 1929 (2013).
SEB SEGR
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• Los Alamos National Lab Neutron source at LANSCE; test acceleration of ~109 X that at sea level (S. Wender, LANL 2013)
• Test groups of devices at given VDS to failure
• Calculate failures in time FIT (per 109
device*hrs) scaled to sea level N flux
3.1 Single-Event Burnout (SEB) due to terrestrial Neutrons
• No lifetime extrapolation required
we measure actual failure rate due to N
irradiation at device use fields
• Failure rate data fitting: we follow a
simplified ABB formula (H.R. Zeller
1995; & ABB Appl. note 5SYA 2046-03):
FIT = C3*exp(C2/(C1-VDS))
Where
C3 A,r
C2 = VDS to reach asymptotic regime
C1 = VDS failure onset / threshold
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263.1 MEASUREMENT SETUP
• 6 devices/holder (2 holders max)
• VDS monitored during run; failure time correlated to measured N fluence
• Re-load fresh devices, apply VDS, run until fail
• Repeat to get enough VDS points for predicting FIT vs VDS
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• For each VDS group, the failures occur at a ~constant rate with time
•
formed in the active area due to material overheating
3.2 GENERAL FAILURE BEHAVIOR
0
10
20
30
40
50
60
70
80
90
100
0E+00 1E+10 2E+10
% s
urv
ivin
g
N fluence (N/cm2)
1200V diode: failures per VDS test group
900
1000
1100
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• FIT vs VDS for 7 different Cree SiC MOSFET device ratings
• All scale similarly with Active area & drift field (~avalanche breakdown)
3.2 UNDERSTANDING FIT RATES: ACTIVE AREA & DRIFT DESIGN
0.1
1
10
100
1000
10000
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Sea
leve
l FIT
/cm
2
VDS/Vaval
Wolfspeed MOSFETs
C3M0065090X3M0010090C2M0025120C2M0080120C2M0045170C2M1000170X3M00453300.1
1
10
100
1000
10000
100000
400 1000 1600 2200 2800 3400
Sea
leve
l FIT
/cm
2
Drain-Source Voltage, VDS (V)
C3M0065090X3M0010090C2M0080120C2M0025120C2M1000170C2M0045170X3M0045330
TJ = 25 °C
3.3kV MOSFET
900V MOSFET 1200V
MOSFET
1700V MOSFET
no fails
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• FIT vs VDS for Cree 1200V SiC MOSFET & Diode
• Both device types scale similarly
•
3.3 FIT RATES: MOSFET vs DIODE
0.1
1
10
100
1000
10000
600 800 1000 1200 1400
FIT/
cm2
Voltage (V)
Sea-level Neutron FIT/cm2
TJ = 25 °C
C2M0080120 1200V
MOSFET
C4D020120 1200V Diode
0.1
1
10
100
1000
10000
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1FI
T/cm
2
VD / Vaval
Sea-level Neutron FIT/cm2
TJ = 25 °C
C2M0080120 1200V MOSFET
C4D020120 1200V Diode
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Devices Compared:
• All devices show ~similar performance when scaled by area & field (drift field dominates)
3.4 SiC MOSFETS: CREE vs ROHM, MICROSEMI, STMICRO
0.1
1
10
100
1000
10000
100000
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
FIT/
cm2
VDS / Vaval
SiC MOSFET comparisonSTMicro 1200V 240mohmWolfspeed 1200V 75mohmMicrosemi 1200V 80mohmWolfspeed 1700V 20mohmRohm 1200V 160mohmRohm Tr1200V 40mohm
Devices V ratingR rating (mohm)
Vaval(approx.)
Wolfspeed 1200 75 1560Wolfspeed 1700 20 1660
Rohm 1200 160 2250Rohm 1200 40 1900
Microsemi 1200 80 1850STMicro 1200 240 1300
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• Si parts show sharper failure onset, but higher max failure rate
• SiC & Si parts may require derating to ~900VDS; but SiC is best at higher VDS
3.5 SiC vs Si: 1200V Cree MOSFET vs Infineon Si IGBT4
0.001
0.01
0.1
1
10
100
700 800 900 1000 1100 1200 1300
Sea
leve
l FIT
/Am
p
Drain-Source Voltage, VDS (V)
0/6 failed
TJ = 25 °C
Wolfspeed SiC MOSFET
1200V 25mohm 0/6
failed
InfineonSi IGBT4
1200V 60A
A comparison of ‘Si’ versus ‘SiC’ material radiation hardness is not a fair way to understand this data, as SiC parts have many orders of magnitude longer
lifetime than Si at the same drift fields
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Oxide breakdown (TDDB)
• Intrinsic behavior shows that good oxide lifetime can be expected on SiC, despite interface traps and SiC defects
• Thick epi with increased roughness has virtually no impact on the MOS oxide lifetime
High-energy Neutron Single-event burnout
• SiC diode & MOSFET lifetime is dominated by the drift field and the active area
• The VDS derating for Si and SiC devices may be ~similar, but this does not diminish the many performance advantages of SiC devices
• Device design modifications may further improve the radiation hardness of SiC devices (Si rad-hard device design is more mature)
SUMMARY
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Powering More.Consuming Less.