Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF,...

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Shuvra S. Bhattacharyya Department of Electrical and Computer Engineering, and Institute for Advanced Computer Studies University of Maryland, College Park, MD, USA [email protected] , http://www.ece.umd.edu/~ssb/ With contributions from Chia-Jui Hsu, Mary Kiemb, William Plishker, Sankalita Saha ,and Nimish Sane Summer School on Models for Embedded Signal Processing Systems, Lorentz Center, Leiden, The Netherlands, Aug 30 – Sep 3, 2010.

Transcript of Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF,...

Page 1: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Shuvra S. Bhattacharyya Department of Electrical and Computer Engineering, and

Institute for Advanced Computer Studies University of Maryland, College Park, MD, USA [email protected], http://www.ece.umd.edu/~ssb/

With contributions from Chia-Jui Hsu, Mary Kiemb, William Plishker, Sankalita Saha ,and Nimish Sane

Summer School on Models for Embedded Signal Processing Systems, Lorentz Center, Leiden, The Netherlands, Aug 30 – Sep 3, 2010.

Page 2: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Module Outline

•  Dynamic Dataflow Graphs •  Parameterized Dataflow Graphs •  Cross Platform Project Development

– DICE – Hands-on Session

Page 3: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Dynamic Dataflow Graphs: Outline

•  Dynamic dataflow background •  Representative dynamic dataflow models of

computation –  Boolean dataflow (BDF) –  Stream-based functions (SBF) –  Enable-invoke dataflow (EIDF)

•  Design Tool Example: Support in the dataflow interchange format for EIDF Functional DIF

Page 4: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Background: Dataflow graphs

X Y 5 Z 2 1 1 1 D

•  Vertices (actors) represent computation •  Edges represent FIFO buffers •  Edges may have delays, implemented as initial

tokens •  Synchronous dataflow (SDF)

–  The number of data values (tokens) produced and consumed by each actor is fixed

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Modeling Design Space

X PSDF

X PCSDF

E x

p r e

s s i

v e

p o

w e

r

Verification / synthesis power

X C, BDF, DDF

X SDF

X CSDF

X CSDF, SSDF MDSDF,

WBDF

X

Other important “dimensions” include intuitive appeal, legacy support, and productivity …

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Dynamic Dataflow Graphs

•  Production and consumption rates of actors can vary in ways that are not entirely predictable at compile time

•  Under such a classification, CSDF, for example is not considered “dynamic” even though different phases can have different production and consumption behavior

•  Dynamic dataflow models of computation are usually not decidable models, although this is not always the case –  E.g., well-behaved dataflow (WBDF) is an

exception

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Dynamic Dataflow Models •  Most dynamic dataflow models are Turing

complete •  They differ in how the actor and communication

functionality is structured or constrained … for example … –  Interfaces to enclosing schedulers –  Abstractions that lead to different types of application

programming interfaces –  The granularity or style of formal specification

required to handle the same functionality •  They influence the kinds of analysis techniques

and synthesis styles that are targeted

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Boolean Dataflow (BDF) [Buck 1993] •  Turing complete dynamic dataflow model •  BDF actors can be SDF actors (“static BDF

actors”) or “dynamic BDF actors” •  Dataflow behavior of dynamic BDF actors is

determined by designated control ports •  Dynamic BDF actors: switch and select •  Quasi-static scheduling techniques can

automatically derive compact software control structures from certain kinds of BDF subsystems

Page 9: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Dynamic BDF Actors: Basic Definitions

•  Control tokens: two-valued (Boolean data) •  Control ports: actor ports that are designated

for consuming or producing control tokens – Control input port: consumption rate is 1 – Control output port: production rate is 1

•  Conditional input port: consumption rate is a function of a control token value from a corresponding control input port

Page 10: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Conditional Output Ports

•  The production rate for a conditional (dynamic) output port can be controlled by a control input port or a control output port

•  For an input-controlled output port, the production rate is a function of the Boolean value consumed on the corresponding control input

•  For an output-controlled output port, the production rate is a function of the Boolean value produced on the corresponding control output

Page 11: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Switch and Select Actors

•  wc is a control input port •  wd is a homogenous SDF input port •  wx and wy are conditional output ports

•  sc is a control input port •  sx and sy are conditional input ports •  so is a homogeneous SDF output port

•  SDF + {Swtich, Select} is Turing Complete

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Switch and Select: Dynamic Data Rate Functions

Data(wc) Prod(wx) Prod(wy) F 1 0 T 0 1

Data(sc) Cons(sx) Cons(sy) F 1 0 T 0 1

Switch actor: Production rate functions of conditional output ports

Select actor: Consumption rate functions of conditional input ports

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If-Then-Else Construct in BDF

U

V

if (U[i]) { fB(wd[i]) V[i] } else { fA(wd[i]) V[i] }

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BDF Summary •  Turing complete dynamic dataflow model •  BDF actors can be SDF actors (“static BDF

actors”) or “dynamic BDF actors” •  Dataflow behavior of dynamic BDF actors is

determined by designated control ports •  Dynamic BDF actors: switch and select •  Quasi-static scheduling techniques can

automatically derive compact software control structures from certain kinds of BDF subsystems

•  Natural generalization to integer-valued control tokens [Buck 1994]

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Stream-based Functions (SBF) [Kienhuis and Deprettere 2001]

•  Also Turing complete •  Actors are decomposed into mutually

exclusive functions and control logic •  Motivated by Compaan toolset

– Distributed memory, distributed control –  FPGA mapping

•  General formulation is abstract and implementation-independent

Page 16: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Stream Based Functions (SBF): Actor Model

•  Function repertoire: a set of functions that can characterize the behavior of an actor firing

•  These are mutually exclusive functions •  Controller: transition and selection function •  Private memory: combined function and

data state •  Actors synchronize with blocking reads •  … and blocking writes (in practical

implementations)

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Architecture of an SBF Actor

Fire and exit behavior: An actor controller repeatedly executes actors from the function repertoire until the application deadlocks or is terminated through external control a sequence of mathematical function executions from the function repertoire

Page 18: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Merging of SBF Actors with a Unified Thread of Control

Page 19: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Application of SBF

•  A deterministic, dynamic dataflow model •  Developed in the context of the Compaan

Project (Leiden University) •  Naturally provides the distributed-control and

distributed-memory implementation styles that are emphasized in Compaan

•  Powerful dataflow-oriented analysis techniques have been developed for mapping Compaan programs into parallel implementations

Page 20: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Dynamic Dataflow Graphs: Outline

•  Dynamic dataflow background •  Representative dynamic dataflow models of

computation –  Boolean dataflow (BDF) –  Stream-based functions (SBF) –  Enable-invoke dataflow (EIDF)

•  Design Tool Example: Support in the dataflow interchange format for EIDF Functional DIF

Page 21: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Dataflow Interchange Format (DIF): Objectives [Hsu 2005]

1.  Design a standard language for specifying dataflow semantics. •  Dataflow Interchange Format •  Keywords associated with specific dataflow MoCs

2.  Develop a software package for working with and developing dataflow models, and dataflow-oriented transformations •  The DIF package •  Functional DIF

3.  Facilitate transferring DSP applications across dataflow-based design tools. •  The DIF porting mechanism

4.  Automate hardware/software implementation of DSP system designs from dataflow modeling specifications. •  The DIF-to-C software synthesis framework •  DIF-to-VSIPL synthesis capability

Page 22: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

The DIF Package

•  DIF representation –  Internal structures (Java classes) for representing and

manipulating dataflow graphs.

•  Algorithm implementation –  Dataflow-based analysis, scheduling, and optimization.

•  DIF front-end (language parser) –  Translates between DIF specifications and DIF

representations.

•  Infrastructure –  Porting –  Software

synthesis

Page 23: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Components of the DIF Project •  The DIF Language (TDL)

–  Scalable specification of DSP-oriented dataflow models

–  Vendor neutral textual design language for specifying mixed granularity dataflow graphs

•  The DIF Package (TDP) –  Analysis strategies – Optimization engines –  Functional simulation (Functional DIF) –  Software synthesis

•  “Lite” version of DIF available from http://www.ece.umd.edu/DSPCAD/dif/index.htm

Page 24: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Functional DIF Overview •  Motivation

–  The DIF language has formal semantics for various forms of dataflow

–  The DIF intermediate representation is coupled with analyzers, a software synthesizer, and porting mechanisms to/from other design environments

–  Functional DIF provides the DIF environment with inline functional simulation, and facilities rapid prototyping, and experimentation with modeling/transformation co-design

•  Functional DIF extends DIF with –  Natural actor description –  Efficient interface for prototyping static, quasi-static, and

dynamic schedulers, and heterogeneous schedulers for different specialized dataflow models

–  Semantic foundation for simulating non-deterministic and deterministic dataflow applications

Page 25: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Writing actors in Functional DIF •  Divide actors into sets of modes

–  Each mode has a fixed consumption and production behavior •  Write the enabling conditions for each mode •  Write the computation associated with each mode

–  Including next mode to enable and then invoke •  For example, consider a standard switch actor:

Control Mode

True Mode

False Mode

Production & consumption behavior of switch modes

Mode transition diagram between switch modes Switch Actor

Switch

1

1

[1,0]

[1,0] False Output

True Output

Control

Data

Page 26: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Semantic Foundation: Enable-Invoke Dataflow [Plishker 2008]

•  Enable-Invoke Dataflow (EIDF) –  Enabling Function, ε, for an actor, a:

•  Ta, the number of input tokens on each edge •  Ma, the set of modes associated with actor a •  B is the Boolean set of {true, false}

–  Invoking function, κ (Non-Deterministic)

•  Ia,Oa, input and output tokens consumed and produced by this mode

•  Pow(Ma), set of valid next modes

•  Core Functional Dataflow (CFDF) •  Restrict invoking function to be deterministic by ensuring only one unique

next mode:

Page 27: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Relationship to SBF •  EIDF modes are similar to functions in SBF, except that

there is no separate controller controller functionality is integrated into the mode abstraction

•  In EIDF, elimination of blocking reads within mode execution, and the separation of enable and invoke APIs are requirements (first class citizens) of the model

•  Actor execution in EIDF is controlled through these APIs •  EIDF allows for multiple next modes, and associated non-

determinism •  EIDF-like separation of enable and invoke functionality

can be adapted to implement SBF •  The fire-and exit representation of SBF actor execution

can be adapted as a useful mathematical characterization for EIDF (CFDF) actors

•  Migrating designs between the models should be relatively easy

Page 28: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Dataflow-Based FPGA Implementation: A Design Flow

Dataflow graph application or subsystem model

C-based actor libraries for simulation and co-design

Functional unit testing

HDL-based actor libraries for FPGA implementation

Implementation-oriented unit testing

Graph-level functional validation

Canonical (“simple”) scheduler

Self-timed scheduling and buffer mapping

Graph-level implementation validation

Graph transformations and analysis

Page 29: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

The Role of Simulation Models

•  Implementation-independent functional (“golden”) reference

•  Rapid prototyping •  Design reuse (object-oriented components) •  Streamline debugging of functional aspects •  All of these help to make designers more

productive, and designs more reliable

Page 30: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Semantic Hierarchy

•  EIDF is a refinement of DIF Graphs that captures basic dataflow features (nodes, edges, tokens, etc.)

•  CFDF restricts EIDF to deterministic dataflow applications

•  Many popular forms of dataflow are directly supported by CFDF –  SDF needs only one mode –  CSDF phases correspond to

different modes

•  Functional DIF integrates CFDF into the DIF package

Page 31: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Functional DIF Schedule Tree

•  Represents a schedule as a tree with internal nodes representing iteration counts

•  Leaves represent actor invocations

•  Execution may be guarded using the enabling function of CFDF

Example GST of a CFDF application

Subtree iterations

Guarded actor invocations

Page 32: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Functional DIF Application Design Features

•  Supports Heterogeneous Composition

•  No need for blocking reads

•  FDIF Schedule Tree –  Canonical, functionally

correct schedules can be built automatically regardless of dataflow model mixes within CFDF

•  Heterogeneous Simulator –  Simulating is as simple

as walking the schedule tree

Example design using CSDF and BDF

Example GST of a CFDF application

Subtree iterations

Guarded actor invocations

Page 33: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Results: Polynomial Evaluation Accelerator (PEA)

•  Polynomial evaluation is a commonly used primitive in the digital communication domain.

•  The degree of P and the coefficients can change at run time.

•  There are four types of instructions. –  Reset (RST), Store Polynomial (STP), Evaluate

Polynomial (EVP), Evaluate Block (EVB)

Page 34: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Dataflow Modeling of PEA Testbench

Polynomial Evaluation Accelerator

Control Input Buffer

Result Output Buffer

Data Input Buffer

Status Output Buffer

Page 35: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

The Modes in PEA Mode behavior Consumption Production

Control Data Result Status Normal Wait for an instruction 1 0 0 0

RST Reset all of the coefficients

0 0 0 0

STP Store coefficients 0 1 0 1 EVP Evaluate the value of P 0 1 1 1 EVB Evaluate block 0 1 1 1

Mode execution in general affects the internal state (coefficient storage, block count, etc.) of the actor as well as the state of incident FIFOs

Page 36: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

PEA Results

Simulation times of Verilog and Functional DIF for two different sets of instructions

Provides for efficient functional debugging/validation of dataflow modeling architecture before migration to hardware

Page 37: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Functional DIF Summary

•  Extends DIF with functional simulation by –  Actor design considerations –  Semantic foundation for execution –  Supporting simulation and scheduling in the DIF

package •  Simulation speeds better than Verilog •  Ongoing work

– Hardware and and software synthesis –  Parameterization of CFDF

Page 38: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Problem: tools miss important opportunities for optimization of dynamic applications

•  Standard practice for dynamic scheduling: –  Islands of static behavior –  Probabilistic analysis –  …but this misses overlapping static

regions, leading to suboptimal performance and excess resource allocation

•  DIF now facilitates finding these through: –  A new dynamic dataflow model: Core

Functional Dataflow (CFDF) –  Mode grouping –  Generalized scheduling

•  Up to 37% improvement in buffer memory requirements

Traditional: dynamic dataflow

with “static islands”

New: dynamic dataflow with overlapping static regions

Static

Static

Static

Static

Page 39: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Generalized scheduling: apply traditional static scheduling to dynamic applications

•  Describe application in CFDF •  Create static chains of modes (mode

graphs) •  Schedule mode graphs to FDIF Schedule

Trees using traditional Synchronous Dataflow (SDF) schedulers

•  Simulate with guarded execution

•  B-Spline example: –  No non-trivial static islands found –  5 mode graphs found by grouping

modes with cyclic mode transitions

Page 40: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

Dynamic Dataflow Graphs: Summary

•  Dynamic dataflow background •  Representative dynamic dataflow models of

computation –  Boolean dataflow (BDF) –  Stream-based functions (SBF) –  Enable-invoke dataflow (EIDF)

•  Design Tool Example: Support in the dataflow interchange format for EIDF Functional DIF

•  For Further Reading …

Page 41: Shuvra S. Bhattacharyya - Lorentz Center · 2010-09-02 · Verification / synthesis power X C, BDF, DDF X SDF X ... Example design using CSDF and BDF ... Simulation times of Verilog

For Further Reading

In Part 4 (Design Methods): S. S. Bhattacharyya, E. F. Deprettere, and J. Keinert. Dynamic and multidimensional dataflow graphs. In S. S. Bhattacharyya, E. F. Deprettere, R. Leupers, and J. Takala, editors, Handbook of Signal Processing Systems. Springer, 2010. To appear.