Short Channel Bandgap Voltage Reference

EE-584 Final Report

Authors:

Thymour Legba Yugu Yang

Chris Magruder Steve Dominick

Table of Contents Table of Figures .................................................................................................................. 3 Abstract ............................................................................................................................... 4 Introduction......................................................................................................................... 5 Theory and Circuit Parameters ........................................................................................... 5 Simulation Results ............................................................................................................ 10

Vdd Sweep ..................................................................................................................... 10 Center........................................................................................................................ 10 Corners...................................................................................................................... 11 Corners for Fixed Temperature................................................................................. 12

Temperature Sweep ...................................................................................................... 13 Center........................................................................................................................ 13 Corners...................................................................................................................... 14 Corners for Fixed Vdd ................................................................................................ 15

Circuit Parameters............................................................................................................. 15 Layout ............................................................................................................................... 18 Conclusions....................................................................................................................... 21

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Table of Figures Figure 1: Circuit Schematic ................................................................................................ 6 Figure 2: Current Mirror Schematic ................................................................................... 7 Figure 3: Schematic for measuring the temperature coefficient ......................................... 7 Figure 4: Temperature coefficient measurements............................................................... 8 Figure 5: Bandgap Schematic ............................................................................................. 9 Figure 6: Vref vs. VDD, Typical ...................................................................................... 10 Figure 7: Vref vs. VDD, Typical ...................................................................................... 11 Figure 8 Fast Slow Corner ................................................................................................ 12 Figure 9 Fast Fast Corner.................................................................................................. 12 Figure 10 Slow Slow Corner............................................................................................. 12 Figure 11 Slow Fast Corner .............................................................................................. 12 Figure 12: Vref vs. VDD, Corners.................................................................................... 13 Figure 13: Vref vs. Temperature....................................................................................... 14 Figure 14 Fast Slow Corner .............................................................................................. 14 Figure 15 Fast Fast Corner................................................................................................ 14 Figure 16 Slow Slow Corner............................................................................................. 14 Figure 17 Slow Fast Corner .............................................................................................. 14 Figure 18: Vref Vs. Temperature, Corners ....................................................................... 15 Figure 19: Vref vs. VDD, Channel Length = 2 ................................................................ 16 Figure 20: Vref vs. Temperature, Channel Length = 2..................................................... 17 Figure 21: Vref vs. VDD, Varying R................................................................................ 17 Figure 22: Temperature vs. VDD, Varying R................................................................... 18 Figure 23: NMOS Resistor Schematic.............................................................................. 19 Figure 24: Channel Resistance vs. VDD, Channel Width = 2.......................................... 20 Figure 25: Channel Resistance vs. VDD, Channel Width = 20........................................ 20 Figure 26: Channel Resistance vs. VDD, Channel Width = 200...................................... 21

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Abstract This paper describes the design of a bandgap reference voltage, implemented in

Cypress’ Ram7 CMOS technology using the Cadence IC fabrication design tool. The circuit provides a reference voltage of 500mV and has a temperature coefficient of - 2.31mV/˚C. It can operate with supply voltages within 5% of VDD at temperature varying from 0˚C to 50˚C in a typical process. This circuit shows to operate better in a slow-slow corner than in a typical corner; however, its range of operation in the fast-fast corner is significantly small. A startup circuit is required for a good operation of the system.

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Introduction Voltage reference circuits are commonly used as parts of analog-to-digital

converters (ADCs) or digital-to-analog converters (DACs) to design the input or output voltage ranges. The main goal of this design project is to generate a fixed reference voltage, Vref, which exhibits a very small dependence on power supply voltage VDD, temperature and also process parameters such as different corners (fast-fast, slow-slow, typical, fast-slow and slow-fast). In this design, a short-channel bandgap reference voltage was implemented with a power voltage supply VDD set to 1. 8 V and a desired Vref set to 500 mV. The circuitry of this device was divided into three essential components, a start–up circuit that allows to avoid the situation where zero current flows in the reference1, a self-biased differential amplifier and finally a combination of NMOS, PMOS, resistors and BJTs that forced current in each branch to be equal, and made the Vref much less sensitive to changes in VDD and temperature. This last part of the circuit block was implemented by using two essential circuits. The first part was made of two parasitic BJT diodes D1 and D2 (with an M factor of 1000), whose temperature coefficient was determined through simulations, and combined with a resistor R that would force Vref to be proportional to absolute temperature (PTAT). The second part was made of two resistors L.R where resistor R is sized by a factor of L determined through simulations and parameter calculations, and that would force Vref to be complementary to absolute temperature (CTAT). The combination of these two circuits yields an overall design that produced a Vref relatively independent of temperature (in a certain range), and voltage supply VDD depending on process corners. Temperature was swept from -50˚C to 125˚C to observe temperature dependence of the bandgap reference voltage, while VDD was swept from 0V to 5 V to observe voltage supply dependence. An N.R resistance (N derived from parameter calculations) was used and trimmed to obtain the desired output voltage of approximately 500 mV. The next sections will describe and discuss the results of the bandgap circuit in details, present steps to determine parameters (temperature coefficient, R, L, N), discuss Vref simulations at different corners for a VDD sweep while holding temperature constant, and temperature sweep while holding VDD constant.

Theory and Circuit Parameters The schematic is based on Figure 1 modified from the circuit in textbook. The

differential amplifier is to force the same current through transistor M1, M2 and M3. In order to minimize the voltage difference between node A and B, M5 should be long channel to obtain small total current flowing through the diff-amp. The start-up circuit is to bring the reference to the desired state when the gate voltages on M1 and M2 are low. Since no current drawn by the start-up circuit is desired once the reference is stabilized,

1 CMOS Circuit Design, Layout, and Simulation , R. Jacob Baker, pp.752

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the transistor M4, which is on in steady state, is required to be long channel. Parallel connection of K diodes (D2, same size as D1) is to avoid zero current flowing through the circuit. Because the current through1I R and D2 is proportional to absolute temperature (PTAT) and the current though2I RL ⋅ is complementary to absolute temperature (CTAT), the total current can be designed to change little with temperature, resulting in almost zero temperature coefficient of reference voltage.

REFI

Figure 1: Circuit Schematic In order to determine the parameters (L, N and R) in the circuit, first step was to measure the current flowing through one branch of the current mirror shown as in Figure 2. The minimum channel length was used for the normal transistors and W/L (5 for PMOS and 2.5 for NMOS) was kept the same as provide by textbook. For the long channel transistors, W/L was set to 2.5/25. The current were simulated with different resistance values and the average current of was measured. Then this current value was used as the current supply in the circuit as shown in

nA3.1Figure 3 to get the temperature coefficient

of the parasitic PNP. The output voltages were measured at different temperatures and simulation data is shown is Figure 4. The temperature coefficient was estimated to be . CmV /31.2−

6

Figure 2: Current Mirror Schematic

Figure 3: Schematic for measuring the temperature coefficient

7

556

559

562

565

568

26. 5 27 27. 5 28 28. 5 29 29. 5

t emper at ur e/ C

volt

age/

mV

Figure 4: Temperature coefficient measurements

The following equations from textbook were used to calculate the parameters needed

for output reference voltage mVVREF 500= .

I

KnVR T ln⋅=

085.0ln

31.2⋅⋅

=Kn

L

LVKnV

VND

T

REF

+⋅=

ln

K was set to be 1000 and n was assumed to be 1 in the calculation. The calculated values are , , . Based on the calculated values, smaller resistors were tried in simulation, and the smallest resistance values that keep the bandgap circuit working properly were used in the final schematic. To adjust the reference voltage to be 500mV, the resistor

Ω= 838.1 ER 36.5=N 58.13=L

RN ⋅ was also trimmed. Figure 5 shows the final schematic simulation. Table 1 gives the parameter values used in the final schematic.

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Figure 5: Bandgap Schematic

Table 1: parameter values

R ( ) Ω L N K

8E7 13.58 5.36 1000

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Simulation Results To evaluate the performance of the bang gap circuit simulations were run across corners to test the impact of VDD on Vref and temperature on Vref.

VDD Sweep The sweeps of VDD for each corner were performed for three different temperatures 0˚C, 27˚C, and 50˚C to show how the temperature affects performance.

Center Vref vs Vdd, Center

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1.00E+00

2.00E+00

3.00E+00

4.00E+00

5.00E+00

6.00E+00

0.00E+00 1.00E+00 2.00E+00 3.00E+00 4.00E+00 5.00E+00 6.00E+00

Vdd (V)

Vref

(V)

50C 27C 0C Figure 6: Vref vs. VDD, Typical

In Figure 6 there is a constant Vref starting between 1V-2V. Figure 7 looks closer at that region in Figure 6 where the circuit is operating as a band gap.

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Vref vs Vdd, Center

0.00E+00

2.00E-01

4.00E-01

6.00E-01

8.00E-01

1.00E+00

1.20E+00

1.40E+00

0.00E+00 5.00E-01 1.00E+00 1.50E+00 2.00E+00 2.50E+00

Vdd (V)

Vref

(V)

50C 27C 0C Figure 7: Vref vs. VDD, Typical

In the area of band gap operation Figure 6 and 7 show very little change in the amplitude of Vref as temperature changes. However, the figures do show that temperature affects when the band gap circuit ‘turns on’, and the higher the temperature, the faster the bandgap ‘turns on’.

Corners The band gap circuit was tested across the following process corners: Fast Fast, Slow Slow, Fast Slow, and Slow Fast.

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Vref vs. Vdd, Fast Slow Corner

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1.00E+00

2.00E+00

3.00E+00

4.00E+00

5.00E+00

6.00E+00

0.00E+00 1.00E+00 2.00E+00 3.00E+00 4.00E+00 5.00E+00 6.00E+00

Vdd (V)

Vref

(V)

50C 27C 0C

Figure 8 Fast Slow Corner

Vref vs. Vdd, Fast Corner

0.00E+00

1.00E+00

2.00E+00

3.00E+00

4.00E+00

5.00E+00

6.00E+00

0.00E+00 1.00E+00 2.00E+00 3.00E+00 4.00E+00 5.00E+00 6.00E+00

Vdd (V)

Vref

(V)

50C 27C 0C Figure 9 Fast Fast Corner

Vref vs. Vdd, Slow Corner

0

1

2

3

4

5

6

0 1 2 3 4 5 6

Vdd (V)

Vref

(V)

50C 27C 0C Figure 10 Slow Slow Corner

Vref vs. Vdd, Slow Fast Corner

0.00E+00

1.00E+00

2.00E+00

3.00E+00

4.00E+00

5.00E+00

6.00E+00

0.00E+00 1.00E+00 2.00E+00 3.00E+00 4.00E+00 5.00E+00 6.00E+00

Vdd (V)

Vref

(V)

50C 27C 0C

Figure 11 Slow Fast Corner

Testing the circuit across corners shows that for the slow slow corner in Figure 10 the band gap circuits Vref stays constant for a larger VDD ranger. The fast fast corner behaves like a band gap for the smallest range of VDD.

Corners for Fixed Temperature Figure 12 shows the effects of corners at 27˚C. When looking at how corners affects operation it seems that slower the corner the more to the right the curve is. This is true except for when the band gap turns on. In Figure 12, the slow slow corner ‘turns on’ before the slow fast corner. Also, as the corners change, there is only a slight change in the amplitude of Vref in the band gap operation region. .

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Vref vs. Vdd at 27 C

0.00E+00

1.00E+00

2.00E+00

3.00E+00

4.00E+00

5.00E+00

6.00E+00

0.00E+00 1.00E+00 2.00E+00 3.00E+00 4.00E+00 5.00E+00 6.00E+00

Vdd (V)

Vref

(V)

Fast Fast Slow Center Slow Fast Slow Figure 12: Vref vs. VDD, Corners

Temperature Sweep To analyze the temperature dependence of the band gap circuit a sweep between -50C and 125C was performed to see for fixed VDD where Vref would remain at 500 mV.

Center Three VDD values were examined 1.62 V, 1.8 V, and 1.92 V. This is the 10% range of Ram 7 VDD which is 1.8 V. The curves in Figure 13 show that the lower the VDD affects what temperature the band gap circuit turns on. Therefore the lower the VDD the higher the minimum temperature for band gap operation.

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Vref vs Temp, Center

0.00E+00

2.00E-01

4.00E-01

6.00E-01

8.00E-01

1.00E+00

1.20E+00

1.40E+00

1.60E+00

1.80E+00

-6.00E+01 -4.00E+01 -2.00E+01 0.00E+00 2.00E+01 4.00E+01 6.00E+01 8.00E+01 1.00E+02 1.20E+02 1.40E+02

Temp (C)

Vref

(V)

1.98 Vdd 1.8 Vdd 1.62 Vdd Figure 13: Vref vs. Temperature

Corners Vref vs. Temp, Fast Slow Corner

0.00E+00

2.00E-01

4.00E-01

6.00E-01

8.00E-01

1.00E+00

1.20E+00

1.40E+00

1.60E+00

1.80E+00

2.00E+00

-6.00E+01 -4.00E+01 -2.00E+01 0.00E+00 2.00E+01 4.00E+01 6.00E+01 8.00E+01 1.00E+02 1.20E+02 1.40E+02

Temp (C)

Vref

(V)

1.98 Vdd 1.8 Vdd 1.62 Vdd Figure 14 Fast Slow Corner

Vref vs. Temp, Fast Corner

0

0.5

1

1.5

2

2.5

-60 -40 -20 0 20 40 60 80 100 120 140

Temp (C)

Vref

(V)

1.98 Vdd 1.8 Vdd 1.62 Vdd Figure 15 Fast Fast Corner

Vref vs. Temp, Slow Corner

0.00E+00

1.00E-01

2.00E-01

3.00E-01

4.00E-01

5.00E-01

6.00E-01

7.00E-01

8.00E-01

9.00E-01

-6.00E+01 -4.00E+01 -2.00E+01 0.00E+00 2.00E+01 4.00E+01 6.00E+01 8.00E+01 1.00E+02 1.20E+02 1.40E+02

Temp (C)

Vref

(V)

1.98 Vdd 1.8 Vdd 1.62 Vdd Figure 16 Slow Slow Corner

Vref vs. Temp, Slow Fast Corner

0.00E+00

2.00E-01

4.00E-01

6.00E-01

8.00E-01

1.00E+00

1.20E+00

1.40E+00

1.60E+00

-6.00E+01 -4.00E+01 -2.00E+01 0.00E+00 2.00E+01 4.00E+01 6.00E+01 8.00E+01 1.00E+02 1.20E+02 1.40E+02

Temp (C)

Vref

(V)

1.98 Vdd 1.8 Vdd 1.62 Vdd Figure 17 Slow Fast Corner

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The performance of the band gap circuit over temperature shows that a period of constant Vref can be achieved. However the corners show a large variation in how the device performs. In each corner the PTAT and CTAT aspects can be seen. The slow slow corner in Figure 16 Slow Slow Corner, shows the best behavior as a band gap circuit.

Corners for Fixed Vdd

Figure 18 shows how going across corners changes the performance of the circuit for different temperatures. Fixing the Vdd at 1.8 V shows that the bang gap become more like a PTAT reference as the circuit is closer to the fast fast corner. Since the slow slow curve reaches 500 mV before the slow fast curve then the length of the PMOS affects how long the circuit stays at a constant value. The greater the length (slower the PMOS) the longer range is stay at the desired reference voltage.

Vref vs. Temp at Vdd = 1.8

0.00E+00

2.00E-01

4.00E-01

6.00E-01

8.00E-01

1.00E+00

1.20E+00

1.40E+00

1.60E+00

1.80E+00

2.00E+00

-6.00E+01 -4.00E+01 -2.00E+01 0.00E+00 2.00E+01 4.00E+01 6.00E+01 8.00E+01 1.00E+02 1.20E+02 1.40E+02

Temp (C)

Vref

(V)

Fast Fast Slow Center Slow Fast Slow

n

Figure 18: Vref Vs. Temperature, Corners

Circuit Parameters Several circuit parameters were varied in order to attempt to achieve better performance across VDD and temperature in the bandgap circuit. One of these parameters was the channel length of all of the PMOS and NMOS devices. The width/length ratio was held constant as the channel length was increased from 0.5 (min. length) to 2. It was expected that a longer channel length would produce a Vref across a wider range of VDD than the short channel implementation because of the process corner simulations. Simulations in the slow corner, which correspond to a longer channel length, yielded

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more favorable results as discussed in the previous section. Below in Figure 19 is a curve showing the Vref vs. VDD for the longer channel implementation at 27ºC.

Vref vs. VDD

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1.00E+00

2.00E+00

3.00E+00

4.00E+00

5.00E+00

6.00E+00

0 1 2 3 4 5

VDD (V)

Vref

(V)

6

Channel Length = 2

Figure 19: Vref vs. VDD, Channel Length = 2

For the longer channel device, a Vref of 480mV ±5% was maintained for a VDD from 1.3V to 2.58V. This is a wider range than was achieved using the short channel implementation. The temperature response of the longer channel implementation (with a VDD of 1.8V) was also measured, and shown below in Figure 20. This figure shows that the device operates over a wider range of temperatures but has a greater temperature dependency in the valid range. The circuit maintains 480mV ±5% over a range of temperatures from -18ºC to 80ºC.

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Vref vs. Temperature

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0.10

0.20

0.30

0.40

0.50

0.60

-50.00 -30.00 -10.00 10.00 30.00 50.00 70.00 90.00 110.00 130.00 150.00

Temperature (C)

Vref

(V)

Channel Length = 2

Figure 20: Vref vs. Temperature, Channel Length = 2

Another circuit parameter that was examined was the resistance values. The resistors used are quite large, and it would much more practical from a layout standpoint to have resistors on the order of 100kΩ rather than 100MΩ. All resistors in the circuit are scaled by a common resistance R. The temperature and VDD response of the circuit was measured as R changed by orders of magnitude. The results of these simulations are shown below.

Vref vs. Vdd

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2.00E+00

3.00E+00

4.00E+00

5.00E+00

6.00E+00

0 1 2 3 4 5 6

Vdd (V)

Vref

(V)

R = 8E4 Ohms R = 8E5 Ohms R = 8E6 Ohms R = 8E7 Ohms R = 8E8 Ohms

Figure 21: Vref vs. VDD, Varying R

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Temperature vs. Vref, Vdd = 1.8V

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2.00E-01

4.00E-01

6.00E-01

8.00E-01

1.00E+00

1.20E+00

1.40E+00

1.60E+00

1.80E+00

2.00E+00

-50 0 50 100 150

Temperature (C)

Vre

f (V

)

R = 8E4 Ohms R = 8E5 Ohms R = 8E6 Ohms R = 8E7 Ohms R = 8E8 Ohms

Figure 22: Temperature vs. VDD, Varying R

Figure 21 above shows that the VDD at which the circuit turns on is inversely proportional to the size of resistors in the circuit. The minimum temperature at which the circuit can operate as a bandgap reference is also inversely proportional to R, as evidenced by the plot in Figure 22. Therefore, though the resistors used in the circuit are large and impractical using conventional methods, the large values are required in order to operate in the target range of a VDD of 1.8V ±10%.

Only examining the plot in Figure 21, it would appear that the circuit with an R = 8E6Ω has better performance than the one with R = 8E7Ω used in this project. For R = 8E6Ω, a Vref of 445mV ±5% is maintained across a range of VDD from 1.56V to 2.20V. However, when the temperature response is examined in Figure 22, it can be seen that the temperature range is rather impractical at a resistance of this value. The circuit does not exhibit a constant Vref until above a temperature of 26ºC. The optimal solution for the circuit would be to use a resistance of somewhere between these values, where the performance vs. temperature is in a more acceptable range, and the circuit maintains Vref over a wider range of VDD.

Layout Layout was not actually performed for this circuit. However, issues involving layout were examined, specifically the layout of the very large resistors required to make the circuit perform over the required ranges of temperature and VDD. Creating multiple resistors on the orders of magnitude required for this circuit using conventional methods

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such as poly or n-well would take up very large amounts of chip space and be impractical for any real design. However, using an NMOS transistor as a resistor was examined. This would have the advantage of taking up a very small amount of space in the layout of the design. However, the challenge in implementing such a resistor is that the gate and drain voltages of the transistor must be tightly controlled to provide a given resistance. Simulations were run using the circuit shown below in Figure 23 to obtain the relationship of IDS vs. VDD for given gate voltages and channel widths for the NMOS in this process. The resistor of 1Ω was chosen for ease of current calculation using Ohm’s Law, and it is many orders of magnitude smaller than the channel resistance being measured so it has minimal effects on the circuit.

Figure 23: NMOS Resistor Schematic

This circuit was simulated at gate voltages of 0V, 100mV, 200mV, 300mV, 400mV, and 500mV for channel widths of 2, 20, and 200. Once the current IDS was obtained, the resistance across the channel for the VDD sweep was calculated using Rchannel = VDD/IDS. The results of these calculations for channel widths of 2, 20, and 200 are shown in the figures below.

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NMOS Channel Resistance vs. Vdd, Channel Width = 2

1.00E+09

1.00E+10

1.00E+11

1.00E+12

1.00E+13

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Vdd (V)

Log

(Cha

nnel

Res

ista

nce)

(O

hms)

Vgs = 0VVgs = 0.1VVgs = 0.2VVgs = 0.3VVgs = 0.4VVgs = 0.5V

Figure 24: Channel Resistance vs. VDD, Channel Width = 2

NMOS Channel Resistance vs. Vdd, Channel Width = 20

1.00E+07

1.00E+08

1.00E+09

1.00E+10

1.00E+11

1.00E+12

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Vdd (V)

Log

(Cha

nnel

Res

ista

nce)

, Ohm

s

Vgs = 0VVgs = 0.1VVgs = 0.2VVgs = 0.3VVgs = 0.4VVgs = 0.5V

Figure 25: Channel Resistance vs. VDD, Channel Width = 20

20

NMOS Channel Resistance vs. Vdd, Channel Width = 200

1.00E+06

1.00E+07

1.00E+08

1.00E+09

1.00E+10

1.00E+11

1.00E+12

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Vdd (V)

log

(Cha

nnel

Res

ista

nce)

, ohm

s

Vgs = 0VVgs = 0.1VVgs = 0.2VVgs = 0.3VVgs = 0.4VVgs = 0.5V

Figure 26: Channel Resistance vs. VDD, Channel Width = 200

The results in the figures above show that resistances on the orders of magnitude required for this bandgap circuit could be produced using the channel resistance of the NMOS device. However, this resistance varies significantly with VDD and Vref. A channel width of 200 appears to provide resistances closest to the bandgap resistances (on the orders of magnitude of 107 and 108), however the resistance varies the most with voltage at this channel width. The gate voltage and drain voltage of the NMOS would have to be very precisely controlled in order to provide accurate resistances. Controlling the voltage on the NMOS may be more realizable in an actual design than laying out a very large poly resistor, so this would likely be the method of choice to produce resistors of the size needed for the bandgap circuit.

Conclusions The circuit was able to achieve bandgap-like results in terms of providing a constant reference voltage over a range of VDD and temperature. However, the temperature and voltage ranges were less than expected, and not ideal for a commercial bandgap voltage reference. In addition, testing across process corners proved that process variations have a significant effect on the performance of the circuit. The device performs much better with regard to a constant reference voltage over a range of VDD in the slow corner and much worse in the fast corner. The circuit as it stands would not be commercially viable. However, testing variations in several circuit parameters showed

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that the device can be tuned to perform better across VDD and temperature. One method of tuning the circuit would be to increase the channel length. Another would be to find the R value that provided the best performance over the desired VDD and temperature range. Aside from performance, the other potential roadblock to commercial viability is the values of the resistances for the circuit. They are simply too large to be layed out using a standard poly resistance techniques. However, through testing it was shown that an NMOS could be biased in such a way as to provide the resistances required for the circuit. In conclusion, while this device performs as a bandgap voltage reference, the VDD and temperature ranges over which it performs as desired are too small for commercial applications. However, circuit parameters can be adjusted to provide somewhat better performance, and this could be an avenue of future research to produce a circuit that performs within acceptable commercial limits.

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