Shih-Fan, Peng 2013 IEE5008 –Autumn 2013 Memory Systems DRAM Controller for Video Application...

Shih-Fan, Peng 2013

IEE5008 –Autumn 2013Memory Systems

DRAM Controller for Video Application

Shih-Fan, PengDepartment of Electronics Engineering

National Chiao Tung [email protected]

NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng

Outline IntroductionTraditional ControllerDRAM Memory Controller for Video ApplicationConclusionReference

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DRAM WORK

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DRAM WORK(cont.)

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DRAM Organization

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Introduction

What is DRAM Memory Controller?

Manage the movement of data in and out of DRAM devices

Error detection and correction

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Abstract DRAM Memory Controller

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Address Mapping (Translation)Translation a given physical address in to indices in

a DRAM memory systemChannel ID, rank ID, bank ID, row ID, column ID

Mapping scheme is often coupled to the row-buffer-management policy

Ex: memory request sequenceMapping to different rows of the same bankMapping to different rows of different bank

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Write cachingWrite requests are typically non-critical in terms of

latencyDefer write requests and allow read requests to

proceed aheadBut sometime it is not good

Read requests must be checked against the address of cached writes

Controller must ensure the correctness of memory-access order

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Request Queue OrganizationsPlace the commands into single queue or multiple

queuePrioritize commands on many different factor

Priority of the request, availability of resources to a given queue, bank address of the request, age of request…..

Ex: per-bank queuing organizationBase on bank address

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Refresh ManagementDRAM must be refreshed to ensure the integrity of

the dataEx: pseudo-static DRAM

Temperature-compensated self-refresh is usedIf request collides with refresh action, assert a wait

signal used in low frequency

Separate refresh to each bank

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Method: Optimized the data arrangementMinimize the number of overhead cycles needed for

row-activationsConsider the feature of SDRAM and memory-

access patterns of video-processing applicationVideo-processing algorithms usually uses multi-

dimensional arrays and nested loops

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NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng 13

Timing diagram of two consecutive read cycle


Row changes for logical array with (1,128) window

Consider a 2-D array of 8X8 dataCause seven row changes→more latency and

power consumption

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Row changes for logical array with (8,16) window

A logical array is portioned into a set of rectangles called windows

Each window is stored in a row of SDRAM

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Condition for Minimal Overhead Cycles

Condition: two banks, the horizontal size of windows is greater than the loop bound

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Method: History-based predictive approach(HDTV)What if the row address differs from the previous

one?Page missAdditional cycles cannot be hidden

What can do for it?Statically schedule the address sequenceControl the memory operation modeBut if it is irregular?

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History-based predictive approach If trp can be overlapped to burst accesses or data transfer

between the memory controller and the processorEffective latency=tRCD + tCL

Use the past history of memory reference Predict next access (built a two-bit counter for each

row)If history predicts to same row

Bank remain in row active stateIf not

Change to idle state

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Two-bit saturated up/down counter(per-row)

SH,WH→auto-precharge is not issuedSM,WM→auto-precharge is issued

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Method: Burst Terminates Burst and Anticipative Row Activation In video application, most bandwidth is consumed

by 2-D block dataBlock data may consist of several non-sequential

accessesData length is inconstant

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Organization of Address BusAllocate and address space larger than the physical

addressSeamless transfer Mode Control Information (MCI)

to memory controllerBurst access operation is pre-calculated by

embedded address generator(EAG)MCI=Mode Select (MS)& Stride control (SC)

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Organization of Address Bus

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BTB and ARA

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ConclusionOptimize data arrangement

Select the suitable window sizeHistory-based predictive approach

Predict the successive memory accessBTB and ARA

Provide the parallel access of different banks

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Reference [1] H. Kim and I. C. Park, “High Performance and Low Power Memory Interface Architecture for Video

Processing Applications”, IEEE Transaction on Circuits and Systems for Video Technology, vol.11, pp. 1160 – 1170, 2001.

[2] J. Zhu, L. Hou, W. Wu, R. Wang, C. Huang, and J. Li, “High performance synchronous DRAMs controller in H.264 HDTV decoder,” in Proc. International Conference on Solid State and Integrated Circuits Technology, vol. 3, pp. 1621 – 1624, 2004.

[3] S. I. Park, Y. Yi, and I. C Park, “High Performance Memory Mode Control for HDTV Decoders,” IEEE Transactions on Consumer Electronics, vol. 49, no. 4, pp. 1348 – 1353, November, 2003.

[4] H-Y Kang, K-A Jeong, J-Y Bae, Y-S Lee, and S-H Lee, “MPEG4 AVC/H.264 Decoder with Scalable Bus Architecture and Dual Memory Controller,” in Proc. ISCAS, vol. 2, pp. 145 – 148, May, 2004.

[5] K. B. Lee, T. C. Lin, and C. W Jen, “An Efficient Qual ity- Aware Memory Controller for Multimedia Platform SoC,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 15, no. 5, pp. 620 – 633, May 2005.

[6]G. Hyun, Y. Jin, J. Jung, S. Kim, “A Synchronous DRAM Controller of an H.264/AVC Encoder” International SoC Design Conference, Vol. 02, pp. II-113 - II-116,2008

[7]Textbook: Memory Systems: Cache, DRAM, Disk chapter 13

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NCTU IEE5008 Memory Systems 2013Shih-Fan, Peng 26

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