Shaodi Wang 004033643

EE201C : Stochastic Modeling of FinFET LEREE201C : Stochastic Modeling of FinFET LERand Circuits Optimization based on Stochastic and Circuits Optimization based on Stochastic

ModelingModeling

Shaodi WangShaodi Wang

004033643004033643

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OutlineOutline

Stochastic modeling of FinFET LERStochastic modeling of FinFET LER

Stochastic modeling based circuits optimizationStochastic modeling based circuits optimization

22nm FinFET circuits optimization22nm FinFET circuits optimization

ConclusionConclusion

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Devices VariabilityDevices Variability

Line Edge Roughness (LER) Line Edge Roughness (LER) LER is the main variability in FinFETLER is the main variability in FinFET

Gate Dielectric Thickness (Tox)Gate Dielectric Thickness (Tox)

Random Dopant Fluctuations (RDF)Random Dopant Fluctuations (RDF)

Metal-gate Work Function (WFV)Metal-gate Work Function (WFV)

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Line Edge Roughness Line Edge Roughness

StochasticStochastic

Consequence of Lithography processingConsequence of Lithography processing

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LER vs. LWRLER vs. LWR

Line width roughness (LWR) Line width roughness (LWR)

2 2 2 2LWR L R X L R

22 1

1

n

ii

LWR

L L

N

L R LER

2 22 1LWR LER X

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Correlation Correlation Resist-definedResist-defined

Spacer-definedSpacer-defined

0X

1X

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CorrelationCorrelation

2exp /A y

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Gate LER and Fin LERGate LER and Fin LER

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Gate LER Affection Gate LER Affection

Fin LWR affects device performance by changing the Fin LWR affects device performance by changing the

average Fin width in the channel region.average Fin width in the channel region.

Gate LWR induce the FG and BG mismatch and offset.Gate LWR induce the FG and BG mismatch and offset.

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Stochastic modeling of Gate LWRStochastic modeling of Gate LWR

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Stochastic modeling of Gate LWRStochastic modeling of Gate LWR

2 2 2 2 21 2 3 4 14 1 4

23 2 3 12 1 2 34 3 4

13 1 3 24 2 4

2

2 2 2

2 2

L

Resist Forming Gate: Spacer Forming Gate:

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Experimental grids are established Experimental grids are established

2 22 2 2,P g L

P P

L

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ResultResult

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ResultsResults

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ResultsResults

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ResultsResults

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OutlineOutline





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Stochastic Circuits OptimizationStochastic Circuits Optimization

Performance vs. scalingPerformance vs. scaling

Power vs. scalingPower vs. scaling Leakage PowerLeakage Power

Dynamic PowerDynamic Power

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Optimization methodologyOptimization methodology

Stochastic timing analysis Stochastic timing analysis Instead of static timing analysisInstead of static timing analysis

Every path can be critical pathEvery path can be critical path Every path has a probity to become a critical pathEvery path has a probity to become a critical path

The given yield to constrain the clock frequencyThe given yield to constrain the clock frequency

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Optimization processOptimization process

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Models:Models:

Power ModelPower Model

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ModelsModels

Delay modelDelay model

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ModelsModels

Devices model depends on different devices.Devices model depends on different devices. MOSFETMOSFET

SOISOI

FinFETFinFET

Devices simulation resultsDevices simulation results Output from Spice, etc.Output from Spice, etc.

Empirical fitting modelEmpirical fitting model

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Tolerance modelingTolerance modeling

Process variation Process variation LERLER

RDF (Not important for FinFET)RDF (Not important for FinFET)

Intra-die, inter-die and across-die variationIntra-die, inter-die and across-die variation

Supply voltage variationSupply voltage variation Vdd and Ground noiseVdd and Ground noise

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Variation affectionVariation affection

Example: Vt shift and follows a Gaussian distributionExample: Vt shift and follows a Gaussian distribution Delay distribution:Delay distribution:

• One stage delay:One stage delay:• N stage path delay: N stage path delay:

Average Off Current:Average Off Current:• Assume Ioff follows Gaussian distribution

0 0( , )N n n 0 0( , )N

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Given a clock period tGiven a clock period tCKCK

Each path has a delay distribution. Delay over tEach path has a delay distribution. Delay over tCKCK results failure. results failure.

The total yield:The total yield:

Given the yield and reverse the equation to solve tGiven the yield and reverse the equation to solve tCKCK..

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Thermal modelingThermal modeling

Temperature dependenceTemperature dependence Subthreshold leakageSubthreshold leakage

Mobility modelMobility model

Wire resistance modelWire resistance model

Heat-sink model Heat-sink model

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ResultsResults

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ResultsResults

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DefectsDefects

This works contribute the process variation into the VThis works contribute the process variation into the Vtt

variability. However, the device performance variability variability. However, the device performance variability

cannot be easily appropriately modeled by Vcannot be easily appropriately modeled by Vtt..

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OutlineOutline





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FinFET variabilityFinFET variability

The FinFET is 22nm technology. The FinFET is 22nm technology. The thin channel suppresses short channel effects. The thin channel suppresses short channel effects.

Low doping makes RDF affection lower.Low doping makes RDF affection lower.

The restriction of Tox is released. The restriction of Tox is released.

LER become the important process variation.LER become the important process variation.

Voltage supply noise is still a problemVoltage supply noise is still a problem

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FinFET optimization based on Stochastic modelingFinFET optimization based on Stochastic modeling

FinFET Device LER Simulation

Principle component analysis on FinFET LER results

Fitting model to FinFET behavior

Transfer the principle component from device LER to model parameters

Circuits performance variability is done based on model

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FinFET 3-D LER MC simulation is done based on sentaurus FinFET 3-D LER MC simulation is done based on sentaurus

TCAD tool.TCAD tool. Non-variation current behavior is obtained. ( Works in model Non-variation current behavior is obtained. ( Works in model

fitting)fitting)

Key parameters are obtainedKey parameters are obtained• Threshold voltageThreshold voltage• Saturation voltageSaturation voltage• Ion currentIon current• DIBLDIBL

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Principle component analysis performed on device LER Principle component analysis performed on device LER

resultsresults Calculate the covariance matrix of the results of FinFET.Calculate the covariance matrix of the results of FinFET.

• Covariance matrix:Covariance matrix:

Calculate the eigen vectors and eigen valuesCalculate the eigen vectors and eigen values• Eigen vectors Eigen valueEigen vectors Eigen value

• These eigen vectors are independent These eigen vectors are independent

Cov(a1,a1) Cov(a2,a1) Cov(a3,a1) Cov(a4,a1)




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Calculate the sensitive vectors of devices key behavior Calculate the sensitive vectors of devices key behavior

parameters to model parameters.parameters to model parameters. My model has 9 parameters. This sensitive vectors are the 4 My model has 9 parameters. This sensitive vectors are the 4

devices key parameters’ derivation to 9 parameters of modeldevices key parameters’ derivation to 9 parameters of model

Calculate the principle components in emperical modelCalculate the principle components in emperical model

31 2 4

1 1 1 1

31 2 4

2 2 2 2

31 2 4

9 9 9 9

DD D D

M M M M

DD D D

M M M MSen

DD D D

M M M M

mod * _el DevicePCA Sen Eigen vectors

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Variability model in my workVariability model in my work LER VariationLER Variation

• Based on PCA, I used 9 parameters in the model to represent the LER Based on PCA, I used 9 parameters in the model to represent the LER variability. ( Ion, Ioff, Vt, CLM, Vtsat, Vt,lin …)variability. ( Ion, Ioff, Vt, CLM, Vtsat, Vt,lin …)

Voltage supply variationVoltage supply variation• I model this into the supply voltage Vdd variability.I model this into the supply voltage Vdd variability.

Across-die, inter-die and intra-die variationAcross-die, inter-die and intra-die variation• I model this by threshold voltage variabilityI model this by threshold voltage variability

All of these 3 variation are independent All of these 3 variation are independent

Model delay variabilityModel delay variability Based on MC simulation. Based on MC simulation.

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Optimization processOptimization process Given the restriction ( Power and Yield)Given the restriction ( Power and Yield)

Outer loop : optimized parameters ( Vt, W and etc)Outer loop : optimized parameters ( Vt, W and etc)

Inner loop : optimized parameters (Vdd)Inner loop : optimized parameters (Vdd)

In each one of the all loop:In each one of the all loop:• 100 samples MC performed to get the distribution of one stage Delay.100 samples MC performed to get the distribution of one stage Delay.• Based on the given Yield, using iteration to find the chip clock Based on the given Yield, using iteration to find the chip clock

frequency.frequency.• Calculate the total power, the power must < Power restriction.Calculate the total power, the power must < Power restriction.• Choose the fast clock in given Power restriction.Choose the fast clock in given Power restriction.

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Optimization Results Optimization Results Optimized Block : Gate 5000, longest path 22 stages.Optimized Block : Gate 5000, longest path 22 stages.

5E-5 5E-4 0.005 0.05

100

1000

Clo

ck P

erio

d (p

s)

Total Power(W)

Delay vs. PowerBlock: 5000 Gates

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LER is one of the important variability in FinFET LER is one of the important variability in FinFET

technology.technology.

As power restricts devices scaling, circuits optimization As power restricts devices scaling, circuits optimization

becomes an important process to reduce power.becomes an important process to reduce power.

FinFET circuits optimization is done by considering LER, FinFET circuits optimization is done by considering LER,

supply voltage, process variation.supply voltage, process variation.

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ReferenceReference

Kedar Patel, et all, “L. I. Smith. “A Tutorial on Principal Kedar Patel, et all, “L. I. Smith. “A Tutorial on Principal

Components Analysis”. Cornell University, USA, 2002. ”, Components Analysis”. Cornell University, USA, 2002. ”,

IEEE Transactions on Electronics Devices, vol. 56, no. 12, IEEE Transactions on Electronics Devices, vol. 56, no. 12,

Dec. 2009.Dec. 2009.

L. I. Smith. “A Tutorial on Principal Components Analysis”. L. I. Smith. “A Tutorial on Principal Components Analysis”.

Cornell University, USA, 2002. Cornell University, USA, 2002.

D. J. Frank, et all, “Optimizing CMOS technology for D. J. Frank, et all, “Optimizing CMOS technology for

maximum performance” , IBM J. RES & DEV. vol.50, no. 4/5, maximum performance” , IBM J. RES & DEV. vol.50, no. 4/5,

2006 2006

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