SH2 DMAC and Interrupt

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1© 2008, Renesas Technology America, Inc., All Rights Reserved

Course Introduction

Purpose:

This course provides an overview of the Direct Memory AccessController and the Interrupt Controller on the SH-2 and SH-2A

families of 32-bit RISC microcontrollers, which are members of theSuperH® series

Objectives:

Gain a basic knowledge of the features and operation of the directmemory access controller

Learn about the features and operation of the interrupt controller

Content: 27 pages 4 questions

Learning Time: 20 minutes


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© 2008, Renesas Technology America, Inc., All Rights Reserved

SuperH Peripheral Functions

Microcontrollers for embedded

system applications require

extensive on-chip peripherals to

Minimize system chip count

Reduce overall system cost

Facilitate small system size, etc.

Built-in peripheral functions

must Provide required capabilities

Deliver needed performance levels

Offer design flexibility

Maintain a basic commonalitywithin product family, if possible

Offer an acceptable cost-benefit

compromise, etc.

SH-2 SuperH32-bit RISC CPU

SH7145 SuperH Series Microcontroller

Multi-function Timer

Pulse Unit

Compare-MatchTimer

Watchdog Timer

A/D Converter

BusInterface

Flash

Bus StateController

High-performanceUser Debug Interface

Clock PulseGenerator

RAM

Data Transfer

Controller

Direct MemoryAccess Controller

Interrupt Controller

I/OPorts

Serial CommunicationInterface

User BreakController

Advanced UserDebugger


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Direct Memory Access Controller

Performs data transfers

between:

External devices with DACK

External memory

On-chip memory

Memory-mapped external I/O

On-chip peripheral modules

Frees the CPU from

handling these data

transfers

So CPU resources can be

focused on computational

operationsMicrocontroller

DMAC

On-chipPeripherals

On-chipMemory

Memory-mapped I/O

ExternalDevices

with DACK

ExternalMemory

SuperH

CPU


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DMAC Features

4 or 8 channels — 2 or 4 with external triggering

4GB of address space

Transfers of up to 16,777,216 units

Byte, word, longword, and 16-byte data transfer units

Dual-and single-address modes

Processing of transfer requests from

External devices On-chip peripherals

– SCIF x 8 sources – IIC3 x 2 sources (supported by SH-2A only) – ADC x 2 sources – MTU2 x 5 sources – CMT x 2 sources (supported by SH-2A only)

Software (auto request)

Cycle-steal and burst-bus modes

Fixed and round-robin priority schemes

Interrupts after half or full data transfer


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Dual-Address Mode

Both source and destination are accessed by internal or external

addresses

Two bus cycles are required for data transfer

First bus cycle

Second bus cycle


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Single-Address Mode

Both source and destination are external

devices

One source is accessed by the DACK signal

and the other by the address

Transfer can be performed in one cycle

MCU


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Supported Data Transfers

Notes: • Dual = Dual-address mode; Single = Single address mode

• A 16-byte transfer is available only for on-chip peripherals that support longword access.

DMAC Address Mode vs. Transfer Destination


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PROPERTIES

On passing, 'Finish' button: Goes to Next Slide

On failing, 'Finish' button: Goes to SlideAllow user to leave quiz: At any time

User may view slides after quiz: After passing quiz

User may attempt quiz: Unlimited times


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Channel Priority

When more than one DMAC channel is triggered, channel-priority modes determine the order of transfers.

DMAC has two channel priority modes:

Fixed – The priority among channels remains fixed

– Two schemes are available:

Round robin

– Priority changes after each unit is transferred

– Channel of just-completed transfer moves to the position of lowest priority – Priority after reset:

CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7




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Bus Modes

Cycle-steal mode

Normal

– Upon completion of a transfer, the bus is given to another bus master (CPU, external bus request, etc.)

– Bus released for 1 cycle

Intermittent (SH-2A series devices only) – Upon completion of a transfer, the bus is given to another bus master

(CPU, external bus request, etc.) – Bus released for 16 or 64 cycles

– DMAC occupies the bus less frequently

Burst mode

Fastest way to transfer data

DMAC doesn’t release the bus until all requested transfers have been

completed

Two bus modes direct the use of the microcontroller’s buses


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Interrupt Controller

Controls interruptrequests to the CPU

Ascertains the priority of

interrupt sources Provides key features

and functions

16 levels of priority

NMI noise-canceller function

/IRQOUT pin, which cansignal the occurrence of aninterrupt

Register bank interaction(in SH-2A devices) to saveand restore CPU registersat high speed

INTC

InterruptSource 4

InterruptSource n

InterruptSource 3

InterruptSource 2

InterruptSource 1

CPU

..


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Exceptions and Interrupts

Exceptions are unusual andunexpected occurrences

Time and location generally

cannot be predicted

Example is an Illegal instruction

Hardware offers methods to

react, recover, and restart

Exception sources include:

Resets

Address errors

Illegal instructions TRAPA instructions

Interrupt sources include:

NMI

User Break

External IRQ

On-chip peripherals

Interrupts are unusualoccurrences that are expectedto occur

Example is data-byte reception bya serial communications channel

CPU can launch a routine to

handle the event


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Interrupt Acceptance & Handling

INTC accepts interrupt requests according to priority

If interrupt request is accepted, interrupt handling processbegins:

/IRQOUT driven low

Status Register pushed on stack and

interrupt priority adjusted in CPU status

register

Program counter pushed onto stack

/IRQOUT driven high Address of interrupt service routine

read from vector table

Interrupt service routine executed

Stack

R0R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11R12

R13

R14

R15

31 0

MQI3I2I1I0ST

31 0Status Register

GBR

Global Base Register

VBR

Vector Base Register

MAC H

MAC Registers

MAC L

PR

Procedure Register

PC

Program Counter

Stack

grows

down

Low Address

High Address

TBR

Jump Table Base Register


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Interrupt Handling Flow


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PROPERTIES






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SH-2 Series Interrupt Controller


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Number of States

______________________________________________

NMI, Peripheral Module IRQ Remarks

_____________________________________________________________________________________________________________________

DMAC/DTC active judgment 0 or 1 1 1 state required for interrupt signals for which

DMAC/DTC activation is possible

_____________________________________________________________________________________________________________________

Compare identified interrupt 2 3

priority with SR mask level

_____________________________________________________________________________________________________________________

Wait for completion of X (≥ 0) The longest sequence is for interrupt or

sequence currently being address-error processing (X = 4 + m1 + M2 +

executed by CPU m3 + m4). If an interrupt-masking instruction

follows, the time may be longer

_____________________________________________________________________________________________________________________

Time from start of interrupt 5 + m1 + m2 + m3

exception processing until

start of fetch of exception

service routine’s first instruction

_____________________________________________________________________________________________________________________

Interrupt total: 7 + m1 + m2 + m3 9 + m1 + m3

_________________________________________________________________________________________

Response, minimum: 10 12 0.25µs to 0.3µs

_________________________________________________________________________________________

Time, maximum: 12 + 2 (m1 + m2 + m3) + m4 13 + 2 (m1 + m2 + m3) + m4 0.48µs @ 40MHz

_____________________________________________________________________________________________________________________

Note: m1 — m4 are the number of states needed for the following memory accesses:m1: SR save (longword); m2: PC save (longword write); m3: vector address read (longword write); m4: fetch first ISR instruction

SH-2 Interrupt Response Time


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PROPERTIES






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SH-2A Interrupt Controller


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SH-2A Register Banks

SH-2A CPU has

15 register banks, one for

each interrupt priority

Register banks save andrestore CPU register

contents during interrupt

handling

When bank is full and

overflows, the stack can

be used

SH-2A CPU can generatebank overflow and

underflow exceptions


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SH-2A Interrupt Latency


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SH-2A Interrupt Response Times


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Vector Table

Complete table contains entries for Exception processing

Interrupt processing

Entries are always 32 bits wide

and longword aligned

Vector table entries point to

functions with no calling

parameters and no return values Vector base register provides a

location base for the vector table

that helps improve

Interrupt processing speed in ROM-lesssystems

Memory access in ROM monitor or

bootloader applications

IRQ0 64 0x00000100-0x00000103

IRQ1 65 0x00000104-0x00000107

IRQ2 66 0x00000108-0x0000010B

IRQ3 67 0x0000010C-0x0000010F

IRQ4 68 0x00000110-0x00000113

IRQ5 69 0x00000114-0x00000117

IRQ6 70 0x00000118-0x0000011B

IRQ7 71 0x0000011C-0x0000011F

On-chip peripheral modules 72

...255

0x00000120-0x00000123

...

0x000003FC-0x000003FF

Interrupt source Vector Vector table address offset

Vector tables can be0x400 bytes long!


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CPU reads initial values for PC

and SP from exception vector table

Vector base register is initialized

to 0x00000000 Interrupt mask bits of the SR are set to maximum

(all interrupts masked)

Program execution begins at PC value read from

exception vector table

Two reset types are supported:

Power-on reset

– Reset vector from 0x00000000

– SP from 0x00000004

Manual reset (/RES=1, /MRES=0)

– Reset vector from 0x00000008

– SP from 0x0000000C

Exception Processing - Resets


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Exception Processing-Instructions

Exceptions can be triggered by instructions

TRAPA

General illegal (unimplemented) op-code

Illegal slots

General illegal instruction

Instruction that rewrites the PC


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PROPERTIES



User may view slides after quiz: At any time


C S


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Course Summary

Direct memory access controller

Interrupt controller

SH2 DMAC and Interrupt

Documents

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