SGMI Research Themes & Subjects - Samsung US · PDF fileSGMI Research Themes & Subjects ... It...

SGMI (Samsung Global MRAM Innovation) Program / 23

SGMI Research Themes & Subjects

The SGMI program is seeking proposals in thirty-two (32) research items outlined below.

Research Category Research Title No.

Ⅰ. Magnetic Materials for

MTJ

1. High iPMA 1.1

2. High Hex SAF Structure 1.2

3. Bulk PMA 1.3

4. Material for Low Switching Current 1.4

5. Magnetostriction & Mechanical Stress Effect 1.5

Ⅱ. MTJ Integration & MgO

1. MgO Crystallinity & Interface Epitaxy 2.1

2. Damage-free MTJ Etch 2.2

3. Etch Residue Removal (Cleaning) 2.3

4. Post Treatment & Encapsulation 2.4

Ⅲ. MTJ Characteristics

(Read/Write & Reliability)

1. High TMR 3.1

2. Low Switching Current 3.2

3. MTJ Write Error Rate 3.3

4. MTJ Thermal Stability 3.4

5. MTJ Switching Back (Back-Hopping) 3.5

6. MTJ Endurance 3.6

Ⅳ. MTJ Analysis (Modeling) 1. Micro Magnetic Simulator 4.1

2. Material Development Simulator 4.2

Ⅴ. Packaging 1. Magnetic Shielding 5.1

Ⅵ. Transistor 1. Strain Engineering 6.1

2. Gate Work Function Engineering 6.2

Ⅶ. Circuit Design

1. Resistive Memory Architecture 7.1

2. Read Sensing Circuits 7.2

3. Write Programming Circuits 7.3

4. Design for Test 7.4

5. Redundancy and ECC 7.5

Ⅷ. Application (H/W, S/W)

1. H/W and S/W Techniques to Hide Weaknesses of STT-MRAM

8.1

2. Techniques to Protect STT-MRAM Systems against Attacks and Power Failures

8.2

3. Novel Applications on STT-MRAM Systems 8.3

4. Exploiting New Design Trade-offs 8.4

Ⅸ. Emerging Technology

1. Materials and Designs Exploiting Spin-orbit Effects for Memory Switching

9.1

2. Materials and Designs Exploiting Voltage-Controlled Anisotropy for Memory Switching

9.2

3. MLC and 3D STT-MRAM Technology 9.3


1. Magnetic Materials for MTJ

1.1 High iPMA

iPMA is a key technology for MTJ module development based on CoFeB electrodes. The

engineering window for PMA control is narrow in terms of magnetization, thickness, and

the degree of spin-orbit coupling at the interface. The thermal budget for TMR improvement

can also deteriorate PMA. It is necessary to develop very strong iPMA film that is thermally

stable upon 400℃ annealing.

Targets

① Perpendicularly magnetized CoFeB-based layers with MgO interface

- Ku*t > 0.5 erg/cm2 at single MgO interface or dual MgO interface

- Maintain PMA at annealing temperature > 400℃

② Metallic or dielectric elements to induce large iPMA at the interface with CoFeB layer

- Ku*t greater than MgO interface

1.2 High Hex SAF Structure

As a pinned layer, Synthetic Anti-ferro (SAF) coupled structure is used in MTJs. In order to

ensure read/write failure margin, a very high exchange field (Hex) is required. The SAF

pinned layer also should sustain high annealing temperature because RKKY coupling can

be weakened by intermixing of diffusion within the SAF pinned layer materials.

Targets

① RKKY coupled Synthetic Anti-ferro (SAF) layers with PMA

- Jex > 0.7 erg/cm2 (positive corresponds to antiferromagnetic coupling)

- Free of intermixing or diffusion under annealing temperature > 400℃

② Seed layers for uniform L11 superlattice formation

- Isotropic crystallinity of L11 film Δθ50(FWHM) by XRD < 3 degrees


1.3 Bulk PMA

Bulk PMA is one of the candidate systems for thermal stability of MTJ cells. This can be

applied both in free and pinned layers when it is combined with relatively soft CoFeB as a

spin polarizer. In order to be applied into devices, bulk PMA should be based on Si

substrates.

Targets

① Highly ordered fct L10 structure on Si substrate and finite buffer layers with Ku > 107

erg/cc

- Develop conductive buffer layer for Si substrate

- Ku > 107 erg/cc

- Low ordering temperature < 350℃ to achieve ordering parameter: S > 0.9

② Hybridization of bulk PMA and iPMA for both extremely high thermal stability and TMR

- Control of bulk PMA by exchange coupling with low Ku layers

1.4 Material for Low Switching Current

The critical current to write an MTJ bit is confined to the amount of current generated from

the transistor, which is limited by the scaling rule. It is theoretically known that the damping

constant, saturation magnetization, effective anisotropy field, and magnetic volume are

determinants of critical current density. Development of low switching current material

maintaining high enough thermal stability is essential.

Targets

① Perpendicular magnetic film requirements

- Gilbert damping constant < 0.005

- Ms <600 emu/cc

- Ku*t > 0.5 erg/cm2

② Application of electric field effect on STT-switching

- Demonstration of Jc reduction by electric field effect


1.5 Magnetostriction & Mechanical Stress Effect

Physical stress and strain can induce the change of magnetic characteristics, and magnetic

configuration can induce the physical strain. The stress can be three-dimensional on MTJ

by capping and patterning. Its effect should be controlled or enhanced on the properties of

MTJ. This research item on the effects on MTJ covers 1) effects on general properties of

MTJ: Ms, Hk, TMR, Hex of SAF, etc.; 2) differences in stress effects for different sizes of

MTJ; and 3) effects by stress release.

Targets

① Analysis Requirements

- Stress direction (compressive/tensile) and strength by various patterning and capping

- Effects of compressive/tensile stresses on MTJ properties and consequent

improvements

② MTJ Requirements

- Perpendicular MTJ using MgO

- MTJ Pattern Size: < 60nm


2. MTJ Integration & MgO

2.1 MgO Crystallinity & Interface Epitaxy

Magnetotransport properties are dependent on the MgO quality (crystallinity) and epitaxial

relationship with ferromagnetic electrode. Quantitative characterization of MgO properties

would give more insight for better MTJ performance.

Targets

① Growth of MgO film with high crystallinity

- Growth technique to promote MgO crystallization

- Post treatment technique to promote MgO crystallization

② Characterization of MgO film

- Qauntitative analysis of MgO crystallinity

- Extraction of material parameters by electrical characterization

③ Grain-to-grain epitaxy between MgO and CoFeB

- Control of lattice mismatch

- Control of boron diffusion

④ Control of MgO pinhole

- Quantitative characterization of pinholes

- MgO growth technology for pinhole control

- Structure analysis for pinhole control

⑤ Control of MgO particle defects

⑥ MgO degradation on MTJ patterning

- Effect of etch chemistry

- Characterization methods to quantify the effects of patterning on MgO degradation

2.2 Damage-free MTJ Etch

MTJ damage during MTJ patterning is severe at low D/R. The major factors, Cl*, O* and F*

etchants and high energy ion (or atom), must be excluded during physical etching.


Targets

① MgO and free layer damage free etch process

- Chemical damage free (MgO, free layer)

- Chemical damage modeling

- Physical damage free

② Effect of etch parameter on MTJ patterning

- Ultra low pressure, bias power limit

- Gas (Ne, Ar, Kr, Xe…)

③ Mask Material

- High selectivity

- Easy RIE etch

2.3 Etch Residue Removal (Cleaning)

MTJ patterning uses mainly the physical etching, and so there remains the sputtered metal

atom within MTJ stack. The cleaning process, which removes the metal residue without

any MTJ damage, is needed.

Targets

① MTJ Re-depo residue cleaning technique

- Co, Fe, Pt, W byproducts cleaning

- MgO attack free

- MTJ side attack <1nm

- Development of etch chemistry for various potential MTJ material

② Electrochemistry modeling

- Electrochemical database for various potential MTJ materials

- Metrology of electrochemical analysis for MTJ byproduct removal

③ Basic study for MTJ degradation by cleaning process

- Modeling MTJ degradation by wet cleaning

2.4 Post Treatment & Encapsulation

There remains metal residue within MTJ stack because MTJ patterning uses mainly


physical etching, which can cause an electrical short. Penetration of MTJ damage source

into MTJ stack can cause the MTJ degradation. An efficient metal residue removal process

and a strong capping layer for diffusion blocking are necessary.

Targets

① Removal technique for sidewall byproduct

- Remove subject: Fe,Co,Pt,W + etch polymer

- Limiting conditions: selective sidewall/bottom removal (minimize top loss),

minimize H2O molecules, minimize physical/chemical damage

② Oxidation technique of sidewall byproduct

- Oxidation subject: Fe, Co, Pt, W

- Limiting conditions: selective oxidation of etch by-product, minimize magnetic layers

oxidation

③ Magnetic material capping layer formation

- Needs: Blocking penetration of Hydrogen, H2O into MTJ

- Limiting conditions: Process temperature ≤ 275℃, Step coverage ≥90%, no Chlorine,

minimize hydrogen/plasma damage, minimize oxidation of magnetic materials


3. MTJ Characteristics (Read/Write & Reliability)

3.1 High TMR

A high TMR (Tunnel Magnetoresistance Ratio) is required for sufficiently fast read

operation. TMR is (RAP – RP) / RP, where RAP and RP are high and low resistances of MTJ,

respectively. It is necessary to have control of the essential technical factors for TMR

enhancement: magnetic layer composition, MgO layer formation, annealing methods, etc.

Targets

①TMR Requirements

- By CIPT method: 280%

- CPP-TMR at Patterned MTJ: 230%

- Clarify RA value with TMR result

- Distribution: σ<5% (Blanket CIPT)



- RA: < 40Ω·um2

3.2 Low Switching Current

Low switching current is required to develop the MTJ with low switching current density

because MTJ must be switched by current that a cell transistor can supply. Improvement of

stack structure to lower the switching current density is needed.

Targets

① Switching Current Density Requirements

- Jc (Switching Probability = 50%) by 20ns pulse: < 1.2MA/cm2



- Thermal Stability Δ > 40@85˚C

- MTJ Pattern Size < 60nm


3.3 MTJ Write Error Rate

Occurrence of errors in the write operation is an intrinsic characteristic of MTJ. WER is

generally lower, as the pulse voltage is higher than Vc. High write voltage is required to

keep the WER lower than 10-12, which is the level correctable by ECC.

Targets

① WER Requirements

- Fast test method is required to be developed to evaluate the WER lower than 10-12

- Evaluate and minimize the ratio of Vpgm (WER<10-12) to Vc (50% switching voltage)

- Test Pulse Width ~20ns




3.4 MTJ Thermal Stability

Thermal stability determines how long the bit written in MTJ can be stored without error.

Thermal Stability is Δ=Eb/kBT. A fast, efficient, and accurate method must be determined

among the various evaluation methods.

Targets

① Thermal Stability Requirements

-Thermal Stability Δ >70 @85˚C




3.5 MTJ Switching Back (Back-Hopping)

Switching of MTJ in the opposite direction to the applied current results in the increase in

the write error. Sufficient margin is necessary between the voltages with low write error rate

and with low back-hopping rate.


Targets

① Mechanism and Solution of Switching Back

- Establish plausible and essential causes.

- It is important to not happen between the write voltage and the breakdown voltage.



- Thermal Stability Δ > 40@85˚C


3.6 MTJ Endurance

MTJ must secure its properties for the guaranteed time with its operation. As well, dielectric

breakdown must not occur in MgO by repeated electrical stress. A time-dependent

dielectric breakdown test generally estimates the quality of oxide thin film. The change of

MTJ properties under the successive operations must be explored to be modeled and

estimated appropriately.

Breakdown voltage (BV) of MgO layer in MTJ can be comparable to the MTJ’s switching

voltage since MgO layer should be very thin to be used in MTJ with suitable RA for

application. The higher the BV of MgO layer the better; as well, the BV of MgO layer must

be sufficiently higher than the MTJ switching voltage. (BV > Voltage for 10-12 WER)

Targets

① TDDB

- Detect the major region where the dielectric breakdown occurs in MTJ

(inside, perimeter)

- Maximize 10-year lifetime voltage for given RAs

② Endurance

- Estimation and model establishment of the change of the MTJ properties with

successive operations

③ MgO Breakdown Voltage

- BV variation according to the RA value change

- Maximize the BV for given RAs


④ MTJ Requirements

- (Perpendicular) MTJ using MgO

- RA: < 40Ω•um2



4. MTJ Analysis (Modeling)

4.1 Micro Magnetic Simulator

Micro Magnetic simulator is a modeling method used to describe the behavior of

magnetization based on the LLG equation. It analyzes the MTJ write operation from the

switching behavior of magnetization. A suitable scheme of appropriate input parameters is

necessary to accomplish consistency with experimental results.

Targets

① Micro Magnetic Simulator Requirements

- Precision Specialization: STT-induced operation of perpendicular MTJ

- Efficiency enhancement or adequate approximation scheme for massive calculation,

such as reliability test like WER

4.2 Material Development Simulator

Selection and composition of materials are essential for developing MTJ and improving its

properties. Simulation with proper models can reduce trial and error while narrowing down

the direction of experimental exploration.

Targets

① Ab-initio simulation for high PMA

- Interfacial PMA for various material systems

② TMR modeling

- Effect of defects on TMR

- Effect of crystallinity, orientation, and structure

③ Switching current and damping modeling

- Material design for Jc reduction

- MTJ stack design for fast and reliable switching

- Simulation of damping constants for various material designs


5. Packaging

5.1 Magnetic Shielding

Bits stored in MTJ can be lost due to a strong external magnetic field. It is necessary to

investigate the magnetic field on MTJ during its use and to investigate the necessity and

efficiency of shielding the magnetic field.

Targets

① Low Temperature Packaging

- MTJ characteristics are sensitive to the temperature of the following processes,

thus the packaging should also have low process temperature.

- Packaging process temperature needs to be lower than 275˚C.


6. Transistor

6.1 Strain Engineering

The strain technology is necessary for cell transistors with 3-D structure for high density

memory to enhance the carrier mobility.

Targets

① Structure

- Technology to enhance the carrier mobility in channel and source/drain region using

the stress induced by the change in cell transistor structure and the process conditions

- Application of stressor with change in cell transistor structure to take advantage of

stress

② Material

- Develop the material to induce stress in the channel region and the low doping S/D

region (for example: SiBN, SiGe, STI fill material)

③ Stress Analysis tool

- Develop the measurement tool to examine the effect of strain

- Develop the electrical measurement method

6.2 Gate Work Function Engineering

Development of gate material of the DRAM cell transistor is oriented to the word-line

resistance and the process-feasibility not the performance of transistor. MRAM cell

transistor is required to show high performance like logic transistor, thus gate material

should be developed to drive high current.

Targets

① Gap-Fill

- Good gap-fill metallic material with low resistivity is necessary because high aspect

ratio fill is required in gate formation in transistors with BCAT-shape.

② Work Function


- Develop n+ like gate material for NMOS cell transistor

- Develop tunable work-function material for Vth control


7. Circuit Design

7.1 Resistive Memory Architecture

Resistive memory architecture that has small cell size and array is required. STT-MRAM

requires careful consideration because, unlike other resistive memory, the TMR of STT-

MRAM is relatively very low (TMR ≤ 300%). In addition, the difference between the write

and read current is relatively small as well (<15uA). For small bit cell sizes such as 6F2 to 8

F2 cells, the cell transistor resistance will dominate the read/write path forcing higher MTJ

RA requirements for adequate read signal-to-noise ratio. This in turn may force higher

voltage operation to maintain adequate current density, and may cause higher stress to the

MgO barrier.

Targets

① Small cell size and array

- Small cell size(<6F2)

- High array efficiency

- Source line structure for small cell size, low VDD and easy chip repair

② Page operation & power consumption

- Low latency read/write operation

- High speed burst read/write operation (e.g. SERDES, DDRx)

- Low active operating power and ultra low power standby mode

7.2 Read Sensing Circuits

High-speed, low current read sensing circuit is required under big variations such as PVT,

Rmtj, and transistor mismatch. For increase of sensing margin, self-reference cell scheme

may be an option with acceptable latency.

Targets

① Read sensing circuit requirements

- Robust to PVT variations: All process corner, < 1.5V, -5C~110C


- Low current sensing circuit: < 100% TMR, < 1uA current difference

- High-speed access time sensing circuit : <10ns

- Vmtj< 0.2V when read operation for RDR (Read Disturb Rate)

- Robust to RMTJ variation: 1σ=5%

- Transistor mismatch compensating sensing circuit: >30mV Vth mismatch

- MTJ circuit modeling including temperature variation

- Small size, compact layout sensing circuit

② Reference cell scheme

- High-speed self-reference sensing scheme: non-destructive, access time< 10ns

- Reference cell scheme that can track variation of each cell

- Low area penalty reference cell scheme

7.3 Write Programming Circuit

Low-voltage, high-current write circuit is required for bidirectional flowing of write current.

Targets

① Low-voltage, high-current driving

- Low-voltage (<1.5V), bidirectional high-current injection (>20uA)

(Current is limited by cell transistor and voltage developed across MTJ depends on RA

and driving current.)

- Write scheme that can reduce write time, current, and power

(even though they are dependent on Δ and Jc)

- Transparent write delay for reliable MTJ switching during high speed burst write

operation

- PVT compensation circuits to deliver the right amount of write voltage and current

7.4 Design for Test

DFT (Design for Test) circuits for mass production are required. Need fast error rate

screening at wafer test as well as at final test. Use of temperature and voltage stress if

possible. Need to correlate temperature, voltage, and read/write pulse width to correlate

results with acceptable error rates without over stressing the bit cells.


Targets

① WER (write error rate) test methodology: fast wafer level and/or package level WER

screening and measurement

② BHR (back hopping rate) test methodology: fast wafer level and/or package level RDR

screening BHR screening and measurement

③ RDR (read disturb rate) test methodology: fast wafer level and/or package level RDR

screening and measurement

7.5 Redundancy and ECC

Redundancy is the repair scheme or algorithm to isolate and replace the bad memory cells.

The goal is to use as little real estate as possible for the largest amount of coverage and

flexibility. ECC is more closely related to redundancy where bad data is detected and

corrected on the fly but the bad physical bit cells are still in use (not repaired).

Targets

① Redundancy

- Programmability at any stage, and ability to replace bad redundant elements

- Efficient repair architecture: global repair schemes, high speed address matching and

replacement, etc

- Low power match circuits, small area penalty

② ECC

- High-speed, low-area penalty ECC scheme


8. Application (H/W, S/W)

8.1 H/W and S/W Techniques to Hide Weaknesses of STT-

MRAM

STT-MRAM is one of the most promising candidates for next-generation NVM. Fast write

and read, a good read signal window, very high endurance, and intrinsic scalability are

expected. The advent of STT-MRAM, a byte-addressable and non-volatile memory

technology, has the potential to usher in a new era of computing where in-memory data

structures are persistent and can be reused directly across machine restarts. However,

mass-produced STT-MRAM products may not achieve the low latency performance of

existing DRAM products. Will this become a roadblock to fast adoption of STT-MRAM in

mainstream computing? What are techniques to overcome relatively long access latency of

STT-MRAM (as compared to DRAM)? Additionally, how can we identify, monitor, repair

and isolate problematic memory cells? How can we incorporate or enable effective system-

level error correction capabilities?

Topics of Interest (not limited to)

① New intelligent memory controller architectures

② Novel CPU architectures and memory hierarchy designs

③ New effective memory and storage management techniques at the system level

8.2 Techniques to Protect STT-MRAM Systems against

Attacks and Power Failures

Arguably the most difficult security problems in several fields of computer science involve

protecting applications and sensitive data from malicious and errant users and programs.

The available solutions are not expected to be sufficient in future STT-MRAM systems as

they all culminate in some complex piece of software protection that determined and skilled

parties can analyze and remove, given enough resources and time. What are new

innovative ways of protecting future STT-MRAM systems from attacks, errors and power

failures? Will new software that exploits STT-MRAM's non-volatility be more vulnerable to


attacks or not? In turn, can we utilize the large, non-volatile capacity offered by STT-MRAM

to develop strong security measures?


① Potential new problems in future STT-MRAM systems and effective countermeasures

② Novel algorithms for guaranteeing system level security

③ Trusted yet efficient data processing in STT-MRAM systems

8.3 Novel Applications on STT-MRAM Systems

STT-MRAM is a scalable technology that has the potential to enable unprecedented main

memory density in future systems. Furthermore, STT-MRAM offers large, non-volatile

memory capacity on the fast system bus (or elsewhere). How can we utilize the capacity,

speed, and non-volatility of STT-MRAM in mobile platforms for better user experiences?

How can STT-MRAM help improve the capabilities of servers in enterprises and data

centers? Would storage systems benefit from the use of STT-MRAM? Will STT-MRAM

facilitate new forms of computing platforms?


① New killer applications and system use cases enabled by the STT-MRAM technology

② Practical single address space computer systems

③ Novel techniques to enhance the performance, power and usability of mobile platforms

using STT-MRAM

④ New server systems and storage box designs that build on STT-MRAM

8.4 Exploiting New Design Trade-Offs

There are established memory technologies like DRAM and NAND flash that have stood

the test of time. When STT-MRAM is added to the mix, interesting new hybrid memory and

storage designs and new design trade-offs may have to be made. For example, flash

memory could continuously offer the best storage density, albeit at much lower

performance levels compared with DRAM and STT-MRAM. What are the system design

implications of having these technologies with different characteristics? What are new


requirements on individual devices when all these technologies are available to platforms?


① New high performance, low power, and reliable system architectures that exploit

different memory technologies

② Techniques to exploit new system and device level design trade-offs,

e.g., performance vs. data retention time

③ Novel hybrid memory system architectures and new requirements on devices


9. Emerging Technology

9.1 Materials and Designs Exploiting Spin-orbit Effects for

Memory Switching

Spin-Orbit effects, like the Spin-Hall effect and Rashba effect, can induce high spin

accumulation with in-plane polarization in presence of in-plane currents. It was demonstrated

recently that this effect can be utilized to enable magnetic layer switching using in-plane

currents. However need to demonstrate high efficiency of the SO-induced switching for

standard for STT-MRAM i-PMA and B-PMA magnetic layers. Need also to develop materials

with perpendicular SO-induced polarization.

Targets

① High efficiency SO-induced switching: SO-induced polarization more than 0.35 for

standard iPMA and BPMA magnetic layers

② STT-MRAM compatible materials with perpendicular SO-induced polarization

9.2 Materials and Designs Exploiting Voltage-Controlled

Anisotropy for Memory Switching

Modification of magnetic anisotropy by application of a voltage to an insulating layer adjacent

to the magnetic layer was demonstrated recently as a powerful mean of controlling the cell

stability. The magnitude of this effect however very small: total change of the anisotropy by

-MRAM applications

Targets

① -MRAM

compatible magnetic material

9.3 MLC and 3D STT-MRAM Technology

STT-MRAM cost per bit can be reduced significantly by utilizing arrays of MTJs that can

each store more than one bit (MLC or multi-level cell) or by stacking multiple arrays of MTJs


on top of each other to form a 3D structure.

Targets

① Novel MTJ materials and structures that can store two or more bits per cell (four or more

discrete resistance states).

②Novel cell designs, fabrication processes and circuit designs and architectures for 3D

stacked STT-MRAM arrays.

③Novel selector device materials and structures for 3D stacked cross-point STT-MRAM

arrays. The ideal selector device is a thin-film bipolar diode with high on-off ratio.

④Novel switching and reading mechanisms to allow reliable writing and reading of the MLC

device stack.

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