Setup and Hold Violations
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Tutorial: Understanding Setup and Hold Violations in Digital System Design Anil Krishna Student, NCSU February 2008
Transcript of Setup and Hold Violations
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Tutorial:
Understanding Setup and Hold Violations in DigitalSystem Design
Anil Krishna
Student, NCSU
February 2008
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D1 Q1 Q2 Q3D2 D3
Flipflop1 Flipflop2 Flipflop3Comb 1 Comb 2 Comb 3
Clock
Signals
at inputsto FFs
The flipflops shown are positive edge triggered, i.e. on the positive edge of the clock, theytakes the value of the signal at its input and send it to the flipflop’s output after a small delaycalled the tclock-to-Q
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D1 Q1 Q2 Q3D2 D3
The flipflops do their job correctly only if the signal at their inputs does not change for sometime before the clock edge (tsetup) and some time after the clock edge (thold).
tholdtsetup
OK
OK Violation!!
(hold violation , to bespecific)
Flipflop1 Flipflop2 Flipflop3Comb 1 Comb 2 Comb 3
Clock
Signals
at inputsto FFs
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D1 Q1 Q2 Q3D2 D3
In addition, the clock signal, which flows around the system on a separate set of wirescalled the clock tree, has its own variability, called skew .
Flipflop1 Flipflop2 Flipflop3Comb 1 Comb 2 Comb 3
Ideal Clock
Real Clock
tskew
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D1 Q1 Q2 Q3D2 D3
Time to propagate a valid (no violations) signal at D2, to D3, counting from the clock edgeat Flipflop2, is invariably = tclock-to-Q + tlogic. And for Flipflop3 to latch it, this signal has to bemaintained at D3 for tsetup time before the clock tree sends the next positive edge of theclock to Flipflop3.
Flipflop1 Flipflop2 Flipflop3Comb 1 Comb 2 Comb 3
Clock tsetuptlogictclock-to-Q
As long as the next clock edge reaches Flipflop3 after this time, D2 will faithfully
make it to Q3
D2 makes it to Q2
Q2 makes it to D3
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D1 Q1 Q2 Q3D2 D3
<=
Flipflop1 Flipflop2 Flipflop3Comb 1 Comb 2 Comb 3
Ideal Clock
Real Clock
(worst case – both edges as close to each other as possible)tclock-to-Q + tlogic + tsetup
tclock
tclock - tskew
tclock-to-Q + tlogic + tsetup tclock - tskew
Therefore, to make sure the signal is SETUP at the input of Flipflop3 far enough ahead ofthe clock edge …
That is, to prevent setup violations…
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D1 Q1 Q2 Q3D2 D3
For D2 to be able to send its signal to Q2, it must be left unchanged for thold time after aclock edge. That is, during this time, a signal from D1 should not be able to race through thecombinational logic Comb1 and make it to D2.
Flipflop1 Flipflop2 Flipflop3Comb 1 Comb 2 Comb 3
Clock at ff2
Clock at ff1
thold
tlogictclock-to-Q
As long as it takes D1 longer to get to D2 than the time D2
should be left undisturbed after its clock (t hold ), D2 will
faithfully make it to Q2.
D1 makes it to Q1
Q1 makes it to D2
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D1 Q1 Q2 Q3D2 D3
Flipflop1 Flipflop2 Flipflop3Comb 1 Comb 2 Comb 3
Clock at ff2
Clock at ff1
thold
tclock-to-Q + tlogic
tskew + thold
<=
Therefore, to make sure the signal is HELD properly at the input of Flipflop2 without theinput of the previous Flipflop (D1) racing through …
That is, to prevent hold violations…
tskew
tskew + tholdtclock-to-Q + tlogic
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<=
to prevent hold violations …
tskew + thold_maxtclock-to-Q_min + tlogic_min
<=
tclock-to-Q_max + tlogic_max + tsetup_max tclock - tskew
to prevent setup violations …
In general, an inequality should still be satisfied if you use the largest possible values on the side that is supposed to be smaller, and the smallest possible values on the side that is supposed to be larger.
Summary
