Session 3: Test and...
Transcript of Session 3: Test and...
Session 3: Test and Verification
Shiva – a Hybrid Constraint Solver for Verification and Test: Tim Cheng (15 min.)Embedded flash memory testing – CW Wu (15 min.)Fault Diagnosis – Shi-Yu Huang (15 min.)Verification – Jing-Yang Jou (15 min.)Analog/Mixed-Signal Testing - Juin-Lang Huang (15 min.)Discussion – Tim Cheng
Shiva – A Hybrid Constraint Solver for Verification and Test
Tim ChengUniv. of CaliforniaSanta Barbara, CA
Outline
SHIVA – A hybrid constraint-solver for verificationA self-referential technique for gate-level arithmetic circuit verification
SHIVA - Overview
Efficient constraint solver for Boolean and arithmetic domains
ATPG for Boolean controlPresburger Math for Arithmetic Data-pathTightly integratedFinds best partition dynamicallyCan handle limited non-linear math (not implemented yet)Has application in property checking and function vector test generation10-1000x improvement over Boolean ATPG
SHIVA Architecture
ParserParser
ADDADD
GenerateCuts
GenerateCuts
FrontFront--EndEnd
ATPGSolverATPGSolver
SolverManagerSolver
ManagerArithmetic
SolverArithmetic
Solver
BackBack--EndEnd
GeneratorGenerator
Learned Constr.Learned Constr.
AnalyzeAnalyze
Constr. ModuleConstr. Module
Templates
Circuit Model
Control Logic
Arithmetic Data-path
SystemMemory
Output
Output
Output
Input
Input
Data
Data
Data
Control-Data path-Memory Cut
Overall Solver
BooleanSpace
Pruned byConstraint Propagation
Arithmetic Space
Decision
Conflict
Boolean / Arithmetic Boundary
Arithmetic Space
Pruned byConstraint Propagation
Example
Non-Linear systemg = ( f == e) ∧ (e = ((sel’.c ∨ sel.d) ∧ ( c = a1 + a2) ∧ (d = b1 +b2)))
Value Assignments on sel and g by ATPGEg: {sel, g} = {0,1}Solution is IS_Satisfiable (f == a1 + a2)
AdvantageOnly decision points here are 1 bit g and 1 bit selIf comparator was in Boolean solver, we have 64 decision points.
32
32a1
c
d eg=
+
+
f
sel
32a232b132b2
Boolean / Arithmetic Boundary
To controller
from controller
Hybrid Solver
ATPG for search in Boolean SpaceSequential ATPGModified FAN with several enhancements
Improved back-trace, Conflict analysis & Dynamic learningGlobal arithmetic solution for Arithmetic space
Based on value requirements for given property and requirements generated during ATPG
Efficient bounding techniques usingImplication in Boolean LogicConstraint Propagation in ArithmeticLearned constraints from the Constraint Module
Data-Path Constraint Solving
System of equationsVariable are inputs and outputs Equations are derived from
data-path functionality & constraints
+
ab
c
o a + 2.b + c = o; a <= 4; a > 0;b <= 4; b > 0;c <= 8; c > 0;o = 2; (constraint)Solution :
{a,b,c} = { (2,0,0), (0,1,0), (0,0,2), (1,0,1) }
++
Arithmetic SolverBased on Omega Library (U. Maryland, Coll. Park.)
Based on Presburger Arithmetic Arithmetic based on set algebra
Can handle mod-2 arithmeticHandles { ≥ , ≤ , < , = , > , − , + , ¬ }Handles multiply by const only.Can handle shift, div, rotate
Not implemented yetNon-linear operations can increase complexityExtend solver to non-linear operations in future.
Preliminary Experiments
GCD circuitUsed Assignment Decision Diagram (ADD) to extract properties8 properties extracted Hybrid approach was compared with ATPG
ADD GenerationAn Example
L DFF
!
+ +
&0
x1FFFE
0x17FFE
||
&
!
&
Fpufrcpainstfp1h
Fpufrcpainstfp1h
Fpufrc pai n
stfp1l
1
Fpuw
akeupm
iscregh
Fpulbpmsrcfp1h[80:64]
Fpulbpm
srcfp 1h81
Fpudivexpevencifp1h
qclk10
Fpuwakeupmiscfp1l
Fpuscancmd111l
LDFF
Fpuwakeupmiscfp1l Fpudivsignfp2h Fpudivexpfp2h
qclkfpudivexpd1
w1 w2 w3
w4
w2
Results on GCD
Prop No Shiva4-bit 8-bit 16-bit
1 0.03 0 0.01 0.012 0.12 0.01 0 0.013 0.19 0.67 239.33 *4 0.2 0.48 195.57 *5 0.21 0.59 212.77 *6 0.19 0.65 252.43 *
7(F) 1.19 1.17 * *8(F) 0.61 0 * *
9 2.29 7236.8 * *10 1.6 4125.54 * *
Boolean ATPG
On-Going Work/Research Plan
Improve Sequential ATPG to fastest known SAT/ATPG solverContinue the development of the hybrid solverConstraint extraction using ADD/EFSM Use extracted constraints for efficient property checkingShow functional TG is feasible using SHIVA
Outline
SHIVA – A hybrid constraint-solver for verificationA self-referential technique for gate-level arithmetic circuit verification
Gate-Level Arithmetic Circuit Verification
Problem: Is the given gate-level netlist implementing the function of A*B*C+A*E?Key issues:
Difficulty of verifying individual arithmetic operatorsOperand ordering problemMerged arithmeticCircuit transformation by arithmetic relation
Self-referential technique: addresses the first three issues at the gate level.
Varieties of Arithmetic Architectures
ab
Addstep Radix-4BoothCSA tree Wallace Tree
CPA or CLA
CSA
Recode Logic
2's compl' signed
Different addition reduction trees with/without recoding.
Example: Multiplier
Self-Referential Verification – Basic Idea
Use a gate-level implementation to verify itselfUtilize functional equations of the intended arithmetic functionApply inductive definition to divide the problem into a set of sub-problemsApply logic equivalence checking to solve each sub-problemExample: A × B
(an-1 an-2 .. a0) × (bn-1 bn-2 .. b0)= (an-1 an-2 .. a0) × (0 bn-2 .. b0) + (an-1 an-2 .. a0) × (bn-1 0 .. 0)
Multiplier Verification – Step I
Multiplier under Verification
Multiplier under Verification
…an-1 …a0an-2
…bn-1 …b0bn-2
Equivalence Checking
Equivalence Checking
Equivalence If the reduced multiplier (aIf the reduced multiplier (ann--11 aann--22 .. a.. a00) ) ×× ((00 bbnn--22 .. b.. b00) is correct,) is correct,then the original multiplier then the original multiplier (a(ann--11 aann--22 .. a.. a00) ) ×× ((bbnn--11 bbnn--22 .. b.. b00) is also ) is also correctcorrect..
bn-1
constructMultiplier under
VerificationMultiplier under
Verification
…an-1 … a0an-2
…0 … b0bn-2
an-1
Mux
… a0an-2 ……00 0
AdderAdder
…
Multiplier Verification – Step II
Multiplier under Verification
Multiplier under Verification
…an-1 …a0an-2
…0 …b0bn-2
Equivalence Checking
Equivalence Checking
Equivalence If the reduced multiplier (aIf the reduced multiplier (ann--11 aann--22 .. a.. a00) ) ×× ((00 00 bbnn--33 .. b.. b00) is ) is correct,correct, then the original multiplier then the original multiplier (a(ann--11 aann--22 .. a.. a00) ) ×× ((bbnn--11 bbnn--22 .. .. bb00) is also correct) is also correct..
bn-2
constructMultiplier under
VerificationMultiplier under
Verification
…an-1 … a0an-2
…0 … b00 bn-2
an-1
Mux
… a0an-2 ……00 0
AdderAdder
…
More Examples
Triple product
)..()0..00..0()..()..0..0()..()..(
)..()..0..0()..()..(
011
01020101
01010101
wwzwwzzyyxx
wwzzyyxx
nln
nlnnn
nlnnn
−−−
−−−−−
−−−−−
×+×+×=
×+×
).( wzyx ×+×
).( zyx ××
)..()..()0..00..0()..()..()..0..0()..()..()..0..0(
01011010102
010101
zzyyxzzyyxxzzyyxx
nnlnnnln
nnln
−−−−−−−−
−−−−
××+××=××
Inner product
)..()..0..0()..()..0..0()..()..0..0(
01010102
0101
yyxxyyxxyyxx
nlnnln
nln
−−−−−−
−−−
×+×=×
Which Operand to Decompose?
Decompose the one with small fanout cone first.Results in simpler equivalence checking problems.Handles the operand ordering problem and produce the correct decomposition properly.
Which Operand to Decompose?
HA
HA
HA
HA
HA
HA
HAFAFAFAFAFAFAFA
FA
FA
FA
FA FA FA FA FA FA FA
FA FA FA FA FA FA FA
FA FA FA FA FA FA
FA FA FA FA FA FA FA
FA FA FA FA FA FA
FA FA FA FA FA FA
An 8-bit multiplier
a0a1a2a3a4a5a6a7
b7
b6
b5
b4
b3
b2
b1
b0fanout cone of a's MSB
fanout cone of b's MSB
Analyze the fanout cone of bit variablesDecompose the ones with small fanout cone first.
Experimental Results - A*B
0
1000
2000
3000
4000
5000
6000
7000
16 32 48 64 80 96 112 128
Multiplier size (bit)
Tim
e (se
c)
addstepcsatreeclaboothwallace
Platform: P3 733Mhz computer with 256MB memory
Memory Usage - A*B
0
1
2
3
4
5
16 32 48 64 80 96 112 128
Multiplier size (bit)
Mem
ory u
sage
(MB)
addstepcsatreeclaboothwallace
*Verification of C6288 takes only 4.67sec and 0.94MB!
Experimental Results – A*B+C
0
500
1000
1500
2000
2500
16 32 48 64 80
Multiplier size (bit)
Tim
e (se
c)
addstep
csatree
wallcebooth
*Memory usage is between 0.5M to 4.6M
Experimental Results
0
500
1000
1500
2000
16 32 48 64 80
Multiplier size (bit)
Tim
e (se
c)
addstep - AxB+CxD
csatree - AxB+CxD
addstep - AxBxCcsatree - AxBxC
*Memory usage is between 0.4M to 2.0M
Self-Referential Verification
A framework for gate-level arithmetic circuit verification utilizing functional equations and structural information.Heuristics proposed to simplify the resulting equivalence checking problems.Capable of verifying a large class of arithmetic circuits.Publications: ICCAD2001, DAC2002