Serial Transmission & Synchronization

Mukesh Patel School of Technology Management and Engineering

Content

Transmission modeParallel transmissionSerial transmission

Synchronous transmissionasynchronous transmission

Transmission mode

A given transmission on a communications channel between two machines can occur in several different ways.

The transmission is characterized by: the direction of the exchanges. the transmission mode: the number of bits sent

simultaneously simultaneously. synchronization between the transmitter and receiver.

The direction of the exchanges

There are 3 different transmission modes characterized according to the direction of the exchanges.

Simplex Half Duplex Full Duplex

Simplex Mode In simplex mode the communication is uni-directional as on a one-way

street. Only one of the two stations on a link can transmit, the other can only

receive. Examples: Keyboard, Monitor, Mouse

Half Duplex In half-duplex mode, each station can both transmit and receive but not at

the same time. When one device is sending, the other can only receive. The half-duplex mode is like a one-lane road with two-directional traffic. The entire capacity of the communication channel is taken over by

whichever of the two devices is transmitting at the time. e.g. walkie-talkie

Full duplex In full-duplex mode both stations can transmit and receive

simultaneously. The full duplex mode is like a two-way street with traffic flowing in

both directions at the same time. In full duplex mode signals going in either direction share the capacity

of the link. This sharing can occur in two ways either the link must contain two

physically separate transmission paths, one for sending and the other for receiving or the capacity of the channel is divided between signals traveling in opposite directions.

Data Transmission-Modes

Parallel Transmission Binary data, consisting of 1’s and 0’s,may be

organized in to groups of n bits each.Computers produce and consume data in groups of

bits.By grouping we can send data n bits at one time.Each bit has its own wire.N bits of one group can be transmitted with each

clock tick from one device to another.

Parallel Transmission

Serial TransmissionIn serial transmission one bit follows another, so we need

only one communication channel instead of n to send n bits.

The advantage of serial over parallel transmission is that with only one communication channel.

Serial transmission reduces the cost of transmission over parallel roughly by a factor of n.

Communication within devices is parallel, conversion devices are required at the interface between the sender(parallel-to-serial) and receiver (serial-to-parallel).

Serial Transmission

Serial Transmission

Serial transmission can occur in one of two ways.

SynchronousAsynchronous

Synchronous TransmissionIn synchronous transmission, the bit stream is

combined in to longer frames which may contain multiple bytes.

Each byte is introduced on to the transmission link without a gap between it and the next one.

It is left to the receiver to separate the bit stream in to bytes for decoding purposes.

Timing is important in synchronous transmission

Synchronous Transmission

Advantages of synchronous transmission

The advantage of synchronous transmission is speed.

Byte synchronization is accomplished in the data link layer.

The start and stop bits in each frame of asynchronous format represents wasted overhead bytes that reduce the overall character rate. These start and stop bits can be eliminated by synchronizing receiver and transmitter. Receiver and transmitter can be synchronized by having a common clock signal as shown in above fig.

Synchronous Transmission

Serial In - Serial OutShift Registers

• A basic four-bit shift register can be constructed using four D flip-flops, as shown below.  

• The operation of the circuit is as follows.  The register is first cleared, forcing all four outputs to zero.  

• The input data is then applied sequentially to the D input of the first flip-flop on the left (FF0).  

• During each clock pulse, one bit is transmitted from left to right.  Assume a data word to be 1001.  The least significant bit of the data has to be shifted through the register from FF0 to FF3.

FF0 FF1 FF2 FF3

0 0 0 0CLEAR

FF0 FF1 FF2 FF3

0 0 0 01001

FF0 FF1 FF2 FF3

1 0 0 0100

FF0 FF1 FF2 FF3

0 1 0 010

FF0 FF1 FF2 FF3

0 0 1 01

FF0 FF1 FF2 FF3

1 0 0 1

0

00

000

0000

• In order to get the data out of the register, they must be shifted out serially.  

• This can be done destructively or non-destructively.  For destructive readout, the original data is lost and at the end of the read cycle, all flip-flops are reset to zero.

FF0 FF1 FF2 FF3

1 0 0 10000 0000

FF0 FF1 FF2 FF3

0 1 0 0000 1000

FF0 FF1 FF2 FF3

0 0 1 000 0100

FF0 FF1 FF2 FF3

0 0 0 10 0010

FF0 FF1 FF2 FF3

0 0 0 0 1001

• To avoid the loss of data, an arrangement for a non-destructive reading can be done by adding two AND gates, an OR gate and an inverter to the system.  The construction of this circuit is shown below.

• The data is loaded to the register when the control line is HIGH (ie WRITE).  The data can be shifted out of the register when the control line is LOW (ie READ).  This is shown in the animation below.

FF0 FF1 FF2 FF3

0 0 0 01001

FF0 FF1 FF2 FF3

1 0 0 0100 0

FF0 FF1 FF2 FF3

0 1 0 010 00

CLEAR

WRITE

WRITE

FF0 FF1 FF2 FF3

0 0 1 01 000

WRITE

FF0 FF1 FF2 FF3

1 0 0 1 0000

WRITE

FF0 FF1 FF2 FF3

0 1 0 0 1000

READ

FF0 FF1 FF2 FF3

0 0 1 0 0100

READ

FF0 FF1 FF2 FF3

0 0 0 1 0010

READ

FF0 FF1 FF2 FF3

0 0 0 0 1001

READ

Synchronous input/output transfer

• In synchronous input/output data transfer, all devices derive timing information for a common clock signal.

• The fig. shows the timing diagram for synchronous input/ouput transfer.

• At time t0, the processer places the device address on the address lines of system bus and sets the control lines to perform the input operation.

• During time t0-t1, addressed device gets the address and it recognized that and input operation is requested.

• At time t1, address device places its data on the data bus. At the end of bus cycle that is at time t2 the processor reads the data lines and loads the data from data bus into its input buffer.

• The timing diagram for an output operation is shown in the fig. Here , processor places the output data on the data lines when it transmits the address and control line information’s.

• At time t1, the addressed device reads the data lines and loads the data into its data buffer. The processor simply assumes that, at t2, the output data have been received by the i/o device and the cycle ends