Serial Port Usage Board can be powered by 8-28 VDC or ...
Transcript of Serial Port Usage Board can be powered by 8-28 VDC or ...
Te chnologic Sys t e ms Da te
Tit le :
Re v: De s igne r She e t of
TS-7680 Docume nta t ion
1B
Se pt . 1, 2015
20
Boa rd ca n be powe re d by 8-28 VDC or 24VAC
SiLa b uC is powe re d up firs t , t he n
- USB De vice t o Cons ole conve rs ion
SiLa b uC doe s t he s e funct ions :
- Cont rols MX286 Sle e p mode
- Ca n re a d Pus h Swit ch for Wa ke -up
- Cont rols MX286 powe r up s e que nce
- Me a s ure s Ana log Powe r Ra ils
- Cont rols Supe rCa p cha rging
Comme nt s :
UART0 --> Blue Tooth or othe r
RS-232 RJ45 (2)
Modbus RJ45
Scre w Te rm RS-485UART4
Se ria l Port Us a ge
it cont rols t he MX286 s t a rt up
All Pa rt s a re Indus t ria l Te mp
Re v.A --> B Cha nge s
2) Cha nge d NAND to e MMC
3) Cha nge d to SiLa b micro
5) Curre nt Loop ca n be cont rolle d
6) Adde d SPI Fla s h for boot ing
8) Adde d Supe rCa p Opt ion
9) Blue tooth now ha s UART HS
10) Cha nge d FPGA to MACH X02
1) Cha nge d to Ve rt ica l ba t t e ry holde r
7) Adde d a cce lome te r opt ion
4) Cha nge d RTC chip t o ST Micro
MAX3100 Da ughte r Ca rd (TTL)
UART1
UART2
UART3
MUX
- Ca n t run on Blue LED
11) Adde d CAN J1939 RC to both port s
ofShe e tDe s igne rRe v:
Tit le :
Da teTe chnologic Sys t e ms
2
TS-7680 SiLa b uC a nd USB De vice port
Se pt . 1, 2015
B 20
USB De vice Port a nd SiLa b uC
USB De vice Port
Blue LED
Pus h Swit ch
SiLa b 4.7V
Progra m
USB
Sca le = 5.57%
Sca le = 44.6%
A/D full s ca le = 2.50V
24 mA ma x loa d
I2C
Sca le = 50%
Sca le = 50%
Ana log
PWM
Sca le = 50%
USBSingle
4GND
15V
2D-
3D+
5FRAME
6FRAME
P2
CONN_USB_B_RA_BLACK
2
3
1
4TVS4
BGX50A_SOT143
C107.1 uF
1
2 LED6
Blue
1
234
SW1
SW_PUSH_RT_TH
D
S
G2
6
1
Q5-A
2
7
RN12-B1.5K
3
6
RN12-C1.5K
4
5
RN12-D1.5K
D
S
G5
3
4
Q5-B
R66
5.1 ohm
FB21
220 ohm
1
2
3
D11
C195.1 uF
C196.1 uF
R138
475K
C6910 uF
SiLa bs
A/D
5.25V Ma x
A/D
TXD
RXD
A/D
A/D
A/D
25P1.1
10DEBUG_DATA
30TXD0_P0.4
15P2.3
14P2.4
26P1.0
13P2.5
8USB_VBUS
22P1.4
21P1.5
23P1.3
5USB_DM
4USB_DP
12P2.6
2P0.0
33PAD
18P2.0
20P1.6
7PWR_IN
17P2.1
31P0.3
16P2.2
6REG_3.3V
29RXD0_P0.5
27P0.7_VREF
28P0.6
24P1.2
9DEBUG_CLK/RESET# 32
P0.2
1P0.1
19P1.7
11P2.7
3GND
U16
SILAB_C8051F383_QFN32
C223.1 uF
C6010 uF
C5910 uF
R161
25.5K
R11820.5K
2500 mV
2
3
1
U8
REF_AN431A_SOT23
R140
475
R14228K
R167
9.1K
R1689.1K
R169
9.1K
R1709.1K
SiL_3.3V
R116
20.5K
R11720.5K
1 8RN11-A
1.5K
5
4
RN20-D10K
3
6
RN16-C47K
4 5RN16-D
47K
1 8RN12-A
1.5K
USB_SILAB_M
USB_SILAB_P
PUSH_SW#
EN_BLUE_LED
SILAB_3.3V
MX286_BLUE_LED
EN_PWR_RAILS#
SILAB_3.3V
5V_BOOST
CPU_PSWITCH
USB_SILAB_M
USB_SILAB_P
CONSOLE_TXD
VIN
CONSOLE_RXD
SILAB_CLK
SILAB_DATA
SILAB_3.3V
5V_BOOST
I2C_DAT
I2C_CLK
EN_BLUE_LED
CPU_1.8V
CPU_CORE
CPU_3.3V
AUX_3.3V
CPU_RESET#
AN_SCAP_1
AN_SCAP_2
SILAB_PWM
AN_CHRG
RAM_1.8V
AN_VINT
USB_5V_DET
5V_BOOST
USB_5V_DET
SILAB_CLK
EN_TOP_OFF
EN_CHRG#
SILAB_DATA
EN_SILAB_REF
EN_SILAB_REF
Te chnologic Sys t e ms Da te
Tit le :
Re v: De s igne r She e t of
TS-7680 MX286 CPU
3
LCD
JTAG, I2C
NAND, PWM
MX286 ARM9 CPU
20
Se pt . 1, 2015
B
UARTs , ADC
NC on
MX283
SD Ca rd
SPI Boot
NC on
MX283
NC on
MX283
SD0
SD2
LCD_00 thru LCD_04
Cont rol Boot Source
All JTAG ha ve 47K int e rna l PU e xce pt RTCK
NC on MX283
a nd 286
a nd 286
a nd 286
BootSPI
RESET#
4 CAN s igna ls
a nd ba ll D7
MX286 a dds
e MMC Int e rfa ce
EN_SPI_BOOT_FLASH is s e t low by CPU
a ft e r done boot ing from SPI
The n SPI s igna ls a re cha nge d to UART2
SD1
To FPGASD3
e MMC
1.8V
Ha rd s t ra ppe d for SPI
a nd UART3 funct ions
The s e s igna ls a re on t he s a me MX28
pins on both Re v.A a nd Re v.B
WIFI_IRQ
PUSH_SW#
FPGA_IRQAll MODBUS s igna ls
DC_DIO4 thru DIO6
FPGA_29LCD_00 thru D06
B14ADC0_HS
C14ADC6
D15ADC5
D13ADC4
D9ADC3
C8ADC2
C9ADC1
C15ADC0
J6AUART0_CTS/DEBUG_RXD
J7AUART0_RTS/DEBUG_TXD
G5AUART0_RX
H5AUART0_TX
K5 AUART1_CTSJ5 AUART1_RTS
L4AUART1_RX
K4AUART1_TX
H6 AUART2_CTSH7 AUART2_RTS
F6 AUART2_RXF5 AUART2_TX
L6 AUART3_CTSK6 AUART3_RTSM5 AUART3_RXL5 AUART3_TX
U3-A
MX286_CPU_IND
R5LCD_D23T5LCD_D22U5LCD_D21R4LCD_D20T4LCD_D19U4LCD_D18R3LCD_D17T3LCD_D16
U3LCD_D15U2LCD_D14T2LCD_D13T1LCD_D12R2LCD_D11R1LCD_D10P3LCD_D09P2LCD_D08
P1LCD_D07N2LCD_D06M3LCD_D05M2LCD_D04L3LCD_D03L2LCD_D02K3LCD_D01K2LCD_D00
P5LCD_CS/ENABLE
N1 LCD_DOTCLKN5 LCD_ENABLEM1 LCD_HSYNC
P4LCD_RD_E/VSYNCH
M6LCD_RESET/VSYNCH
M4LCD_RS/DOTCLK
L1 LCD_VSYNC
K1LCD_WR_RWN/HSYNCH
U3-D
MX286_CPU_IND
Boot
SPI
F7SAIF0_BITCLK/UART4_RXD/PWM5
G6SAIF0_LRCLK/PWM4
G7SAIF0_MCLK/PWM3
E7SAIF0_SDATA0/UART4_TXD/PWM6
E8SAIF1_SDATA0/PWM7
D7SPDIF
A4SSP0_CMD
B4SSP0_DATA7/SSP2_SCK
D5SSP0_DATA6/SSP2_CMD
C5SSP0_DATA5/SSP2_D3
B5SSP0_DATA4/SSP2_D0
A5SSP0_DATA3
D6SSP0_DATA2
C6SSP0_DATA1
B6SSP0_DATA0
D10SSP0_DETECT
A6SSP0_SCK
C1 SSP1_CMDE1 SSP1_DATA3D1 SSP1_DATA0B1 SSP1_SCK
B3SSP2_MISO/UART3_RXD
C3SSP2_MOSI/UART2_TXD
A3SSP2_SCK/UART2_RXD
D4SSP2_SS2/SSP2_D2
D3SSP2_SS1/SSP2_D1
C4SSP2_SS0/UART3_TXD
B2 SSP3_MISOC2 SSP3_MOSIA2 SSP3_SCKD2 SSP3_SS0
U3-F
MX286_CPU_IND
1 8RN21-A
10K
3 6RN18-C
47K
U7GPMI_D03/SSP1_D3
R8GPMI_D02/SSP1_D2
T8GPMI_D01/SSP1_D1
U8GPMI_D00/SSP1_D0
R6SSP3_SCK
L8 CAN_RX0
M8 CAN_TX0
N8GPMI_RDY1/SSP1_CMD
N6GPMI_RDY0/USB0_ID
L9SSP3_MOSI
P8GPMI_WRN/SSP1_SCK
C7I2C0_SCL
D8I2C0_SDA
E14JTAG_RTCK
E11JTAG_TCK
E12JTAG_TDI
E13JTAG_TDO
D12JTAG_TMS
D14JTAG_TRST
T6GPMI_D07
U6GPMI_D06
R7GPMI_D05
T7GPMI_D04
P6SSP3_CS1#
N7SSP3_MISO
N9SSP3_CS0#
M7 CAN_TX1
M9 CAN_RX1
P7SSP3_CS2#
E10PWM4
E9PWM3
K8PWM2/USB0_ID
L7PWM1/DEBUG_TXD
K7PWM0/DEBUG_RXD
U3-C
MX286_CPU_IND
4 5RN19-D
47K
6
3
RN20-C10K
LCD_D[00:23]
LCD_D00
LCD_D01
LCD_D02
LCD_D03
UART0_TXD
RXD2_SPI_CLK
TXD2_SPI_MOSI
RXD3_SPI_MISO
CPU_3.3V
SD0_CLK
SD0_CMD
SD0_D0
SD0_D1
SD0_D2
SD0_D3
YEL_LED#
SD2_D0
SD2_CLK
SD2_CMD
SD2_D1
SD2_D2
SD2_D3
UART0_RTS
UART1_TXD
FPGA_27
FPGA_23
FPGA_25
WIFI_IRQ
EN_HOST_USB_5V
EN_MODBUS_3V#
DC_DIO_5
FPGA_29
DC_DIO_6
MODBUS_FAULT
EN_MODBUS_24V
DC_DIO_4
MX286_BLUE_LED
PUSH_SW#
EN_CAN#
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
JP_SD_BOOT#
LCD_D04
LCD_D05
LCD_D06
JTAG_FPGA_TCK
JTAG_FPGA_TDO
JP_UBOOT#
I2C_CLK
I2C_DAT
CONSOLE_TXD
CONSOLE_RXD
EMMC_CMD
EMMC_D0
EMMC_D1
EMMC_D2
EMMC_D3
EMMC_CLK
FPGA_SPI_MOSI
TXD_CAN0
RXD_CAN0_3V
TXD_CAN1
RXD_CAN1_3V
EN_SPI_BOOT_FLASH
AUX_3.3V
FPGA_SPI_CLK
FPGA_SPI_MISO
GREEN_LED#
RED_LED#
FPGA_21
EN_SD_3.3V#
JTAG_FPGA_TDI
JTAG_FPGA_TMS
POWER_FAIL
FPGA_SPI_CS0#
UART4_RXD
FPGA_12MHZ
TXD3_SPI_CS#
FPGA_IRQ
UART1_RXD
FPGA_SPI_CS1#
UART0_RXD
UART0_CTS
UART4_TXD
ACCEL_INT
ACCEL_INT2
ofShe e tDe s igne rRe v:
Tit le :
Da teTe chnologic Sys t e ms
TS-7680 MX286 CPU Powe r
4B
Se pt . 1, 2015
20PSWITCH ca n be drive n t o 3.3V if a s e rie s 10K re s is us e d
Re g VDD1P5 goe s t o nothing
only fe e ds two 1.2K re s is tors
USB
10K PU
to 3.3V
1V
VDD4P2 is a n output --
D16VDD1P5
A13VDD4P2_DCDC
E17VDD5V
C13 VDDA1
F12 VDDD7G12 VDDD6K12 VDDD4G11 VDDD3G10 VDDD2F11 VDDD1F10 VDDD0
G13 VDDIO_EMI10G17 VDDIO_EMI9G15 VDDIO_EMI8L13 VDDIO_EMI7N15 VDDIO_EMI6N13 VDDIO_EMI5M12 VDDIO_EMI4M11 VDDIO_EMI3R13 VDDIO_EMI2P11 VDDIO_EMI1M10 VDDIO_EMI0
J13 VDDIO_EMIQ2K15 VDDIO_EMIQ1R15 VDDIO_EMIQ0
F9 VDDIO18_3G9 VDDIO18_2G8 VDDIO18_1F8 VDDIO18_0
A7 VDDIO33_8E16 VDDIO33_7J10 VDDIO33_6
J9 VDDIO33_5N3 VDDIO33_4J8 VDDIO33_3
H8 VDDIO33_2G3 VDDIO33_1E6 VDDIO33_0
N17 VDDIO33_EMIA9VSS_USBB11VSSA2_AB13VSSA1C16VSSD6L11VSSD5L10VSSD4U1VSSD3J12VSSD2H12VSSD1A1VSSD0F14VSSIO_EMI10F16VSSIO_EMI9H14VSSIO_EMI8L12VSSIO_EMI7M16VSSIO_EMI6P16VSSIO_EMI5P14VSSIO_EMI4T14VSSIO_EMI3U17VSSIO_EMI2R12VSSIO_EMI1R10VSSIO_EMI0J15VSSIO_EMIQ2M14VSSIO_EMIQ1H16VSSIO_EMIQ0H10VSSIO18_2H9VSSIO18_1H11VSSIO18_0B7VSSIO33_8E15VSSIO33_7K11VSSIO33_6K10VSSIO33_5N4VSSIO33_4K9VSSIO33_3J11VSSIO33_2H3VSSIO33_1E5VSSIO33_0
U3-G
MX286_CPU_IND
C41
15 pF
C42
15 pF
1.2V
1.8V
3.3V
0 = Bounda ry
1 = ETM
A15BATTERY
B15DCDC_BATTA17 DCDC_GND
B17 DCDC_LN
A16 DCDC_LP
B16DCDC_VDDA
D17DCDC_VDDD
C17DCDC_VDDIO
B9 DEBUG_JTAG
A11 PSWITCH
A14 RESETN
C10 TESTMODE
A10USB0DMB10USB0DP
B8USB1DMA8USB1DP
C12 XTAL_VDD
D11XTALI_RTC
A12XTALI
C11XTALO_RTC
B12XTALO
U3-H
MX286_CPU_IND
L5 15 uH
C165.1 uF
C6310 uFC153
.1 uF
C154.1 uF
C6810 uF
C152.1 uF
C151.1 uF
C150.1 uF
C149.1 uF
C148.1 uF
C147.1 uF
C146.1 uF
C145.1 uF
C144.1 uF
C143.1 uF
C142.1 uF
C141.1 uF
C140.1 uF
C139.1 uF
C138.1 uF
C137.1 uF
C136.1 uF
C135.1 uF
C134.1 uF
C133.1 uF
C132.1 uF
C131.1 uF
C130.1 uF
C129.1 uF
C128.1 uF
C125.1 uF
C123.1 uF
C119.1 uF
C118.1 uF
C117.1 uF
C115.1 uF
C114.1 uF
C6110 uF
C157.1 uF
C6210 uF
C156.1 uF
C6510 uF
C155.1 uF
R870.10 ohms
CORE
CP-1.8
CP-3.3
C54
22 uF
25V
R860.10 ohms
C55
22 uF
25V
C56
22 uF
25V
C57
22 uF
25V
C58
22 uF
25V
C185.1 uF
D21
Y1
24 MHz
C186.1 uF
C161.1 uF
2 7RN10-B
1.5K
1
8
RN18-A47K
4 5RN18-D
47K2
7
RN18-B47K
FB10
220 ohm
8
1
RN4-A3.3K
CPU_1.8V
CPU_3.3V
CPU_CORE
CPU_3.3V
CPU_1.8V
CPU_CORE
USB_HOST_P
USB_HOST_M
USB_OTG_M
USB_OTG_P
VDD_4P2
VDD_4P2
CPU_RESET#
CPU_3.3V
CPU_1.8V
CPU_PSWITCH
SW_5V
ofShe e tDe s igne rRe v:
Tit le :
Da teTe chnologic Sys t e ms
TS-7680 DDR2 RAM
5
DDR2 SDRAM
MX286
64M x 16
128 MB
(128 or 256 MByte )
Le ngth of t his t ra ce is
e qua l t o [CLK + Da ta ] le ngths
20B
Se pt . 1, 2015
NC
NC
256 MB
128M x 16
OR
Da ta = Ave ra ge le ngth of a ll da t a t ra ce s
C176.1 uF
C175.1 uF
C174.1 uF
C173.1 uF
C172.1 uF
C171.1 uF
C170.1 uF
M8 A0M3 A1M7 A2N2 A3N8 A4N3 A5N7 A6P2 A7P8 A8P3 A9M2 A10P7 A11R2 A12R8 A13
L2 BA0L3 BA1L1 BA2
J8 CKK8 CK#
K2 CKEL8 CS#F3 LDMB3 UDMK7 RAS#L7 CAS#K3 WE#
A1
VD
D0
E1
VD
D1
J9V
DD
2
M9
VD
D3
R1
VD
D4
J1V
DD
L
J2 VREF
R3 A14R7 A15
A2NC0K9 ODT
F1DQ6G2DQ1H7DQ2G8DQ0H1DQ4H9DQ5H3DQ3F9DQ7D1DQ12C2DQ9D7DQ10D3DQ11C8DQ8D9DQ13B9DQ15B1DQ14
F7LDQSE8LDQS#
B7UDQSA8UDQS#
A9VDDQ0C1VDDQ1C3VDDQ2C7VDDQ3C9VDDQ4E9VDDQ5G1VDDQ6G3VDDQ7G7VDDQ8G9VDDQ9
H8
VS
SQ
9
H2
VS
SQ
8
F8V
SS
Q7
F2V
SS
Q6
E7
VS
SQ
5
D8
VS
SQ
4
D2
VS
SQ
3
B8
VS
SQ
2
B2
VS
SQ
1
A7
VS
SQ
0
J7V
SS
DL
P9
VS
S4
N1
VS
S3
J3V
SS
2
E3
VS
S1
A3
VS
S0
E2NC1
U19
DDR2_128MB_X16_ITEMP
C160.1 uF
R517.87K
R527.87K
N10EMI_A14T9EMI_A13U11EMI_A12T10EMI_A11U13EMI_A10P10EMI_A09U9EMI_A08N11EMI_A07R9EMI_A06R11EMI_A05U10EMI_A04T11EMI_A03U14EMI_A02U12EMI_A01U15EMI_A00
N12EMI_BA2T12EMI_BA1T16EMI_BA0
U16EMI_CASN
P12EMI_CE0N
P9EMI_CE1N
T13EMI_CKE
L17EMI_CLK
L16EMI_CLKN
F17 EMI_D15
F13 EMI_D14
H17 EMI_D13
H13 EMI_D12
J14 EMI_D11
G14 EMI_D10
H15 EMI_D09
G16 EMI_D08
M17 EMI_D07
L14 EMI_D06
P17 EMI_D05
P13 EMI_D04
N14 EMI_D03
P15 EMI_D02
M13 EMI_D01
N16 EMI_D00
L15 EMI_DDR_OPEN_FB
K14 EMI_DDR_OPEN
F15 EMI_DQM1
M15 EMI_DQM0
K16 EMI_DQS0N
J16 EMI_DQS1N
J17 EMI_DQS1
K17 EMI_DQS0
T17 EMI_ODT1
R17 EMI_ODT0
R16EMI_RASN
K13EMI_VREF1
R14EMI_VREF0
T15EMI_WEN
U3-B
MX286_CPU_IND
C158.1 uF
C177.1 uF
C178.1 uF
C103.1 uF
C106.1 uF
C104.1 uF
R547.87K
R537.87K
RAM_1.8V
RAM_A[00:15]
RAM_A00
RAM_A01
RAM_A02
RAM_A03
RAM_A04
RAM_A05
RAM_A06
RAM_A07
RAM_A08
RAM_A09
RAM_A10
RAM_A11
RAM_A12
RAM_A13
RAM_BA0
RAM_BA1
RAM_BA2
RAM_CLK_P
RAM_CLK_M
RAM_CKE
RAM_CS#
RAM_DQM0
RAM_DQM1
RAM_RAS#
RAM_CAS#
RAM_WE#
RAM_1.8V
RAM_DQS0_P
RAM_DQS1_P
RAM_1.8V
RAM_ODT
RAM_D[00:15]
RAM_A14
CPU_1.8V
RAM_DQS0_M
RAM_DQS1_M
RAM_D07
RAM_D03
RAM_D06
RAM_D11
RAM_D14
RAM_D15
RAM_A00
RAM_A01
RAM_A02
RAM_A03
RAM_A04
RAM_A05
RAM_A06
RAM_A07
RAM_A08
RAM_A09
RAM_A10
RAM_A11
RAM_A12
RAM_A13
RAM_A14
RAM_D14
RAM_D15
RAM_BA2
RAM_BA1
RAM_BA0
RAM_CAS#
RAM_RAS#
RAM_WE#
RAM_CKE
RAM_CLK_P
RAM_CLK_M
RAM_ODT
RAM_DQM1
RAM_DQM0
RAM_DQS1_P
RAM_DQS0_P
RAM_DQS1_M
RAM_DQS0_M
RAM_CS#
RAM_D00
RAM_D01
RAM_D02
RAM_D03
RAM_D04
RAM_D05
RAM_D06
RAM_D07
RAM_D08
RAM_D09
RAM_D10
RAM_D11
RAM_D12
RAM_D13RAM_D00
RAM_D02
RAM_D01
RAM_D05
RAM_D04
RAM_D13
RAM_D08
RAM_D12
RAM_D10
RAM_D09
RAM_1.8V
Te chnologic Sys t e ms Da te
Tit le :
Re v: De s igne r She e t of
5V Powe r Supply (2000 mA)
C81 mus t be ve ry ne a r U17
Powe r Input
8-28 VDC or AC
.063 hole
6
TS-7680 5V a nd Swit che d Powe r
Se pt . 1, 2015
B 20
Swit che d Powe r
Ris e t ime of both output s
me a s ure d a t ~ 1V/ms
USB a nd Da ughte r
1.225V
Sca le = 44.6%
FB26 not pop if
SCa p us e d
Swit che d 5V Powe r
C98
10 uF
50V
VIN
C80
.1 uF
C81
.1 uFTVS18
43V
FB12
220 ohm
1
2
3
CN5
CONN_OSTOQ037501_BLACK
GND
C95
1 uF
FB16
220 ohm
6VDD
3EN_FET1
2EN_FET2
7GND
4DRAIN_1
5SOURCE_1
8SOURCE_2
1DRAIN_2
U22
SLG_DUAL_FET_SW_SMT8
C168
SW_5V
1 8RN17-A
47K
2 7RN17-B
47K
-
+
3
4
1
2
FW1
RECT_FW1A_DF10S_1000V
C99470 uF63V
FB15
220 ohm
3VIN
4VIN
1VCC
2SHUTDN#
11SS
8RT
5SYNCH
9RAMP
17SW
18SW
19PRE
15IS
16IS
12OUT
7FB
6COMP
20BOOST
14
PG
ND
13
PG
ND
10AGND 21
PAD
U17
LM5005_SMT20
C49
22 nF
C48
22 nF
C44
330 pF
C43
330 pF
R115
20.5K
R78
41.2K
R1461.58K
D3
C46
22 nF
C47
22 nF
R694.99K
C51
22 uF
25V
C52
22 uF
25V
C53
22 uF
25V
L7
33 uH
R64
5.1 ohm
R65
5.1 ohm5V
FB20
220 ohm
R16225.5K
R11920.5K
FB26
220 ohm
6VDD
3EN_FET1
2EN_FET2
7GND
4DRAIN_1
5SOURCE_1
8SOURCE_2
1DRAIN_2
U11
SLG_DUAL_FET_SW_SMT8
1 8RN16-A
47K
2 7RN16-B
47K
D
S
G2
6
1
Q45-A
D
S
G5
3
4
Q45-B
V_INT
VIN
HOST_USB_5V
DC_5V
5V_BOOST
EN_DC_5V
EN_HOST_USB_5V
AN_VINT
5V_BOOST
5V_BOOST
SILAB_3.3V
SW_5V
EN_PWR_RAILS#
Te chnologic Sys t e ms Da te
Tit le :
Re v: De s igne r She e t of
TS-7680 AUX Powe r Re g, Boot St ra p
20B
Se pt . 1, 2015
7
Boot
3.3V
ETM off
TEST off
Boot St ra pBia s Re s .
Source
LCD_3 LCD_0
0 0 1 0
1 0 0 1
SPI
SD Ca rd
0 0 0 0 USB
Aux. 3.3V Re g
RC = 4 x e -6
St ra ppe d
SPI Boot
0 1 0 0 NAND
RAM 1.8V Re g
RC = 4 x e -6
3.31V typ
1.81V typ
Se le ct Boot
Da ughte r Ca rdInt e rfa ce
0.4V = L
1.5V = H
600 mV
3VIN
1GND
2EN
4SW
5GND
6FB
7PAD
U6
REG_1A_RT8016_DFN6
L23.3V
C6410 uF
FB13
220 ohm
R1729.1K
R8241.2K
C31
100 pF
1 2
3D6
DIODE_BAV99-2_SOT23
C6610 uF
4 5RN27-D
10K
3 6RN27-C
10K
2 7RN27-B
10K
1 8RN27-A
10K
1 8RN23-A
10K
2 7RN23-B
10K
3 6RN23-C
10K
4 5RN23-D
10K
0.4V = L
1.5V = H
600 mV
3VIN
1GND
2EN
4SW
5GND
6FB
7PAD
U5
REG_1A_RT8016_DFN6
L11.8V
C7110 uF
FB25
220 ohm
R8141.2K
C30100 pF C72
10 uF
R11420.5K
2
7
RN21-B10K
3
6
RN21-C10K
14
12
10
8
6
4
2
11USB-
9
7
5GND
3GND
1
13USB+
165V
155V
HD1
HD_2X8_DC_2.54MM_TH
FB11
220 ohm
2 7RN7-B
3.3K
R1719.1K
LCD_D[00:23]
AUX_3.3V YEL_LED#
AUX_3.3V
CPU_3.3V
SW_5V
LCD_D01
RAM_1.8VSW_5V
LCD_D00
LCD_D03
LCD_D02
LCD_D04
LCD_D05
LCD_D06
EN_1.8V_RAIL
EN_1.8V_RAIL
DC_RXD_5V
DC_DIO_6
DC_5V
DC_TXD_3V
POE_TX
POE_45
POE_RX
POE_78
USB_OTG_P
USB_OTG_M
DC_DIO_4
DC_DIO_5
VIN
AUX_3.3V
Te chnologic Sys t e ms Da te
Tit le :
Re v: De s igne r She e t of8
TS-7680 Ethe rne t Swit ch
Se pt . 1, 2015
B 20
Auto MDIX is s upport e d
Pola rit y Corre ct ion a ls o s upport e d
1.2V
10/100 Ethe rne t 4-Port Swit ch
St ra ppe d for
RMII MAC mode
with 3.3V Le ve ls
MDI a ddre s s A4 de fa ult s t o "1"
Port 1 LEDs
Port 0 LED
All Port 6 pins
ha ve PU or PD bia s
Re quire s Re s e t# a s s e rt e d
for 10 ms a ft e r powe r
MX283
"0111" = RMII MAC mode
NC on
MX283
1.2V Re gula tor
R12051
R12151
R12251
R12351
C206.1 uF
8 MHz ma x.
PHY 1
PHY 0
Input
a nd OD Output
We a k PU
40MDIO
39MDC
58ROW_0_LED/SMI_ADD4
59ROW_1_LED/NO_CPU
60ROW_2_LED
61COL_0_LED
63COL_1_LED
64COL_2_LED
1COL_3_LED
5AVDD_PLL
50P5_OUT_EN/PWR2.5V
53P5_IN_D2/GPIO2
52P5_IN_D3/GPIO3
44P5_OUT_D3/MODE3
45P5_OUT_D2/MODE2
46P5_OUT_D1/MODE1
47P5_OUT_D0/MODE0
49P5_OUT_CLK
51P5_IN_CLK
54P5_IN_D1
55P5_IN_D0
56P5_IN_DV
34VDD18_OUT
35VDD18_IN
33VDD_33
48P5_VDDO
2VDD_CORE_0
17P6_COL/GPIO5
57VDD_CORE_2
41INT#
43P5_CRS/GPIO0
42P5_COL/GPIO1/FIBER
62EE_VDDO
36VDD_CORE_IN_OUT
37RESET#
38VSS
30P6_IN_D0
4XTAL_OUT
3XTAL_IN
7P0_RX_P
8P0_RX_M
10P0_TX_P
11P0_TX_M
16P1_RX_P
15P1_RX_M
13P1_TX_P
12P1_TX_M
18P6_CRS/GPIO4
19P6_OUT_D3/MODE3
21P6_OUT_D1/MODE1
22P6_OUT_D0/MODE0
27P6_IN_D3/GPIO7
26P6_IN_CLK
24P6_OUT_CLK
23P6_VDDO
28P6_IN_D2/GPIO6
29P6_IN_D1
31P6_IN_DV
32VDD_CORE_1
6I_REF
9P0_AVDD
14P1_AVDD
20P6_OUT_D2/MODE2
25P6_OUT_EN/PWR2.5V
65GND_PAD
U20
88E6020_QFN64_IND
R684.99K
C202.1 uF
C201.1 uF
C200.1 uF
C199.1 uF
C209.1 uF
C208.1 uF
C207.1 uF
C205.1 uF
C204.1 uF
C203.1 uF
R12651
R12751
C198.1 uF
R12451
R12551
C197.1 uF
C194.1 uF
C193.1 uF
1 8RN6-A
3.3K
2 7RN6-B
3.3K
3 6RN6-C
3.3K
4 5RN6-D
3.3K
1
8
RN5-A3.3K
2
7
RN5-B3.3K
3
6
RN5-C3.3K
4
5
RN5-D3.3K
E2ENET_CLK
J4 ENET0_COL
J3 ENET0_CRS
G4ENET0_MDC
H4ENET0_MDIO
F3 ENET0_RX_CLK
E4ENET0_RX_ENJ2 ENET0_RXD3
J1 ENET0_RXD2
H2ENET0_RXD1
H1ENET0_RXD0
E3 ENET0_TX_CLK
F4ENET0_TX_EN
G2 ENET0_TXD3
G1 ENET0_TXD2
F2ENET0_TXD1
F1ENET0_TXD0
U3-E
MX286_CPU_IND
1 8RN14-A
1.5K
2 7RN14-B
1.5K
1.0V = H0.3V = L
Low = LP3% LP
1.5-6.0V 1.20V2% FT
1VIN
3EN
5VOUT
2GND
4ECO
U24
REG_NCP585D_1.2V_SOT23
C7010 uF
AUX_3.3V
RAM_1.8V
RXD0
RXD1
RXD2
RXD3 MDIO
MDC
PORT1_ACT_LED
PORT0_ACT_LED
PORT1_RX_P
PORT1_RX_M
PORT1_TX_P
PORT1_TX_M
ETH_RESET#
PORT0_RX_P
PORT0_RX_M
PORT0_TX_P
PORT0_TX_M
RXD0
RXD1
RXD2
RXD3
ENET_CLK
RX_DV
TXD0
TXD1
TX_EN
PORT1_TX_P
PORT1_TX_M
PORT1_RX_P
PORT1_RX_M
PORT1_SPEED_LED
MDIO
MDC
RXD0
RXD1
RX_DV
TXD0
TXD1
TX_EN
ENET_CLK
1.2V
AUX_3.3V
AUX_3.3V
LED_ROW_0
PORT0_SPEED_LED
25MHZ_1.8V
RAM_1.8V 1.2V
Te chnologic Sys t e ms Da te
Tit le :
Re v: De s igne r She e t of9
TS-7680 Ma gJa cks
Se pt . 1, 2015
B 20
Gre e n
Ye llow
Port # 1
10/100 Ma gJa ck
Gre e n
Ye llow
Port # 0
10/100 Ma gJa ck
4RX+
5RX-
6RX_CT
3TX_CT
1TX+
2TX-
7POE_RX
9POE_45
11LLED+
12LLED-
13RLED+
14RLED-
17ALIGN
18ALIGN
15SHD
16SHD
8POE_TX
10POE_78
T2
MAGJACK_POE_10_100
C163.1 uF
R44
140
R46
140
4RX+
5RX-
6RX_CT
3TX_CT
1TX+
2TX-
7POE_RX
9POE_45
11LLED+
12LLED-
13RLED+
14RLED-
17ALIGN
18ALIGN
15SHD
16SHD
8POE_TX
10POE_78
T1
MAGJACK_POE_10_100
C101.1 uF
R41
140
R40
140
RAM_1.8V
PORT1_TX_P
PORT1_TX_M
PORT1_RX_P
PORT1_RX_M
PORT1_SPEED_LED
PORT1_ACT_LED
RAM_1.8V
PORT0_RX_P
PORT0_RX_M
PORT0_TX_P
PORT0_TX_M
PORT0_SPEED_LED
PORT0_ACT_LED
LED_ROW_0 LED_ROW_0
POE_78
POE_45
POE_TX
POE_RX
ofShe e tDe s igne rRe v:
Tit le :
Da teTe chnologic Sys t e ms
10
TS-7680 NAND a nd SD Ca rd
Micro SD Ca rd Socke t
Se pt . 1, 2015
B 20
Fla s h Me mory
e MMC 4GB
Edge Conn.
SPI Boot Fla s h
C122
7DATA_0
8DATA_1
1DATA_2
2DATA_3
5CLK
3COMMAND
4VDD
6GND
10FRM2
9FRM1
11FRM3
12FRM4
CN3
CONN_MICRO_SD
1 8RN28-A
10K
2
7
RN28-B10K
4
5
RN21-D10K
1
MT7
MT125 1
MT8
MT125 1
MT9
MT125
G
S D
1
2 3
Q29
C102.1 uF
C105.1 uF
C108.1 uF
C110.1 uF
C111.1 uF
C112.1 uF
C941 uF
1
8
RN30-A10K
2
7
RN30-B10K
3
6
RN30-C10K
4
5
RN30-D10K
R173
9.1K
A3DATA_0
A4DATA_1
A5DATA_2
B2DATA_3
M6CLK
M5COMMAND
E6VCC
P6GND
P4GND
N5GND
N2GND
K8GND
H10GND
E7GND
C4GND
F5VCC
J10VCC
K9VCC
C6VCCQ
P3VCCQ
N4VCCQ
P5VCCQ
B3DATA_4
B4DATA_5
B5DATA_6
B6DATA_7
K5RESET#
C2VDD_I
G5GND
M4VCCQ
A6TOSH_GND
J5TOSH_GND
U21
EMMC_MICRON_4GB_BG153_ITEMP
Edge
Conn.
A11JTAG_PWR
B11GND
A10CONSOLE_TXD
A9JTAG_TDO
A8JTAG_TDI
A7JTAG_TMS
A6JTAG_TCK
A5SPI_CPU_CS#
A4SPI_MISO
A3SPI_MOSI
A2SPI_CLK
A1GND
B1SPI_PWR
B2BOOT_SELECT
B3SPI_DATA3
B4SPI_DATA2
B5SPI_FLASH_CS#
B6OPTION
B7UC_DATA
B8UC_CLK
B9RESET#
B10CONSOLE_RXD
CN99
CON22_EDGE_PCIE
1 CS#
5DIN_DQ0
6CLK
8VCC
4GND
7 HOLD# _DQ3
3 WP# _DQ2
2DOUT_DQ1
U13
FLASH_N25Q064_8MB_SOIC
C180.1 uF
SD0_CMD
SD0_D3
SD0_CMD
SD0_CLK
SD0_D0
SD0_D1
SD0_D2
AUX_3.3V
EN_SD_3.3V#
AUX_3.3V
EMMC_CLK
EMMC_CMD
EMMC_D3
EMMC_D2
EMMC_D1
EMMC_D0
AUX_3.3V
AUX_3.3V
AUX_3.3V
RXD2_SPI_CLK
TXD2_SPI_MOSI
RXD3_SPI_MISO
EN_7690_SPI_FLASH#
JTAG_FPGA_TMS
JTAG_FPGA_TDI
JTAG_FPGA_TDO
SILAB_CLK
SILAB_DATA
JTAG_FPGA_TCK
SPI_OFF_BD_SEL#
AUX_3.3VRXD2_SPI_CLK
TXD2_SPI_MOSI
RXD3_SPI_MISO
AUX_3.3V
SPI_ON_BD_CS#
SPI_OFF_BD_CS#
Te chnologic Sys t e ms Da te
Tit le :
Re v: De s igne r She e t of
TS-7680 RTC a nd Hos t USB
11B
Se pt . 1, 2015
20
RTC a nd Hos t USB
SMT RA LEDs
Exte rna l Hos t USB PortST Micro RTC
Boot Jumpe rs
2
7
RN4-B3.3K
3
6
RN4-C3.3K
R63649
D20
R34
30
R45140
R42140
R43140
1
2 LED2
Ye llow1
2 LED3
Gre e n 1
2 LED4
Re d
PF1PTC_1100MA_1812
C109.1 uF
2
3
1
4TVS3
BGX50A_SOT143
Ve rt ica l
Single
USB
4GND
15V
2D-
3D+
5FRAME1
6FRAME2
8FRAME4
7FRAME3
CN1
CONN_USB_A_RA_VERT_SINGLE
FB14
220 ohm
FB17
220 ohm
21
3 4
K1
6SCL
5SDA
1XIN
2XOUT
8VCC
7OUT 3
BAT
4GND
U15
M41T00S_RTC_SOIC812 pF
1 4
2 3
Y3
XTAL_32KHZ_SMT
C224.1 uF
C225.1 uF
2
7
RN19-B47K
3
6
RN19-C47K
AUX_3.3V
AUX_3.3V
GREEN_LED#
RED_LED#
YEL_LED#
HOST_USB_5V
SW_5V
USB_HOST_M
USB_HOST_P
I2C_CLK
I2C_DAT
AUX_3.3V
JP_SD_BOOT#
JP_UBOOT#
AUX_3.3V
ofShe e tDe s igne rRe v:
Tit le :
Da teTe chnologic Sys t e ms
12
TS-7680 RS-232 Port s
Se pt . 1, 2015
B 20
RS-232 Port s a nd Da ughte r Ca rd He a de rs
RS-232 Tra ns ce ive r
Le ve l s hift e r
3.3V < -- 5V
RS-232/CAN
STC RS-485 Drive r
Dig. Input
Do not us e
J1939 Shie ld
Opt ion
19 OE
1 DIR
2 A1
3 A2
4 A3
5 A4
18B1
17B2
16B3
15B4
6 A5
7 A6
8 A7
9A8
14B5
13B6
12B7
11B8
20VCC
10GND
U27
74LVC245_TSSOP20
(CAN_H)
(CAN_L)
(CAN_GND)
8RTS
7CTS
6TXD
5RXD
4GND
2DCD
3DTR
1DSR/RI
9SHLD
10SHLD
J4
RJ45_RA_SHIELD_PJ031_EIA561_CAN
C162.1 uF
4TXD
1RXD
3TXEN
2 RXEN#
8VCC
6X+
7X-
5GND
U29
SP485EEN_SOIC8
R2260.4
R2360.4
4 5RN29-D
10K
T1
T2
R1
R2
C1+
C1-
C2+
C2-
GND
Vcc
V+
V-
1
2
3
4
5
6
7
89
10
11
12 13
14
15
16
U14
SP202_SOIC16
C159.1 uF
C126.1 uF
C121.1 uF
C116.1 uF
C120.1 uF
2
7
RN29-B10K
3
6
RN29-C10K
1 2
3D7
DIODE_BAV99-2_SOT23
1
8
RN24-A10K
2 7RN24-B
10K
36RN24-C
10K
4
5
RN24-D10K
1
8
RN29-A10K
R701 ohm
C370.68 uF
R128
51
AUX_3.3V
RXD_CAN1_5V
RXD2_485_5V
DC_RXD_5V
RXD_CAN0_5V
RXD_CAN1_3V
RXD_CAN0_3V
CAN1_H
CAN1_L
TXEN3_485
SW_5V
RXD3_485_5V
485_PLUS
485_MINUS
RXD3_485_5V
SW_5V
SW_5V
SW_5V
DIG_IN
DIG_IN_5VDIG_IN_3V
DIG_IN_5V
COM2_RXD_232_3V
DC_RXD_3V
RXD2_485_3V
RXD3_485_3V
COM1_RXD_232_3V
COM1_TXD_232_3V
COM2_TXD_232_3V
TXD3_485
Remove for J1939 Shie ld Opt ion
ofShe e tDe s igne rRe v:
Tit le :
Da teTe chnologic Sys t e ms
Mod Bus RS-485 a nd CAN Port s
RS-485 Drive r
RJ45
Modbus
13
TS-7680 Modbus a nd CAN
Se pt . 1, 2015
B 20
Powe r Swit ch
Modbus
CAN_0 Tra nce ive r
24V
CAN_1 Tra nce ive r
24VTJA1040 a llows low
powe r 15 uA mode
C167.1 uF
4TXD
1RXD
3TXEN
2 RXEN#
8VCC
6X+
7X-
5GND
U28
SP485EEN_SOIC8
R2760.4
R2660.4 RS-485
8GND
712V-24V
612V-24V
5DATA-
4DATA+
2GND
3MODE
1GND
9SHLD
10SHLD
J6
RJ45_RA_SHIELD_PJ031
R61649
R62649
FB24
220 ohm
FB22
220 ohm
FB19
220 ohm
FB18
220 ohm
TVS9
30V
R21
60.4
R28
60.4
2
1
3
Q16
2
1
3
Q14
D12
PF3
1500 mA
3
6
RN13-C1.5K
4
5
RN13-D1.5K
D
S
G2
6
1
Q3-A
3
6
RN17-C47K
1 8RN13-A
1.5K
2 7RN13-B
1.5K
4RXD
1TXD
5VREF
8EN#
3VCC
7CANH
6CANL
2GND
U25
TJA1040_SOIC8
C164.1 uF
21
3
TVS15
NUP2105L_SOT23
C127.1 uF
R20
60.4
R19
60.4
3
6
RN11-C1.5K
4
5
RN11-D1.5K
4RXD
1TXD
5VREF
8EN#
3VCC
7CANH
6CANL
2GND
U26
TJA1040_SOIC8
C166.1 uF
21
3
TVS16
NUP2105L_SOT23
C124.1 uF
R25
60.4
R24
60.4
4 5RN28-D
10K
3
2
1
4Q9
2
1
3Q10
2
1
3
Q12
R67
4.99K
R103100K
R104100K
15V
1 2
3 D54
ZENER_15V_SOT23
15V
1 2
3 D53
ZENER_15V_SOT23
3
6
RN14-C1.5K
4
5
RN14-D1.5K
SW_5V
MODBUS_24V
RXD2_485_5V
VIN
MODBUS_24VAUX_3.3V
MODBUS_FAULT
EN_MODBUS_3V#
EN_MODBUS_24V
SW_5V
RXD_CAN0_5V
TXD_CAN0SW_5V
RXD_CAN1_5V
CAN1_H
CAN1_L
TXD_CAN1
TXEN2_485
EN_CAN#
EN_CAN#
AN5_CAN_H
AN4_CAN_L
TXD2_485
ofShe e tDe s igne rRe v:
Tit le :
Da teTe chnologic Sys t e ms
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NCNC
NC
NC
VBAT mus t powe r up firs t
1.8V Le ve ls
WiFi Ra dio (Optional Feature)
Silicon
14
TS-7680 WIFI a nd DIO
Se pt . 1, 2015
B 20
14V Supply
DAC
DIO_2
Sinks 500 mA
Ma x. Input = 30V
DIO_0
Sinks 500 mA
Ma x. Input = 30V
DIO_1
Sinks 500 mA
Ma x. Input = 30V
NC
1VBAT
2BT_FUNC5
3WL_UART_DBG
4WLAN_IRQ
5BT_EN
6FM_EN
7WL_RS232_RX
8WL_RS232_TX
9FM_I2S_FSYNC
10WL_EN
11VIO
12GND1
13SDIO_D3
14SDIO_D2
15SDIO_D1
16SDIO_D0
17SDIO_CMD
18SDIO_CLK
19SLOW_CLK
20FM_IRQ
21FM_SDA
22FM_SCL
23FM_I2S_CLK
24FM_I2S_DI
25FM_I2S_DO
26FM_AUD_RIN
27FM_AUD_LIN
28FMRFOUT
29FMRFIN
30GND2
31FM_AUD_ROUT
32FM_AUD_LOUT
33AUD_FSYNC
34HCI_RX
35HCI_RTS
36HCI_TX
37AUD_CLK
38AUD_OUT
39HCI_CTS
40AUD_IN
41BT_FUNC2
42BT_FUNC4
43VDD_LDO_CLASS_1P5
44GND3
45GND4
46GND5
47GND6
48ANT
49GND7
50GND8
51GND9
52GND10
53GND11
54GND12
55GND13
56GND14
K5
WIFI_MODULE_LSR
C219.1 uF
C220.1 uF
L6COIL_2.7NH_0402
D9
3
2
1
4Q8
15V
1 2
3
D52
ZENER_15V_SOT23
C77.1 uF
G
S
DQ22
TVS8
30V
D19
40V
1
8
RN9-A1.5K
2
7
RN9-B1.5K
G
S
DQ21
TVS6
30V
D13
40V
1
8
RN20-A10K
2
7
RN20-B10K
G
S
DQ20
TVS7
30V
D18
40V
R97
Ze ro
R95
Ze ro
R99
Ze ro
5
4
RN10-D1.5K
3 6RN28-C
10K
2
7
RN8-B3.3K
3
6
RN8-C3.3K
4
5
RN8-D3.3K
RAM_1.8V
SD2_D0
SD2_D1
SD2_D2
SD2_D3
SD2_CMD
SD2_CLKWIFI_IRQ
SW_5VVIN
14V
DIO_2
AUX_3.3V
DIO_2_IN
DIO_0
AUX_3.3V
DIO_0_IN
DIO_1
AUX_3.3V
DIO_1_IN
WL_EN
EN_LS_OUT_0
EN_LS_OUT_1EN_LS_OUT_2
SD2_CMDRAM_1.8V
BT_CTS
BT_EN
BT_RTS
BT_RXD
BT_TXD
WIFI_32KHZ_1.8V
Te chnologic Sys t e ms Da te
Tit le :
Re v: De s igne r She e t of15
TS-7680 FPGA
Se pt . 1, 2015
B 20
FPGA re quire d for:
- Auto-485 for two UARTs
- PWMs for DACs
- MUX for a ll UARTs
- Blue Tooth Le ve l Shift ing
- Addit iona l I/O
- HD4 Da ughte r Ca rd (Future )
UART2 a nd UART3 cha nge d to SPI
whe n Boot ing from SPI
R126 pop whe n WiFi is
MACH XO2 FPGA
1.8V
Ba nk 5
SPI Bootor
UARTs
From CN99
Input s
BootFla s h
SPI Bus
From
MX286
(50 MHz)
Da ughte r Ca rd
1
8
RN7-A3.3K
4
5
RN7-D3.3K
3
6
RN7-C3.3K
C187.1 uF
C184.1 uF
C192.1 uF
C190.1 uF
C189.1 uF
C191.1 uF
C183.1 uF
C181.1 uF
C169.1 uF
C182.1 uF
C188.1 uF
R1592.0K
R1582.0K
R1572.0K
JTAG
A7IO_B0
C5VCC_IO_0
H2IO_B4
N8IO_B2
K3IO_B3
N6IO_B2
G14IO_B1
B12IO_B0
K13IO_B1
D12IO_B1
A2IO_B0
N7IO_B2
B5IO_B0
H3IO_B4
G3IO_B4
A4TDO
C4IO_B0
L13
GND
M1IO_B3
P14VCC_CORE
C2IO_B5
H14VCC_IO_1
M8IO_B2
D2
GND
M3IO_B2
A5
GND
J1IO_B4
B11
GND
F1IO_B4
N5IO_B2
B10VCC_IO_0
G12IO_B1
B8IO_B0_SDA
N2IO_B2
C13IO_B1
J2IO_B4
M9IO_B2
K1IO_B3
A1VCC_CORE
A9IO_B0
P7IO_B2
A13DONE_IO_B0
A14VCC_CORE
B9IO_B0
D14VCC_IO_1
C14IO_B1
C1IO_B5
D1IO_B5
J13IO_B1
P10
GND
L14IO_B1
P12IO_B2
P1VCC_IO_2
B14IO_B1
M13IO_B1
E2IO_B5
E12IO_B1
G13IO_B1
N4IO_B2_SPI_SO
C7NC
N1VCC_CORE
F13IO_B1
B1IO_B5
C11IO_B0
P9IO_B2
F14IO_B1
F12IO_B1
M12IO_B1
N11VCC_IO_2
A12IO_B0
N9IO_B2
J14IO_B1
M11IO_B2
N12IO_B2_SPI_SN
A11IO_B0
N10IO_B2
M7IO_B2
D3VCC_IO_5
A3IO_B0
M4IO_B2_MCLK
C9IO_B0
B13INIT# _IO_B0
P3IO_B2_CSS
L2
GND
K12IO_B1
L1VCC_IO_3
N14IO_B1
L12VCC_IO_1
N3IO_B2
K2IO_B3
B3IO_B0
C8IO_B0_SCL
N13IO_B1
H1IO_B4
G2
GND
E13IO_B1
A10IO_B0
E14IO_B1
M10IO_B2
C6IO_B0
M5IO_B2
B2IO_B5
F2IO_B5
H13
GND
A6TMS
B6TCK
G1VCC_IO_4
B7IO_B0
P8IO_B2
M2IO_B3
M6VCC_IO_2
P13IO_B2_SPI_SI
J3IO_B3
F3IO_B4
H12IO_B1
C12IO_B0
P4IO_B2
D13
GND
P5
GND
B4TDI
A8VCC_IO_0
L3IO_B3
J12IO_B1
P6IO_B2
M14IO_B1
P11IO_B2
P2IO_B2
K14IO_B1
C10PROG# _IO_B0
E3IO_B5
E1IO_B5
C3IO_B5U7
LATTICE_MACHXO_4000LUT_CB132
C179.1 uF
2
7
RN11-B1.5K
AUX_3.3V
AUX_3.3V
AUX_3.3V
250KHZ_PH0
FPGA_29
FPGA_31
FPGA_32
FPGA_34
DAC_PWM_3
RAM_1.8V
WL_EN
AUX_3.3V
JTAG_FPGA_TDO
JTAG_FPGA_TDI
JTAG_FPGA_TMS
JTAG_FPGA_TCK
RXD2_SPI_CLK
FPGA_SPI_CLK
FPGA_SPI_MOSI
RXD3_SPI_MISO
UART0_TXD
UART0_RTS
EN_7690_SPI_FLASH#
EN_SPI_BOOT_FLASH
AUX_3.3V
I2C_CLK
ETH_RESET#
FPGA_SPI_MISO
SPI_OFF_BD_SEL#
SPI_ON_BD_CS#
DIO_0_IN
TXEN3_485
UART1_TXD
EN_LS_OUT_2
DIO_2_IN
DIG_IN_3V
DC_TXD_3V
EN_RELAY_1
EN_RELAY_2
25MHZ_1.8V
BT_CTS
BT_EN
BT_RTS
BT_RXD
BT_TXD
ENET_CLK
FPGA_SPI_CS0#
WIFI_32KHZ_1.8V
250KHZ_PH1
DAC_PWM_1
FPGA_23
FPGA_25
FPGA_26
FPGA_27
FPGA_28
FPGA_30
FPGA_33
FPGA_35
DIO_1_IN
EN_LS_OUT_1
COM2_RXD_232_3V
DAC_PWM_2
DC_RXD_3V
RXD2_485_3V
RXD3_485_3V
UART4_RXD
TXD2_SPI_MOSI
EN_LS_OUT_0
FPGA_12MHZ
TXD3_SPI_CS#
EN_CL_0_1
EN_PU_AD0
EN_PU_AD1
EN_PU_AD2
EN_PU_AD3
TXEN2_485
CPU_RESET#
DAC_PWM_0
EN_CL_2_3
COM1_RXD_232_3V
COM1_TXD_232_3V
COM2_TXD_232_3V
FPGA_IRQ
UART1_RXD
FPGA_SPI_CS1#
I2C_DAT
UART0_RXD
SPI_OFF_BD_CS#
TXD2_485
TXD3_485
UART0_CTS
UART4_TXD
EN_DC_5V
Te chnologic Sys t e ms Da te
Tit le :
Re v: De s igne r She e t of
Re la ys
16
TS-7680 DACs a nd Re la ys
Se pt . 1, 2015
B 20
Ga in = 3.3
0-10V Out
150 Hz low pa s s filt e r
Ga in = 3.3
0-10V Out
150 Hz low pa s s filt e r
Ga in = 3.3
0-10V Out
150 Hz low pa s s filt e r
Ga in = 3.3
0-10V Out
150 Hz low pa s s filt e r
10-bit DACs1
2
3
5
4
K2
RELAY_SPDT_5V_5A_TH
1
2
3
D10
DIODE_BAT54-CC_SOT23
D
S
G2
6
1
Q4-A
D
S
G5
3
4
Q4-B
+
-2
31
11
4
U4-A
R75
41.2K
C82
.1 uF
R107
100K
C215.1 uF
C214.1 uF
R33
30
C33
3.3 nF
R32
30
1
2
3
5
4
K3
RELAY_SPDT_5V_5A_TH
D
S
G2
6
1
Q6-A
D
S
G5
3
4
Q6-B
R74
41.2K
R105
100K
C213.1 uF
C212.1 uF
C34
3.3 nF
R31
30+
-6
57U4-B
+
-9
108U4-C
+
-13
1214U4-D
R76
41.2K
R106
100K
C211.1 uF
C210.1 uF
C35
3.3 nF
R30
30
R77
41.2K
R108
100K
C217.1 uF
C218.1 uF
C36
3.3 nF
R29
30
DAC3
DAC2
3
6
RN9-C1.5K
4
5
RN9-D1.5K
R92
Ze ro
R91
Ze ro
4 5RN25-D
10K
36RN25-C
10K
2 7RN25-B
10K
18RN25-A
10K
3 6RN26-C
10K
45RN26-D
10K
1 8RN26-A
10K
27RN26-B
10K
SW_5V
SW_5V
14V
DAC_0
EN_RELAY_1
RELAY_1_NO
RELAY_1_NC
RELAY_1_COM
SW_5V
EN_RELAY_2
RELAY_2_NO
RELAY_2_NC
RELAY_2_COM
DAC_1
DAC_2
DAC_3DAC_PWM_3
DAC_PWM_1
DAC_PWM_2
DAC_PWM_0
ofShe e tDe s igne rRe v:
Tit le :
Da teTe chnologic Sys t e ms
17
TS-7680 Ana log
Se pt . 1, 2015
B 20
Ana log In Cha nne ls
0-10V Input
0-10V Input
0-10V Input
0-10V Input
24V
Bipola r Ana log Input s-5V to + 5V Input Ra nge
By a djus t ing re s is t or va lue s
All A/D Input s ca n be conve rt e d
to Bipola r, but mus t re move FETs
2
1
3
Q11
4
5
RN15-D1.5K
2
7
RN15-B1.5K
3
6
RN15-C1.5K
1
8
RN15-A1.5K
1 8RN22-A
10K
3 6RN22-C
10K
2 7RN22-B
10K
4 5RN22-D
10K
D14
40V
R80
41.2K
R507.87K
C221.1 uF R38
240
G
S
DQ25
R98
Ze ro
2
1
3
Q13
D15
40V
R73
41.2K
R567.87K
C216.1 uF R37
240
G
S
DQ26
R96
Ze ro
2
1
3
Q15
D16
40V
R79
41.2K
R577.87K
C222.1 uF R35
240
G
S
DQ24
R94
Ze ro
2
1
3
Q17
D17
40V
R83
41.2K
R587.87K
C113.1 uF R36
240
G
S
DQ23
R93
Ze ro
21
3
TVS14
NUP2105L_SOT23
21
3
TVS13
NUP2105L_SOT23
R85
41.2K
R55
7.87K
C78
.1 uF
R84
41.2K
R59
7.87K
C79
.1 uF
R102100K
R101100K
R134
475K
R135
475K
R137
475K
R136
475K
AUX_3.3V
ADC0
EN_CL_0_1
AN_DIN_0
AUX_3.3V
ADC1
EN_CL_0_1
AN_DIN_1
AUX_3.3V
ADC2
EN_CL_2_3
AN_DIN_2
AUX_3.3V
ADC3
EN_CL_2_3
AN_DIN_3
ADC4 AN4_CAN_L ADC5 AN5_CAN_H
1.2V1.2V
1.2V
1.2V
1.2V
1.2V
EN_PU_AD0
EN_PU_AD1
EN_PU_AD2
EN_PU_AD3
Te chnologic Sys t e ms Da te
Tit le :
Re v: De s igne r She e t of
Supe rCa p 20 Se cond Powe r Hold
20 s e conds a s s ume s 3 wa t t loa d
18
TS-7680 Supe r Ca p Circuit
Se pt . 1, 2015
B 20
(Optional Feature)
Super Cap(20 sec.)
Supper Cap Charging
Circuit
Boost Regulator
Super Cap Monitoring
SW_5V
AUX_3.3V
EN_CHRG#
SILAB_PWM
EN_TOP_OFF
5V_BOOST
POWER_FAIL
AN_SCAP_2
AN_SCAP_1
AN_CHRG
Te chnologic Sys t e ms Da te
Tit le :
Re v: De s igne r She e t of19
TS-7680 5V Boos t a nd Acce lome te r
Se pt . 1, 2015
B 20
Accelerometer (Optional Feature)
C228.1 uF
C5022 nF4
SCL
6SDA
8NC
5GND
10GND
12GND
11INT1
9INT2
7I2C_LSB
2CAP
1VDIO
16NC
15NC
13NC
3DNC
14VDD
U23
ACCEL_MMA8451_QFN16
AUX_3.3V
I2C_CLK
I2C_DAT
ACCEL_INT
ACCEL_INT2
ofShe e tDe s igne rRe v:
Tit le :
Da teTe chnologic Sys t e ms
Top Row Bot tom Row
Le ft Le ft
20
TS-7680 Scre w Te rm. Conne ctors
Se pt . 1, 2015
B 20
DC He a de r
Right Right
24 Scre w Te rm. Pos it ions
FPGA_22 thru FPGA_35 go t o FPGA (14)
FPGA_21, 23, 25, 27, 29 go t o MX286 (5)
17 STC pos it ions go t o HD4
J1939 Shie ld
Opt ion
FPGA_29 to SiLa b uC
1
2
3
4
5
6
7
8
9
10
11
12
P1-A
13
14
15
16
17
18
19
20
21
22
23
24
P1-B
R89
Ze ro
R90
Ze ro
R88
Ze ro
16
14
12
10
8
6
4
2
15
13
11
9
7
5
3
1
18
20
22
24
34
26
28
30
32
17
19
21
23
25
27
29
31
33
36
38
35
37
HD4
HD_19X2_2.54MM
R711 ohm
C380.68 uF
RELAY_1_NO
RELAY_1_COM
RELAY_1_NC
RELAY_2_NC
RELAY_2_COM
RELAY_2_NO
AN_DIN_0
AN_DIN_1
AN_DIN_2
AN_DIN_3
485_PLUS
485_MINUS
DIO_0
AN4_CAN_L
AN5_CAN_H
DAC_2
DAC_3
DAC_2
DAC_1
DAC_0
P1_19
P1_18
AN_DIN_1
AN_DIN_0
250KHZ_PH0
VIN
SW_5V
AUX_3.3V
DIO_1
DIO_2
DAC_0
DAC_1
DIG_IN
TXD_CAN0
RXD_CAN0_5V
P1_20
DIO_1
DIO_0
AN_DIN_3
AN_DIN_2 DIO_2
DAC_3
FPGA_23
FPGA_25
FPGA_27
FPGA_29
FPGA_31FPGA_32
FPGA_34
P1_20
P1_19
P1_18
FPGA_21250KHZ_PH1
FPGA_26
FPGA_28
FPGA_30
FPGA_33
FPGA_35