SERIAL PERIPHERAL INTERFACE Razvan Bogdan Embedded Systems.

SERIAL PERIPHERAL INTERFACE

Razvan BogdanEmbedded Systems

Content

What is Serial Peripheral Interface (SPI)? The HCS12 SPI Modules SPI Related Registers The I2C Protocol An Overview of the HCS12 I2C Module

Copyright © 2010 Delmar Cengage Learning

What is Serial Peripheral Interface (SPI)?

SPI is a synchronous serial protocol proposed by Motorola to be used as a standard forinterfacing peripheral chips to a microcontroller.

Devices operate in master or slave mode. The SPI protocol uses four wires to carry out the task of data communication:

MOSI: master out slave inMISO: master in slave outSCK: serial clockSS: slave select

An SPI data transfer is initiated by the master device. A master is responsible for generating the SCK signal to synchronize the data transfer.

The SPI protocol is mainly used to interface with shift registers, LED/LCD drivers, phaselocked loop chips, memory components with SPI interface, or A/D or D/A converterchips.


The HCS12 SPI Modules

An HCS12 device may have from one to three SPI modules. The MC9S12DP256 has three SPI modules: SPI0, SPI1, and SPI2. By default, the SPI0 share the use of the upper 4 Port S pins:

PS7 SS0 (can be rerouted to PM3)PS6 SCK0 (can be rerouted to PM5)PS5 MOSI0 (can be rerouted to PM4)

PS4 MISO0 (can be rerouted to PM2) By default, the SPI1 shares the use of the lower 4 Port P pins:

PP3 SS1 (can be rerouted to PH3)PP2 SCK1 (can be rerouted to PH2)PP1 MOSI1 (can be rerouted to PH1)PP0 MISO1 (can be rerouted to PH0)

By default, the SPI2 shares the use of the upper 4 Port P pins:PP6 SS2 (can be rerouted to PH7)PP7 SCK2 (can be rerouted to PH6)PP5 MOSI2 (can be rerouted to PH5)PP4 MISO2 (can be rerouted to PH4)

It is important to make sure that there is no conflict in the use of signal pins when making rerouting decision.


SPI Related Registers

The operating parameters of each SPI module are controlled by two control registers: SPIxCR1: (x = 0, 1, or 2)SPIxCR2

The baud rate of the SPI transfer is controlled by the SPIxBR register

The operation status of the SPI operation is recorded in the SPIxSR register.

The contents of the SPIxCR1, SPIxCR2, SPIxBR, and SPIxSR registers are illustratedin Figure 10.1 to 10.4, respectively.

The SS pin may be disconnected from SPI by clearing the SSOE bit in the SPIxCR1register. After that, it can be used as a general I/O pin.

If the SSOE bit in the SPIxCR1 register is set to 1, then the SS signal will be asserted to enable the slave device whenever a new SPI transfer is started.

The equation for setting the SPI baud rate is given in Figure 10.3.

The term baud rate is defined as the number of signal changes per second


7 6 5 4 3 2 1 0MSTR CPOL CPHA SSOESPIE SPE SPTIE LSBFE

Figure 10.1 SPI control register 1 (SPIxCR1, x = 0, 1, or 2)

SPIE: SPI interrupt enable bit 0 = SPI interrupts are disabled. 1 = SPI interrupts are enabled.SPE: SPI system enable bit 0 = SPI disabled. 1 = SPI enabled and pins PS4-PS7 are dedicated to SPI function.SPTIE: SPI transmit interrupt enable 0 = SPTEF interrupt disabled. 1 = SPTEF interrupt enabled.MSTR: SPI master/ slave mode select bit 0 = slave mode 1 = master modeCPOL: SPI clock polarity bit 0 = active high clocks selected; SCK idle low 1 = active low clocks selected, SCK idle highCPHA: SPI clock phase bit 0 = The first SCK edge is issued one-half cycle into the 8-cycle transfer operation. 1 = The SCK edge is issued at the beginning of the 8-cycle transfer operation.SSOE: slave select output enable bit The SS output feature is enabled only in master mode by asserting the SSOE bit and the MODFEN bit of the SPIxCR2 register.LSBF: SPI least significant bit first enable bit 0 = data is transferred most significant bit first. 1 = data is transferred least significant bit first.

Reset value= 0x04


7 6 5 4 3 2 1 0MODFEN BIDIROE 0 SPSWAI0 0 0 SPC0

Figure 10.2 SPI control register 2 (SPIxCR2, x = 0, 1, or 2)

MODFEN: mode fault enable bit 0 = disable the MODF error. 1 = enable settinig the MODF error.BIDIROE: output enable in the bidirectional mode of operation 0 = output buffer disabled 1 = output buffer enabledSPSWAI: SPI stop in wait mode 0 = SPI clock operates normally in stop mode. 1 = stop SPI clock generation in Wait mode.SPC0: serial pin control bit 0 With the MSTR bit in the SPIxCR1 register, this bit enables bidirectional pin configuration, as shown in Table 10.2.

Reset value= 0x08

Table 10.2 Bidirectional pin configurations

Pin mode

ABCD

normal

bidirectional

SPC0

0

1

MSTR

0101

MISO1

slave outmaster inslave I/O

--

MOSI2

slave inmaster out

--master I/O

SCK3 SS4

SCK inSCK outSCK in

SCK out

SS inSS I/OSS in

SS I/O1. Slave output is enabled if BIDIROE bit = 1, SS = 0, and MSTR = 0, (C).2. Master output is enabled if BIDIROE bit = 1 and MSTR = 1, (D).3. SCK output is enabled if MSTR = 1 (B,D).4. SS output is enabled if MODFEN = 1, SSOE = 1, and MSTR = 1, (B,D).


7 6 5 4 3 2 1 0SPPR0 0 SPR2 SPR10 SPPR2 SPPR1 SPR0

Figure 10.3 SPI baud rate register (SPIxBR, x = 0, 1, or 2)

SPPR2~SPPR0: SPI baud rate preselection bitsSPR2~SPR0: SPI baud rate selection bitsBaudRateDivisor = (SPPR + 1) 2(SPR + 1)

Baud Rate = Bus Clock BaudRateDivisor

Reset value = 0x00

7 6 5 4 3 2 1 0MODF 0 0 0SPIF SPTEF0 0

Figure 10.4 SPI status register (SPIxSR)

SPIF: SPI interrupt request bit SPIF is set after the eight SCK cycles in a data transfer, and it is cleared by reading the SP0SR register (with SPIF set) followed by a read access to the SPI data register. 0 = transfer not yet complete 1 = new data copied to SPIxDRSPTEF: SPI data register empty interrupt flag 0 = SPI data register not empty 1 = SPI data register empty MODF: mode error interrupt status flag 0 = mode fault has not occurred 1 = mode fault has occurred

Reset value= 0x20


Example 1: Give a value to be loaded to the SPIxBR register to set the baud rate to 2 MHz for a 24 MHz bus clock.Solution: 24 MHz 2 MHz = 12. One possibility is to set SPPR2-SPPR0 and SPR2-SPR0 to 010 and 001, respectively. The value to be loaded into the SPIxBR register is $21.

Example 2: What is the highest possible baud rate for the SPI with 24 MHz bus clock?Solution: The highest SPI baud rate occurs when both the SPPR2-SPPR0 and SPR2-SPR0 are 000. In this case the baud rate is 24 MHz 2 = 12 MHz.

SPI Transmission Format

The data bits can be shifted on the rising or the falling edge of the SCK clock.

Since the SCK can be idle high or idle low, there are four possible combinations as

shown in Figure 10.5 and 10.6. To shift data bits on the rising edge, set CPOL-CPHA to 00 or 11. To shift data bits on the falling edge, set CPOL-CPHA to 01 or 10. Data byte can be shifted in and out most significant bit first or least

significant bit first.


SS (O)master only

SS (I)

SCK (CPOL = 0)

SCK (CPOL = 1)Sample I

MOSI/MISO

Change OMOSI Pin

Change OMISO Pin

tT tI tLMinimum 1/2 SCK

for tT, tI, tL

tLMSB first (LSBF = 0)LSB first (LSBF = 1)

MSBLSB

Bit 6Bit 1

Bit 5Bit 2

Bit 4Bit 3

Bit 3Bit 4

Bit 2Bit 5

Bit 1Bit 6

LSBMSB

Begin EndTransfer

Figure 10.5 SPI clock format 0 (CPHA = 0)


SS (O)master only

SS (I)

SCK (CPOL = 0)

SCK (CPOL = 1)Sample I

MOSI/MISO

Change OMOSI Pin

Change OMISO Pin

tT tI tLMinimum 1/2 SCK for tT, tI, tL

tLMSB first (LSBF = 0)LSB first (LSBF = 1)

MSBLSB

Bit 6Bit 1

Bit 5Bit 2

Bit 4Bit 3

Bit 3Bit 4

Bit 2Bit 5

Bit 1Bit 6

LSBMSB

Begin EndTransfer

Figure 10.6 SPI clock format 1 (CPHA = 1)


Bidirectional Mode (MOMI or SISO)

A mode that uses only one data pin to shift data in and out. This mode is provided to deal with peripheral devices with only one

data pin. Either the MOSI pin or the MISO pin can be used as the bidirectional

pin.

When the SPI is configured to the master mode (MSTR bit = 1), the MOSI pin is used in data transmission and becomes the MOMI pin.

When the SPI is configured to the slave mode (MSTR bit = 0), the MISO pin is used in data transmission and becomes the SISO pin.

The direction of each serial pin depends on the BIDIROE bit of the SPIxCR2 register.

The pin configuration for MOSI and MISO are illustrated in Figure 10.7.

If one wants to read data from the peripheral device, clear the BIDIROE bit to 0.

If one wants to output data to the peripheral device, set the BIDIROE bit to 1.


Figure 10.7 Normal mode and bidirectional mode

Serial Out

SPISerial In

MOSI

MISO

When SPE = 1

Normal Mode

SPC0 = 0

Master ModeMSTR = 1

Serial Out

SPISerial In

MOMI

BIDIROE

Serial Out

SPISerial In

SISO

BIDIROE

Serial Out

SPISerial In MOSI

MISO

Slave ModeMSTR = 0

SWOM enables open-drain output SWOM enables open-drain output

Bidirectional mode

SPC0 = 1


Mode Fault Error

If the SSx signal goes low while the SPIx is configured as a master, it indicates asystem error where more than one master may be trying to drive the MOSIx and SCKxpins simultaneously.

The MODF bit in the SPIxSR register will be set to 1 when mode fault condition occurs. When mode fault occurs, the MSTR bit will be cleared to 0 and the output enable for

the MOSIx and SCKx pins will be deasserted.

SPI Circuit Connection

In an SPI system, one device is configured as a master. Other devices are configured asslaves.

The circuit connection for a single-slave system is shown in Figure 10.8. A multi-slave system may have two different connection methods as illustrated in

Figure 10.9 and 10.10. In Figure 10.9, the master can exchange data with each individual slave without affecting

other slaves. In Figure 10.10, all the slaves are configured into a larger ring. A data transmission

with certain slave will go through other slaves.


Shift register

Shift register

Baud RateGenerator

VDD

MISO

MOSI

SCK SCK

MOSI

MISO

SSSS

Master SPI Slave SPI

Figure 10.8 Master/ slave transfer block diagram

SS

+5 V

MOSI SCK MISO SS

Shift register

MOSI SCK MISO SS

Shift register

MOSI SCK MISO

Shift register

SS

SPI Master(HCS12)

SCKx

MOSIx

MISOx

PP0

PP1

PPk

.

.

.

.

.

.

. . .

Slave 0 Slave 1 Slave k

Figure 10.9 Single-master and multiple-slave device connection (method 1)


SS

+5V

MOSI SCK MISO SS

Shiftregister

MOSI SCK MISO SS

Shiftregister

MOSI SCK MISO

Shiftregister

SS

SPI Master(HCS12)

SCKx

MOSIx

MISOx

. . .

Slave 0 Slave 1 Slave k

Figure 10.10 Single-master and multiple-slave device connection (method 2)

. . .


Solution: fE / baud rate = 24 MHz/6 MHz = 4. We need to set SPPR2-SPPR0 andSPR2-SPR0 to 001 and 000, respectively. Write the value $10 into the SPI0BR register.The following instruction sequence will configure the SPI0 as desired:

movb #$10,SPI0BR ; set baud rate to 6 MHzmovb #$50,SPI0CR1 ; disable interrupt, enable SPI, SCK

idle low, data ; latched on rising edge, data transferred msb first

movb #$02,SPI0CR2 ; disable bidirectional mode, stop SPI in wait mode

movb #0,WOMS ; enable Port S pull-up

Example 3: Configure the SPI0 to operate with the following setting assuming that E clock is 24 MHz: 6 MHz baud rate enable SPI0 to master mode SCK0 pin idle low with data shifted on the rising edge of SCK transfer data most significant bit first and disable interrupt disable SS0 function stop SPI in Wait mode. normal SPI operation (not bidirectional mode)

Homework: Write the C variant for Example 3


SPI Utility Functions The following operations are common in many applications and should be made into

library functions to be called by many SPI applications:(a) Send a character to SPI putcspix (x = 0, 1, or 2)(b) Send a string to SPI putsspix (x = 0, 1, or 2)(c) Read a character from SPI getcspix (x = 0, 1, or 2)(d) Read a string from SPI getsspix (x = 0, 1, or 2)

Function putcSPI0putcspi0 brclr SPI0SR,SPTEF,* ; wait until write operation is permissible

staa SPI0DR ; output the character to SPI0brclr SPI0SR,SPIF,* ; wait until the byte is shifted outldaa SPI0DR ; clear the SPIF flagrts

void putcspi0 (char cx){

char temp; while(!(SPI0SR & SPTEF)); // wait until write is permissible SPI0DR = cx; // output the byte to the SPI while(!(SPI0SR & SPIF)); // wait until write operation is complete

temp = SPI0DR; // clear the SPIF flag}


Function putsSPI0

; the string to be output is pointed to by Xputsspi0 ldaa 1,x+ ; get one byte to be output to SPI port

beq doneps0 ; reach the end of the string?jsr putcspi0 ; call subroutine to output the bytebra putsspi0 ; continue to output

doneps0 rtsvoid putsspi0(char *ptr){ while(*ptr) { /* continue until all characters have been output */ putcspi0(*ptr); ptr++; }}


Function getcSPI0

; This function reads a character from SPI0 and returns it in accumulator A

getcspi0 brclr SPI0SR,SPTEF,* ; wait until write operation is permissiblestaa SPI0DR ; trigger eight clock pulses for SPI transferbrclr SPI0SR,SPIF,* ; wait until a byte has been shifted inldaa SPI0DR ; return the byte in A and clear the SPIF flagrts

char getcspi0(void){ while(!(SPI0SR & SPTEF)); // wait until write is permissible SPI0DR = 0x00; // trigger 8 SCK pulses to shift in data while(!(SPI0SR & SPIF)); // wait until a byte has been shifted in return SPI0DR; // return the character}


; This function reads a string from the SPI and store it in a buffer pointed to by X; The number of bytes to be read in passed in accumulator B

getsspi0 tstb ; check the byte countbeq donegs0 ; return when byte count is zerojsr getcspi0 ; call subroutine to read a bytestaa 1,x+ ; save the returned byte in the bufferdecb ; decrement the byte countbra getsspi0

donegs0 clr 0,x ; terminate the string with a NULL characterrts

Function getsSPI0

void getsspi0(char *ptr, char count){ while(count) { // continue while byte count is nonzero *ptr++ = getcspi0(); // get a byte and save it in buffer count--; } *ptr = 0; // terminate the string with a NULL}


The HC595 Shift Register The HC595 consists of an 8-bit shift register and a D-type latch

with three-state parallel output. The shift register provides parallel data to the latch. The maximum data shift rate is 100 MHz (Philips part).

Shiftregister

QA

QBQC

QD

QE

QFQG

QH

Latch

SQH

15

13

1234567

912

10

11

DS 14

Reset

LC

OE

SC

Figure 10.11 The 74HC595 block diagram and pin assignment

VCC = Pin 16GND = Pin 8


Signal Pins of the HC595- DS: serial data input- SC: shift clock. A low-to-high transition on this pin causes the data at the serial input pin to be shifted into the 8-bit shift register. - Reset. A low on this pin resets the shift register portion of this device.- LC: latch clock. A low-to-high transition on this pin loads the contents of the shift register into the output latch.- OE: output enable. A low on this pin allows the data from the latches to be presented at the outputs. - QA to QH: tri-state latch output- SQH: the output of the eight stage of the shift register

Applications of the HC595 The HC595 is often used to add parallel ports to the

microcontroller. Both the connection methods shown in Figure 10.9 and 10.10 can

be used to add parallel ports to the MCU.


Example 5: Describe how to use two 74HC595s to drive eight common cathode sevensegment displays assuming that the E clock frequency of the HCS12 is 24 MHz.Solution: Two 74HC595s can be cascaded using the method shown in Figure 10.10. One74HC595 is used to hold the seven-segment pattern, whereas the other 74HC595 is used to carry digit-select signals. The circuit connection is shown in Figure 10.12.Since there are only seven segments, the QH bit of the segment-control 74HC595 is notneeded. The PK7 pin is used to control the LC input of the 74HC595. The time-multiplexingtechnique illustrated in connecting the 7seg will be used to display multiple digits in Figure 10.12To light the digit on display 7, the voltage at QH of the digit-select 74HC595 must be driven to high. To light the digit on display 6, the voltage at QG of the digit-select 74HC595 must be driven to high, and so on.


Example 5: Describe how to use two 74HC595s to drive eight common cathode sevensegment displays assuming that the E clock frequency of the HCS12 is 24 MHz.Solution:


Example 5: Describe how to use two 74HC595s to drive eight common cathode sevensegment displays assuming that the E clock frequency of the HCS12 is 24 MHz.Solution: Use the circuit in figure 10.12 to connect two 74HC595s to the HCS12.

ab

g

Figure 10.12 Two 74HC595s together drive eight seven-segment displays

. . .. . .

. . .

ab

g

.

.

.

commoncathode

commoncathode

ab

g

I MAX

= 7

0 m

A

.

.

.

R

R

R 2N2222

2N2222

2N2222

300

300

#7 #6 #0

HCS12

MOSI0

SCK0

.

.

.

SC

SC

DS

DS

SQHLC

LC

5V

5V

QGQF

QA

.

.

.

74HC595

74HC595

reset

resetQH

QG

QA

.

.

.OE

OE

commoncathode

PK7


Program to display 87654321 on display #7 to #0.

#include “c:\miniide\hcs12.inc"org $1000

icnt ds.b 1 ; loop countorg $1500lds #$1500 ; set up stack pointerbset DDRK,$80 ; configure the PK7 pin for outputjsr openspi0 ; configure SPI0

forever ldx #dispTab ; use X as a pointer to the tablemovb #8,icnt ; set loop count to 8

loop ldaa 1,x+ ; send the digit select byte to the 74HC595jsr putcspi0 ; "ldaa 1,x+ ; send segment pattern to 74HC595jsr putcspi0 ; "bclr PTK,BIT7 ; transfer data from shift register to outputbset PTK,BIT7 ; latchldy #1 ; display the digit for one msjsr delayby1ms ; "dec icnt ; bne loop ; if not reach digit 1, then nextbra forever ; start from the start of the table


openspi0 movb #0,SPI0BR ; set baud rate to 12 MHzmovb #$50,SPI0CR1 ; disable interrupt, enable SPI, SCK idle low,

; latch data on rising edge, transfer data msb firstmovb #$02,SPI0CR2 ; disable bidirectional mode, stop SPI in wait modemovb #0,WOMS ; enable Port S pull-uprts

#include "c:\miniide\delay.asm"#include "c:\miniide\spi0util.asm"; ********************************************************************; Each digit consists of two bytes of data. The first byte is; digit select, the second byte is the digit pattern.; ********************************************************************dispTab dc.b $80,$7F,$40,$70,$20,$5F,$10,$5B

dc.b $08,$33,$04,$79,$02,$6D,$01,$30end


#include "c:\cwHCS12\include\hcs12.h"#include "c:\cwHCS12\include\spi0util.h" // include spi0util.c into the project#include "c:\cwHCS12\include\delay.h" // include delay.c into the projectvoid openspi0(void);void main (void){ unsigned char disp_tab[8][2] = {{0x80,0x7F},{0x40,0x70},{0x20,0x5F},{0x10,0x5B}, {0x08,0x33},{0x04,0x79},{0x02,0x6D},{0x01,0x30}}; char i; openspi0(); /* configure the SPI0 module */ DDRK |= BIT7; /* configure pin PK7 as output */ while(1) { for (i = 0; i < 8; i++) { putcspi0(disp_tab[i][0]); /* send out digit select value */ putcspi0(disp_tab[i][1]); /* send out segment pattern */ PTK &= ~BIT7; /* transfer values to latches of 74HC595s */ PTK |= BIT7; /* " */ delayby1ms(1); /* display a digit for 1 ms */ } }}


The TC72 Digital Thermometer Ten-bit resolution and SPI interface Pin assignment and block diagram shown in Figure 10.13. Capable of reading temperature from -55oC to 125oC. Can be used in continuous temperature conversion or one-shot conversion mode. Has internal clock generator to control the automatic temperature conversion sequence.

NC

CE

SCK

GND

VDD

NC

SDI

SDO

TC72

Internaldiode

temperaturesensor

10-bitsigma Delta

A/ Dconverter

temperatureregister

ManufacturerID register

ControlRegister

SerialPort

Interface

CESCKSDOSDI

GND

VDDTC72

Figure 10.13 TC72 pin assignment and functional block diagram

1

2

3

4 5

67

8


Temperature Data Format Temperature is represented by a 10-bit two’s complement word with a resolution of

0.25oC per least significant bit. The converter is scaled from -128oC to +127oC with 0oC represented as 0x0000. The temperature value is stored in two 8-bit registers. Whenever the most significant bit is 1, the temperature is negative. A sample of temperature reading is shown in Table 10.3.

Binaryhigh byte/low byte

0010 0001/0100 00000100 1010/1000 00000001 1010/1100 00000000 0001/1000 00000000 0000/0000 00001111 1111/1000 00001111 0010/1100 00001110 0111/0000 00001100 1001/0100 0000

Hex

21404A801AC001800000FF80F2C0E700C900

Temperature

33.25oC74.5oC

26.75oC1.5oC0oC

-0.5oC-13.25oC

-24oC-55oC

Table 10.3 TC72 Temperature output data


TC72’s Serial Interface The CE input to the TC72 must be asserted (high) to enable SPI transfer. Data can be shifted on the rising edge or the falling edge depending on the idle polarity

of the SCK source. Data transfer to and from the TC72 consists of one address byte followed by one or

multiple data (2 to 4) bytes. The TC72 registers and their addresses are shown in Table 10.4. The most significant bit of the address byte determines whether a read (A7 = 0) or a

write (A7 = 1) operation will occur. A multiple byte read operation will start from high address toward lower addresses. The user can send in the temperature result high byte address and read the temperature

result high byte, low byte, and the control registers.

Register Readaddress

Writeaddress

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Value onPOR/BOR

ControlLSB temperature

MSB temperatureManufacturer ID

0x000x010x020x03

0x80N/AN/AN/A

0T1T90

0T0T81

00

T70

OS0

T61

00

T50

00

T41

00

T30

SHDN0

T20

0x050x000x000x54

Table 10.4 Register for TC72

Note. 1. OS is One-Shot 2. SHDN is Shutdown


Procedure for reading the temperature

Step 1Pull the CE pin high to enable SPI transfer.Step 1Send the temperature result high byte read address (0x02) to the TC72. Wait until the SPItransfer complete.Step 3Read the temperature result high byte. The user needs to write a dummy byte into the SPIdata register to trigger eight clock pulses.Step 4Read the temperature result low byte. Again the user needs to write a dummy byte into theSPI data register to trigger eight clock pulses.Step 5Pull CE pin to low so that a new transfer can be started.


Control Register

The control register is used to select the shutdown, continuous, or one-shot conversionoperating mode.

The temperature conversion mode selection logic is shown in Table 10.5. At power up, the SHDN bit is 1. Thus the TC72 is in the shutdown mode. If the SHDN bit is 0, the TC72 will perform a temperature conversion approximately

every 150 ms. A temperature conversion will be initiated by a write operation into the control register

to select the continuous mode or one-shot mode. A typical circuit connection between the TC72 and the HCS12 is shown in Figure 10.16.

Operation mode

Continuous temperature conversionShutdownContinuous temperature conversionOne-shot

One-Shot bit

0011

0101

Shutdown bit

Table 10.5 Control register temperature conversion mode selection


CE

SCK

SDO

SDI

PK7

SCK0

MISO0

MOSI0

HCS12 MCUTC72

VDD VDD

GND

0.1F

Figure 10.16 Circuit connection between the TC72 and the HCS12

Example 6: Write a C program to read the temperature every 200 ms. Convert the temperature to a string so that it can be displayed in an appropriate output device. A pointer to hold the string will be passed to this function. The bus clock is 24 MHz.


#include "c:\cwHCS12\include\hcs12.h"#include "c:\cwHCS12\include\spi0util.h“ // need to include delay.c, spi0Util.c and#include "c:\cwHCS12\include\delay.h“ // convert.c into the projectvoid read_temp (char *ptr); void openspi0(void);char buf[10];void main (void){

DDRM |= BIT1; // configure the PM1 pin for outputopenspi0(); // configure SPI0 moduleread_temp(&buf[0]);

}void openspi0(void){ SPI0BR = 0x10; // set baud rate to 6 MHz SPI0CR1 = 0x50;// enable SPI0 to master mode, select rising edge to

// shift data in and out SPI0CR2 = 0x02;// select normal mode and stop SPI in wait mode WOMS = 0x00; // enable Port S pull-up}


void int2alpha(unsigned int xx, char *ptr) { int quo; *(ptr+2) = xx % 10 + 0x30; // derive ASCII code of the one’s digit quo = xx / 10; if(quo != 0){ *(ptr+1) = quo % 10 + 0x30; // derive the ASCII code of ten’s digit quo = quo / 10; // hundred’s digit } if(quo != 0) *ptr = quo + 0x30; // derive the ASCII code of hundred’s digit}


void read_temp (char *ptr){

char hi_byte, lo_byte, temp, *bptr;unsigned int result;bptr = ptr;PTM |= BIT1; /* enable TC72 data transfer */

putcspi0(0x80); /* send out TC72 control register write address */ putcspi0(0x11); /* perform one shot conversion */

PTM &= ~BIT1; /* disable TC72 data transfer */delayby100ms(2); /* wait until temperature conversion is complete */PTM |= BIT1; /* enable TC72 data transfer */putcspi0(0x02); /* send MSB temperature read address */hi_byte = getcspi0(); /* read the temperature high byte */lo_byte = getcspi0(); /* save temperature low byte and clear SPIF */PTM &= ~BIT1; /* disable TC72 data transfer */

lo_byte &= 0xC0; /* make sure the lower 6 bits are 0s */result = (int) hi_byte * 256 + (int) lo_byte;if (hi_byte & 0x80) { /* temperature is negative */

result = ~result + 1; /* take the two' complement of result */result >>= 6;


temp = result & 0x0003; // place the lowest two bits in tempresult >>= 2; // get rid of fractional part*ptr++ = 0x2D; // store the minus signint2alpha(result, ptr);

}else { // temperature is positive

result >>= 6;temp = result & 0x0003; // save fractional partresult >>= 2; // get rid of fractional partint2alpha(result, ptr); // convert to ASCII string

}while(*bptr){ // search the end of the string

bptr++;};switch (temp){ // add fractional digits to the temperature

case 0:break;

case 1: // fractional part is .25*bptr++ = 0x2E; // add decimal point*bptr++ = 0x32;*bptr++ = 0x35;*bptr = '\0';break;


case 2: /* fractional part is .5 */*bptr++ = 0x2E; /* add decimal point */*bptr++ = 0x35;*bptr = '\0';break;

case 3: /* fractional part is .75 */*bptr++ = 0x2E; /* add decimal point */*bptr++ = 0x37;*bptr++ = 0x35;*bptr = '\0';break;

default:break;

}}


Homework: Write the C variant for Example 3


Inter-Integrated Circuit (I2C) Interface


The I2C Protocol

Developed by Philips in late 1980s Version 1.0 was published in 1992. This version supports standard (100

Kbps) and fast(400 Kbps) mode.

Version 2.0 was published in 1998. The high-speed mode (3.4 Mbps) was added.

Classifies devices into slave and master Allow multiple masters to be attached to the same bus The master device uses either a 7-bit or 10-bit address to specify the

slave device as itspartner of data communication.

Supports bi-directional data transfer Allow multiple masters (microcontrollers) to share the same peripheral

devices

I2C Signal Level Float high and driven low Use the SCL signal to carry clock signal to synchronize data transfer Use the SDA signal to carry data and address The SDA and SCL pins of I2C devices (masters and slaves) are open-

drain and needexternal pull up resistors

The resistors 2.2 KW and 1 KW are recommended for 100 kbps and 400 kbps baud rate.


+VDD

RP RP

CLK1OUT

CLK1IN

Data1OUT

Data1IN

CLK2OUT

CLK2IN

Data2OUT

Data2IN

Device 1 Device 2

SDA line

SCL line

Figure 11.1 Connecting standard- and fast-mode devices to the I2C bus


Signal Components I2C data transfer consists of 5 signal components:

(a) Start (S)(b) Stop (P)(c) Repeated Start (R)(d) Data(e) Acknowledge (A)

Start Condition Used to indicate that a device would like to transfer data on the

I2C bus Represented by the SDA line going low when the clock (SCL)

signal is high Will initialize the I2C busSDA

SCL

Figure 11.2 I2C Start condition


Stop Condition

A condition that a device wants to release the I2C bus Is represented by the SDA signal going high when the SCL signal is high Once the stop condition is complete, both the SCL and SDA signals are high. This is

the idle bus.

SDA

SCL

Figure 11.3 Stop (P) condition


Repeated Start (R) Condition A Start signal generated without first generating a Stop condition to terminate the communication Used by the master to communicate with another slave or change data transfer directionwithout releasing the bus Also referred to as Restart condition

SDA

SCL

Figure 11.4 Restart conditionstart condtion data transfer restart

condition


Data

Represents the transfer of eight bits of information Data on the SDA line is considered valid only when the SCL signal is high. When the SCL signal is low, data is allowed to change. The eight-bit data may be a control code, an address, or data.

SDA

SCL

Figure 11.5 I2C bus data elements

Note. Data bit is always stable when clock (SCL) is high


Acknowledge (ACK) Condition

Data transfer needs to be acknowledged either positively (A) or negatively (NACK). A device acknowledges a byte it received positively by bringing the SDA line low

during the ninth clock pulse of SCL. If the device allows the SDA line to float high, it is transmitting a negative

acknowledge (NACK).

SDA

SCL

Figure 11.6 ACK condition

SDA

SCL

Figure 11.7 NACK condition


Synchronization

All masters generate their clocks on the SCL line to transfer messages on the I2C bus.

A defined clock is needed for the bit-by-bit arbitration procedure to take place.

Most microcontrollers generate the SCL clock by counting down a programmablereload value using the instruction clock signal.

Clock synchronization occurs when multiple masters attempt to drive the I2C bus andbefore the arbitration scheme can decide which master is the winner.

Clock synchronization is performed using the wired-AND connection of I2C interfacesto the SCL line.

The high-to-low transition on the SCL line causes the devices concerned (masters) tostart counting off their low period.

A master device that is counting off their low period will hold the SCL line low untilthe counter is count down to 0. At this point the device will release the

SCL line to high. If there is other devices holding the SCL low, then the SCL line will

remain low until allmaster devices have counted down to 0. At this point, the SCL line will

go high andall devices will start to count high.

The SCL line will be held low by the device with the longest low period.

By the same reasoning, the high period of the SCL signal is determined by the device with the shortest high period.


waitstate

start countinghigh period

counterreset

CLK1

CLK2

SCL

Figure 11.8 Clock synchronization during thearbitration procedure

Handshaking The clock synchronization mechanism can be used as a

handshake in data transfer. Slave device can hold the SCL line low after completion of one

byte transfer (9 bits). Slave halts the bus until it gets ready for the next operation and

then release the SCL line.


Arbitration In the event two or more master devices attempt to begin a

transfer at the same time, an arbitration scheme is employed to force one or more masters to give up the bus.

The master devices continue to transmit data until one master attempt to send a high while the other transmits a low.

Since the SDA bus has open drain, the master device that attempts to send a high will detect a low. At this point, it will stop driving the bus.

The arbitration process does not slow down the winning master’s transfer and no data gets lost.

master 1 loses arbitrationData 1 SDA

SCL

Data1

Data2

SDA

Figure 11.9 Arbitration procedure of two masters


I2C Addressing Methods

I2C protocol allows master devices to use either the 7-bit and 10-bit address to specify theslave device for data communication.

The 7-bit addressing uses the upper 7 bits of the address byte for address and the leastsignificant bit to specify the data transfer direction. The format is shown in Figure 11.13.

The 10-bit addressing uses two bytes to carry the address information. (a) The bit 0 of the high byte is used to indicate the data transfer direction.(b) The upper 7 bits have the pattern of 1111 0xx with xx representing the most significant two address bits of the slave. (c) The second byte carries the lower 8 address bits.

A6 A5 A4 A3 A2 A1 A0 R/W

Figure 11.13a 7-bit I2C address

1 1 1 1 0 A9 A8 R/W A7 A6 A5 A4 A3 A2 A1 A0

Figure 11.13b 10-bit I2C address


Data Transfer Format (7-bit addressing)

Master transmitter to slave receiver – shown in Figure 11.10. Master reads slave immediately after the first byte (address byte) – shown in Figure

11.11. Combined format. A master may transfer some data to the slave and then generate a

restart condition to read data from the slave or send/read data to/from other slave.-- shown in Figure 11.12.

S Slave address R/W A Data A Data A/A P

data transferred(n bytes + acknowledge)'0' (write)

from master to slave

from slave to master

A = acknowledge (SDA low)A = not acknowledge (SDA high)S = start conditionP = stop condition

Figure 11.10 A master-transmitter addressing a slave receiver with a 7-bit address. The transfer direction is not changed.


S Slave address R/W A Data Data P

data transferred(n bytes + acknowledge)'1' (read)

Figure 11.11 A master reads a slave immediately after the first byte

AA

S Slave address R/W A Data Data

read orwrite

Figure 11.12 Combined format

A/A R Slave address R/W A/A P

(n bytes +ack.)

repeated start

read orwrite

A

(n bytes +ack.)*

direction of transfer may change at this point

* not shaded because transfer direction of data and acknowledge bits depends on R/W bits


Data Transfer Format—10-bit Addressing

Master transmitter transmits to slave receiver with a 10-bit address – shown in Figure 11.16.

Master receiver reads slave transmitter with a 10-bit address – shown in Figure 11.17.Restart condition is generated in this format.

Combined format – A master sends data to a slave and then reads data from the sameslave. This is shown in Figure 11.18.

Combined format – A master sends data to one slave and then transmit data to anotherslave. This format is shown in Figure 11.19.

Combined format – Ten-bit and 7-bit addressing combined in one transfer. This formatis shown in Figure 11.20.

S slave address1st 7 bits

R/W A1 slave address2nd byte A2 data A data A/A P

(write)Figure 11.16 A master-transmitter addresses a slave-receiver with a 10-bit address

11110XX 0


S slave address1st 7 bits R/ W A1 slave address

2nd byte A2 dataR data P

(write)Figure 11.17 A master-receiver addresses a slave-transmitter with a 10-bit address

slave address1st 7 bits R/ W A3 A A

11110XX 0 11110XX 1

(read)

S slave address1st 7 bits R/ W A slave address

2nd byte A data A data A/ A

P

(write)

Figure 11.18 Combined format. A master addresses a slave with a 10-bit address, then transmit data to this slave and reads data from this slave.

R slave address1st 7 bits R/ W A data A data A

11110XX 0

11110XX 1

(read)


Figure 11.19 Combined format. A master transmits data to two slaves, both with 10-bit addresses.

S slave address1st 7 bits

R/W A slave address2nd byte A data A data A/A

P

(write)

R slave address1st 7 bits

R/W A data A data A/A

11110XX 0

11110XX 0

(write)

slave address2nd byte A

S 7-bit slaveaddress R/ W A data A data A/ A

P

(write)

Figure 11.20 Combined format. A master transmits data to two slaves, one with 7-bit address, and one with 10-bit address.

R 1st 7 bits of 10-bitslave address R/ W A data A data A/ A

0

11110XX 0

(write)

2nd byte of 10-bitslave address A


An Overview of the HCS12 I2C Module

The HCS12 I2C implements a subset of the I2C protocol. Provides interrupts on start and stop bits in hardware to determine if the I2C bus is free. Supports only 7-bit addressing Supports 100 kbps baud rate but requires the user to limit the slew rate to no higher than

100 ns if the 400 kbps baud is to be used. Limit the maximum bus capacitance to 400 pF for all conditions. Use PJ7 (SCL) and PJ6 (SDA) pins to support the I2C communication. Use 5 registers to support its operation:

(a) I2C Control Register (IBCR)(b) I2C status Register (IBSR)(c) I2C data I/O register (IBDR)(d) I2C Frequency Divider Register (IBFD)(e) I2C Address Register (IBAD)


ADDR_DECODE

CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG

DATA_MUX

input sync

In/Out datashift registerStart/stop

arbitrationcontrolclock

controladdresscompare

SCL SDA

AddressI2C

interruptdata bus

Figure 11.21 I2C block diagram


Registers for I2C Operation

I2C Address Register (IBAD) Contains an address to which it will respond when the I2C module is configured as a

slave device.

ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 001234567

Figure 11.22 I2C address register (IBAD)

I2C Data Register (IBDR) In master transmit mode, a data transfer is started whenever this register is written into.

The most significant bit is shifted out first. In master receive mode, reading this register initiates the reception of the next byte (the

master sends out 9 clock pulses to shift in data bits and replies with an acknowledge.)


The I2C Control Register

IBEN IBIE MS/SL Tx/Rx TxAK RSTA 0 IBSWAI

01234567

Figure 11.23 I2C control register (IBCR)

reset: 0 0 0 0 0 0 0 0

IBEN: I2C bus enable 0 = I2C module is reset and disabled 1 = I2C module is enabled. This bit must be set before any other IBCR bits have any effect.IBIE: I2C bus interrupt enable 0 = interrupts from the I2C module are disabled. 1 = interrupts from the I2C module enabledMS/SL: master/slave mode select 0 = slave mode 1 = master modeTx/Rx: Transmit/Receive mode select 0 = receive 1 = transmitTXAK: Transmit acknowledge 0 = An acknowledge signal will be sent out to the I2C bus on the 9th clock bit after receiving one byte of data 1 = No acknowledge signal response is sentRSTA: Repeat start 0 = no action 1 = generate a repeat start cycleIBSWAI: I2C bus stop in wait mode 0 = I2C module clock operates normally 1 = stop generating I2C module clock in wait mode


The I2C Control Register (continued) When setting the MS/SL bit from 0 to1, a start signal is generated on the I2C bus

and the master mode is selected. In the master mode, the Tx/Rx bit should be set according to the type of transfer required. The TxAK bit specifies the value driven onto the SDA line during data acknowledge

cycles for both master and slave receivers. I2C module always acknowledges the address matches regardless of the value of TxAK. Writing a 1 to the RSTA bit will generate a Restart condition on the I2C bus.

The I2C Status Register (IBSR) When a byte is being transferred, the TCF bit is cleared. When the I2C is configured as a slave and the address matches then the IAAS

bit will be set . The IBIF bit will be set under three circumstances:

(a) arbitration lost (IBAL bit is set)(b) byte transfer complete (TCF bit is set)(c) addressed as a slave (IAAS bit is set)


TCF IAAS IBB IBAL 0 SRW IBIF RXAK

01234567

Figure 11.24 I2C status register (IBSR)

reset: 1 0 0 0 0 0 0 0

TCF: Data transferring bit 0 = I2C transfer in progress 1 = I2C transfer completeIAAS: Addressed as a slave 0 = not addressed 1 = addressed as a slaveIBB: Bus busy bit 0 = the bus enters idle state 1 = I2C bus is busyIBAL: Arbitration lost 0 = arbitration is not lost 1 = arbitration is lostSRW: Slave read/write 0 = slave receive, master writing to slave 1 = slave transmit, master reading from slaveIBIF: I2C bus interrupt 0 = no bus interrupt 1 = bus interruptRXAK: Receive acknowledge This bit reflects the value of SDA during the acknowledge bit of a cycle. 0 = acknowledge received 1 = no acknowledge received


I2C Frequency Divider Register (IBFD) Four timing requirements to be met:

(a) SCL divider(b) SDA hold time(c) SCL hold time for start condition(d) SCL hold time for stop condition

SCL divider

SDA hold

SCL

SDASCL hold (start) SCL hold

(stop)

startcondition

stopcondition

SCL

SDA

Figure 11.25 SCL divider and SDA hold

Table 11.2 I2C bus timing requirements

symbol

SCL clock frequencySCL hold (start)SCL hold (stop)SDA hold

fSCLtHD;STAtSU;STOtHD;DAT

parameter standard mode fast modemin. max. min. max.

04.04.00

100--

3.45

00.60.60

400--

0.9

unit

KHzsss


IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC001234567

Figure 11.26 I2C frequency divider register (IBFD)

The use of the IBFD register

IBC7-IBC6: multiply factor (shown in Table 11.3) IBC5-IBC3: prescaler divider (shown in Table 11.4) IBC2-IBC0: shift register tap points (shown in Table 11.5)

Table 11.3 Multiply factorIBC7~IBC6 Multiply factor

00011011

010204

reserved

Table 11.4 Prescaler divider

IBC5~IBC3

000001010011100101110111

scl2start(clocks)

2226143062126

scl2stop(clocks)

7799173365129

scl2tap(clocks)

4466143062126

tap2tap(clocks)

1248163264128


Table 11.5 I2C bus tap and prescale values

IBC2~IBC0

000001010011100101110111

SCL tap(clocks)

56789101215

SDA tap(clocks)

11223344

Using Table 11.3, 11.4, and 11.5 is a laborious process. These three tables can be combined into Table 11.6. With Table 11.6, finding values to be written into the IBFD register becomes a

simple table lookup. By dividing the intended baud rate into the bus clock, one can locate one or

multiple rows in Table 11.6 with the same SCL divider value. One needs to verify that the SDA hold time, SCL hold time (start), and SCL hold

time (stop) all satisfies the timing requirements set out in Table 11.2 before making the selection.


Example 7: Assuming that the HCS12 is running with a 24 MHz bus clock, compute the values to be written into the IBFD register to set the baud rate to 100 KHz and 400 KHz.Solution: Case 1: Baud Rate = 100 KHz

SCL divider = 24 MHz 100KHz = 240 From Table 11.6,

SDA hold time = 33 E clock cycles = 1.375 ms < 3.45 msSCL hold time (start) = 118 E clock cycles = 4.92 ms > 4.0 msSCL hold time (stop) = 121 E clock cycles = 5.04 ms > 4.0 ms

The computed value satisfies the timing requirement.Write the value $1F into the IBFD register at 100 KHz baud rate.

Case 2: Baud rate = 400 KHzSCL divider = 24 MHz 400KHz = 60 From Table 11.6, the corresponding IBC value is $45.

SDA hold time = 18 E clock cycles = 0.75 ms < 0.9 ms SCL hold time (start) = 22 E clock cycles = 0.917 ms > 0.6 ms SCL hold time (stop) = 121 E clock cycles = 1.33 ms > 0.6 ms The computed value satisfies the timing requirement.

Write the value $45 into the IBFD register at 400 KHz baud rate.


Configuring the I2C Module Compute an appropriate value and write it into the IBFD register Load a value into the IBAD register if the MCU may operate in slave mode. Set the IBEN bit of the IBCR register to enable I2C module. Modify the bits of the IBCR register to select master/slave mode, transmit/receive mode,

and interrupt enable mode; parameters are passed in accumulator A (baud rate) and B (slave address)openI2C bset IBCR,IBEN ; enable I2C module

staa IBFD ; establish SCL frequencystab IBAD ; establish I2C module slave addressbclr IBCR,IBIE ; disable I2C interruptbset IBCR,IBSWAI ; disable I2C in wait moderts

void openI2C (char ibc, char i2c_ID){

IBCR |= IBEN; // enable I2C moduleIBFD = ibc; // set up I2C baud rateIBAD = i2c_ID; // set up slave addressIBCR &= ~IBIE; // disable I2C interruptIBCR |= IBSWAI; // disable I2C in wait mode

}


Programming the I2C Module

Generating Start Condition and send Slave ID

sendSlaveIDbrset IBSR,IBB,* ; wait until I2C bus is freebset IBCR,TXRX+MSSL ; generate a start conditionstaa IBDR ; send out the slave address

brclr IBSR,IBIF,* ; wait for address transmission to completemovb #IBIF,IBSR ; clear the IBIF flagrts

void sendSlaveID (char cx){

while (IBSR&IBB); // wait until I2C bus is idleIBCR |= TXRX+MSSL; // generate a start conditionIBDR = cx; // send out the slave address with R/W bit set to 1while(!(IBSR & IBIF)); // wait for address transmission to completeIBSR = IBIF; // clear IBIF flag

}


Instruction sequence to send a byte in accumulator Astaa IBDRbrclr IBSR,IBIF,* ; wait until IBIF flag is set to 1movb #IBIF,IBSR ; clear the IBIF flag

C statements to send a byte to I2C bus

IBDR = cx; // send out the value cxwhile (!(IBSR & IBIF)); // wait until the byte is shifted outIBSR = IBIF; // clear the IBIF flag

Instruction sequence to read a byte and acknowledge itbclr IBCR,TXRX+TXAK ; prepare to receive and acknowledgeldaa IBDR ; a dummy read to trigger 9 clock pulses brclr IBSR,IBIF,* ; wait until the data byte is shifted inmovb #IBIF,IBSR ; clear the IBIF flagldaa IBDR ; place the received byte in A and also initiate the

; next read sequence


C Statements to read a byte from the I2C bus

IBCR &= ~(TXRX + TXAK); // prepare to receive and acknowledgedummy = IBDR; // a dummy readwhile(!(IBSR & IBIF)); // wait for the byte to shift inIBSR = IBIF; // clear the IBIF flagbuf = IBDR; // place the received byte in buf and also initiate

// the next read sequence

Instruction Sequence to Read a Byte, Send NACK, and Generate Stop Conditionbclr IBCR,TXRX ; prepare to receivebset IBCR,TXAK ; perpare to send negative acknowledgement ldaa IBDR ; dummy read to trigger clock pulsesbrclr IBSR,IBIF,* ; wait until the byte is shifted inmovb #IBIF,IBSR ; clear the IBIF flagbclr IBCR,MSSL ; generate a stop conditionldaa IBDR ; place the received byte in A


C Statements to Read a Byte, Send NACK, and generate a Stop ConditionIBCR &= ~TXRX; // prepare to receiveIBCR |= TXAK; // prepare not to acknowledgedummy = IBDR; // a dummy read to trigger 9 clock pulseswhile(!(IBSR & IBIF)); // wait for a byte to shift inIBSR = IBIF; // clear the IBIF flagIBCR &= ~MSSL; // generate a stop conditionbuf = IBDR; // place the received byte in buf


I2C Data Transfer in Slave Mode

After reset and stop condition, the I2C module is in slave mode. Once in slave mode, the I2C module waits for a start condition to come. Following the start condition, eight bits are shifted into the IBAD register. The value of the upper 7 bits of the received byte is compared with the IBAD register. If the address matches, the following events occur:

(a) The bit 0 of the address byte is copied into the SRW bit of the IBSR register.(b) The IAAS bit is set to indicate the address match.(c) An ACK pulse is generated regardless of the value of the TXAK bit.(d) The IBIF bit is set


Instruction sequence to make sure the address match and take appropriate action

brset IBSR,IAAS,addr_match ; is address matched?…

addr_match brclr IBSR,SRW,slave_rdbset IBCR,TXRX ; prepare to transmit datamovbtx_buf,IBDR ; place data in IBDR to wait for SCL to shift it outbrclr IBSR,IBIF,* ; wait for data to be shifted out…

slave_rd bclr IBCR,TXAK+TXRX ; prepare to receive and send ACKbrclr IBSR,IBIF,* ; wait for data byte to shift inmovb#IBIF,IBSR ; clear the IBIF flagmovbIBDR,rcv_buf ; save the received data


Exercise 8: Digital Thermometer and Thermostat DS1631A

Mainly used to warn the possible overheat of the embedded system to prevent systemfailure.

When the ambient temperature exceeds the trip point, the DS1631A asserts the TOUTsignal.

Addressand

I/O Control

Configuration Register and Control Logic

Temperature Sensorand ADC

Temperature Register

TH Register

TL Register

DigitalComparator/

LogicTOUT

VDD

SCL

SDA

A0

A1

A2

GND

Figure 11.32 DS1631A functional diagram


DS1631A converts temperature into 9-, 10-, 11-, or 12-bit readings over a range of -55oC to 125oC.

TOUT is asserted whenever the converted ambient temperature is equal to or higher thanthe value stored in the TH register.

Once asserted, the TOUT output will stay high until the temperature drops below the valuestored in the TL register.

Negative temperatures are represented in twos complement format.

DS1631A Registers

Config, TH, TL, and Temperature are DS1631A internal registers. The Config register is 8-bit. The Config register can be read from and written into. TH, TL, and Temperature registers are 16-bit.


7 6 5 4 3 2 1 0DONE THF TLF NVB R1 R0 POL* 1SHOT*

*NV (EEPROM)power-upvalue 1 0 0 0 1 1 X X

Done: Temperature conversion done (read-only) 0 = Temperature conversion is in progress. 1 = Temperature conversion is complete. Will be cleared when the Temperature register is read.THF: Temperature high flag (read/ write) 0 = The measured temperature has not exceeded the value in TH register. 1 = The measured temperature has exceeded the value in TH register. THF remains at 1 until it is overwritten with a 0 by the user, the power is recycled, or a software POR command is issued.TLF: Temperature low flag (read/ write) 0 = The measured temperature has not been lower than the value in TL register. 1 = At some point after power up, the measured temperature is lower than the value stored in the TL register. TLF remains at 1 until it is overwritten with a 0 by the user, the power is recycled, or a software POR command is issued.NVB: Nonvolatile memory busy (read only) 0 = NV memory is not busy. 1 = A write to EEPROM memory is in progress.R1:R0 : Resolution bits (read/ write) 00 = 9-bit resolution (conversion time is 93.75 ms) 01 = 10-bit resolution (conversion time is 187.5 ms) 10 = 11-bit resolution (conversion time is 375 ms) 11 = 12-bit resolution (conversion time is 750 ms)POL: TOUT polarity (read/ write) 0 = TOUT active low 1 = TOUT active high1SHOT: Conversion mode (read/ write) 0 = Continuous conversion mode. The Start Convert T command initiates continuous temperature conversions. 1 = One-shot mode. The Start Convert T command initiates a single temperature conversion and then the device enters a low-power standby mode.

Figure 11.33 DS1631A Configuration register


Converting the Conversion Result to temperature The conversion result cannot be higher than 0x7D00 or lower

than 0xC900. A sample of temperature reading is shown in Table 11.8 .

Positive Conversion ResultStep 1

Truncate the lowest four bits.Step 2

Divide the upper 12 bits by 16.

Negative Conversion ResultStep 1

Compute the twos complement of the conversion result.Step 2

Truncate the lowest 4 bits.Step 3

Divide the upper 12 bits of the twos complement of the conversion result by 16.


DS1631A Command Set1. Start Convert T (0x51)2. Stop Convert T (0x22)3. Read Temperature (0xAA)4. Access TH (0xA1)5. Access TL (0xA2)6. Access Config (0xAC)7. Software POR (0x54)

Circuit Connection

SDA

SCL

5V

5V

5V

SDA

SCL

TOUT

GND

VDD

A0

A1

A2

DS1631A2.2K2.2KHCS12 MCU

IRQ.... other I2C slaves

SDA

SCL

Figure 11.34 Typical circuit connection between the HCS12 MCU and DS1631A


DS1631A Control Byte (Device ID)1 0 0 1 A2 A1 A0 R/W

7 6 5 4 3 2 1 0

Figure 11.35 Control byte for DS1631A

Example 8.1: Write a function to configure the DS1631A in Figure 11.34 to operate in continuous conversion mode and set the TOUT polarity to active high. Assume that the I2C has only one master and there is no possibility in getting bus collision.

Solution: Call the openDS1631 function on the next slide with the configuration byte of 0xE0:

ldab #$E0jsr openDS1631


openDS1631 ldaa #$92jsr sendSlaveIDbrclr IBSR,RXAK,openOK0 ; did DS1631A acknowledge?ldab #$FF ; return error code -1rts

openOK0 movb #$AC,IBDR ; send the "Access Config" commandbrclr IBSR,IBIF,*movb #IBIF,IBSR ; clear the IBIF flagbrclr IBSR,RXAK,openOK1 ; did DS1316A acknowledge?ldab #$FFrts

openOK1 stab IBDR ; sends configuration databrclr IBSR,IBIF,* ; wait until the byte has been shifted outmovb #IBIF,IBSR ; clear the IBIF flagbrclr IBSR,RXAK,openOK2 ; did DS1316A acknowledge?ldab #$FFrts

openOK2 bclr IBCR,MSSL ; generate a stop conditionldab #0 ; normal return coderts


C function to initialize the DS1631A

char openDS1631(char cy){ sendSlaveID(0x92); // generate a start condition and send ID if (IBSR & RXAK) return -1; // error code when DS1631 did not acknowledge IBDR = 0xAC; // send command "Access Config" while(!(IBSR & IBIF));

IBSR = IBIF; // clear the IBIF flag if (IBSR & RXAK) return -1; // error code when DS1631 did not acknowledge IBDR = cy; // send configuration byte while(!(IBSR & IBIF));

IBSR = IBIF; if (IBSR & RXAK) return -1; // error code when DS1631 did not acknowledge IBCR &= ~MSSL; // generate a stop condition return 0; // normal return code}


Example 8.2: Write a function to command the DS1631A to start temperature conversion.Solution:



startConv ldaa #$92jsr sendSlaveID ; generate a start condition and send DS1631's IDbrclr IBSR,RXAK,startOK0 ; did DS1631A acknowledge?ldab #$FF ; return error code -1rts

startOK0movb #$51,IBDR ; send "Start Convert T" commandbrclr IBSR,IBIF,* ; wait until the byte is shifted outmovb #IBIF,IBSR ; clear the IBIF flagbrclr IBSR,RXAK,startOK1 ; did DS1631A acknowledge?ldab #$FFrts

startOK1bclr IBCR,MSSL ; generate a stop conditionldab #0 ; normal return coderts


Example 8.3: Write a function to set the high thermostat temperature. The upper and lower bytes of the high thermostat temperatures are passed in stack. Solution:


Example 8.3: Write a function to set the high thermostat temperature. The upper and lower bytes of the high thermostat temperatures are passed in stack. (the highest temp to be accepted)Solution: THhi equ 2

THlo equ 3setTH ldaa #$92

jsr sendSlaveIDbrclr IBSR,RXAK,setTHok1 ; did DS1631A acknowledge?ldab #$FF ; return error code -1rts

setTHok1 movb #$A1,IBDR ; send out access TH command */brclr IBSR,IBIF,* ; wait until command is shifted outmovb #IBIF,IBSR ; clear IBIF flagbrclr IBSR,RXAK,setTHok2 ; did DS1631A acknowledge?ldab #$FFrts

setTHok2 ldaa THhi,sp ; get the upper byte of TH from stackstaa IBDR ; send out TH high bytebrclr IBSR,IBIF,*movb #IBIF,IBSR ; clear the IBIF flagbrclr IBSR,RXAK,setTHok3 ; did DS1631A acknowledge?ldab #$FFrts


setTHok3 ldaa THlo,sp ; get the lower byte of TH from stackstaa IBDRbrclr IBSR,IBIF,*movb #IBIF,IBSR ; clear the IBIF flagbrclr IBSR,RXAK,setTHok4 ; did DS1631A acknowledge?ldab #$FFrts

setTHok4 bclr IBCR,MSSL ; generate the stop conditionldab #0 ; normal return coderts


Example 8.4 Write a function to read the Config register from the DS1631A and return its value in accumulator B.


Example 8.5: Write a subroutine to read the converted temperature and return the upper and lower bytes in double accumulator D. Assume that the temperature conversion has been started but this function needs to make sure that the converted temperature value is resulted from the most recent “Start Convert T” command.


readTemp ldx #0 ; initialize return error coderdLoop jsr readConf ; is temperature conversion done yet?

cmpb #-1 ; is there any error?beq rdErr ; "andb #$80 ; check DONE bitbpl rdLoop ; conversion not done yet?ldaa #$92 ; generate a start condition and send outjsr sendSlaveID ; the DS1631A IDbrclr IBSR,RXAK,rdTempok1 ; did DS1631A acknowledge?ldx #-1rts

rdTempok1 movb #$AA,IBDR ; sends "Read Temperature command"brclr IBSR,IBIF,* ; movb #IBIF,IBSRbrclr IBSR,RXAK,rdTempok2 ; did DS1631A acknowledge?ldx #-1rts

rdTempok2 bset IBCR,RSTA ; generate a restart conditionmovb #$93,IBDR ; send DS1631A's ID with R/W set to 1brclr IBSR,IBIF,*movb #IBIF,IBSRbrclr IBSR,RXAK,rdTempok3 ; did DS1631A acknowledge?ldx #-1rts


rdTempok3bclr IBCR,TXRX+TXAK ; prepare to receive and ACKldaa IBDR ; perform a dummy read brclr IBSR,IBIF,* ; wait for high byte of temperature to shift inmovb #IBIF,IBSR

bset IBCR,TXAK ; prepare send NACK for the last readldaa IBDR ; place the high byte of Temperature in Abrclr IBSR,IBIF,* ; wait for the low byte read to completemovb #IBIF,IBSR ; clear the IBIF flagbclr IBCR,MSSL ; generate a stop conditionldab IBDR ; place the low byte of temperature in Bldx #0 ; correct return coderts

rdErr ldx #-1rts


Homework: 1. Write the C variant for Example 8.5 2. For the circuit shown in Figure 11.34, add a LED to HCS12 and set

the high-temperature trip point to 50°C. Whenever temperature reaches 50°C or higher, turn on the LED until the temperature drops down to 23°C. Please write the scheme, code and explanations.

void main (void){ openI2C(…,…); // set I2C baud rate to 100 KHz openDS1631(…); // configure DS1631 to perform 12-bit DTA conversion // continuously at set TOUT to be idle high setTH(…,…); // set TH to 50oC setTL(…,…); // set TL to 23oC startConv(); // start the DS1631A temperature conversion // LED specific operations or functions’ calling … while(1); // wait forever}

Content

What is Serial Peripheral Interface (SPI)? The HCS12 SPI Modules SPI Related Registers The I2C Protocol An Overview of the HCS12 I2C Module

SERIAL PERIPHERAL INTERFACE Razvan Bogdan Embedded Systems.

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