Sequential ckts

8/13/2019 Sequential ckts

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Principles of VLSI Design CMPE 413Sequential Circuits

Sequential Circuits

Combinational Circuits

Outputs depend on the current inputs

Sequential Circuits

Outputs depend on current and previous inputs

Requires separating previous, current and future

Calledstatesortokens

Example: Finite State Machines (FSMs), Pipelines

CL

clk

in out

clk clk clk

CL CL

PipelineFinite State Machine


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Sequential Circuits

If tokens moved through pipeline at constant speed, no sequencing elements will be needed

Ex: Fibre-optic cable, called wave pipeliningin circuits

However, dispersion is high in most circuits

We need to delay fast tokens, so that they don't catch up with slow tokens

Use flip-flops to delay fast tokens so that they move through exactly one stage per cycle

Inevitably adds some delay to slow tokens

Makes circuit slower than just the logic delay

Called sequencing overhead

Sometimes called clocking overhead

But it applies to asynchronous circuits too

Inevitable side effect of maintaining sequence


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Sequential Elements

Latch

Level sensitive

Transparent latch

D latch

Flip-Flop

Edge triggered

Master-slave flip-flop

D flip-flop, D register

DFlop

Latch

Q

clk clk

D Q

clk

D

Q (latch)

Q (flop)


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Sequential Elements: Latch

Pass Transistor Latch

Pros:

Tiny

Low clock loads

Cons:

Vtdrop

nonrestoringbackdriving

output noise sensitivity

dynamic

diffusion input

D Q


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Transmission Gate Latch

No Vtdrop

Requires inverted clock

Inverting Buffer

Pros:

Restoring

No backdriving

Fixes either:output noise sensitivity

Or diffusion input

Cons:

Inverted output

D Q

D

XQ

D Q


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Tristate feedback

Static

Backdriving risk

Static latches are now essential

Buffered Input

Fixes diffusion input

Noninverting

QDX

QDX


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Buffered Output

Non backdriving

Widely used in standard cells

Very robust (important feature)Rather large

Rather slow (1.5 - 2 FO4 delays)

High clock loading

Datapath Latch

Smaller, faster

Unbuffered input

Q

DX

Q

DX


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Sequential Elements: Flip-Flop

Flip-Flop

Built as a pair of back-to-back latches

D Q

X

D

X

Q

Q


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Sequential Elements

Enable

Ignore clock when enable is inactive

Mux: increase latch D-Q delay

Clock-gating: increase enable setup time, skew

D Q

Latc

h

D Q

en

en

Latc

hD

Q

0

1

en

Latc

h

D Q

en

DQ

0

1

enD Q

en

Flop

Flop

Flop

Symbol Multiplexer Design Clock Gating Design


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Sequential Elements

Reset

Force output low when reset is asserted

Synchronous vs. asynchronous

D

Q

Q

reset

D

Q

D

reset

Q

D

reset

reset

reset

SynchronousReset

AsynchronousReset

Symbol F

lop

D QLatch

D Q

reset reset

Q

reset


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Sequential Elements

Set / Reset

Set forces output high when asserted

Flip-Flop with asynchronous set and reset

D

Q

reset

set

reset

set


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Timing Diagrams

Flop

A

Y

tpd

Combinational

LogicA Y

D Q

clk clk

D

Q

Latc

h

D Q

clkclk

D

Q

tcd

tsetup t

hold

tccq

tpcq

tccq

tsetup

thold

tpcq

tpdqtcdq

Latch/Flop Hold Timethold

Latch/Flop Setup Timetsetup

Latch D-Q Cont. Delaytpcq

Latch D-Q Prop Delaytpdq

Latch/Flop Clk-Q Cont. Delaytccq

Latch/Flop Clk-Q Prop Delaytpcq

Logic Cont. Delaytcd

Logic Prop. Delaytpd

Latch/Flop Hold Timethold

Latch/Flop Setup Timetsetup

Latch D-Q Cont. Delaytpcq

Latch D-Q Prop Delaytpdq

Latch/Flop Clk-Q Cont. Delaytccq

Latch/Flop Clk-Q Prop Delaytpcq

Logic Cont. Delaytcd

Logic Prop. Delaytpd

Contamination

propogation delaysand


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Sequencing Methods

Flip-Flops

2-Phase latches

Pulsed latches

Flip-Flops

F

lop

Latch

F

lop

clk

1

2

p

clk clk

Latch

Latch

p

p

1

1

2

2-PhaseTrans

parentLatches

P

ulsedLatches

Combinational Logic

Combinational

Logic

Combinational

Logic

Combinational LogicLatch

Latch

Tc

Tc/2

tnonoverlap

tnonoverlap

tpw

Half-Cycle 1 Half-Cycle 1


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Max-Delay: Flip-Flops

F1

F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tpd

tsetup

tpcq

TC

tpcq

tpd

tsetup

+ +=

tpd

TC

tsetup

tpcq

+( )

sequencing delay


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Max-Delay: Pulsed Latches

Tc

Q1 Q2D1 D2

Q1

D2

D1

p

p

p

Combinational LogicL1

L2

tpw

(a) tpw

> tsetup

Q1

D2

(b) tpw

< tsetup

Tc

tpd

tpdq

tpcq

tpd

tsetup

TC max tpdq tpdtpcq tpd tsetup tpw+ +,+( )

tpd

TC

max tpdq

tpcq

tsetup

tpw

+,( )

sequencing delay


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Min-Delay: Flip-Flops

CL

clk

Q1

D2

F1

clk

Q1

F2

clk

D2

tcd

thold

tccq

tcd

thold

tccq


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Min-Delay: 2 Phase Latches

CL

Q1

D2

D2

Q1

1

L1

2

L2

1

2

tnonoverlap

tcd

thold

tccq

tcd1

tcd2

, thold

tccq

tnonoverlap

Hold time reduced by nonoverlap

Paradox: Hold applies twice each cycle

vs. only once for flops

But flops have two latches !!!


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Min-Delay: Pulsed Latches

CL

Q1

D2

Q1

D2

p t

pw

p

L1

p

L2

tcd

thold

tccq

tcd

thold

tccq

tpw

+Hold time increased by pulse width


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Time Borrowing

In a flip-flop based system

Data launches on one rising/falling edge

Must setup before next rising/falling edge

If it arrives late, system failsIf it arrives early, time is wasted

Flops have hard edges

In a latch-based system

Data can pass through latch when transperent

Long cycle of logic can borrow time into the next cycle

As long as each loop completes in one cycle

This mechanism is calledtime borrowing


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Time Borrowing

Latch

Latch

Latch

Combinational LogicCombinational

Logic

Borrowing time across

half-cycle boundary

Borrowing time across

pipeline stage boundary

(a)

(b)Latch

Latch

Combinational LogicCombinational

Logic

Loops may borrow time internally but must complete within the cycle

1

2

1 1

1

2

2


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Time Borrowing

Q1L1

1

2

L2

1 2

Combinational Logic 1Q2D1 D2

D2

Tc

Tc/2

Nominal Half-Cycle 1 Delay

tborrow

tnonoverlap

tsetup

How much borrowing?

2 phased latches:

pulsed latches:

tborrow

TC

2------- t

setup t

nonoverlap+( )

tborrow

tpw

tsetup


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Clock Skew

F1

F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tskew

CL

Q1

D2

F1

clk

Q1

F2

clk

D2

clk

tskew

tsetup

tpcq

tpdq

tcd

thold

tccq

We have assumed zero clock skew

Clock really have uncertainty in arrival time

decrease max-delay

increases min-delay

decreases time borrowing

Clock Skew: Flip-flops

tpd

TC

tpcq

tsetup

tskew

( )

tcd thold tccq tskew+


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Clock Skew: Latches

Q1L1

1

2

L2

L3

1 12

Combinational

Logic 1

Combinational

Logic 2

Q2 Q3D1 D2 D3

2 phased latches

tcd1

tcd2

, thold

tccq

tnonoverlap

tskew

+

tpd

Tc

2tpdq

( )

tborrow

TC

2------- t

setup t

nonoverlap t

skew+ +( )

pulsed latches

t

pd

T

C

max t

pdq

t

pcq

t

setup

t

pw

+, t

skew

+( )

tcd

thold

tccq

tpw

tskew

+ +

tborrow

tpw

tsetup

tskew

+( )

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