Seoul National University CMOS for Power Device CMOS for Power Device 전파공학 연구실...

Seoul National University

CMOS for Power CMOS for Power DeviceDevice CMOS for Power CMOS for Power DeviceDevice

전파공학 연구실전파공학 연구실2003-215762003-21576

노 영 우노 영 우

전파공학 연구실전파공학 연구실2003-215762003-21576

노 영 우노 영 우

2004-12004-1

Microwave Device Term ProjectMicrowave Device Term Project

2004-12004-1

Microwave Device Term ProjectMicrowave Device Term Project


OutlineOutlineOutlineOutline

• RF Performance of CMOS • RF Performance of CMOS

• RF CMOS Modeling• RF CMOS Modeling

• Problem of CMOS for Power device• Problem of CMOS for Power device

• Power performance of CMOS• Power performance of CMOS

• Solution for CMOS Power Amplifier• Solution for CMOS Power Amplifier

• Conclusion• Conclusion


View of RF CMOS for System on a ChipView of RF CMOS for System on a ChipView of RF CMOS for System on a ChipView of RF CMOS for System on a Chip

5~6 years ago5~6 years ago5~6 years ago5~6 years ago

RF CMOS ?

Few works in Device modeling

Insufficient design environment

Digital CMOS Tech.

Most work from Univ.

CMOS PA (Study)

Only LDMOS , BV > 20V

RF CMOS ?

Few works in Device modeling

Insufficient design environment

Digital CMOS Tech.

Most work from Univ.

CMOS PA (Study)

Only LDMOS , BV > 20V

RF CMOS is optional Much work Sufficient design enviroment RF CMOS Tech. Inductor, MIM, Varactor How many product ! No commercial Handle design for CMOS RF/Analog/Digital chip Much work for CMOS PA Integration

RF CMOS is optional Much work Sufficient design enviroment RF CMOS Tech. Inductor, MIM, Varactor How many product ! No commercial Handle design for CMOS RF/Analog/Digital chip Much work for CMOS PA Integration

Essential for low cost product Provide design kit model, layout DB Deep well tech. GSM phone (Si-lab)1.8 V/ 3.3 V & Circuit below 200 mW is common

Essential for low cost product Provide design kit model, layout DB Deep well tech. GSM phone (Si-lab)1.8 V/ 3.3 V & Circuit below 200 mW is common

2~3 years ago2~3 years ago2~3 years ago2~3 years ago TodayTodayTodayToday

Expectation of CMOS limit always changes with timeExpectation of CMOS limit always changes with time

- Enormous research, investment, engineers, - Enormous research, investment, engineers, foundry……….foundry……….

Expectation of CMOS limit always changes with timeExpectation of CMOS limit always changes with time

- Enormous research, investment, engineers, - Enormous research, investment, engineers, foundry……….foundry……….


RF performance of CMOSRF performance of CMOSRF performance of CMOSRF performance of CMOS

0.18 CMOS shows 150 G0.18 CMOS shows 150 GHz fHz fmax max

0.05 um SOI of CMOS0.05 um SOI of CMOS

- f- fT T of 178 GHzof 178 GHz

- f- fmax max of 193 GHzof 193 GHz Comparable with SiGe HComparable with SiGe HBT TechnologyBT Technology

- f- fmax max of 240 GHzof 240 GHz

0.18 CMOS shows 150 G0.18 CMOS shows 150 GHz fHz fmax max

0.05 um SOI of CMOS0.05 um SOI of CMOS

- f- fT T of 178 GHzof 178 GHz

- f- fmax max of 193 GHzof 193 GHz Comparable with SiGe HComparable with SiGe HBT TechnologyBT Technology

- f- fmax max of 240 GHzof 240 GHz

PerformancePerformance

Ref. : L. F. Tiemeijer, et al., ’01 IEDM, Secession 10-4Ref. : L. F. Tiemeijer, et al., ’01 IEDM, Secession 10-4

S. Narasimha, et al., ’01 IEDM, Secession 29-2S. Narasimha, et al., ’01 IEDM, Secession 29-2

RF performance of Active Device



Device Performance with Scale-down

Fmax & Noise of CMOS Fmax & Noise of CMOS Inductor Q, linearity Inductor Q, linearity

Gm increase : improve fmax, Fmin, IP3

Metal layer increase : improve inductor Q

Gm increase : improve fmax, Fmin, IP3

Metal layer increase : improve inductor Q

Ref. : SIA The national Technology Roadmap for Semiconductors, 1998Ref. : SIA The national Technology Roadmap for Semiconductors, 1998

E.Moriuji, et al., Sysm. On VLSI Circuits, 1999E.Moriuji, et al., Sysm. On VLSI Circuits, 1999

Year 1997 1999 2002Gate length (um) 0.25 0.18 0.13Vdd [V] 2.5~1.8 1.8~1.5 1.5~1.2Inductor (Q) 25 30 75IP3 (dBm) - 6 - 4 - 2.5Year 2005 2008 2011Gate length (um) 0.1 0.07 0.05Vdd [V] 1.2~0.9 0.9~0.6 0.8~0.5Inductor (Q) 75 75 100IP3 (dBm) - 1.5 - 1 0



Noise performance NMOSFET vs PMOSFET

Two times lower fmax, fT compared with NMOSFET because of mobility (Transconductance) Two times lower fmax, fT compared with NMOSFET because of mobility (Transconductance)

Ref. : C. S. Kim, et al., EDL, pp 607-609, Dec.2000Ref. : C. S. Kim, et al., EDL, pp 607-609, Dec.2000


RF CMOS ModelingRF CMOS ModelingRF CMOS ModelingRF CMOS Modeling

Basic CMOS model for RFBasic CMOS model for RF Basic CMOS model for RFBasic CMOS model for RF

UC Berkeley ModelUC Berkeley Model UC Berkeley ModelUC Berkeley Model

For successful RF circuit design, the proper prediction of

Frequency characteristics (fT, fmax) Small signal modeling

Linearity characteristics (P1dB, IP3) Large signal modeling

Noise characteristics (NF, Rn) Noise modeling

are required.

For successful RF circuit design, the proper prediction of

Frequency characteristics (fT, fmax) Small signal modeling

Linearity characteristics (P1dB, IP3) Large signal modeling

Noise characteristics (NF, Rn) Noise modeling

are required.

Limit of SPICE Model (BSIM3v3)Limit of SPICE Model (BSIM3v3) Limit of SPICE Model (BSIM3v3)Limit of SPICE Model (BSIM3v3)

Limit in High freq. For Digital, low freq Analog Circuit

Need Rg for S11, Rsub for S22

Limit in High freq. For Digital, low freq Analog Circuit

Need Rg for S11, Rsub for S22


What is the market asking for ?What is the market asking for ?What is the market asking for ?What is the market asking for ?

Distributed ActiveDistributed ActiveTransformerTransformerDistributed ActiveDistributed ActiveTransformerTransformer


Problem of CMOS for PAProblem of CMOS for PAProblem of CMOS for PAProblem of CMOS for PA

Unsuitable Device for PA ( High Knee Voltage ) Unsuitable Device for PA ( High Knee Voltage )

in

out

T

knee

kneeT

kneeT

CD

out

DC

inout

P

PG

VV

V

G

GVVVI

VVVI

GP

P

P

PP

,

)1

1()1(

)1(

2

1

)1

1()(

4

)(8

)1

1()(

max

maxmax

maxmax

For high efficiency, Vknee should be low,

Vmax should be high (~BVdss ~ 2VDD)

For high efficiency, Vknee should be low,

Vmax should be high (~BVdss ~ 2VDD)



Unsuitable Device for PA ( Large Voltage Swing ) Unsuitable Device for PA ( Large Voltage Swing )

30 dBm 1 W 10 Vp Celluar29 dBm 0.8 W 9 Vp PCS27 dBm 0.5 W 7 Vp23 dBm 0.2 W 4.4 Vp WLAN20 dBm 0.1 W 3.1 Vp16 dBm 40 mW 2.0 Vp WLAN10 dBm 10 mW 1.0 Vp Bluetooth0 dBm 1 mW 0.32 Vp Bluetooth

Load line for Pin=25 dBm ~ 2Vdd

BVdss of LDMOS ~ 20V, Unsuitable for integration

Oxide breakdoun limit

Hot carrier effect Reliability limit

Excellent potential for 2~5 GHz wireless comm.

Load line for Pin=25 dBm ~ 2Vdd

BVdss of LDMOS ~ 20V, Unsuitable for integration

Oxide breakdoun limit

Hot carrier effect Reliability limit

Excellent potential for 2~5 GHz wireless comm.



Effect of Scaling on the Design of CMOS PA Effect of Scaling on the Design of CMOS PA

As minimum channel length Lmin of MOS Tr scales down,

Reduced supply voltage

( 3.3 V for 0.35 um & 2.5 V for 0.25 um )

Required load resistance to be reduced

The smaller load resistance required for a down scaled CMOS technology results in larger power loss in the impedance matching network lower efficiency

L

DDout R

VP

2

outloss PQ

mP

1

LRm

50

““1 W still remains a challenge !”1 W still remains a challenge !”


Power performance of CMOSPower performance of CMOSPower performance of CMOSPower performance of CMOS

800 ~ 900 MHz 800 ~ 900 MHz

Performance Pout PAE Class Supply Voltage Year

[1] Hewlett-Packard 1 W 42% A/ B/ C 2.5 V 1997[2] Motorola 85 mW 55% A/ B/ C 3 V 2001[3] Univ. of Minnesota 20 dBm 31% oscillator 3.3 V 2001[4] Samsung 0.9 W 41% E 1.8 V 2001[5] Philips & Stanford 1.5 W 43% F 3V 2001

1700 ~ 1900 MHz 1700 ~ 1900 MHz

Performance Frequency Pout PAE Class Supply Voltage Year

[1] Berkeley 1.9 GHz 1 W 48% E 2 V 1999[2] CNET France Telecoom 1.9 GHz 23.5 dBm 35% AB 2.5 V 2000[3] Georgia Institute of Tech.1.9 GHz 25 dBm 40% F (LTCC) 3.3 V 2001[4] Lisbon 1.9 GHz 22.8 dBm 42% F 3 V 2001[5] Nokia GSM 1800 1 W 55% AB 3.4 V 2001[6] Ohio state univ. 2 GHz 16 dBm 33% AB 3.3 V 2001


Power performance of CMOSPower performance of CMOSPower performance of CMOSPower performance of CMOS

2.4 GHz 2.4 GHz

5 ~ 5.3 GHz 5 ~ 5.3 GHz


[1] Georgia Tech. 20 dBm 31% AB (MEMS L) 2.5 V 2001[2] Cal. Tech. 2.2 W 27% E 2 V 2001[3] Philips 23 dBm 42% AB 3.3 V 2002[4] Hong Kong univ. 18 dBm 33% E 1 V 2003[5] Cheng Kung univ. 20 dBm 28% AB 2.5 V 2003


Nanyang Tech. Univ. 19 dBm 32% A 1.8 V 2004


Power performance for WPower performance for WfingerfingerPower performance for WPower performance for Wfingerfinger

Device SizeDevice Size

VDD = 3.0 V

Thick Oxide, L= 0.35 um

Current 22 mA

VDD = 3.0 V


Current 22 mA

Load pull measurementLoad pull measurement


Load Pull Measurement of Power Load Pull Measurement of Power TransistorTransistorLoad Pull Measurement of Power Load Pull Measurement of Power TransistorTransistor

@ 2 GHz@ 2 GHz @ 5 GHz@ 5 GHz

VDD = 3.0 V


VDD = 3.0 V


Thick Oxide power transistor using 0.25 umThick Oxide power transistor using 0.25 um


Solutions for Large Swing (Case 1) Solutions for Large Swing (Case 1) Solutions for Large Swing (Case 1) Solutions for Large Swing (Case 1)

Thick Gate Oxide in 0.2 um CMOS ( Timothy C. Kuo, Philips, ISSCC’01Thick Gate Oxide in 0.2 um CMOS ( Timothy C. Kuo, Philips, ISSCC’01 Thick Gate Oxide in 0.2 um CMOS ( Timothy C. Kuo, Philips, ISSCC’01Thick Gate Oxide in 0.2 um CMOS ( Timothy C. Kuo, Philips, ISSCC’01

A 1.5W Class F RF PA in 0.2 um CMOS

By using Thick Ox. : output node sustain 7 Vp

A 1.5W Class F RF PA in 0.2 um CMOS

By using Thick Ox. : output node sustain 7 Vp

<Cascode Topology><Cascode Topology>

Sine wave driver VS square wave driver

Inductor tuning driver: Negative swing damage oxide

Higher efficiency in square driver case

Sine wave driver VS square wave driver

Inductor tuning driver: Negative swing damage oxide

Higher efficiency in square driver case



Inverter Driven 2-stg Power Amplifier in 0.2 um CMOSInverter Driven 2-stg Power Amplifier in 0.2 um CMOS Inverter Driven 2-stg Power Amplifier in 0.2 um CMOSInverter Driven 2-stg Power Amplifier in 0.2 um CMOS

Class F: Resonate Co & Lo @ 2fo

Power control: Control the cascode bias Class D, E (switching PA) : BVds

s > 3.6 VDD

VDD (3V/1.8V), 900 MHz, 1.5W, PAE(43%), Class F

Class F: Resonate Co & Lo @ 2fo

Power control: Control the cascode bias Class D, E (switching PA) : BVds

s > 3.6 VDD

VDD (3V/1.8V), 900 MHz, 1.5W, PAE(43%), Class F



Self-biased Cascode 0.18 um CMOS ( Tirdad Sowlati, Philips, ISSCC’02 )Self-biased Cascode 0.18 um CMOS ( Tirdad Sowlati, Philips, ISSCC’02 ) Self-biased Cascode 0.18 um CMOS ( Tirdad Sowlati, Philips, ISSCC’02 )Self-biased Cascode 0.18 um CMOS ( Tirdad Sowlati, Philips, ISSCC’02 )

DC of D2 and G2 : same Bias for G2 is provided by Rb /Cb

Rb /Cb is chosen for Equal gate-drain signal swing on M1 and M2

DC of D2 and G2 : same Bias for G2 is provided by Rb /Cb

Rb /Cb is chosen for Equal gate-drain signal swing on M1 and M2



Self-biased Cascode 0.18 um CMOS ( Tirdad Sowlati, Philips, ISSCC’02 )Self-biased Cascode 0.18 um CMOS ( Tirdad Sowlati, Philips, ISSCC’02 ) Self-biased Cascode 0.18 um CMOS ( Tirdad Sowlati, Philips, ISSCC’02 )Self-biased Cascode 0.18 um CMOS ( Tirdad Sowlati, Philips, ISSCC’02 )

Inter stage LC, Output MN (off chip)

VDD=2.4 V, Po= 23.5 dBm, PAE(45%), Gain 38 dB

Hot carrier degradation @ 23.5 dBm (6 days) 23.4 dBm

Inter stage LC, Output MN (off chip)

VDD=2.4 V, Po= 23.5 dBm, PAE(45%), Gain 38 dB

Hot carrier degradation @ 23.5 dBm (6 days) 23.4 dBm


5 GHz CMOS Power Amplifier (Case 3) 5 GHz CMOS Power Amplifier (Case 3) 5 GHz CMOS Power Amplifier (Case 3) 5 GHz CMOS Power Amplifier (Case 3)

802.11a WLAN ( David Su, Atheros, ISSCC’02 )802.11a WLAN ( David Su, Atheros, ISSCC’02 ) 802.11a WLAN ( David Su, Atheros, ISSCC’02 )802.11a WLAN ( David Su, Atheros, ISSCC’02 )

Fully differential Class A

0.25 um CMOS, 3.3 V, 190 mA

22 dBm

Fully differential Class A

0.25 um CMOS, 3.3 V, 190 mA

22 dBm


Multi-Band/ Mode CMOS PAMulti-Band/ Mode CMOS PAMulti-Band/ Mode CMOS PAMulti-Band/ Mode CMOS PA

Dual Band PA ( WLAN Application )Dual Band PA ( WLAN Application ) Dual Band PA ( WLAN Application )Dual Band PA ( WLAN Application )

Highly linear PA for OFDM

Single power supply 3.3 V

Small size package with heat sink

Highly linear PA for OFDM

Single power supply 3.3 V

Small size package with heat sink


ConclusionConclusionConclusionConclusion

CMOS is most unsuitable device for power amplifier, but much works to integrate the PA will be continue. Good performance RFIC ~ Good active device design Library is not sufficient for high performance IC design. 802.11 a/b/g low power, multi-band, multi-mode PA application - High integration level

CMOS is most unsuitable device for power amplifier, but much works to integrate the PA will be continue. Good performance RFIC ~ Good active device design Library is not sufficient for high performance IC design. 802.11 a/b/g low power, multi-band, multi-mode PA application - High integration level

Seoul National University CMOS for Power Device CMOS for Power Device 전파공학 연구실...

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