Lehigh UniversityLehigh Preserve

Theses and Dissertations

1984

Sense amplifier circuitry for a 32K X 8 staticNMOS read only memory /Hai Q. PhamLehigh University

Follow this and additional works at: https://preserve.lehigh.edu/etd

Part of the Electrical and Computer Engineering Commons

This Thesis is brought to you for free and open access by Lehigh Preserve. It has been accepted for inclusion in Theses and Dissertations by anauthorized administrator of Lehigh Preserve. For more information, please contact preserve@lehigh.edu.

Recommended CitationPham, Hai Q., "Sense amplifier circuitry for a 32K X 8 static NMOS read only memory /" (1984). Theses and Dissertations. 4478.https://preserve.lehigh.edu/etd/4478

SENSE AMPLIFIER CIRCUITRY

FOR A 32K X 8 STATIC NHOS

READ ONLY HEHORY

by

Hal Q. Pham

A Thesis

Presented co the Graduate Committee

of Lehigh University

in Candidacy for the Degree of

Master of Science

in

Electrical and Computer Engineering Department

Lehigh University

1984

© 1984 AT&T Technologies, Inc.

n1h thl'sh h nccl'ptl'd nnd iipprov<'d In pnrt in) ful rt I JIIK'nt af tlw

J)11e.. 4t!', dH (dllt<')

~~-rofessor i ~ge

.................... : '":-.·~·-_ .. _ ._.

ACK.~OWLEDGEHENTS

Tho author wfshos to oxpross his npproclntion to lndlvldunls who

contributions hnvo mndo complotfon of this pap~r posslblo: Professor

H. If. ~hlto for Initiation and guldnnco and J. F. Cunn who crftlcnlly

rovlowod this papor.

···------ .. - .....

- iii -

TABLE OF COHTENTS

Abstract

l Introduction

A. Description of R,Md Only Hcmorlos (ROMs)

B. History of ROMs

C. Scopr o( thi ~. work

11 TcchnoloNy

111 Memory Op1•r,1t ion

lV Design Considerations

V Sense Amplifier Circultry

A. Sense Amplifier Clock

8. Data Latch Clock

C. Sense Amplifier Circuit

VI Design Evaluation

VII Advantages of the Sense Amplifier Circuitry VIII Conclusion

lfoference

Appendix

Biographical Sketch

.. ____ .. _.__._. ... ,---·-··--.......... .. _-..•• ! .....

- iv -

Pnga

1

3

3

4

7

7

10

14

16

16

18

20

24

26

27

29

30

46

LIST OF FICURES

Fig. l Blt don1lty vi tlmo (yanr1) ror ROH1, PROH1, EPROH1,

Ft,;. 2

Fig. 3

Flg. 4

Fig. s

Flg. 6

Fig. 7

nnd EEPROH1 In Btpolnr, CHOS, .1nd NHOS tochnologio1.

Schcmilt le d lngrnm of ., NHOS t rnns lstor

2S6K NHOS ROH block diagram.

Timing dlagram for 2S6K NHOS ROH.

Sense amplifier clock.

Data latch clock.

Sense amplifier circuit.

-v-

SENSE AMPLIFIER CIRCllfTRY FOR A l2K X 8 NHOS STATIC

READ ONLY MEHORY

by

11.1 i Q. Ph,1m

ABSTRACT

A 32K by 8 NMOS SLatic ROH (Read Only Memory) has been developed.

Since this ROH has static operation iL does not require an lnput

strobe. The memory cell is a NMOS transistor. Information is mask

encoded at either the thin oxide or threshold implant level.

As ml•mnry c.1p,1c i ty requi remc>nts for permanent stnr;ige increased,

NMOS dl•sign rult.'S h,1vc slc,H.lily shrunk, .al lowing LIil' fabrication or more densely packed chips. In order to take ;idv;int,1ge of these

red111ology improvements, Llw 2'.ibK ROM h,1s bet.'n redl•sigrwd with tighter

design rules. B,1scd on characterization of the original design, the

redesign has some new circuitry to improve performance and reduce chip

,ire a.

Completely new sensing circuitry w,is employed and will be the

scope of this paper, The new sense amplifier circuitry is simpler and

requires Less area than the original design. Noise coupling on the

memory array bit Lines has been isolated from the sense amplifier. ' This results in an increase in signal level and makes the circuit less

sensitive to variations in power supply (VCC). The new sense amplifier

should work well in next generation ROMS designed in either NMOS or

CMOS technology.

- 1-

This paper will hlghllghc tho NHOS technology, briefly doscrlbo the basic operation of the 256K ROH and present a detailed description of the sense ampllfler clrcultry. Results of the circuit response based on computer simulations for varlatiuns in process pnr~meters, temperature and power supply will be included.

:..:.:::--··~·------~ .... i,e_.. :·· ·-· ··•••• •

- 2-

I. Introduction

A. Doscrlptlon of Road Only Homorlos (ROHs)

ROHs aro doslgnod having ono or throo dlfforont typos of control circuitry. Tho cholco of control clrcultry dotormlnos If the part Is dynamic (clocked), edge actlvatod or completely static. A dynamic ROM is a synchronous device and clocked by a chip enable pulse. During standby tho peripheral circuitry ls not powered which gives good performance with respect to power consumption. During the active cycle the addresses arc normally latched and the internal peripheral

circuitry is powered up. Edge activated ROMs arc asynchronous devices and require no input clock. They have equal access and cycle times. One type of pare uses edge activated buffers co create internal timing thus reducing standby current. The completely static ROM uses ripple through circuitry chat remains powered up during an active cycle.

The 256K ROM referred in this work is organized as 32,768 words by 8 bits. The chip has 15 addresses (AO through A14) and 8 outputs (01 through 08). The ROM is accessed by an address change and edge acti­vated address buffers are used to create the internal clocks; this reduces standby current~!) Slow address changes are allowed and the

address inputs are TTL compatible. This part also uses an output

enable lead which gives an access time that is approximately twice as fast as chip enable,

The memory consists of four separated 64K arrays, each containing --· ••··•r1l•••t II dats1 for 2 outputs and each- o;-g~_ni_?;_g,9,_t"l.S .512 ro1o1:s. .. by.. ... t 28···-co1\.trlTfi~. '..'f.he ··~·--·-·· ......... .--_... .. _ ........ ---~ • •• '4 ··-···· ·-

... ROM memory cell consists of a single NMOS transistor that shares its bit line and column select line with other cells along a common word

-3-

lino. Roforonco coils dro omployod dnd consist of two NHOS tr4n1i1tor1

which 1ro connoctad fn 1orlo1. Tho roforonco coll, roforonco bit lino

dnd roforanco soloct lino .iro physlcdlly locdtod fn tho mlddlo of tho

,urays. Data ls suppl lod by the! usor .1nd fs oncodod during w4for

fabrication at either the! thin oxlda or thr«!shold implant IC!vel.

8. History of the ROMs

RC!ad Only HC!morlC!s (ROMs) are! memories who data ls non-volatile.

Power can be removed and the stored lnformaton is unaffected. Thls

contrasts with dynamic and static RAMs whlch loose information if power

is removed.

Mask encoded ROMs arc programmed during wafer fabrication. Other

members of the ROM family arc PROMs (Programmable ROHs) that can be

encoded once using techniques such as fusible links after wafer fabri­

cation. EPROMs (Erasable PROMs) that can be erased by ultra violet

light after writing with high voltage. EEPROMs (Electrical Erasable

PROMs) can be written and erased by high voltage. Since EPROMs arc

more expensive than mask encoded ROMs, they have often been used only

for primary investigations. Then, once major production levels arc

required, ROMs having pinout compatibility the with EPROM arc employed.

Before the advent of the high density integrated circuit, several

different ROM techniques were used such as capacitive coupling,

inductive coupling and resistive coupling. These techniques could not

be entirely integrated because of the diversification of components

involved. The semiconductor technology made it possible .. to .. c;:.Q,w.g,1i;,t.e.ly

integrate the ROM into a single si 1 icon chip~2) Initially ROMs used

slow P-channcl, metal gate technology and access time ranged from 500

-4-

nanoseconds to a couple oC microseconds. ROH dpplicatlons woro codo convorslon, random logic synthesis, table look-up and character

gcnorat ion.

Today tho semiconductor technology, using Bipolar and HOS (Metal Oxide Semiconductor) technology, dominates tho ROH market. Tho Bipolar technology has boon used for high speed ROHs. The first 256 bit Bipolar ROH apppearcd on the market in 1968 and the 1024 bit chip

(2) arranged 256 by a 4 bit words appeared at the end of 1969. In general, the disadvantages of the Bipolar ROHs were a higher cost per bit and higher power consumption. Initially the MOS technology offered lower cost and lower power consumption but its access time was slower. With improved processing, MOS technology can now offer the high speed ROMs compatible with Bipolar ROM but at a lower cost, Thus, MOS technology dominates the high density ROM market. The NMOS (N-channel MOS) and CMOS (Complementary MOS) are the two primary technologies used in fabrication of MOS ROMs. Compared with NMOS, CMOS offers very low standby power. However, the NMOS technology still dominates the ROM market since it is a well-known technology, it offers a higher density capacity, With the improvement in the CMOS technology and with low power required in many systems, CMOS technology may be the answer for future ROM designs, Over the years, the density of the EPROM has trailed that of ROM with EEPROM and Bipolar PROM coming in third, Figure 1 shows the bit density of diff~ren~ ~ypes of ROM for variqus.

"' (3) - -·--· technol?~ies;

- 5 -

lM

512K

256K

>-... -0)

~ 128K C

.... - 64K Cl)

CIOS 32K PIOii

16K

1980 1981 1982 1983 1984 1985

BIT DENSITY VS TIME (YEARS) FOR ROM•, PROM1, EPROM1, AND EEPROM1 IN BIPOLAR, CMOS, AND NMOS TECHNOLOGIES(3)

FIGURE 1

-6-

1M

512K

256K

>-~

en ~ 128K Q

~

m 64K

32K

16K EEPIOl1 (IIOS AID CIO~

IIPOLAR PIOii

CIOS PROl1

1980 1981 1982 1983 1984 1985

BIT DENSITY VS TIME (YEARS)

FOR ROM,, PROM,, EPROM1, AND EEPROMs

IN BIPOLAR, CMOS, ANO NMOS TECHNOLOGIES(3)

FIGURE 1

-6-

C. Scope Of This Work

The scope of this work will be the sense amplifier circuitry om­ployed In the 256K NHOS Static ROM. A detailed description of the

sense amplifer circuitry as well as the sense amplifier clock, data latch clock, the memory cell and the reference cell will be discussod. The results of the circuit response based on computer simulation over the operating temperature range, the VCC power supply range and the

various processing parameters will be included. A description of the basic NMOS transistor and processing steps will also be mentioned. In addition, the basic operation of the memory will be described and this section will clarify the discussion about the sensing operation.

II. NMOS Technology

The Metal-Oxide-Semiconductor (MOS) technology can be used to fabricate low cost, small size and low power consumption devices. It is widely used for Very Large Scale Integrated circuits (VLSI) such as micro-processor and semiconductor memories.

The basic structure of a N-channel MOS transistor which is used in the 256K ROM design is shown in Figure 2. It is a four terminal device and consists of a p-type semiconductor substrate. A thin oxide gate region is topped by a gate electrode. The gate is a layer of

polycrystalline silicon (polysilicon), To reduce the capacitance due to the overlap of the gate with the source and drain, the self-aligned gated process is used. Two n+ regions, the source and drain are formed . ... .,.~ .. ···~ ..... by ion implantation into the substrate, using the gate as a mask, The

-7-

-···

CHANNEL

SOURCE

p-type NA

VBB

FIELD OXIDE

THIN OXIDE REGION

DRAIN

(SUBSTRATE BIAS)

SCHEMATIC DIAGRAM OF A NMOS TRANSISTOR FIGURE 2

- 8 -

baslc physical device parnmeters are the channel length L, whlch ls the

distance between the two implanted n•regions; the channel width W; the

insulator thickness d; the Junction depth Xj, and the substrate doping (4)

NA• The voltage between the gate and ground necessary to create a

channel is called threshold voltage VT. lf the device requires a

positive voltage on the gate to form a channel, it is called an

enhancement-mode transistor. If no voltage is applied to the gate

there is no conduction between the source and drain since they form

back to back diodes. Then the only current that can flow from drain to

source is the leakage current. When a sufficiently large positive

voltage is applied to the gate, electrons are attracted to the surface

and a channel is formed between the two n+regions. The source and

drain are then connected by this channel and current can flow. If a

channel is formed by ion implantation, the device is called a

depletion-mode transistor. In this case, the device has a negative

threshold voltage and is normally on. A negative voltage (VBB) is

supplied by an on-chip generator and contacts the substrate. This

negative voltage helps conrol device parameters such as threshold and

helps eliminate the current leakage (subthreshold leakage) when the

device is turned off.

Two levels of interconnect, aluminum and polysilicon are used in

the 256K ROM design. In the memory array, polysilicon runners similar

to the gate material and having a low resistance are used for the word

lines. Aluminum runners having lower sheet resistance are used for

the bit lines. Aluminum runners are also used for power busses and

control signal paths.

- 9 -

Four throshold voltagos (Two doplotion 4nd two onhancomcnt modos)

arc usod in this clrcult design. Tho hoavy doplotlon throshold device

ls fabricatod by ton implanting a donor clement through the gate oxide

insulator. It provides full power supply voltage levels without boot­

strapping. The high enhancement threshold device is created by ion

implanting an acceptor clement through the gate oxide. The low

enhancement threshold device ls made the same way as for the high

enhancement threshold device except the acceptor doping dose is lower.

Both enhancement device types arc used to provide the flexibility co

generate proper operating margins without sacrificing performance. The

light depletion threshold devices arc created by the combination of the

heavy depletion and high enhancement threshold ion implantation. They

are used as pull up devices with the gate driven from a previous stage,

thus achieving full signal swings with a reduced power consumption

during power down. All the bit line precharge devices are light

depletion threshold transistors.

III. Memory Operation

The basic operation of the memory will be described briefly in

this portion. It will be referenced in explaining the sense amplifier

circuitry.

The detailed block and timing diagrams in Figures 3 and 4,

respectively, will be used to describe the basic memory operation.

The following assumptions will be made. The addresses are

stable and the chip enable (CE) lead is held low thus enabling the chip

and all circuits are powered up.

- 10-

C3

IOICLI IOICLI

PULS£ a,;;&4v+.;;.;av:.:.1_t.------11 .. IOI CLOCI ...._ .................. STIETCH£11

ADDRESS IUFFERS

AID TIAISITIOI DETECTORS

CE CHIP

EIAILE IUFFER

fl RSEL

1101 DECODER

COLCL I

...._ _____ ____ SEISE

AIPLIFIER CLOCK

ISYDD

HUD

C3

IOICU

If IOU AIIIIAYS 512 IOHS

" 512 IITS

DATA LIIES

COLCLI

IOI DECODER

IEFEIEICE DATA LIIE

SA+5AI

256K NMOS ROM BLOCK DIAGRAM FIGURE 3

- 11-

lDDlfSSfS :X-------------­CAVI

PULS( STIUCN(I VALID

IOI CLOCI

COLU• CLOCI

IIT Lllf PRECNHCE

COLUII SELECT

SEISE AIPLIFIU CLOCI

SEISE AIPLIFIU CLOCI OUTPUT

DATA LATCH CLOCI

DATA OUTPUT BUFFER CLOCI

SEISE AIPLIFIU OUTPUT

OUTPUT

(AVII

IIOWCLIC

WL

COLCLIC

CUI

COLSEL

RSEL

RSY20

RSYDD

C3

C4

SA (SAi)

Ul(U)

VALID

TIMING DIAGRAM FOR 2~6K NMOS ROM FIGURE 4

- 12-

Whon Any addross transition occurs, 4 narrow clock signal (EDCE)

ls croatod by tho translclon dotoccor portion of the address buffers.

Tho EDCE pulso lnlclates tho soquenco of operation chat initially

prepares the chip for lnterrogatlon, then selocts the appropriate

address and transfers tho memory data to the output buffers.

Tho initial, or non valid portion of an address cycle ls used to

prepare all circuits for operation. During this portion of an address

cycle, the EDCE signals are expanded by a pulse stretcher circuit to

create two signals, address valid (AV) which goes low, and its

complement AVB which goes high. The static address buffers become

stable. The row decoder clock (ROWCLK) and the column decoder clock (COLCLK) are still low. The l of 512 word line and the 1 of 64 column

line are still not selected until ROWCLK and COLCLK go high. The bit

line precharge (CIRB) is high and charges all the bit lines to VCC.

The data output buffer clock (C4) goes low putting the output in the

high impedance state. C4 going low starts turning off the data latch

clock (C3), the output signals SA and SAB from the sense amplifier

circuit are released and both go high.

After the circuits have been prepared for operation, the valid

portion of the address cycle begins. When the pulse stretcher turns

off, AVB goes low and AV goes high, ROWCLK goes high and the 1 of 512

work line is selected, ROWCLK going high turns off the bit line

precharge clock (CIRB), ROWCLK also turns on COLCLK after a delay,

This delay compensates for the word line delay and guarantees that end cells are properly interrogated, This delay also assures all the bit line precharge devices turn off before a column is selected and

-D-

provonc1 largo cran1iont curront1 ln tho ,nomory arrays. Whon COLCLK turns on, a column lino In oach 64K array ls solocted. Seloccod bit llnos ronmln high tr no coll ls programmod and go low tr a cell ls presont. COLCLK turning on pulls the rororonco soloct signal (RSEL) low and tho roforonco bit lino ts pulled down halfway botweon tho voltage level of a bit line having a cell present and tho case whore no coll is programmed. RSEL goes low turning on the sense amplifier clock {RSY2D) which starts the sensing operation. SA goes low and SAB goes high if no cell is present, and SA goes high and SAB goes low if a cell is programmed. When the SA and SAB levels arc separated, CJ turns on and latches SA and SAS. As CJ goes high, it turns on the data output buffer clock C4 and the outputs are valid. CJ turns off the row and column clocks. ROWCLK and COLCLK go low turning on CIRB and all the bit lines are charged to VCC level and the internal nodes in the sense amplifier are recovered in preparation for the next cycle.

IV. Design Considerations

The sense amplifier circuitry has been designed to optimize the performance of the 256K ROM. Several of the major concerns leading to the sense amplifier design will be discussed in this section.

1. Noise coupling

Silicon nitride (Si3N4) which is used as the encapsulating material for the final passivation of the device has a high dielectric constant. When applied to the chip, the capacitance between the column select line and the bit line is increased substantially. Detailed

-~-

analysis of tho origlnnl 256K ROH part lndlcntod thnt tho lncroaso in

cnpacltnnco caused a docroaso In tho bit lino signal duo to the noise

coupling bocwoon tho column select line and tho blt line. The noise

coupling only affects the sensing operation whon no coll is progranrned

at the solccted bit location. In this case, the bit line level should

remain higher than the reference level. However, the noise coupling

can cause a negative transition. This transition can cause the bit

line level to be lower than the reference level. This results in the

sense amplifier detecting the wrong information. In the case where a

cell is programmed, the bit line level goes lower than the reference

level during the interrogation. Therefore, any negative transition in

the bit line does not affect the sensing operation. The goal of the

sense amplifier redesign was to minimize the affect of the negative

transition due to the noise coupling.

2, Recovery Time

In order to achieve a reasonable access or cycle time, the

recovery time for the sense amplifier circuitry should be fast, Once

the full MOS level of the sense amplifier outputs are created, these

outputs should be latched, all the bit lines, data lines, reference bit

line and reference data line are recovered to VCC level and the sense

amplifier circuitry is prepared for the next cycle,

3. Reference level

The reference level is the important level for the sensing

operation, The reference level should be halfway between the data line

levels achieved when a cell is programmed and no memory cell exists,

This level requirement must be valid over the full power supply and

- 15-

tomporaturo range when procossod wlth tho allowed variations In device

parameters.

V. Sense Ampll[ier Circultry

A. Sense Amplifier Clock

The schematic for Lhe sense amplifier clock is shown in Figure S.

The sense amplifier clock directly controls the state of the sense

amplifier circuitry. Two input signals are applied in this circuit.

The address valid AV is used to ensure the clock ls only on the valid

cycle. The reference select RSEL directly controls the sense amplifier

clock RSY2D and RSYDD signals. The sense amplifier clock is on when

the output level is "0" and is off when its output level is "1". The

sense amplifier clock output RSY2D is a source follower of the RSYDD

signal. Since the level of the sense amplifier clock does not require

a full VCC level when off, therefore the pull-up transistor M10S is a

low threshold transistor. This also reduces the standby current during

power down. The capacitor M3S is used to create a delay between the

reference select RSEL and the sense amplifier clock. This delay is

used to ensure there is enough difference signal level between the data

line and the reference line before the sense amplifier clock is on.

When the column clock turns on, it pulls the reference select RSEL

low, node RD1 is discharged slowly through transistor M4S. As RDl goes

low M6S turns off and RSY2B goes high. Transistors M8S and M11S are

turned on by RSY2B, and the sense amplifier clock RSY2D and RSYDD are

- 16-

M4S

vcc vcc vcc

o-1 RSEL M1S M7S

MIS

M3S M2S MIS

vss

SENSE AMPLIFIER CLOCK

FIGURE !5

- 17 -

vcc

RSY20

M11S

pulled low. Whon tho 1on10 ampliflor clock RSY20 goos low, tho 1on10

amplifier circuits start to sonso tho lovol dlfforonco bocwoon tho data

lino and tho roforonce lino. At this tlmo, RSYOO turns on the data

latch clock CJ wlth a delay. CJ goes hlgh to latch tho outputs of tho

sense amplifier clrcults. CJ also turns off the row and the column

clocks and RSEL goes high. RSEL golng hlgh, turns on HIS and ROI goes

high. RSY28 is pulled low, HBS and HllS turn off, both RSYDD and RSY2D

go high and are ready for the next cycle. Since the sense amplifier

clock is used for all eight sense amplifier circuits, transistor HllS

should be large to handle the heavy loading.

8. Data latch Clock

The schematic for the data latch clock is shown in Figure 6. The

data latch clock CJ is used to latch the sense amplifier outputs. The

sense amplifier also controls the column and row clock for fast

recovery time and reduced power consumption.

Three input signals are applied in this circuit. The output of

the sense amplifier clock RSYDD directly controls the data latch clock.

The address valid AV and the data output buffer clock C4 are used to

ensure the data latch clock is on as long as one of them is on.

In a previous valid cycle, AV, C4, CJ and RSYDD are high and nodes

50, 51 and 52 are low. When any address transition occurs, AV and C4

are turned off. As AV and C4 go low, nodes 51 and 52 go high and CJ

is pulled down by node 52. Once the memory has been prepared for

operation, AV goes high and pulls down node 51, Node 52 is still high

because both transistors M25L and M26L are off due to node 50 and

CJ being low. As mentioned before, when the column clock is on and

-IB-

vcc

M22L

0 I M21L RSYDD

vcc

52

50

M25L M26L

51

M23L AV I t£! M27L M28L

vss

DATA LATCH CLOCK

FIGURE 6

- 19-

vcc

M21L M30L

~

CJ

M!1L

pull1 down RSEL, RSYDD 3001 low. Whan RSYDD 3001 low, nodo 50 goo1

high and turns on dovico H25L, nodo 52 is pullod coward ground. Al

node 50 goos high and nodo 52 goos low, tho data latch cluck Cl goos

high and latches nil the senso amplifier outputs. Capacitor H2JL Is

usod to create a delay between RSYDD and CJ to guaranteo the sense

amplifier outputs are fully separated.

C. Sense Amplifier Circuit

The schematic for the sense amplifier circuit is shown ln Figure

7. Since the memory cell and the reference cell are important to the

response of the sense amplifier circuit, they have also been included

in this section.

As shown in the schematic, the memory cell consists of a single

NMOS transistor which shares its bit line and column select line with

other cells along a word line. The memory cell can be programmed at

the thin oxide or high threshold implant level. A memory cell when

programmed is a standard low threshold implant device and it will turn

on when the gate level is high. "No-cell programmed" means the

transistor is not formed by a thin oxide or the transistor has been

fabricated with a high threshold implant level. Therefore, there will

be no conduction between the column select line and the bit line even

when the word line is high. The reference cell consists of two

standard low threshold implant transistors which are connected in

series. The reference cell is designed in this way so that the change

in the voltage level of the reference bit line is about a half of the

change in the voltage of the bit line where the memory cell is pro­

grammed. The transistors for the memory cell and the reference are

- 20-

vcc

r --1 ... -•~1,..,1~•'""1_11c: __ 1_1...,• .... •1_L....1

11r,r1tr11c:i KUC? L •• , ••• ..,. I IIY L •• , -!~~!_~I ~I~ .J

I IIIFHINCI

COLUMN sruc, HIT

MIL

YO 1 OYMH HNU a1t,llflllll

vcc

IIHUINCI

\ICC

u

COCL•

1

-, r- --, ,--•A'' MIii I I I I I

vcc

ltlU

I 1tllt011Y I L---.J L---..J L CILL J COlUltN DN COLU. - - - KUCY I llf I HUCY I

.. tr COLUH D[COOfll -

LINI LIN( ...__.__ .. _____ .., YO II OTNIII DATA LINU

TO II OYMH DATA LINH

YO OTMU IUU Alt,Llf 11111

•••

SENSE AMPLIFIER CIRCUIT FIGURE 7

ldentlc4l so the reforonco blt lino and the bit lino levols wlll trAck

rognrdloss of the vAriatlon In tho processing, tempernturo and the

power supply.

The first sense amplifier stage begins with the column decoders

that select an individual column decoder line. A high voltage on a

column decoder line turns on the device H4L and the column select line

ls pulled down toward ground. The selected word line is high, and the

corresponding memory cell If programmed will conduct; otherwise it will

remain off. For example if HA is programmed, the bit line connected to

HA is pulled down toward ground. When the bit line is pulled down to a

level which is a threshold voltage below the column decoder line level,

the transfer device MJL turns on and transfers the bit line level to

the data line. This design intends to alleviate the noise coupling in

the bit line from transferring to the data line. When the column

decoders select a column decoder line, the reference column is also

selected, and results the reference select line (RSEL) is pulled toward

ground. The reference bit line is pulled down through two transistors

MlR and M2R which are turned on by the selected word line. Device M2L

also only turns on when the reference bit line is pulled down to a

level lower than the reference column select level by a threshold

voltage,

With the assumption that cell MA is programmed, the level of the

data line (DA) is lower than the reference data line (RBIT). The

second sense amplifier stage begins detecting when the sense amplifier

clock RSY2D turns on. The higher level of the reference data line

causes the transistor M4 to turn on harder than Ml and the level of

-~-

nodo II ls hlghor thnn node 10. Tr4n1l1tor H2 turns on hnrdor than HS rasultlng in nodo 10 being pullod down toward ground nnd noda 11

ronmtnlng high. Transistors H5 and H6 nre off nnd trnnslstors H2 and H3 are still on. Devices H3A and H6A are already turned on by the sense amplifier Interrupt control signal RD2S, SAB ls pulled down toward ground and SA remains at full VCC level. When the level of SA and SAB are fully separated, CJ turns on and latches these two signals until the next cycle, As CJ goes high, the row decoder and the column

decoder clocks turn off. The word line, column decoder select line and the reference column select line are also off, The bit line precharge CIRB goes high and all the bit lines, column select lines, reference select line and reference bit line are precharged to full VCC level. The data line and the reference data line are pulled up to VCC level by

the depletion devices MlB and M3R. Node 10 and 11 go high and the

complement signal of the column decoder goes high to equalize these two

nodes. The sense interrupt control RD2S also turns off to isolate SA

and SAB from the internal nodes of the sense amplifier. This isolation

is used to speed up the recovery time for the memory without any effect

on the sense amplifier outputs SA and SAB. Therefore, the memory can

be operated at a fast cycle time.

In the case where no cell is programmed, there is no conduction

between the bit line and the column select line, Therefore, the bit

line remains at VCC level, the transfer device M3L is off and the data

line remaining at the precharged VCC level, With a higher level on the

data line, node 11 will be pulled toward ground when the sense

amplifier clock turns on, Devices M2 and M3 are off and SAB remains at

-~-

thv VCC lvvQI. SA ii pullod down through dovico H6 which 11 turnvd on

by nodo 10. Tho lntchlng and rocovory oporatlon will bo tho snmo n1

mantlonod abovo. Tho no coll programming ls tho worst cn10 for tho

sonso ampllflor clock. Evon though the roforonco data lino lovol Is

lower than the data lino, It ls still high enough to turn on device H4 resulting In currant flowing through tho sense ampll(lor clock RSY2D

during tho sensing cycle. Since the sense amplifier clock is used for all eight sense amplifier circuits, the worst case for the sense

amplifier clock RSY2D occurs when all eight of the data lines (one per

output) are higher than the reference data line. Therefore, the pull

down device for the sense amplifier clock RSY2D (See Figure 5) should

be big enough to handle all the current from discharging eight sense

amplifier circuits.

VI. Design Evaluation.

The sense amplifier circuitry peformance has been evaluated by a

computer circuit analysis program call ADVICE (Aid in Design Veri­

fication for Integrated Circuit Engineering).< 5\he circuitry has been

simulated over the temperature and VCC power supply range. The

processing parameters were also varied over the expected ranges for

simulation purposes. The circuitry has been simulated in three

different cases which are called the slow, nominal and fast cases. The variations in processing parameters with the corresponding temperature

and power supply for these cases are shown in Table 1. All the

parasitic capacitors and resisitors are included in these simulations.

-~-

TABLE t

SUIULATlON CONDITIONS

Process VT Mobility C.apncltnncC? vcc Temp

Slow High Low Hlgh 4.3V I00°C

Nomlnnl Nomlnnl Nomlnnl Nominn l 5.0V 2s 0c Fast Low High Low 5.7V o0c

- 25-

Tholr valuas aro dorlvod from tho physical layout using both computer aids and hand calculations. Tho capacltanco o( tho silicon nitride (Sl3N4) passivation Is included to simulate tho noise coupling in the bit lines.

The ADVICE simulations for the sense amplifier circuitry in all three cases arc shown in Appendices Al through Al5. The simulations for the sense amplifier clock arc shown in Appendices Al through AJ and for the data latch clock arc shown in Appendices A4 through A6. In Appendices A7, AS and A9, show the responses of the first sense amplifier stage with cell and no cell progranuned. The results show that the reference data line (RBIT) response very well in all three cases; its level is about a half way between the level of the data line (DA) with cell programmed and the data line (DB) with no cell program­med. The results also indicate that there is a decrease in the bit line signal (088) due to the coupling with the column select line. The noise coupling does not affect the data line (DB) as indicated in these results because the data line (DB) is isolated from the bit line (DBB) by the transfer device. In Appendices AlO through Al5, the results of the second sense amplifier stage with a cell and no cell programmed respectively are shown.

VII. Advantages of the Sense Amplifier Circuitry

1. Isolation from internal bit line noise

With no cell programmed in the selected bit line location, the expected bit line level is high during interrogation. This level can

-~-

bo pullod down duo to n nogntlvo glltch which ls crontod by tho signal

coupling botwoon the blt lino and tho column select line. The detallod

analysis of the original 256K ROM and ·ocher ROH deslgnt6~ndlcaced chat

thls problem can cause the sense amplifier to detect the wrong lnfor­

m11tion. A transfer device ls used to transmit che selected bit llne to

the data lino. This transfer device isolates the data line from any

negative glitches on the bit line that are less than a Vt in amplitude.

2. Simplicity

Since each bit line requires only one transistor to transmit the

selected bit line signal to the data line, the sense amplifier cir­

cuitry is simple and requires little area. In face, all the transfer

devices have been merged with the column decoders because they are

driven directly by the column decoder lines.

3. Fast recovery time

After the sense amplifier outp.uts are latched by the data latch

clock C3, all internal nodes of the sense amplifier circuitry as well

as the bit lines, data lines, reference bit line and reference data

line are precharged and ready for the next cycle. This recovery occurs

before the data output buffer turns on, Therefore, another cycle or an

address change is allowed after the data is valid without any set up

time required, The fast recovery time also helps to reduce the power

consumption for the 256K ROM.

VIII. Conclusion

The sense amplifier circuitry has been evaluated by computer

- 27-

1imuldtion1, Rosult1 lndlcnta thic cha 1on10 ampllflor will porform

vory wall ovor a largo powor supply nnd comporAturo range evon when

fobrlcaud wlth largo v.iriat Ions ln procoulng, Tho fast re?covory c lme? ln cho sonsc .impllfler clrculcry would .illow choso circuits to be usod

in a high spoed ROH with low powor consumption, Thls Hnsing technlquo

is applicable to either NHOS or CHOS designs, Since tho data transfer

technique requires little space and easily fits in the column decoder

pitch, the circuitry could be used in future generations of ROH

designs.

-28-

REFERENCES

I. J. F. Gunn, c. R. Htllor, Prtvaco Co11111unicatfon.

2. R. Dusslno and R. Zlovo, "Re.1d Only Hcimory ln Computcirs-Wherci ,\rci They llciadod", EON, pp. 24-30, r\ugust 1972.

3. D. Bursky, "Hcimory Technology: Nonvolatile Memories", Electronic Design, pp. 120-144, August 1984.

4. S. H. Sze, "Physis of Semiconductors", John Wiley and Sons, lnc., 1981.

5. L. W. Nagel, "ADVICE for Circuit Simulation", Proc. 1980 Internation Symposium on Circuits and Systems, Houston, Texas, April 28, 1980.

6. D. R. Wilson, "Cell Layout Boosts Speed of Lower-Power 64-K ROM", Electronics, pp. 96-99, March 1978.

-29-

APPENDIX- SIMULATION FOR THE SENSE AHPLlFlER CIRCUITRY Air Simulation of the Sanso Ampllflor Clock-Slow case A2: Simulation of the Sense Ampltfler Clock-Nominal case Al: Sfmulntlon of the Sense Amplifier clock-Fast case A4: Simulation of the Data Latch Clock-Slow case A5: Simulation of tho Data Latch Clock-Nominal case A6: Simulation of the Data Latch Clock-Fast case A7: Simulation of the First Sense Amplifier-Slow case A8: Simulation of the First Sense Amplifier-Nominal case A9: Simulation of the First Sense Amplifier-Fast case AlO: Simulation of the Second Sense Amplifier (cell programmed)­Slow case

All: Simulation of the Second Sense Amplifier (cell programmed)­Nominal case

A12: Simulation of the Second Sense Amplifier (cell programmed}­Fast case

A13: Simulation of the Second Sense Amplifier (no cell programmed)­Slow case

Al4: Simulation of the Second Sense Amplifier (no cell programmed}­Nominal case

A15: Simulation of the Second Sense Amplifier (no cell programmed)­Fast case

-~-

..... ....

AS:SIMULATION OF THE SENSE AMPLIFIER CLOCl<-SLON CASE LlllftCII I VAIEL I WIii I VR1Ya 4 VRIYIIJ 8 VRIYal l,OE.00------------------------------

... OE+oa

l,OE+OO

2,0E+OO

S.OE+OO

o. o. 5.0E-08 I.OE-07 1,IIE-07

TINE (SJ 2,0E-07 2,IIE-07 3.0E-07

l.,.J

'"' I

A2:SIMULATI0N OF THE SfNSE AMPLIFIER CLOCK-NOMINAL CASE Legend I VADS I VRl'ta .. VRIYIIJ 8 YAIYaJ

I.CIE+OO .... ---~~~~~~~~~~~~---~~~~~~~~~~~~---~

I.CIE+OO

... OE+OO

o. o. 15.0E-oe S.OE-07

TIME (BJ S.15E-07 2.0E-07

A3: SIMULAllON OF lHE SENSE AMPLIFIER CLOCK-FAST CASE Legend t VHIEL 2 VADl S VA9'f28 4 VA9'fD0 II VAl'f2D

8.0EtOO ---~~~~~~~~~~~~~~~~~~~~~~~~~~~~~----.

8.0E+OO

4.0EtOO

2.0E+OO

o. o. 5.0E-08 l.OE-07 1.5E-07

TIME (SI

A4:SIMULATION OF THE DATA LATCH CLOCK-SLOW CASE L..,.ncl S VAIYIIJ 2 VIIO I VU 4 VAV I YC4 a VCI

1.or+oo...----------------------------------------------------------------------------------~ .......

l,OE+OO

a.oc+oo

1.0E+OO

-1.0E+OO-+-....-....----.....-......-.....-.....-......-...-....-.,._.......--.--....--....-....--..--..--....-.--....-r--,.--,~r--,,--,,........,,--,.--, o. 15.0E-08 S.OE-07 1.!E-07 TIME (9)

2.0E-07 2.!E-07 3.0E-07

w Ul

A5:SIMULATI0N Of THE DATA LATCH CLOCK-NOMINAL CASE L..-ncl S VRIYOD I VIIO I VIII 4 VAY I W:4 I VCI 7.0E+oo,-~~~~~~~~~~~~~~~~~~---~~~~~~~~~-,

I.OE+OO

S.OE+OO

-S.OE+OO-+---..----r--...----..---...----.---.----,--...._~.,........._~.,.....-r----r---r---,,---r---,.----r----t O. 5.0E-08 i.OE-07 S.IIE-07 2.0E-07

TINE(S)

w O"

I

A6:SIMULATI0N OF THE DATA LATCH CLOCK-FAST CASE

Legend s VRBVDD 2 V&O s VD2 4 VAY B VC4 • vcs 1.0E+oo...-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~---.

15.0E+OO

3.0E+OO

1.0E+OO

-1.0E+OO-+-"'T""-r--.---.---.---.---.---.---.-~~~....,.--.---.---,,--,.--,.--,--,--,--,--,--,--,,--,--...-..---...-t O. 5.0E-08 1.0E-07 1.5E-07

TIME (S)

w _, I

A7:SIMUL.ATION OF THE FIRST SENSE AMPLIFIER-SLOW CASE Legend 1 VAIii 2 VAIIIT S VDAII 4 VOA 8 VD111 • voe a.OE+oo..-~~~~~~~~~~~~~~~----------~--~~--~------.

4.0£+00

3.0E+OO

2.0E+OO

1.0E+OO 4--r--.---.---r--r---~......-----......----..,.-......-...--...---r-"T"-...-T-.,..-...--r-,--"r"-,,--...-..-4 0. !5.0E-08 1.0E-07 S.!SE-07

TIME (9) 2.0E-07 2.!SE-07 3.0E-07

AB: SIMULATION Of THE FIRST su,se AMPLIFIER-NOMINAl. CASt

IVIIIIT I VDM • VDA .... ..•. 00-----------------------------

I.OEtOO

4.0E•OO

o. o. I.OE-GI t.OE-07

TINE(IJ t.llE-07 2.0E-07

w '°

A9:S1MULATI0N OF THE FIRST SENSE AMPLIFIER-FAST CASE Legend s VRBD 2 VABIT 3 VOA& 4 VOA !I VDll8 I VIII 8.0E+OO~--~~~~~~~~~~~~~~~~~~~~~~~~~~~--.

... OE+OO

2.0E+OO

0. o. 5.0E-08 S.OE-07 S.5E-07 TINE (9)

AtO:SIMULATION OF THE SEC~~oiE~fie~HPLIFIER(CELL PROGRAMMED) Legend i VflllT I WA I VRIYID I VCI I.OE+oo-----------------------------.

... OE+OO

S.OE+OO

2,0E+OO

S.OE+OO

o. o. 6.0E-08 t.OE-07 t.!IE-07

TINE (8) 2.0E-07 2.IIE-07 8.0E-07

ASS:SIMULATION OF THE SE~~1~EA~IFIEA(CELL PAO&AMIEO) L..-nd s VflltT I VOA I VRIYID I VC8 1.ar+oo..-~~~~~~~~~~~~~~~~~~~~~~~~~ ......

a.ar+oo

~.OE+oo

2.0E+OD

o. o. 11.oe-oa S.OE-07

TIME(I) S.IE-07 2.0E-07

I i, N

I

AS~ SIMULATION OF Tt£ SEC~fE~~IFIEA (CELL PAO&AAMNED) .....,.. 1 van I VIM I WIIYID 4 VIA ... I VCI ...... __________________________ _

......

.......

......

o. o. II.GE-08 I.Ol-o7 I.E-07 TINECIJ

.....

..... I

e I

, .... ..... •• o.

I WIIIT I VIII

, ..... ••• -17 , ..

.... ·-

• •• -17

......... • VRllT I VIII I VIIIYID I VIM I w:I ···---------------------------

..... ......

I.OE+OO

o. o. I.CIE-OI &.OE-07

TIIECII &.E-07 I.OE-07

AS5: SIMlUTION OF Tl£ SECOt.f .nr--IFIEA (NO Ca.L PAO&fWIEO)

LIIIM I wn I VIII I VIIIVID .. VIA I VUI I -............ --------------------------

I.OEtGO

~ .... I.OEtGO

o. o. . ..... I.IE-07 TDE.

· ··- · --.-..-... ·-' a L· ·--...... - · --,-.-... -..._,.,:...._ta,.,....,,.;_,t.:(.llt~,.

BlOCRAPHlCAL SKETCH

HAI Q. PHAM

Born September 8, 1953 in Viet Nam. Parents nnmes Tinh T. Le nnd Cu V. Pham. lnwnigrated to the United States in May 1975 and naturalized in June, 1981. Single.

GRADUATE

Demonstration High Schoo.I, Viet Nam 1972 Bucks County Co11111unity College, Newtown, PA. Associate Degree in Engineering, 1977. The Pennsylvania State University-Capitol Campus, Middletown, PA. Bachelor of Technology Degree in Electrical Design Engineering with highest distinction, 1979.

EXPERIENCE

Employed by Bell Laboratories of Allentown, PA in 1979 as Senior Technical Associate. Past assignments had been related to the development of the 64K Bipolar ROM and 256K NMOS ROM. Transferred to AT&T Technologies Systems of Allentown, PA in 1983 as Development Engineer. Present assignments have been related to the development of the 64K Row Addressable RAM (RARAM) and redesign of custom logic devices for cost reduction.

----~----··-·· -- .. T18IIF ·-···--~-- -------

- 46 -