Senior Project Manager Agilent Technologies...March 2011 Francis Liu 劉宗琪Senior Project Manager...

March 2011

Francis Liu 劉宗琪

Senior Project Manager

Agilent Technologies

The Latest Solution for

Hi-Speed Serial Bus:

PCI Express, SATA and

USB Ver. 3.0 Test

Enabling the Compliance

Test of USB, SATA, PCIe 3.0

啟動USB, SATA, PCIe 3.0認證測試之新紀元

High-Speed Digital Markets & Technologies

PCIe 3.0, SATA Gen 3 & USB 3.0: all above 5 Gb/s

USB 3.0

QPIHT3

MIPI

100G EthernetSAS

DP

SFP+

8G

5.4G14G

4x25G12G

M-PHY

•PCI Express 3.0 – 8Gbps

•SATA Rev. 3.0 – 6Gbps

•USB 3.0 – 5Gbps

•SFF/SFP+ – 10.3125Gbps

•Thunderbolt – 10Gbps

•MIPI M-PHY – 6Gbps

• Agilent position in various Hi-speed Digital

Standards & Applications

• PCI Express 3.0 Spec Development and test

solution

• Storage Total Test solution Coverage –

SATA Rev. 3.0 & SAS -3

• USB 3.0 SuperSpeed Compliance Testing

Challenges

Agenda

Agilent Digital Standards Program Leadership

• Ethernet compliance application

• PCI EXPRESS compliance application

• HDMI compliance application

• SAS compliance application

• DisplayPort compliance application

• MIPI D-PHY compliance application

• 10GBASE-T Automated Test Application

• WiMedia Wrapper Compliance Test Application

• SATA 6Gb/s Compliance

• USB 3.0 Compliance Software

• User Defined Application

Compliance Testing

The Agilent Digital Standards Team directs the

company‟s engagement in the top high tech

standards organizations

Agenda




solution




Challenges

PCI-SIG PCI Express Standards Organization

PCI Express Board of DirectorsAgilent, Intel, IBM, LSI Logic, Dell, HP, Sun Microsystems, nVidia, AMD

PCI-SIG Executive Director: Reen Presnel, VTM

Electrical Work

Group:

Intel, AMD

Protocol Work

Group:

Intel

Card

Electromechanical

Work Group

Cable work

group

Legal: Tim Haslach

PCI Express 3.0

Serial Enabling

Work Group

Electrical Spec

Protocol Spec

C.E.M Spec

Cable Spec

Test Specification

PCI Express 3.0 Specification Changes

• New 12GHz oscilloscope maximum bandwidth specification

• De-embedding required (pin is reference for TX testing)

• CTLE + DFE (1 tap) Reference Receiver

• New jitter measurements for TX (Uncorrelated Jitter, Uncorrelated PWJ)

• Separate Channel Specification

• TX equalization space greatly expanded

• TXRX back channel established for tuning TX EQ settings maximizing

RX EQ performance

• Updated Reference Clock phase jitter requirements

• Calibration of RX jitter stress signal must account for calibration

instrument (Oscilloscope) noise floor.

• New Compliance Patterns (TX and RX)

TX Measurement Challenges for PCIe 3.0

4.3.3.1.2. Measurement Setup for 8.0 GT/s Transmitters

• The PCIe electrical specification references all measurements to the

device‟s pin. However, the pin of a device under test (DUT) is not

generally accessible, and the closest accessible point is usually a

pair of microwave-type coaxial connectors separated from the DUT

pins by several inches of PCB trace, called the breakout channel.

DUT

Low jitter

clock source

TP1TP1

DUT

Breakout

ChannelLow jitter

clock source

TP3TP2

Replica

Channel

Length 3 – 6”

External Generator. Can be a

pulse Generator (Agilent 81134A,

81150A) or sinusoidal source

(Agilent E8663D PSG or N5181A

MXG)

Specification Reference Point

is at the pin

Measurement point is

at TP1

Signal Path Flow

EQ

+

-

Co

nn

ecto

r

TP0 TP1

Channel

Co

nn

ecto

r

EQ

+

-

TP2 TP3 TP4

Txp

Txn Rxn

Rxp

Tx Rx

Signal generated here

Exits IC here

Exits board here

Combine measurements and transmission line

models to view simulated scope measurements at

any location in your design

Load S-Parameters into Signal Path

S-Parameters

S2P File

S21 Insertion Loss

{ 1,0,1} { 1,0,1}

and 1n m n n

n nTX PK c d cV V

1UI

delay

1UI

delay

C-1

C0

C1

dm

{-1,1}

VTX

Transmitter Equalization and Training

-- Transmitter FIR

Coefficient Space and Presets

Shown for the largest coefficient step size of 1/24 (smallest 1/63)

Depending on coefficient resolution some quantization error exists, preset

tolerance is relaxed to ±1dB or ±1.5 dB

Advisable for Rx equalizer to adapt to Tx and channel

11th preset is advertised by Tx and may vary, but must fit between min reduced

and max full swing limits

PS DE

0.0 0.0 0.0 -0.8 0.0 -1.6 0.0 -2.5 0.0 -3.5 0.0 -4.7 0.0 -6.0 0.0 -7.6 0.0 -9.5

0.8 0.0 0.8 -0.8 0.9 -1.7 1.0 -2.8 1.2 -3.9 1.3 -5.3 1.6 -6.8 1.9 -8.8

1.6 0.0 1.7 -0.9 1.9 -1.9 2.2 -3.1 2.5 -4.4 2.9 -6.0 3.5 -8.0

2.5 0.0 2.8 -1.0 3.1 -2.2 3.5 -3.5 4.1 -5.1 4.9 -7.0

3.5 0.0 3.9 -1.2 4.4 -2.5 5.1 -4.1 6.0 -6.0

4.7 0.0 5.3 -1.3 6.0 -2.9 7.0 -4.9

6.0 0.0 6.8 -1.6 8.0 -3.5

C-1

BOOST 4/24 5/24

9.5

4.7 6.0 7.6 9.5

6/24

2/24

3/24

4/24

1.6

2.5

3.5

9.5

C+1

5/24

6/24

0/24 1/24 2/24 3/24

0/24

1/24

2.5 3.5 4.7 6.0 7.6

9.5

7/24 8/24

9.5

3.5 4.7 9.5

7.6

4.7 6.0 7.6

3.5 4.7 6.0 7.6 9.5

6.0 7.6

6.0 7.6

0.8 1.6 2.5 3.5 4.7 6.0

0.0 0.8 1.6 2.5

Min Reduced Swing Limit

Full swing Limit or

Max reduced swing limit

Presets highlighted in red and green

Electrical Validation of Transmitters

PCIe Validation for PC devices

Motherboard Testing

Add-in Card Testing PCI-SIG AIC Test Fixture (CBB2)

PCI-SIG System Test Fixture (CLB2)

Add-in Card (AIC) TX Test

rx_spkg

cbb_conn2

RX SMP

cbb_conn1TX SMP

Test

Equipment

AIC Under Test

Post Processing S/W

Sigtest

(Embed Channel + RX

pkg + use behavioral EQ)

AIC RX Test Calibration

rx_spkg

cbb_conn2

RX SMP

cbb_conn1TX SMP

Test

Equipment

CLB 3.0

Post Processing S/W

(Embed RX pkg + use

behavioral EQ)

Signal

Generator

Sj + Rj +

Diff Noise

TXRX

AIC RX Test

rx_spkg

cbb_conn2

RX SMP

cbb_conn1TX SMP

Error

Detector

AIC Under Test

Signal

Generator

Sj + Rj +

Diff Noise

PCIe 3.0 CBB Fixture

•Limited Detent SMPs

•Similar to Gen2 CBB

•Emulates 20” 2 connector channel

•Prototypes in production

•Availability expected Feb-Mar

2011

N5393C TX Test Application

Agenda




solution

• Receiver Tolerance Validation




Challenges

Key Challenges of PCIe 3.0 RX Test

• Receiver test becomes „normative“

• 8 GT/s over traditional FR4 PC-boards

• Requires post-processing of a step

response signal

• 128/130 bit coded & scrambled –link

training

• Base spec vs. CEM spec -tests are still

changing.

PCIe 3.0 Receiver Test Challenges (Base Spec)

2. How to sweep jitter amount

over jitter modulation frequency?

1. How to optimize pre- and

post cursor de-emphasis?

Source: all graphics from PCIe Rev.3.0 Base Specification

3.Simultaneous!

5. Cannot measure at

reference RX (TP2P)

where stress is defined.

4. Need 3

different

channel

lengths!

Short + breakout

Long+ breakout

Breakout

• Built-in compliant & calibrated jitter injection

• Automated jitter tolerance

• Forwarded and embedded clocks

• Characterization and compliance

The only complete jitter tolerance test

enabling next generation embedded and forward clocking devices

J-BERT N4903B High-Performance Serial BERT

For R&D and test engineers who validate and test compliance of high-speed serial

computer & video bus and communication devices up to 14.2 Gb/s.

J-BERT makes the most accurate receiver tests - with less R&D time and

simpler setups.

Enables the release of robust designs and saves R&D resources!

PCI Express 3.0 RX

testing

Stress calibration

Cal channels

SJ sweep

Link training suite

New!

Generating Pre-and Post-cursor De-emphasis

De-emphasis settings for PCIe 3.0 can be

emulated by entering pre- and post-cursor

values for N4916B directly via J-BERT„s

user interface

11 pre-sets for de-emphasis for PCIe 3.0

are defined

1.

Stressed Jitter RX Test: setting RJ and SJ

Straight forward and complete

jitter set-up for both stressed

jitter and stressed voltage eye

tests

Filtering of RJ for

desired frequency

range 10 MHz – 1

GHz

Jitter tolerance compliance

curve defined for “swept”

SJ according to base

specification

2.

J-BERT N4903B offers built-in and compliant RJ and SJ sources:

PCIe 3.0 Calibration Channels

N4915A-014

-25

-20

-15

-10

-5

0

1 1.5 2 2.5 3 3.5 4

Breakout Channel Only

Breakout + Short Calibration Channel

Breakout + Long Calibration Channel

Frequency / GHz

S21

/ d

B

-20 ± 2dB

-12 ± 2dB

-2.5 ± 1dB-1.0 ± 1dB

-4.0 ± 1dB

-6.5 ± 1.5dB

• ISI Channels in external box (similar to SATA)

• Connectors: SMA/3.5mm female

• Includes suitable coupler on their input to add Interference such that

– BW high enough matching subsequent channel

– Attenuation of „data-leg“ suited for output amplitude of N4916B

suited for N4916B 14G (hi-want: suited for existing N4916B)

• Loss such that

the whole test set-up fulfils

the PCIe3 base specs

(orange-green & orange-blue)

assuming 2.5dB @ 4GHz

for the break-out channel

4.

breakout

short+ breakout

long+breakout

PCIe 3.0 RX Test Stress Calibration Procedure

Measure step response with RT scope to calculate S21 of test setup‟

Apply package model and RX CD,CTLE and DFE

SEASIM software calculates eye width and eye height at PRBS23

Adjust dm-S.I. and RJ until eye is closed enough

Program pattern generator and start RX test

See backup and app note for

more details on stress

calibration

SEASIM

software

from

PCISIG

This Software automates PCIe 3.0 Stress

Calibration and RX Test: N5990A-101 and -301Users can pick receiver

tests and get results

(green=pass). PCIe 3

RX stress calibration

is added.

Customers can

modify sequence

to adapt to

devices and

debug

PCIe 3 link training

sequence brings a

device into loopback

Automated jitter

tolerance and receiver

sensitivity tests provide

graphical results

1.

3.

4.

2.1

N5990A-101 PCIe RX test

automation

5.

2

Draft N5990A-301 user interface (Dec 10)

4

3

1

PCIe 3.0 test Conclusions

1. Probing at pins of device not practical at PCIe 3.0 speeds of 8GT/s.

2. De-embedding may remove fixture effects and recover some jitter margin.

3. Voltage measurements more impacted by de-embedding noise compared

to jitter.

4. Calibration of the stressed eye for receiver test should minimize effect of

instrument noise.

5. Stressed eye for RX testing is referenced to the die pad for the receiver. TX

voltage and jitter parameters are generally referenced to the pin of the

device.

6. Calibration Channel is crucial for ensuring RX signal amplitudes are at the

proper level at the RX Die pad.

7. Advanced active probing required for PCIe 3.0 Protocol Analysis

8. Tools for full PCIe 3.0 TX and RX testing are available today.

Agenda




solution




Challenges

Transmitter

Characterization

(PHY/TSG/OOB)

DSAX93204A

oscilloscope

SATA, SAS

compliance app

N8801A Protocol

viewer software*

Receiver

Characterization

(RSG)

N4903B High-

Performance Serial

BERT

Option A02 Receiver

FER Analysis

N5990A Automated

compliance and device

characterization test

Impedance/Return

Loss

(RX/TX)

DCA 86100D Wideband

sampling oscilloscope

54754A

TDR/TDT

E5071C ENA

Option TDR

Industry’s highest analog

bandwidth, lowest noise

floor/sensitivity, jitter

measurement floor

TDR/TDT Mode for

precision impedance

measurements with S-

Parameter capability

Automated compliance

software for accurate,

efficient, and consistent

measurement

Host/Device Digital

(ASR, GTR, NCQ, SSP,

IPM, DOF)

U3051/52A BusXpert

Protocol Analyzer

U3053A BusMod

Jammer/Error Injector

or BIST Generator

Fast upload and display,

accurate capture, intuitive

GUI and customizable

hardware

Agilent Storage Total Test Solution Coverage

Agilent Contributes to SATA-IO IW Program

• Certification of products for SATA-IO Integrators List

• There are currently 3 physical layer test areas at

Interoperability Workshops, as well as testing for cables

Transmitter

Approved Agilent Method of Implementation Documents for SATA UTD 1.4

Downloads are available from http://www.sata-io.org/interoperabilitydocumentation1_4.asp

ReceiverReturn Loss -

TDR

Return Loss -

ENACable - TDR Cable - ENA

SATA Approved Independent Test Labs

All SATA approved independent test labs use Agilent equipment for

interoperability certification. Be confident with your SATA certification process.

SATA / SAS Test Challenges

Agilent Restricted

T10 Committee SAS Roadmap

Source: http://www.scsita.org

SAS 12Gbps is planned for the year 2010. The T10 committee is finalizing

the SAS-2.1 spec, which will be the base for SAS-3 (12Gbps) spec.


Agilent Restricted

SAS 12G Scope Bandwidth Requirement

The calculation below assumes the data rate of SAS 12Gbps:

• 1UI = 83.33ps

• Rise Time (0.25 * 1UI) = 20.83ps

• Bandwidth (3% measurement accuracy)

= 1.4 * 0.4 / Rise Time (20-80%)

= 1.4 * 0.4 / 20.83ps

= 26.9 GHz

The recommended bandwidth for 12Gbps data rate is 28GHz


Agilent Restricted

True Analog Bandwidth + Low Noise Floor

6 GHz

1st harmonic

18 GHz

3rd harmonic

30 GHz

5th harmonic

JBERT has fast edge,

meaning lots of

harmonic content.

Notice how the low noise

of the 90000 X-Series

shows the full harmonic

content.

12Gbps signal with

21ps rise time (20-80%)

from the JBERT

Challenge: Do your tools meet the measurement requirements?


Agilent Restricted

Gen3i CIC Definition for Jitter and Amplitude

This could represent the 1-

meter internal cable length.

Before CIC

After CIC

Transmitter


Agilent Restricted

EQ

+

-

Test

Fix

ture

TP0 TP1

ScopeTxp

TxnTx

InfiniiSim for Embedding Gen3i CIC Channel

Embed the Gen3i CIC

channel and then make jitter

and amplitude measurements

to simulate the worst case

channel interconnect.

Minimum Differential Voltage Jitter Measurement

Challenge: Can your tools embed the required Gen3i CIC channel and then measurements?

Transmitter


Agilent Restricted

CIC

SATA Jitter Decomposition

How do I extrapolate jitter from Eye-diagram?

TJ

DJ RJ

PJISIDCD

Jitter Decomposition

How do you extrapolate TJ @ BER?

TJ

Bath Tub Curve extrapolates jitter at various BER.

How do you estimate TJ(1E-12) ?

TJ = 14.1 * RJ(rms) + DJ(d-d)

Challenge: Why is separating the jitter components important?

Transmitter


Agilent Restricted

N5411B SATA Compliance Application

• N5411B 6Gb/s transmitter

compliance application for scope and

81134A/N4903B pattern generator

provides automated measurements

for all 6Gb/s, 3Gb/s and 1.5Gb/s test

parameters.

• Covers all the 3 transmitter test

groups – PHY, TSG and OOB.

• SATA Gen3 transmitter needs to

meet the requirement for Gen2 and

Gen1 (for backward compatibility).

SATA-IO Gold Suite Test Tool

N4903B/81134A will work at 6Gb/s


Agilent Restricted

http://cp.home.agilent.com/upload/cmc_upload/Ruby_81134A_Angle.jpg

SAS 12G Physical Layer Transmitter Solution

The initial SAS 12G Transmitter solution will be available through User Defined

Application (UDA) that can be downloaded from www.agilent.com/find/sas12g

• Supports 12Gbps data rate.

• Leverage the UNH-IOL‟s SAS Consortium PHY test suite based on 6Gbps data rate

• REQUIRES the PHY (DUT) to be able to generate D10.2, D24.3, D30.3, CJTPAT and

Scramble_0 Compliance Test Pattern for conformance testing

RJ and TJ

Measurements

Peak-to-peak, Voltage

Mode Amplitude

(VMA) and

Equalization (EQ)

Measurements

SAS 12G UDA

Conformance Test SW


Agilent Restricted

http://www.agilent.com/find/sas12g

Agenda




solution





Challenges

SATA RSG - Receiver Jitter Tolerance Test

My RX

Receives without Error

Jitter Tolerance Test = Verify How Good/Bad your Rx is.

“ What Jitter distribution does my Rx work fine ?”

Jitter injected Pattern Generator

My RX Still

Receives without Error

CRC Error Counter

How Good is My Rx ? How BAD signal could My Rx

stand without error ?


Agilent Restricted

SATA-IO RSG Compliance Test

• Spec Defined Jitter Values:

TJ Gen1:501mUI Gen2:552mUI Gen3:570mUI

Fixed RJ(UI), SJ (UI), ISI (S-Para), Diff Vamp (mV)

with SJ Freq 5MHz,10MHz,33MHz,62MHz

• Remain No CRC error for each SJ Freq for,

Gen1:10min Gen2:5min Gen3 2.5min ( total 40+20+10 min)

5M 10M 33M 62M

SJ Frequency [Hz]

TJ [

UI]

0. 5UI

Challenge: What are the requirements for SATA receiver compliance test?


Agilent Restricted

RSG-01/02/03/05/06 Receiver Test Setup Connection Diagram

N4915A-005

Switch

1 12 2C C

switch

Power Divider

Power Divider

Pro

du

ct u

nd

er te

st

Tx

Rx

BIST L Source

TxRx

TTC ISI

Frame Error Counter

TP1

TP2

Investigation

45A. Schmitt

Dec. 08, 2009

ValiFrame N5990AOption 103, RSG and Receiver Characterization Tests

• Automated Calibration

• Test Selection

• Test parameter Control

(Expert Mode)

• DUTConfiguration

A. Schmitt

Dec. 08, 2009

46

PHY-01 : Unit Interval

PHY-02 : Frequency Long Term Stability

PHY-03 : SSC Modulation Frequency

PHY-04 : SSC Modulation Deviation

TSG-01 : Differential Output Voltage

TSG-02 : Rise/Fall Time

TSG-03 : Differential Skew

TSG-04 : AC Common Mode Voltage

TSG-05 : Rise/Fall Imbalance

TSG-06 : Amplitude Imbalance

TSG-09 : Gen1 (1.5Gb/s) TJ

TSG-10 : Gen1 (1.5Gb/s) DJ

TSG-11 : Gen2 (3Gb/s) TJ

TSG-12 : Gen2 (3Gb/s)

TSG-13 : Gen3 (6Gb/s) Transmit Jitter

TSG-14 : Gen3 (6Gb/s) Max Diff Vamp

TSG-15 : Gen3 (6Gb/s) Min Diff Vamp

TSG-16 : Gen3 (6Gb/s) AC Com Mode Voltage

OOB-01 : OOB Signal Detection Threshold

OOB-02 : UI During OOB Signaling

OOB-03 : COMINIT/RESET/WAKE Burst Length

OOB-04 : COMINIT/RESET Transmit Gap Length

OOB-05 : COMWAKE Transmit Gap Length

OOB-06 : COMWAKE Gap Detection Windows

OOB-07 : COMINIT/RESET Gap Detection Windows

RX-01 : Pair Differential Impedance

RX-02 : Single-Ended Impedance (Obsolete)

RX-03 : Gen2 Diff Mode Return Loss

RX-04 : Gen2 Common Mode Return Loss

RX-05 : Gen2 impedance Balance



RX-08 : Gen3 impedance Balance

TX-01 : Pair Differential Impedance

TX-02 : Single-Ended Impedance (Obsolete)

TX-03 : Gen2 Differential Mode Return Loss

TX-04 : Gen2 Common Mode Return Loss

TX-05 : Gen2 Impedance Balance



TX-08 : Gen3 Impedance Balance

RSG-01 : Gen1 (1.5Gb/s) Receiver Jitter Test

RSG-02 : Gen2 (3Gb/s) Receiver Jitter Test

RSG-03 : Gen3 (6Gb/s) Receiver Jitter Test

RSG-05 : Receiver stress Test at +350ppm (Informative)

RSG-06 : Receiver stress Test with SSC (Informative)

PHY, TSG, OOB Test

- Transmitter Signal Quality

Tx, Rx Test

- Impedance/Return Loss

RSG Test - Receiver Tolerance

Summary of Physical Layer Test ParametersChallenge: How do you quickly verify all the compliance requirement of the spec?


Agilent Restricted

http://cp.home.agilent.com/upload/cmc_upload/Ruby_81134A_Angle.jpg

DisplayPort, USB 3.0, SATA, HDMI Compliance Tests Support

49

Time Domain(For Gen1 device)

Frequency Domain(For Gen1 to Gen3)

SATA RXTX Measurement Example with the ENA Option TDR

All necessary parameters

Measured simultaneously

Displayed in one screen

Flexible measurement setup

New Agilent E5071C Option TDR for SATA RXTX and SI

Measurements

Infiniium 90000 Series Oscilloscopes And J-BERT B Provide

Full Coverage For SATA PHY, TSG, OOB and RSG

Including BIST commanding with true

OOB signaling

Fully compliant jitter sources for clean

SSC, true Rj and accurate Sj

Optional N5990A test automation covers

complete electrical layer test

Industry‟s highest true analog bandwidth

Industry‟s lowest oscilloscope noise floor

Lowest jitter measurement floor (<150 fS)

Integrated automation (option 038) covers

PHY, TSG, OOB

Agenda




solution




Challenges

USB-IF Provides USB 3.0 Certification at Intel PIL

PIL is based at Intel OR, Hillsboro

•All Scope vendor solutions are being

evaluated at the PIL

•Agilent has TX and RX test setups in PIL:

DSA91304A and N4903B JBertB soln‟s with

SER option A02•http://www.usb.org/developers/ssusb/ssusb_pil

•PIL opened in Q1’09

http://www.usb.org/developers/ssusb/ssusb_pil

-or- -or-

SuperSpeed Communication – Physical

Layer Focus

Super

Speed

Non-

Super

Speed

Super

Speed

Non-

Super

Speed

TX

TX

RX

RX

TX

RX

TX RXRXTX

Point to point communication, concurrent data flow

Low power mode

Link training

Independent clock domains – both using Spread Spectrum Clocking (SSC)

Transmitter (TX)

• De-emphasis

• Jitter, RJ, TJ

• Eye opening

• SSC

• LFPS

Cable / Channel

• Backward compatible

• EMI requirements

• Signal integrity requirements

Receiver (RX)

• Equalization

• Clock recovery

• Re-timing (SSC)

• sensitivity

-or-

Super

Speed

Non-

Super

Speed

RX

TX

TX

RX

-or-

Super

Speed

Non-

Super

Speed

TX

RX

TX

RX

USB 3.0 SS Physical Layer Test Solutions

Trans-

mitter

(TX)

Receiver

(RX)Cable

• Agilent 90000 series Infiniium

Oscilloscopes

• Agilent U7243A USB 3.0

Transmitter Compliance Test

Software

• Agilent E5071C Network

Analyzer and TDR option

• Agilent N4903B J-BERT

with

N4916A

De-emphasis

Signal

Converter

• Agilent 81250A

ParBERT

•

• N5990A Automated Compliance

and Characterization Test Software

Test Adapter

• Agilent U7242A USB 3.0 Test

Fixture

http://cp.home.agilent.com/upload/cmc_upload/USB_fixture_large.jpg

Transmitter test requirements

(TX Far End)

Dec. 2008

Compliance Channels•Compliance Channels are used to test TX and

RX for worst case channel conditions

•Back panel USB route solution

•Channel loss will dominate

•Host 11” of trace

•Device 5” of trace

•3 meter USB 3.0 cable

U7243A USB 3.0 TX Compliance Application

Agilent SW embed vs Intel HW channel

Agenda




solution




Challenges


USB 3.0 Technical

Review

. 2009

Turn on loopback by sending LFPS and required training sequences

The receiver stress pattern is BDAT with SKPs inserted as described in the

standard.

The pattern checker receives the looped stress pattern BDAT and

recognizes bit errors

After sufficient test time the error counter of the pattern checker is read

Pattern Generator: J-BERT, ParBERT

…stress pattern…training sequences…LFPS

stress pattern…

.

Pattern Generator

1.2.

Pattern Checker

3.Error

Counter

Receiver Test ProcedureExternal Error Counter

Pattern Checker: JBERTB SER or USB Protocol Analyzer

or Ellisys USB Explorer,

Dec. 2008

Compliance Channels•Compliance Channels are used to test TX and

RX for worst case channel conditions

•Back panel USB route solution

•Channel loss will dominate

•Host 11” of trace

•Device 5” of trace

•3 meter USB 3.0 cableStress signal to test Device Rx

Stress signal to test Host Rx

USB 3.0 Technical Review

. 2009

SuperSpeed Receiver Test Calibration and

compliance channels

Device compliance channel setup

Host compliance channel setup

SuperSpeed Receiver Test Calibration and

compliance channels

USB 3.0 PHY Rx Electrical Test Specification

Key details to note in latest draft

RX compliance calibration and testing performed at end of the channel

Channel definition of 3 meter cable plus 5” trace for host and 11” trace

for Device

Separate calibrations performed for device and host testing with specific

device or host test fixtures

Device Rx eye calibration set to 145mVpp

Host Rx eye calibration set to 180mVpp

Addition compliance Pj test points defined at 10Mhz, 20Mhz and 33Mhz

TX testing will allow channel embedding

Golden s-parameters selected for embedded test

TX testing requires 1M UI but can be captured over 4 acquisitions

USB 3.0 Technical

Review

. 2009

Cable and Connectors Compliance

• Time Domain Measurements• Mated Connector Impedance

• Cable Electrical Performance

• Characteristic Impedance

• Intra-pair Skew

• Near-End Crosstalk between SuperSpeed Pairs*1

• Frequency Domain Measurements• Differential Insertion Loss

• Differential Near-End Crosstalk between SuperSpeed Pairs

• Differential Crosstalk Between D+/D- and SuperSpeed Pairs

• Differential-to-Common-Mode Conversion

E5071C ENA Series + opt. TDR

DisplayPort, USB 3.0, SATA, HDMI Compliance Tests Support

Cable and Connectors Compliance

- New Agilent E5071C Option TDR

All necessary parameters

Measured simultaneously

Displayed in one screen

Flexible measurement setup

Example of USB 3.0 Cable Measured with the ENA Option TDR

Summary

• Agilent is a key contributor in various technologies and

standards over the years.

• New test and interoperability challenges exist at 5Gb/s and

speed beyond.

• Agilent understands the test requirement and ensure tools are

available for physical and protocol layer validation.

• Agilent provides complete and automated Solutions to help

you optimize your compliance verification, assess functional

timing and debug areas of concern.

• InfiniiSim “Compliance Channel” Emulation without requiring

the physical reference channel. (Gen3i CIC Channel in SATA)

• Leading solution adapted by test labs world wide


Agilent Restricted

Senior Project Manager Agilent Technologies...March 2011 Francis Liu 劉宗琪Senior Project Manager...

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