SEMICONDUCTOR RESEARCH CORPORATION 2002 · Conexant Systems, Inc. Eastman Kodak Company IBM Corp....

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2002 ANNUAL REPORT SEMICONDUCTOR RESEARCH CORPORATION ® CELEBRATING 20 YEARS

Transcript of SEMICONDUCTOR RESEARCH CORPORATION 2002 · Conexant Systems, Inc. Eastman Kodak Company IBM Corp....

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2002ANNUAL REPORT

S E M I C O N D U C T O R R E S E A R C H C O R P O R A T I O N ®

C E L E B R A T I N G 2 0 Y E A R S

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MEMBERSAdvanced Micro Devices, Inc.Agere Systems (formerly Lucent)Chartered Semiconductor Manufacturing Conexant Systems, Inc.Eastman Kodak CompanyIBM Corp.Intel Corp.LSI Logic Corp.Motorola, Inc.National Semiconductor Corp.Texas Instruments, Inc.UMC Group

SCIENCE AREA MEMBERSAxcelis Technologies Cadence Design Systems, Inc.Mentor Graphics Corp.Novellus Systems, Inc.Shipley CompanySynopsys, Inc.Ultratech Stepper, Inc.

ADJUNCT MEMBERSHewlett-Packard Company

ASSOCIATE MEMBERThe MITRE Corp.

AFFILIATE MEMBERSCoventor, Inc.Integrated Systems Engineering, Inc.Mission Research Corp.Numerical Technologies, Inc.PDF Solutions, Inc.SILVACO InternationalTessera Technologies, Inc.Torrex Equipment Corp.Ziptronix, Inc.

US GOVERNMENT PARTICIPANTSDARPANational Institute of Standards and TechnologyNational Science Foundation

STRATEGIC SEMICONDUCTORINDUSTRY PARTNERSInternational SEMATECHSemiconductor Industry Association

By 1981, university research in silicon technology hadalmost vanished and industry research was decliningrapidly. By creating Semiconductor ResearchCorporation (SRC) in 1982, industry definedmechanisms permitting cooperation in long-rangeresearch to meet common needs while preservingcompetition. The creation of SRC re-established theimportance of silicon microelectronics research and,over the ensuing two decades, has provided both theknowledge and the appropriately educated scientistsand engineers for continued advancement of theindustry. We are pleased, proud, and congratulate theteam composed of member company personnel,university researchers, and SRC staff for theirsignificant accomplishments during the first 20 years.

C e l e b r a t i n g

20y e a r s

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2002Special Dedication....................................................inside front cover

Message from the President............................................................2-3

Company Profile.................................................................................4-5

Research Contributions..................................................................6-12

Award Recipients................................................................................13

Student Programs..............................................................................14

SRC Education Alliance......................................................................15

Focus Center Research Program......................................................16

Intellectual Property......................................................................17-18

2001 SRC Board of Directors & OCE...............................................19

VisionSemiconductor Research Corporation® (SRC) will provide competitive advantage to its members asthe world’s premier research management consortium in delivering relevant research results andrelevantly educated technical talent.

MissionSRC’s mission is to cost-effectively exceed members’ expectations by delivering:

• Managed, innovative, semiconductor technology research responsive to members' needs andguided by the International Technology Roadmap for Semiconductors (ITRS), focusing onuniversities

• Relevantly educated university graduates with high rate of placement in member companies • Global scope, encompassing membership, performer base, government leveraging and

consortial relationships • Capability to operate in multiple modes distinguished by time horizon, research scope,

management style, membership and organizational structures • Complementary structuring and coordination of research programs to maximize overall research

coverage at minimum cost • Timely transfer of research results • Collaboration to enhance commercialization and leveraged research

Table of Contents

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Messagefrom thePresidentPresident

Twenty years ago, the SemiconductorIndustry Association (SIA) convened anextraordinary group of visionaries whoclearly understood that innovationcreates competitive advantage andpropels every company in our industryforward.

These industry leaders also realized that researchfosters innovation, yet silicon research at the nation'suniversities was virtually non-existent. No singlecompany could afford to focus sufficient universityattention on silicon technology to meet the industry’ssilicon research needs.

Semiconductor Research Corporation was their solution,conceived and established to address this researchdilemma through collaborative fundamental research. Indoing this through universities, SRC also would help fillthe industry's need for more relevantly educatedstudents, who could immediately bring their universityresearch experience and familiarity with the industry'sneeds into the workplace and quickly becomeproductive employees.

SRC was incorporated in February 1982. I was hired asthe Executive Director a few months later andoperations began on May 1, 1982. Research TrianglePark was chosen as the permanent site because of itssetting among major research universities and itssupportive state government. We were up-and-runningin Research Triangle Park by September 1982 with 11charter industry members. Our first two employees,Richard Alberts and Robert Burger were hired, and weheld our first Technical Advisory Board meeting. SRC'sfirst request for proposals was issued, and in November,Hewlett Packard became our first recruited membercompany. Centers of Excellence were established inMicrosciences and Technology at Cornell, in ComputerAided Design at the University of California at Berkeley,and in Systems and Architecture at Carnegie Mellon; fiveadditional awards were made from 166 proposalsresulting from our first request for proposals by year'send.

In 1983, SRC's membership grew to 24 companies, itsfirst patent was issued, and 50 additional researchcontracts were initiated, involving 30 universities, 100faculty and 125 graduate students.

The basic foundation for SRC was firmly established bythe end of 1983, and SRC was already making animpact. During the next several years, we establishedrelationships with the National Science Foundation andthe National Security Agency. Erich Bloch, our first boardchair, Bob Burger and I recognized the need for aconsortium-based development effort for the industrythat eventually was formed and located in Austin, Texas.Bob Burger suggested the name for this newconsortium: SEMATECH.

I "double-hatted" as Managing Director of SEMATECHduring its first year. The focus at that time was to securecongressional support for the government's role in thisnew venture. Working closely with Clark McFadden,SRC’s current corporate attorney, and companyrepresentatives, a strategy to secure the support ofCongress was developed and carried out. Austin, Texas,was selected as the site for SEMATECH, and a budgetwas also created to support university Centers ofExcellence at U.S. universities. These Centers wouldconduct research supportive of SEMATECH's newmission. SRC was selected to manage these Centers,which contributed valuable research efforts for about 10years, after which they were phased out due to changesin SEMATECH's funding sources.

In the early years of SRC, our management teambelieved strongly that we needed to structure researchroadmaps to guide our research activity. Accordingly, weput into place a series of roadmaps which eventually,with the support and guidance of technical experts fromother members, evolved into the present-dayInternational Roadmap for Semiconductors (ITRS) thatis managed by the SIA today.

Our first TECHCON was held in Atlanta, Georgia, in 1988.Our seventh TECHCON will be held in Dallas, Texas in2003. This conference features technical paperspresented by students, poster sessions by students, andrecruiting events and presentations by industry leaders.The keynote address for TECHCON 2000 was given by

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Craig Barrett, CEO of Intel Corporation. The 2003TECHCON keynote address will be given by Paul Horn,Senior VP of Research for IBM. TECHCON has beencompared by our members to the best technicalconferences. Additionally, it offers our members a goodopportunity to connect with our graduate students aspotential employees.

New levels and models of cooperation with the federalgovernment have highlighted the past decade. TheNational Science Foundation and SRC announced itsfirst joint Engineering Research Center at the Universityof Arizona. DARPA and SRC have co-funded theLithography Network for over six years. The Focus CenterResearch Program was conceived by the SIA, with SRCbeing asked to manage it through a new subsidiary,called the Microelectronics Advanced ResearchCorporation (MARCO). Despite a dramatic economicdownturn during the last few years, high satisfactionwith the Focus Center program has led to its expansionand additional funding by US Department of Defenseand DARPA.

As the integrated circuit industry neared the millennium,its structure began to change, becoming moresegmented and global. SRC kept up with the trendtoward globalization by welcoming new internationalmembers, like UMC in Taiwan, and initiating newmembership recruiting efforts for suppliers and otherrelated companies. We also responded to industrychanges by offering more customized researchprograms, new participation and membership options,and new approaches to managing intellectual property.We have also increased our collaboration with otherconsortia, such as STARC of Japan and InternationalSMT (formerly SEMATECH).

International research cooperation is critical to SRC'sfuture. The industry relies on SRC to address theresearch needs outlined in the ITRS. The growing gapbetween the estimated cost of ITRS research needs andthe research actually funded has reached more than US$400 million per year. Factoring the redundancy ofresearch conducted around the world, combined withinaccessibility due to geographic or language barriers,the gap actually rises for any one region, such as theU.S., to between US $700 and $800 million dollars.

To help address this gap, SRC must grow. We mustrecruit more new members from the diverse segmentsof the industry. This requires us to continue to enhance

our comprehensive and compelling Value Proposition.We must establish SRC's presence in new geographiclocations and expand our relationships withinternational universities, governments and consortia.Globalization in all aspects of SRC's activities, frommembership to university research labs, will helpprovide graduates in the regions where they are neededand will also help to reduce the research funding gap.

In looking to the future, SRC must strive to establishresearch programs that are aimed at critical challengesidentified in the ITRS as well as to anticipate memberneeds that may be beyond or outside the ITRS and thatare suitable for the university research environment. Wemust also seek to balance research efforts that addresscommon as well as diverse needs of members. Ourresearch scope must be expanded to address new andemerging needs that include areas such as integratedoptoelectronics, ultra-low power systems, embeddedsoftware and innovative patterning techniques.

As we globalize, we must put into place global studentprograms to address broad technical talent needs inregions where members have a strong presence. Inparallel, we need to strengthen our undergraduate andmaster's programs to create a pipeline for the technicaltalent pool.

SRC has, in effect, created a virtual and geographicallydiverse university-based research laboratory in theUnited States in the last 20 years. Our task now is toglobalize that virtual research laboratory to enhanceresearch capability and best serve member needs.

The integrated circuit industry is changing. Variousindustry segments will continue to adapt and change asthe industry adjusts to changing markets and economicconditions. SRC must continually seek to adapt itsbusiness strategies, operational practices, and memberparticipation structure to meet these changing needsand seek to leverage the new opportunities that arepresented. In doing this, we always seek to maximizevalue to our members by strengthening corecompetencies, increasing financial leverage for ourmembers, and optimizing our Value Proposition.

Overall, SRC is committed to being agile, vital anddynamic as it responds to the continuously changingneeds of the industry. Our vision is to be the world'spremier research management consortium.

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now has members and university researchprograms in countries around the world. Inorder to enable an effective approach fordelivering value to our member companies,research results and publication are posted onthe secured web site for member access. In2002, a record number of publications anddeliverable results were placed on the site,along with patents and software to which themembers have royalty-free access. Also in2002, the site was used for real-timecollaboration as well as threaded discussions.

Through the combined efforts of the Board ofDirectors, our various technical advisory

boards and SRC staff, our researchstrategy and operational plans are

continually refined to producevalue, satisfying the membersas evidenced by the annualmember satisfaction survey.The survey addresses all four

dimensions of the ValueProposition—creation, delivery,

extraction, and advocacy—that aremade available via SRC's primary

products: Research Results, RelevantlyEducated Talent, Integrated UniversityResearch Capability, and Networking.

We have continued to hone the processes andtools associated with the delivery of SRC valueto our member companies. Also, we havecontinued to refine the mechanisms andsupport that are provided to facilitate theextraction of maximum value in the most cost-effective manner for our member companies,as evidenced by the increased use ofelectronic meetings utilizing both the SRC website and "net-meeting" software. Finally, wework with the representatives of our membercompanies on the Board of Directors and thevarious advisory boards to continuouslyrevitalize our products, programs, processesand systems to enhance value for ourmembers.

In 2002, SemiconductorResearch Corporation celebratedits 20th anniversary. Over thepast 20 years the industry has

invested nearly US $600 million through SRC,and well over 3,000 scientists and engineershave received advanced degrees from SRCsupported programs.

SRC’s core directed-research program has acontinuously evolving portfolio of over350 projects that are currentlytargeted at the full spectrum ofsemiconductor technologies,including: circuit and systemdesign; design tools; test andtestability; materials andprocesses; packaging andinterconnect; advancedpatterning; mixed signal/analogtechnologies; metrology;environmental safety and health; andadvanced device and modeling andsimulation. We have described significantresults from the research efforts in the year2002 ((sseeee ppaaggeess 66-1122))..

MARCO, an SRC subsidiary, currently has fourFocus Center Research Centers conductingcomplementary research projects that aredescribed in the MARCO annual report.

SRC continued to enhance student programsin its core program to ensure development ofthe highest quality talent for our membercompanies. In addition, the SRC EducationAlliance, described on ppaaggee 1144,, addresses theneed for developing undergraduate talentrelevant to the industry.

Because the semiconductor industry and itsInternational Technology Roadmap (ITRS) forSemiconductors have become global, SRC

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Year 2002 was another difficult year for theindustry and for SRC. The marketplace hasundergone significant changes that have, in turn,changed the complexion of the industry, researchneeds, and the research budgets. As a result,preparation for 2003 presented even greaterchallenges to maintain critical research programsand to maintain SRC’s reputation as a preferredsponsor of university research. Several examples ofthe dynamic nature of our business and the valuethat the community of our consortium has broughtforth in the year 2002 are presented in this report.This abbreviated report can only describe some ofthe key accomplishments, major initiatives, andimportant events of 2002 that demonstrate thevalue, strength, and agility of the consortium, forexample:

• Our Executive Technical Advisory Board (ETAB)continued to provide high-leveltechnical/strategic directions to shape theresearch portfolio. The ETAB also developed thearchitecture for a modified Science Areastructure, which will be implemented in 2004.

• The SRC Board of Directors approved severalStrategic Initiatives that impact SRC’s businessmodel and practices that would help SRC toenhance its value to all segments of the industry.

•Professors Supriyo Datta and Mark Lundstrom ofPurdue University were the recipients of theTechnical Excellence Award for their work in thearea "Device Physics and Simulation ofNanoscale MOSFETs."

• Well over 100 Fellows, Scholars, industryrepresentatives, and SRC staff attended the2002 Graduate Fellowship Program AnnualConference in September. The keynote addresswas delivered by Tom Engibous, TexasInstruments Chairman and CEO. Ninety-fivepercent of attendees rated the conferencegreater than four on a five-point scale.

• Ten SRC-sponsored U.S. and foreign patents wereissued, bringing the total portfolio of SRC-licensedpatents to 195, all of which can now be queriedby members on the SRC web site.

There were many other noteworthy 2002accomplishments in other areas not described inthis abbreviated report, such as:

• Member companies assigned Industrial Liaisonsto work with researchers on a record percentageof tasks, a strong indicator of the ongoing effortsto derive value from the technology and to mentorthe students toward a rewarding career in theindustry.

• SRC successfully launched an e-meeting initiativeto better enable remote-attendance at meetingsby utilizing state-of-the-art teleconferencing andweb-based solutions. Not only has this strategyprovided a means to reduce travel costs but alsoto significantly enhance participation andcollaboration.

• SRC continued to expand the scope of its web sitecapabilities by providing integrated, simple-to-useweb-based forms to better collect and updateinformation. These included online submission ofpublications descriptions and full documents,software descriptions, student information andfull resumes, web site user information updatesand the first deployment of online eventregistration with e-commerce secured credit-cardtransactions.

•In 2002, SRC clearly saw the benefits of web-based efforts. The SRC web-site saw a 22%increase in logins and a 48% increase in page hitsover 2001 usage data. The number of individualswithin the SRC community that logged into thesite in 2002 increased to over 3,100 in 2002 -- anincrease of nearly 20% over 2001.

Company Profile

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Formidable scientific and technology challenges must beovercome to design and produce integrated circuits andsystems that sustain the traditional exponentialimprovements in performance as characteristic features scalefrom tens of nanometers to angstroms. SemiconductorResearch Corporation operates a comprehensive researchprogram at approximately 70 universities involving over 250faculty and 1,000 graduate students that provides innovativesolutions to industry technology challenges. Summarizedbelow are some of the many contributions made by SRCresearch teams in 2002 to enable the continuedadvancement of semiconductor technology.

The Road to Ul t imate CMOSDevices

Bulk CMOS DevicesScaling of the MOSFET to its ultimate limit requires theintroduction of materials that represent a significantdeparture from silicon and silicon oxides that have served sowell to date. The SRC/ISMT Front End Processes ResearchCenter has identified promising candidate high-K gatedielectric materials, explored their properties, andconducted process-related studies of the oxide interfaciallayer that must be minimized to most aggressively scale thedielectric Equivalent Oxide Thickness (EOT). Figure 1 showsan x-ray diffraction analysis of a chemical vapor depositedhafnium oxy-nitride gate dielectric film that can sustain up to950°C annealing without crystallization and that exhibitsthermal stability superior to hafnium-oxide film.

Modeling and simulation studies of the transistor high-Kgate stack have identified correlations between the d-stateenergies of the transition metal atoms and the electronicstructure of transition metal oxide alloys. This has led to afundamental understanding of the performance of transition

metal alloys as (a) high-K gate dielectrics, and (b) dual metalgate electrodes in advanced CMOS devices. The research isalso providing a systematic methodology for atomic scalematerials engineering of transition metal oxides thatsupports the selection of potential successful candidatematerials.

Research has shown that by applying stacked layers of Ni/Ptto form a Germanosilicide, contact resistance can beeffectively reduced and good thermal stability can beachieved.

Advanced metal gate materials that have also been studiedinclude (a) simple metals and metal alloys, (b) compoundmetals, (TaNx, TaSiNx, Ta-Ru alloy), and (c) metal silicides.Gate electric research has focused on a wide variety ofissues including effective work functions, thermal andchemical stability at metal/dielectric interfaces, processcompatibility, threshold voltage control, interface and bulkfilm characterization, and subsequent device performanceand reliability. Recent results have shown that a Ta-Ru alloyis a very promising candidate for both N-MOS and P-MOSmetal gates because its work function can be readilyadjusted and because it supports process simplification.

Modeling and simulation of the role of dopants on the ONstate current of a device and on OFF state device leakagehas been instrumental in (a) elucidating the role ofdopant/interstitial clusters, {311} crystal lattice orientation,and interaction loops as regulators of interstitialconcentration and hence of diffusivity enhancement, and (b)in elucidating the interactions among these clusters anddefects.

Advanced CMOS DevicesAt least five microelectronics companies, including four SRCmembers, are fabricating and evaluating variations of theFinFET transistor for possible introduction at the 45-nm node.The University of California at Berkeley Team hasdemonstrated a novel FinFET optical spacer process thatprovides the narrowest fin (less than 10nm) with tightparameter control by fabrication of operational p- and n-channel FETs on the same wafer.

Another approach to enhancing MOSFET performance is toutilize strained silicon in the channel to obtain enhancedcarrier mobility. An investigation of mechanisms for electronmobility enhancement at high vertical electric fields in

SRC RESEARCH:Enabling Silicon NEnabling Silicon Nanoelectronicsanoelectronics

FIGURE 1: Analysis of CVD HfOxNy

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Enabling Silicon Nanoelectronicsstrained Si n-MOSFETs has demonstrated that electronmobility at high fields ("surface roughness regime") issignificantly enhanced by strain. This group also found thatat high inversion charge densities, the Coulomb scatteringrelated to the high doping density in the channel (necessaryto be above 1018 /cm3 for bulk devices at sub-45-nm nodes)is screened by the conduction electrons. The observedmobility enhancing result is very significant because itdemonstrates that strain-induced performanceenhancement can be obtained for devices with channeldoping densities as high as 6 x 1018 /cm3.

Parsimonious and accurate circuit-level models for devicesare known as Compact Models, and the SRC research has atradition of developing widely adopted MOSFET CompactModels. A "Surface Potential Approach" has been developedfor Compact Models that is an important new contributionthat both simplifies and accelerates the device simulations.A clever new analytical equation relating surface potential ofthe gate oxide/channel interface to the channel sheetcharge is used to provide an accurate and time-efficientmodel for nano-scale MOSFETs used in circuit simulators.Figure 2 illustrates the high degree of accuracy of this newanalytical solution for surface potential benchmarkedagainst numerical solution. An in-depth evaluation of thismodel by a member company has verified the accuracy,parameter extraction efficiency, and simulation speed-uppossible using this model.

E n a b l i n g W i r e l e s s Te c h n o l o g i e s

SRC wireless research programs spans advanced devices,RF circuit design, system architectures, design tools, andtest strategies. Because of the strategic importance of this

high-growth segment to SRC member companies, SRCestablished in 2002 a cross-disciplinary approach tomanagement of research in all mixed signal technologies,including RF and wireless. This program brings togethermany ongoing research efforts as a focused program andwill result in coming years in many new projects. In onecurrent program, a platform-based radio design approach isbeing developed, allowing the rapid design of multi-protocolwireless receivers for flexible, adaptable digital cell phones.Another program is developing advanced dynamic datashaping algorithms, aimed at multi-rate processing of videodata over bandwidth-limited noisy channels, for use inadvanced personal communication devices. SRCresearchers are breaking new ground in wireless networkingfor a wide range of computing and personal devices withdata rates up to 1 GHz by use of time-space diversity andsophisticated high-rate base-band signal processing. Designand validation of RF and wireless circuits poses enormouschallenges; SRC funds several programs in advanced built-intest methodologies for RF circuits, as well as system-leveldesign tools for studying fundamental algorithms formodulation, signal processing, error control, and dataencoding.

Patterning at the Nanoscale

Current hardware research in patterning technology focuseson non-traditional patterning options for enabling reliableand low-cost advanced mask fabrication, ASIC designtesting, and high volume sub-32 nm patterning applications.In 2002, this initiative explored the feasibility of multi axis e-beams and arrays of scanning probes, micro-mirrors, andmicro inkjet write heads for niche application insertion atand beyond 2010. These efforts strongly couple withcomplementary initiatives in high rate data managementand hardware-software trade-offs. Next GenerationLithography (NGL) related research explores the limits ofExtreme Ultra-Violet (EUV) lithography and the potential forameliorating Electron Projection Lithography (EPL) spacecharge effects. In 2002, exploratory projects in non-lithographic patterning, defect tolerant lithography, directedself-assembly, nanoengineered materials, and thedeterministic positioning of dopant atoms were conducted.The scope of advanced mask research recently expanded toinclude exploring tools for repairing NGL masks andmodeling step-and-flash and immersion mask technologies.

FIGURE 2: Comparison between analytical surface potential model and

numerical solutions

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SRC also maintained its research emphasis ondeveloping novel modeling tools for optimizing advancedmask design.

Imaging materials research is exploring novel families ofresists and optical materials and to develop a firstprinciples understanding of correlations between themolecular structure and patterning performance. Recentresults suggest that novel families of resist materials,such as photo labile dendrimers and block copolymersexhibit potential for 157 nm, NGL, and/or mask-lessapplications. Patterning related modeling researchencompasses molecular models to aid resist and opticsdesign, dynamic models of high aspect ratio patternformation and self-assembled systems, and NGL andpost-NGL pattern transfer simulations. Finally, metrologyresearch addresses the need for novel non-destructivemethods for measuring 3D nanostructures, interfaces,and material properties, including direct monitoring ofacid diffusion during resist processing.

Increasing Factor y Value- AddThrough Resource Management

Factory OperationsA new methodology and software system for dynamicscheduling of preventive maintenance in highlyautomated, 300-mm factories was developed where itdemonstrated in one member's fabrication facility andyielded a 5% improvement in tool availability. In addition,a new methodology for fabrication facility analysis andscheduling was developed that combines a new"Resource Driven" method of scheduling with the original"Job Driven" method. This combination provides a

complete suite of methods and tools to facilitate timely,resource-efficient and accurate tools for scheduling andre-scheduling semiconductor fabrication facilities.Simulation tools resulting from this research will enablefacilities to achieve balanced wafer throughput withdecreased cycle time, provide a more flexible means foradjusting factory output and, thereby, reduce wafer andproduct cost. (See Figure 3.)

Environment al ly BenignManufactur ing

The primary venue for Environmental Safety and Health(ESH) research in SRC is the NSF/SRC EngineeringResearch Center for Environmentally BenignSemiconductor Manufacturing at the University of Arizonain Tucson. Significant progress has been made this yearin the four major areas of research: Back-End Processes,Front-End Processes, Factory Integration, and Patterning.Back-End Process work has included new chemistry foretching low-k dielectrics, novel, low-energy processes fordepositing low-k dielectrics, and work on waste reductionin copper CMP. Front-End process development hasincluded novel dry wafer cleaning processes, novelsurface passivation and selective deposition, and workon etching high-k dielectrics. In Factory Integration,innovative water purification/recycling development andsimulation continues, along with work on integrated ESHimpact assessment processes and technology. Patterningcontinues to explore solvent-less lithography using directpatterning of dielectrics and supercritical CO2 basedprocesses.

Enabling Silicon Nanoelectronics

FIGURE 3: Wafer Fab Scheduling

Disjunctive graph showing a backwardcycle caused by a solution to a specificflow that has been uncovered and can beresolved by the model

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Toward Interconnect and Assembly for the Teraher tz Regime

A new Center for Advanced InterconnectScience and Technology was formed in2002 to develop innovative approaches toameliorate the increasing impact ofinterconnects on integrated circuitperformance. In the new program, thecopper metallization emphasis is on sizeand structure effects that will limit theusefulness of shrinking geometries of metallines. The new program is emphasizing thecritical need for ultra-thin barriers and ultra-low k dielectric that is emphatically evidenced by scaleback of these parameters in the ITRS Interconnect roadmap. Alsoincluded in the Center are new reach-out programs on radical solutions in optical interconnects and a new initiative interahertz interconnects. As an example of the radical approaches being investigated, Figure 4 shows a unique approach tomanufacturing assembly techniques to provide mixed technology capability to insert optical emitters for on-chip opticalinterconnect systems.

In 2002, plasma processing programs havefocused on the bridge between reactor scalemodeling and feature scale modeling. Excitingresults have included new methodologies toinvestigate and visualize harmonic content ofelectron energy distributions and excitation ratesin plasmas commonly used in manufacturingoperations. This capability offers the valuablepossibility for real-time control of plasma systemsbased on optical emission. A snapshot in time ofa dynamic visualization of plasma E fields duringplasma RF excitation is shown in Figure 5. Thisdynamic visualization capability offers majoropportunities to better comprehend the innerworkings of plasma systems.

A constitutive model for eutectic and high-lead(C4) solders, based on a new percolation theory, has been developed to examine damage in high lead solders. This modelincludes the effect of damage developed during fatigue cycling and can be incorporated into an ANSYS finite-element-analytical model of solder joints. The model has been transferred to a member company via a student internship and to twoother member companies. Algorithms for simulating I/O noise in multilayer packages for coupled transmission lines in thepresence of bouncing voltage planes and decoupling capacitors are now available. This work has provided a key enablingcapability for the design of future ASIC products. Better understanding of heat transfer processes has resulted in newpredictive performance evaluation models for two phase heat spreaders, along with design parameters.

SRC's research program in Packaging and Interconnect addresses the difficult challenges of environmentally benign solders(i.e., Pb, Sb, and Bi free packaging materials), the impact of Cu/low-k materials on packaging, thermal dissipation, andimproved underfills for flip-chip on organic substrates. In the longer term beyond 2007, SRC's program is addressing thedifficult challenges of "High frequency die" and "Small, high pad count" through programs in accurate and efficient, full wave

Enabling Silicon Nanoelectronics

FIGURE 4: Magnetic assembly of VCSEL Nanopillsfor Optical Emitters in Photonic Interconnects

FIGURE 5: Plasma Process Models

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electromagnetic field modeling and in novel approaches toglobal interconnect based on microwave free space andguided wave communications techniques.

Constraint -Dr iven DesignMethodologies for Ci rcui ts andSystems

Design Space Exploration refers to the process of specifyinga system architecture that meets a large set of functionalrequirements. The design space must be explored rapidlyand accurately and evaluation of selected technologyoptions must be supported. In 2002, research on a newabstraction algebra has resulted in a prototype system,which uses process algebra models and compileroptimization techniques to optimize system designs,culminating in direct synthesis of the design into the VHDLlanguage. In another research program, nondeterministicfinite automata models are used in transaction-levelspecification of systems, that can be synthesized into cycle-accurate register level representations for synthesis.

Power and energy considerations are of critical importancein all design activities, from specification through circuitdesign and physical implementation. In 2002, importantresults at the circuit design level include an 8 bit, 20 Ms/secanalog to digital converter which operates on a 1.8 voltsupply and consumes only 50 milliwatts. A family of noveldigital logic topologies has been developed which have beenshown to reduce power (relative to conventional static CMOSstructures) by 30% to 60% in certain applications; thesefamilies range from multi-threshold styles, to subthreshholdoperation, to new domino logic architectures, and transistor-ordering schemes.

SRC sponsors extensive research into the effects of crosstalkand coupling, noise tolerance and avoidance, soft errors,logic upsets, and variability. In 2002, new software wasreleased which estimates the substrate current spectrum fordigital logic blocks; these estimates are used in librarycharacterization to calculate bounds on noise andperformance over fabrication and environmental parameters.Another recently completed program has produced highperformance timing analysis algorithms which account fordevice variability, based on actual process statistics.

Recent results on interconnect issues in design includecurrent mode signaling techniques, which exhibit

significantly reduced susceptibility to signal cross-couplingand waveform degradation, compared to conventionalvoltage mode schemes with repeaters. In another project,differential signaling is used for chip-to-chip connections toreduce coupling and power consumption dramatically,requiring only one or two additional wires rather thandoubling the number of wires per bit.

Research focused on the use of advanced devices in designcurrently addresses diverse issues such as application ofsilicon-germanium devices, silicon on insulator technologies,MEMS devices, and quantum dot devices in novel circuitapplications. A revolutionary architecture for quantumcellular automata memory structures is under study,promising storage densities in the range of terabytes persquare centimeter. Other programs study side effects ofadvanced technologies, such as the effect of gate tunnelingcurrent on digital logic structures. In one program, a widevariety of logic structures is being studied via simulation todetermine the sensitivity of performance parameters andpower consumption to gate leakage currents. Another criticalside effect of advanced system on chip technologies is theelectrostatic discharge susceptibility (ESD) of integratedradio frequency components. Novel ESD structures suitablefor antenna terminals of 10 GHz RF receivers weredeveloped this year, employing parts of the protectionstructure as passive components in the RF circuitry.

Design Tools for the Deep Submicron Regime

In place and route, SRC investigators have devised a methodfor generating synthetic examples with prescribedcharacteristics having optimal wire length; for the first time,place and route algorithms can be measured against howclose they come to optimality, as well as against each other.

Enabling Silicon Nanoelectronics

FIGURE 6:Placement

Examples withKnown Optimalwire length pro-vide a standardfor evaluatingplacement ofalgorithims.

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Partitioning algorithms two orders of magnitude faster thanprevious techniques can quickly partition large placeddesigns so that selected design metrics (area, powerdissipation, number of cells, number of timing violations) arebalanced across partitions. As the effects of scaling becomemore important for tools, researchers have developed anefficient integrated RCL interconnect extraction, simulation,and optimization flow which reduces complexity withoutlosing accuracy and stability; this in turn facilitatesaggressive optimizations based on realistic circuit modelsand accurate simulation methods. An efficient substrateresistance matrix extraction tool, integrated with a 3D layoutextractor, can update a net list to capture the effects ofsubstrate coupling. With the need for early estimation ofdesign characteristics becoming more essential, SRCinvestigators have developed a framework to estimate thebest achievable speed for a given design and itscorresponding area cost at an early stage, obtaining goodestimates of achievable performance without performingdetailed design. And to address mixed-signal designs, ascalable substrate noise coupling macro-model has beenincorporated into a commercial framework to performsubstrate noise coupling analysis during schematic designand after post-layout extraction, assisting with overall floorplanning and placement, and shielding of noise sensitiveblocks.

Estimates persist that more than half the resources spent ingetting designs to market are invested in verification. SRCmembers rely on SRC-sponsored work on formal verificationtools for detecting errors and verifying industrial designs. Ahybrid constraint solving framework produced by SRCresearchers handles various levels of circuit abstractionautomatically, targets functional test generation as well asformal verification, and incorporates word-level techniquesand linear integer arithmetic techniques into an efficientsolver. Addressing the state explosion problem which isexacerbated by both larger and more complex designs, anew refinement quickly discards uninteresting parts of thestate space and significantly outperforms previoustechniques. Processor-specific verification advances includetools which are expressive enough to model and verifydiverse systems such as out-of-order processor cores,pipelined processors, complex load-store units fromindustrial microprocessors, and a cache coherence protocol.A technique for automatically abstracting large scalesequential hardware designs has been used to effectively

generate counterexamples to correctness assertions, a keyto detecting and correcting errors. All of these techniquesare in use by SRC member companies.

Test and design for testability also continue to be challengesexacerbated by the move to larger, more heterogeneousdesigns where crosstalk and signal integrity effects play anincreasing role in producing defects. Researchers havedeveloped an efficient approach to testing on-chip ADCs andDACs which reuses existing digital processing units togenerate input stimuli. A comprehensive analysis frameworkfor analyzing and generating tests for switch failures indynamic logic due to multiple sources of noise includingcoupling, charge-sharing and leakage has also beendeveloped. And several efforts are addressing testgeneration and fault simulation for defect aggravatedcrosstalk. SRC members have used test time reductiontechniques to significantly reduce tester time on a number ofparts, resulting in lower test costs. Members have also useduniversity-developed ATPG patterns on industrial parts,finding them to have superior defect detection capabilitieswhen compared to standard commercial ATPG patterns.With an increase in research in analog test, investigatorshave provided promising jitter measurements for PLLs andVCOs. All of this work provides capabilities to membercompanies that are not available commercially.

Explor ing Future Tec hnologies

As CMOS approaches several fundamental scaling limits andthe electronics create a power dissipation nightmare, SRCresearch is creating options to enable a gradual paradigmshift based on new approaches to information processing.Research approaches range from new FET-like structuresthat will preserve design methodologies and systemsarchitectures to completely new approaches to representingthe logic state and information processing. For example,novel FET concepts, such as MOTT Transistors, are beingexplored to sustain FET device architecture for high density,high performance and low power scaling. Conversely, a newphase-based logic technology amenable for implementationby cellular nonlinear networks is under investigation. Thisapproach may permit low-energy, capacitive couplingbetween cells and thereby ultra-low-power logic. Anotherapproach explores highly dense memory structures (floatingback-gate and multi-bit storage quantum-dot memory) aselements integrable with CMOS to perform memory-based

Enabling Silicon Nanoelectronics

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logic. To make use of these emerging devices and logicarchitectures, new systems architectural approaches arebeing explored as alternatives to von Neumann computing.Examples include cellular nonlinear networks, Bio-InspiredComputing and Quantum Computing. An integratedapproach is being pursued to novel information processingschemes leading to building a portfolio of basic conceptsincluding implementations of self-assembly, molecularelectronics, magnetic semiconductors and solid-state qubitsfor quantum computing.

SRC has also begun to explore applications-driven emergingtechnologies. Research is underway to provideunderstanding of the materials and device characteristics of

organic transistors on threads for computational fabric,silicon nano particle devices and novel models for E-textilemanagement. These technologies could have an impact onapplications requiring large area and flex electronics. Forhigh performance computing and emerging technologies, weare also exploring smart embedded software concepts suchas context-aware computing. The objective of this researcheffort is to apply knowledge and models from the cognitiveand social sciences to create context-aware architecturesthat when coupled with sensors, MEMs and embeddedcomputational devices/software (e.g., speech and imagerecognition) will provide enhanced information-humaninterface. Figure 7 captures the sense of impendingchanges in the silicon highway.

Enabling Silicon Nanoelectronics

FIGURE 7: Changing Vectors of the Semiconductor Industry

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AwardRRecipientsecipientsTec hnical Excel lence Award

Professors Supriyo Dattaand Mark Lundstrom ofPurdue University are therecipients of the TechnicalExcellence Award for theirwork in the area "DevicePhysics and Simulation ofNanoscale MOSFETs."Funding for Dr.

Lundstrom's work titled "Physics & Modeling ofHeterostructure Semiconductor Devices" began in 1983, Dr. Datta joined the research team three years later in 1986. Duringthis 20th anniversary year, we are honored to recognize these professors who have made multiple contributions to thesemiconductor industry during the past 20 years.

This award is given to researchers who, over a period of years, have demonstrated creative, consistent contributions to the fieldof semiconductor research, who are ground-breakers and leaders in their fields, and who are regarded as model collaboratorswith their colleagues in the SRC member community.

DATTA LUNDSTROM

Mahboob Khan Award

The Mahboob Khan Outstanding Mentor Award, named in memory of a long-time SRC Industrial Liaison program advocate fromAdvanced Micro Devices, is presented each year to those individuals who have made significant contributions in their roles asIndustrial Liaisons. Recipients represent “ideal mentors” whose commitment more than enhances the SRC research program.The 2002 award recipients were:

Aristot le Award

The 2002 Aristotle Award was presented toProfessor Alberto Sangiovanni-VVincentelli,University of California/Berkeley. TheAristotle Award recognizes SRC-supportedfaculty whose deep commitment to theeducational experience of SRC studentshas had a profound and continuing impactfor SRC members over a long period oftime.

SANGIOVANNI-VINCENTELLI

Doug Garrity of Motorola has worked with Dr. David Allstot'sresearch team at the University of Washington in the area ofAnalog to Digital Converters. According to Dr. Allstot, "Doug'sexperience enables him to identify marginal ideas in favor ofmore promising approaches, thus his mentoring allowed SRCFellow Douglas Beck to focus on an important researchcontribution rather than wasting valuable time and resourceson incremental ideas."

Ram Kumar Krishnamurthy of Intel, an expert in "HighPerformance Digital Design," has worked with Dr. VojinOklobzija at the University of California/Davis. He has been"instrumental in guiding research toward the needs of theindustry, by providing opportunities for graduate students andprofessors to spend time at Intel."

James Libous of IBM has been an advocate within the SRCcommunity for work in Advanced Packaging being done by Dr.Madhavan Swaminathan's team at Georgia Tech. Dr. Libouswas instrumental in arranging summer industrial experiencesfor several students, exposing them to the industrialenvironment then remaining in contact with the students uponreturn to the academic community.

Jeffrey Parkhurst of Intel, an industry expert in the field ofCircuit Design, has been a long-time advocate of the IndustrialLiaison Program within the industry, taking a proactive role inrecruiting new liaisons within Intel. His work with theUniversities of California at Berkeley and Davis has provided abeneficial link between professors and students at both ofthese universities and Intel. Jeff has provided leadership in theidentification of top Ph.D. research projects that address theneeds of the industrial community.

Terry Sparks of Motorola has worked on the AlternativeChemistries for Dielectric Etch project at MIT for the last fiveyears. Three SRC students have completed five summerinternships at Motorola where they interacted with Terry on a dailybasis. An example of his impact on one student can be found inSRC Fellow Simon Karecki's thesis preface, in which Dr. Kareckithanked Terry, "who taught me all I know about plasma etch."

Charles Szmanda of the Shipley Company has worked with Dr.Paul Nealey's research group in the development ofPhotoresist Materials and Processes at the University ofWisconsin for the past five years. His understanding of the roleof components of chemically amplified resist systems in resistdissolution and pattern development resulted in SRC FellowAdam Pawloski's thesis research.

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StudentProgramsPrograms

Over 1,100 students participated in SRC-fundedresearch in 2002. Of the graduates, about 70% went towork for SRC member organizations or areundergraduate or master's students continuing tohigher degrees, further strengthening the links withinthe SRC community. Other 2002 accomplishmentsincluded:

• Two new core Fellowships, four new Company-NamedFellowships and one new International Fellowshipwere awarded through the Graduate FellowshipProgram to bring the number of fellowships at thebeginning of the 2002 fall term to 51.

Winners of Outstanding Research Presentation Awards at the2002 Graduate Fellowship Program Annual Conference were(left to right) AMD/SRC Fellow Ritwick Chatterjee,Massachusettes Institute of Technology; International FellowLuca Daniel, University of California at Berkeley; and IBM/SRCFellow Eric Pop, Stanford University. Research presentationswere judged in three categories: Design, Material and ProcessSciences, and Nanostructure and Integration Sciences.

Nearly 70% of students completingdegrees under SRC-funded research in2002 joined the SRC community or arecontinuing to higher degrees.

2002 SRC STUDENT HIRING STATISTICS

Non-members28%

Left Industry2%

Universities8%

Member Companies40%

Government2%

• Eight new Master's Scholarships were awarded,including three new Company-Named for a total of 15at the beginning of the 2002 Fall term. Two of the newscholarships were awarded to graduates of theUndergraduate Research Assistants Program.

• Well over 100 Fellows, Scholars, industryrepresentatives, and SRC staff attended the 2002Graduate Fellowship Program Annual Conference inSeptember. The keynote address was delivered byTom Engibous, Texas Instruments Chairman and CEO.Ninty-five percent of attendees rated the conferencegreater than four on a five-point scale.

• Over 500 resumes were published on the SRC Website. A new process was developed by SRC to allowstudents to update their database information andsubmit their resumes via the SRC Web site, therebysignificantly reducing barriers for students.

• The annual Student Programs Brochure waspublished to provide student information for membersand prospective Fellows and Scholars. A copy may beobtained by contacting SRC Student Relations at theSRC corporate address.

• The first Simon Karecki Award was made from theSimon Karecki Endowment to Casey Finstad at theUniversity of Arizona. This award recognizesoutstanding student performance through theSRC/NSF Center for Environmentally BenignSemiconductor Manufacturing, centered at theUniversity of Arizona.

ContinuingBS/MS

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The number of students participating in MOSIS in YearTwo was well over 5,000, surpassing the 1998 level(1998 was the last year of government funding forMOSIS and the benchmark for current metrics). MOSISalso showed a continued rise in the number of classesand class projects. Responding to a request from theUEP Advisory Board, MOSIS has provided informationabout class projects and university contacts via theSRCEA Web site. MOSIS continues its efforts to includesmaller schools in the MOSIS educational service, tobuild more extensive libraries for use by students and toexplore options to make fabrication by MOSIS moreattractive for SRC-funded graduate students.

With SIA funding for the Undergraduate EngineeringPrograms ending in June 2003, SRC and SRCEA haveproposed that oversight of the programs should stay inthe SRCEA with funding from other sources. To thatend, SRC and SRCEA continue to explore other fundingoptions for these programs.

SRC EducationAllianceAlliance

The SRC Education Alliance (SRCEA) is a wholly-ownedsubsidiary of the Semiconductor Research Corporation.The SRCEA is a non-profit (501(c)3) charitablefoundation with strong ties to the SRC research andstudent programs. The Undergraduate EngineeringPrograms and the Simon Karecki Endowment aremanaged under the SRCEA.

The Undergraduate Engineering Programs (UEP) weresuccessfully launched in July 2000 with the secondyear completing in June 2002. The UEP includes theUndergraduate Research Assistants (URA) and MOSIS.The SIA Board member companies committed tofunding for the UEP for three years through June 2003.

Undergraduate Engineering Programs Year Two:Assessment and Recommendations was published inOctober 2002 and is on the SRCEA Web site atsrcea.src.org/programs/default.asp.

Eighty-two students participated in the URA Program inYear Two. Retention in the program remained high with89% either continuing from the academic year to thesummer term or graduating. The program hasgraduated a total of 34 students; 56% have eitherjoined sponsoring companies or continued to graduatestudy. The diversity of the student population remainedhigh, with about one-third being female and about 10%in under-represented minority categories. GPA alsoremained relatively high at 3.63 for a representativesample.

Advanced Micro Devices, Inc.

Agere Systems

Analog Devices, Inc.

Conexant Systems, Inc.

Cypress Semiconductor Corp.

IBM Corp.

Intel Corp.

Intersil Corp.

LSI Logic Corp.

MICRON Technology, Inc.

Motorola, Inc.,

National Semiconductor Corp.

Texas Instruments, Inc.

Xilinx, Inc.

URA student Jose Rangle (foreground) and SRC FellowMatt Pinnow work together in Professor Grant Willson'sresearch lab at the University of Texas/Austin.

U N D E R G R A D U AT E E N G I N E E R I N G P R O G R A M S P O N S O R I N G C O M PA N I E S

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Focus Center RResearcesearch Programh ProgramDESIGN AND TEST

The University of California at Berkeley is the lead university for theDesign and Test Focus Center (Gigascale Silicon Research Center--GSRC). Professor Jan Rabaey is the center’s director. The Designand Test Center’s research agenda addresses concepts such ascomponent/communication-based design, constructive fabrics,fully programmable systems, calibration of achievable design,

validation, power and energy. With increased complexity of integrated circuits andrelentless competitive pressures of time-to-market, the GSRC agenda is focusedon the discovery of software design tools, circuit families, libraries and theapproaches used to integrate a design process.

UC/BERKELEYCarnegie Mellon University Mass. Institute of TechnologyPennsylvania State Princeton UniversityPurdue University Stanford University UCLAUC/San Diego UC/Santa BarbaraUC/Santa Cruz University of Michigan Univ. of Texas / Austin University of Wisconsin

GEORGIA TECHMass. Institute of TechnologyRennselaer Polytechnic

InstituteStanford UniversityUniv. of Albany UCLA

MITCornell UniversityPrinceton UniversityPurdue UniversityStanford University University of AlbanyUCLAUC / BerkeleyUniv. of Texas / AustinUniversity of Virginia

CMUColumbia UniversityCornell UniversityMass. Institute of TechnologyPrinceton UniversityStanford UniversityUC /BerkeleyUniversity of Illinois at

Urbana-ChampaignUniversity of MichiganUniversity of Washington

INTERCONNECTThe leadership for the Interconnect Focus Center (IFC) is based atthe Georgia Institute of Technology. Professor James Meindl is thefocus center director. The Center’s research teams examine sixmajor tasks: System architecture, physical design tools, novelcommunications mechanisms, chip to module interconnects,materials/processing/predictive modeling and metrology. With

aggressive scaling, interconnect becomes the dominant source of delay andenergy consumption. The IFC looks to discover and invent new interconnectsolutions that will meet or exceed ITRS projections.

MATERIALS, STRUCTURES & DEVICESThe Massachusetts Institute of Technology was designated as thelead university for the Materials, Structures and Devices FocusCenter (MSD). Professor Dimitri Antoniadis is the Focus Centerdirector. This Center will research sub-10-nanometer silicon-basedFETS, silicon-based quantum-effect devices, molecular and organicsemiconductor electronics, nanotube electronics and modeling &

simulation. Maintaining the historical CMOS performance trend requires newmaterials and structures by 2008-2010, or earlier, if current bulk-Si data do notimprove significantly. The MSD center explores the most promising path for deviceevolution in the next two to three decades.

CIRCUITS, SYSTEMS & SOFTWAREThe Focus Center team for Circuits, Systems and Software (C2S2)is led by the Carnegie Mellon University. Professor Rob Rutenbaris the director. The center’s research will focus on the analysis andsynthesis of analog and analog/mixed signal circuits, explore novelsystem level technologies and search for software solutions andwork-arounds for the deep submicron CMOS process limitations.

The scaling of tomorrow’s semiconductors toward ulitmate physical limitsconflicts with the need for rapid transistors to fruition against the challenges ofreduced design time.

Semiconductor IndustryAssociation (SIA):

Advanced Micro Devices, Inc.

Agere SystemsAgilent TechnologiesAnalog Devices, Inc.Conexant Systems, IncCypress SemiconductorIBM CorporationIntel CorporationLSI Logic CorporationMICRON Technology, Inc.Motorola, IncorporatedNational Semiconductor Texas Instruments Xilinx, Inc.

Semiconductor IndustrySuppliers:

Air Products &Chemicals, Inc.

Applied Materials, Inc.KLA-Tencor CorporationNovellus Systems, Inc.SCP Global TechnologiesSpeedFam-IPECTeradyne, Inc.

Department of Defense:Deputy Undersecretary of

Defense for Laboratories and Basic Sciences(DUSD/LABS)

Defense Advanced Research Projects Agency (DARPA)

DARPADARPA

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IntellectualProperPropertytyIntellectual property (IP) assets covering SRCsponsored university research programs areprovided by SRC to its members to protect andenhance the value of SRC membership. IPassets serve to support the SRC's mission andcharter to transfer and commercialize theresults of SRC-sponsored research programs toSRC member companies. The SRC's significantportfolio of intellectual assets minimizes therisk of infringement and encumbrances asresearch results are utilized by industry.Accordingly, SRC member companies are giventhe freedom to practice, use, andcommercialize the results of research programsfunded through SRC sponsorship. IP assets areinterwoven with the SRC research catalog andcomplement the value chain as an importantbenefit of SRC membership.

In return for sponsorship, SRC receives non-exclusive, worldwide, royalty-free licenses in IPfrom university research programs funded bySRC. These IP rights are transferredcontractually as applicable to SRC membercompanies. Rights in patents, copyrights,software, databases, and other IP, such asmask registrations, are obtained as required toallow SRC members to practice and use theresults of SRC-sponsored research. As anadditional service to members, access tobackground intellectual property licensesnecessary to practice SRC research results maybe provided, whether the background IP is froman industry or academic source. While SRC IPexists primarily for defensive purposes, SRCenforces its IP rights as necessary to provide alevel playing field for members by ensuring thatthose who utilize SRC-sponsored technologiesdo so only within the scope of a valid license.

SRC is investigating ways in which IP assets canprovide new and additional sources of value tothe SRC member community. SRC and NorthCarolina State University have announced aninnovative joint licensing and commercialization

partnership focused on commercializingselected inventions arising from SRC-sponsoreduniversity research programs at NCSU. The newpartnership presents an optional alternativelicensing relationship between SRC and NCSUfor mutually selected inventions developedunder SRC sponsorship. Under the partnership,select SRC and university intellectual propertyrights are combined and licensed to SRC. Theformerly separate IP rights have greater valueonce combined in an escrow managed by SRC.

The formerly separate IP rights have greatervalue once combined and allow exclusivity inlicensing. As a result, SRC can provideenhanced commercialization prospects andgreater licensing value as compared with thetraditional SRC-university licensing model. Theuniversity, SRC, and SRC member companiesagree on terms to sublicense one or morecompanies able to commercialize the inventionand share the royalties collected. SRC, itsmember companies and NCSU are workingtogether to implement this new experimentallicensing model.

SRC has also implemented an IP Advisory Board(IPAB), comprising several SRC membercompany representatives, to work with SRC onthe traditional and new experimental IPlicensing matters. The IPAB will be an integralpart of the decision-making process pertainingto these exciting opportunities. For further

IP PORTFOLIO COMPOSITION

software60%

patents40%

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SRC U.S. and Foreign Patents ISSUED IN 2002

TITLE INVENTOR(S) FILING DATE U.S. PATENT UNIVERSITY

ISSUE DATE NUMBER

Step and Flash Imprint Lithography Grant Willson Mar. 11, 1999 6,334,960 Univ. of Texas at AustinMatthew Colburn Jan. 1, 2002 (U.S.)

Methods of Forming Features of Andrew Ritenour May 24, 2000 6,346,446 Massachusetts Integrated Circuits Using Modified Feb. 12, 2002 (U.S.) Institute of TechnologyBuried Layers and Integrated Circuits Having Features so Formed

Oxidation of Silicon on Germanium Lionel Kimerling June 25, 1999 6,352,942 MassachusettsHsin-Chiao Luan March 5, 2002 (U.S.) Institute of Technology

A Capacitorless Dram Device on Chenming Hu Dec. 1, 1994 69429106T2 Univ. ofSilicon-On-Insulator Substrate Hsing-Jen Wann Mar. 21, 2002 (Germany) California at Berkeley

Methods and Compositions Scott Bukofsky May 26, 1999 6,376,149 Yale University andfor Imaging Acids in Chemically Paul Dentinger April 23, 2002 (U.S.) Univ. of WisconsinAmplified Photoresists Using pH- Robert Grober Dependent Fluorophores James W. Taylor

Using Block Copolymers as Christopher Ober Oct. 26, 1999 6,379,874 Cornell UniversitySupercritical CO2 Developable Photoresists April 30, 2002 (U.S.)

Water-Processable Photoresist Grant Willson Aug. 14, 2000 6,399,273 Univ. of Texas at AustinCompositions Shintaro Yamada June 4, 2002 (U.S.)

Wire Width Planning and Jason Cong Feb. 22, 2000 6,408,427 Univ. of California atPerformance Optimization for David Z. Pan June 18, 2002 (U.S.) Los AngelesVLSI Interconnects

Oxidation of Silicon on Lionel Kimerling Jun. 26, 2000 154359 Massachusetts InstituteGermanium Hsin-Chiao Luan Aug. 15, 2002 (Taiwan) of Technology

Multiple-Thickness Gate Oxide Chenming Hu Dec. 1, 1999 154458 Univ. of California atFormed by Oxygen Implantation Tsu-Jae King Aug. 16, 2002 (Taiwan) Berkeley

details regarding the IPAB, please contact Frank Pita,Director of Corporate Legal Affairs and IP Counsel.

During 2002, ten SRC-sponsored U.S. and foreignpatents issued, bringing the total portfolio of SRClicensed patents to 195. SRC's significant patentportfolio supports both U.S. and international membercompany operations in numerous countries around theworld. SRC's web site permits members to submit real-time queries into SRC's IP database to obtain status onpending and issued patents as well as information onSRC-sponsored software.

The SRC IP portfolio also provides over 288 softwareprograms, software models, and technical databases tomember companies. Software and database licensesfrom SRC-sponsored research programs represent agrowing and complementary part of the SRC IP portfolio.Members are directed to the online software directory athttp://www.src.org for further details. SRC membersreceive non-exclusive, worldwide, royalty-freeintellectual property licenses in applicable softwareprograms and technical databases.

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2002 OFFICE OF THE CHIEF EXECUTIVE

2002 BOARD OF DIRECTORSChairman

Mark Pinto, Agere

Sherry Gillespie Motorola (thru April 15, 2002)

Pawitter Mangat Motorola (as of June 26, 2002)

Yoshio Nishi Texas Instruments (through June 26, 2002)

Hans Stork Texas Instruments (as of June 26, 2002)

Richard Schinella LSI Logic

Walter Class Axcelis

Fu-Tai Liou UMC (through March 14, 2002)

Frank Wen UMC (as of March 14, 2002)

Craig Sander, AMD

Wilbert van den Hoek Novellus

John Warlaumont IBM

Sunlin Chou Intel

Don Harbert Compaq (through August 1, 2002)

Wally Rhines Mentor Graphics

Mohan Yegnashankaran National Semiconductor

Dave Nichols Eastman Kodak

Larry Sumney SRC

Clark McFadden, Dewey Ballentine, Secretary and Counsel

* Executive Director, MARCO

LLaarrrryy SSuummnneeyyPresident and CEO

DDiinneesshh MMeehhttaaVice President,Business Operations& Strategic Initiatives

EE..DD.. ““SSoonnnnyy”” MMaayynnaarrdd**Executive Vice President,Government Affairs

RRaallpphh KK.. CCaavviinn,, IIIIIIVice President,Research Operations

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Semiconductor Research Corporationhttp://www.src.org

NORTH CAROLINABrighton Hall, Suite 120, 1101 Slater Road

Durham, North Carolina 27703(919)941-9400

CALIFORNIA181 Metro Drive, Suite 455San Jose, California 95110

(408) 453-9460

®