Semiconductor Manufacturing

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Semiconductormanufacturingin no particular order

ContentsArticles

Chemical vapor deposition 1Semiconductor device fabrication 5Chemical- mechanical planarization 12Physical vapor deposition 14Atomic layer deposition 16Molecular beam epitaxy 20Czochralski process 22Plasma ashing 26Rapid thermal processing 27Furnace anneal 28Ion implantation 29Etching (microfabrication) 34Dry etching 38Epitaxy 39Photolithography 42Thermal oxidation 50Wafer testing 53Wafer prober 55Non- contact wafer testing 56Die preparation 57Integrated circuit packaging 58Die attachment 60Wire bonding 61Flip chip 63Quilt packaging 68Integrated circuit encapsulation 68Plating 69Semiconductor fabrication plant 73Lights out (manufacturing) 75Foundry model 76Advanced Silicon Etch 81Buffered oxide etch 82Deep reactive- ion etching 82Reactive- ion etching 84

Airgap 86B- staging 87Ball bonding 88Barrier metal 89Borophosphosilicate glass 90Capacitance voltage profiling 90Channel- stopper 92Alfred Y. Cho 93Cleanroom 94Coining, Inc. 99Dark current spectroscopy 99Deal- Grove model 100Device under test 102Doping (semiconductor) 103Electron beam induced current 106Epiwafer 108Evaporation (deposition) 109Fabless semiconductor company 112Finetech 116Focused ion beam 117Gas immersion laser doping 126Gate count 126Hardmask 127Health hazards in semiconductor manufacturing occupations 127Integrated device manufacturer 128Ion Beam Mixing 129Ion beam 131Ion beam lithography 132Laser trimming 133Lift- off (microtechnology) 135Low temperature co- fired ceramic 138MOSIS 139Metal- induced crystallization 140Metalorganic chemical vapor deposition 140Microfabrication 141Multi- project wafer service 145Negative bias temperature instability 146Ohmic contact 147

Overlay Control 151PROLITH 152Package on package 153Phenol formaldehyde resin 155Phosphosilicate glass 157Planar process 158Plasma cleaning 159Plasma etcher 159Plasma etching 160Plasma- immersion ion implantation 161Process design kit 163Product engineering 163Pulsed laser deposition 165RCA clean 170Reliability (semiconductor) 171Resist 174Rigid needle adapter 176SECS/ GEM 178Semiconductor Equipment and Materials International 180Salicide 182Semiconductor industry 183Shallow trench isolation 184Silicate glass 186Silicon on sapphire 187Smart Cut 189Spin coating 190Spreading Resistance Profiling 192Sputter deposition 196Substrate mapping 201Tetrakis(dimethylamido)titanium 203Three- dimensional integrated circuit 205Through- silicon via 208Titanium nitride 209Trimethylgallium 213Vapour phase decomposition 214Wafer (electronics) 214Wafer dicing 220Wafer fabrication 221

Wafer- scale integration 222

ReferencesArticle Sources and Contributors 225Image Sources, Licenses and Contributors 230

Article LicensesLicense 233

Chemical vapor deposition 1

Chemical vapor deposition

DC plasma (violet) enhances the growth ofcarbon nanotubes in this laboratory-scale

PECVD apparatus.

Chemical vapor deposition (CVD) is a chemicalprocess used to produce high-purity,high-performance solid materials. The process isoften used in the semiconductor industry toproduce thin films. In a typical CVD process, the wafer (substrate) is exposed to one or more volatileprecursors, which react and/or decompose on thesubstrate surface to produce the desired deposit.Frequently, volatile by-products are also produced,which are removed by gas flow through the reactionchamber.

Microfabrication processes widely use CVD todeposit materials in various forms, including:monocrystalline, polycrystalline, amorphous, and epitaxial. These materials include: silicon, carbonfiber, carbon nanofibers, filaments, carbonnanotubes, SiO2, silicon-germanium, tungsten,silicon carbide, silicon nitride, silicon oxynitride, titanium nitride, and various high-k dielectrics. TheCVD process is also used to produce syntheticdiamonds.

Types of chemical vapor deposition

hot-wall thermal CVD (batch operationtype)

plasma assisted CVD

A number of forms of CVD are in wide use and arefrequently referenced in the literature. Theseprocesses differ in the means by which chemicalreactions are initiated (e.g., activation process) andprocess conditions. Classified by operating pressure

Atmospheric pressure CVD (APCVD) - CVDprocesses at atmospheric pressure.

Low-pressure CVD (LPCVD) - CVD processes atsubatmospheric pressures[1] . Reducedpressures tend to reduce unwanted gas-phasereactions and improve film uniformity acrossthe wafer. Most modern CVD process are eitherLPCVD or UHVCVD.

Ultrahigh vacuum CVD (UHVCVD) - CVD processes at a very low pressure, typicallybelow 10-6 Pa (~ 10-8 torr). Caution: in other fields, a lower division between high andultra-high vacuum is common, often 10-7 Pa.

Classified by physical characteristics of vapor


Aerosol assisted CVD (AACVD) - A CVD process in which the precursors aretransported to the substrate by means of a liquid/gas aerosol, which can be generatedultrasonically. This technique is suitable for use with non-volatile precursors.

Direct liquid injection CVD (DLICVD) - A CVD process in which the precursors are inliquid form (liquid or solid dissolved in a convenient solvent). Liquid solutions areinjected in a vaporization chamber towards injectors (typically car injectors). Then theprecursor vapors are transported to the substrate as in classical CVD process. Thistechnique is suitable for use on liquid or solid precursors. High growth rates can bereached using this technique.

Plasma methods (see also Plasma processing) Microwave plasma-assisted CVD (MPCVD) Plasma-Enhanced CVD (PECVD) - CVD processes that utilize plasma to enhance

chemical reaction rates of the precursors[2] . PECVD processing allows deposition atlower temperatures, which is often critical in the manufacture of semiconductors.

Remote plasma-enhanced CVD (RPECVD) - Similar to PECVD except that the wafersubstrate is not directly in the plasma discharge region. Removing the wafer from theplasma region allows processing temperatures down to room temperature.

Atomic layer CVD (ALCVD) Deposits successive layers of different substances toproduce layered, crystalline films. See Atomic layer epitaxy.

Hot wire CVD (HWCVD) - also known as catalytic CVD (Cat-CVD) or hot filament CVD(HFCVD). Uses a hot filament to chemically decompose the source gases.[3]

Metalorganic chemical vapor deposition (MOCVD) - CVD processes based onmetalorganic precursors.

Hybrid Physical-Chemical Vapor Deposition (HPCVD) - Vapor deposition processes thatinvolve both chemical decomposition of precursor gas and vaporization of solid a source.

Rapid thermal CVD (RTCVD) - CVD processes that use heating lamps or other methods torapidly heat the wafer substrate. Heating only the substrate rather than the gas orchamber walls helps reduce unwanted gas phase reactions that can lead to particleformation.

Vapor phase epitaxy (VPE)

Substances commonly deposited for ICsThis section discusses the CVD processes often used for integrated circuits (ICs). Particularmaterials are deposited best under particular conditions.

PolysiliconPolycrystalline silicon is deposited from silane (SiH4), using the following reaction:

SiH4 Si + 2H2This reaction is usually performed in LPCVD systems, with either pure silane feedstock, or asolution of silane with 70-80% nitrogen. Temperatures between 600 and 650 C andpressures between 25 and 150 Pa yield a growth rate between 10 and 20 nm per minute.An alternative process uses a hydrogen-based solution. The hydrogen reduces the growthrate, but the temperature is raised to 850 or even 1050 C to compensate.Polysilicon may be grown directly with doping, if gases such as phosphine, arsine ordiborane are added to the CVD chamber. Diborane increases the growth rate, but arsineand phosphine decrease it.


Silicon dioxideSilicon dioxide (usually called simply "oxide" in the semiconductor industry) may bedeposited by several different processes. Common source gases include silane and oxygen,dichlorosilane (SiCl2H2) and nitrous oxide (N2O), or tetraethylorthosilicate (TEOS;Si(OC2H5)4). The reactions are as follows:

SiH4 + O2 SiO2 + 2H2SiCl2H2 + 2N2O SiO2 + 2N2 + 2HClSi(OC2H5)4 SiO2 + byproducts

The choice of source gas depends on the thermal stability of the substrate; for instance,aluminium is sensitive to high temperature. Silane deposits between 300 and 500 C,dichlorosilane at around 900 C, and TEOS between 650 and 750 C, resulting in a layer ofLow Temperature Oxide (LTO). However, silane produces a lower-quality oxide than theother methods (lower dielectric strength, for instance), and it deposits nonconformally. Anyof these reactions may be used in LPCVD, but the silane reaction is also done in APCVD.CVD oxide invariably has lower quality than thermal oxide, but thermal oxidation canonly be used in the earliest stages of IC manufacturing.Oxide may also be grown with impurities (alloying or " doping"). This may have twopurposes. During further process steps that occur at high temperature, the impurities maydiffuse from the oxide into adjacent layers (most notably silicon) and dope them. Oxidescontaining 5% to 15% impurities by mass are often used for this purpose. In addition,silicon dioxide alloyed with phosphorus pentoxide ("P-glass") can be used to smooth outuneven surfaces. P-glass softens and reflows at temperatures above 1000 C. This processrequires a phosphorus concentration of at least 6%, but concentrations above 8% cancorrode aluminium. Phosphorus is deposited from phosphine gas and oxygen:

4PH3 + 5O2 2P2O5 + 6H2Glasses containing both boron and phosphorus (borophosphosilicate glass, BPSG) undergoviscous flow at lower temperatures; around 850 C is achievable with glasses containingaround 5 weight % of both constituents, but stability in air can be difficult to achieve.Phosphorus oxide in high concentrations interacts with ambient moisture to producephosphoric acid. Crystals of BPO4 can also precipitate from the flowing glass on cooling;these crystals are not readily etched in the standard reactive plasmas used to patternoxides, and will result in circuit defects in integrated circuit manufacturing.Besides these intentional impurities, CVD oxide may contain byproducts of the depositionprocess. TEOS produces a relatively pure oxide, whereas silane introduces hydrogenimpurities, and dichlorosilane introduces chlorine.Lower temperature deposition of silicon dioxide and doped glasses from TEOS using ozonerather than oxygen has also been explored (350 to 500 C). Ozone glasses have excellentconformality but tend to be hygroscopic -- that is, they absorb water from the air due to theincorporation of silanol (Si-OH) in the glass. Infrared spectroscopy and mechanical strain asa function of temperature are valuable diagnostic tools for diagnosing such problems.


Silicon nitrideSilicon nitride is often used as an insulator and chemical barrier in manufacturing ICs. Thefollowing two reactions deposit nitride from the gas phase:

3SiH4 + 4NH3 Si3N4 + 12H23SiCl2H2 + 4NH3 Si3N4 + 6HCl + 6H2

Silicon nitride deposited by LPCVD contains up to 8% hydrogen. It also experiences strongtensile stress, which may crack films thicker than 200 nm. However, it has higher resistivityand dielectric strength than most insulators commonly available in microfabrication (1016

cm and 10 MV/cm, respectively).Another two reactions may be used in plasma to deposit SiNH:

2SiH4 + N2 2SiNH + 3H2SiH4 + NH3 SiNH + 3H2

These films have much less tensile stress, but worse electrical properties (resistivity 106 to1015 cm, and dielectric strength 1 to 5 MV/cm).[4]

MetalsSome metals (notably aluminium and copper) are seldom or never deposited by CVD. As of2002[5], a commercially, cost effective, viable CVD process for copper did not exist- thoughmany people have used Copper Formate, Copper(hfac)2, and other precursors(Cu(II) ethylacetoacetate, etc...). Copper deposition of the metal has been done mostly by electroplatingdue to cost. Aluminum can be deposited from tri-isobutyl aluminium (TIBAL), or Tri-ethylAluminum (TEA), but physical vapor deposition methods are usually preferred.However, CVD processes for molybdenum, tantalum, titanium, nickel, and tungsten arewidely used. These metals can form useful silicides when deposited onto silicon. Mo, Ta andTi are deposited by LPCVD, from their pentachlorides. Nickel, Molybdenum, and Tungstencan be deposited at low temperatures from their carbonyl precursors. In general, for anarbitrary metal M, the reaction is as follows:

2MCl5 + 5H2 2M + 10HClThe usual source for tungsten is tungsten hexafluoride, which may be deposited in twoways:

WF6 W + 3F2WF6 + 3H2 W + 6HF

See also Atomic layer deposition, a more precise and conformal coating technology Hot-wire Ion plating, a process that may use chemical vapor precursors Physical vapor deposition, the deposition of materials from vapor without chemical

reactions Plasma-enhanced chemical vapor deposition


References[1] Low Pressure Chemical Vapor Deposition - Technology and Equipment (http:/ / www. crystec. com/ klllpcvde.

htm),[2] Plasma Enhanced Chemical Vapor Deposition - Technology and Equipment (http:/ / www. crystec. com/

tridepe. htm),[3] Schropp, R.E.I.; B. Stannowski, A.M. Brockhoff, P.A.T.T. van Veenendaal and J.K. Rath. " Hot wire CVD of

heterogeneous and polycrystalline silicon semiconducting thin films for application in thin film transistors andsolar cells (http:/ / www. ipme. ru/ e-journals/ MPM/ no_2100/ schropp/ schropp. pdf)" (PDF). Materials Physicsand Mechanics. pp.7382.

[4] S.M.Sze (2008). Semiconductor devices: physics and technology. Wiley-India. p.384. ISBN 812651681X.[5] http:/ / en. wikipedia. org/ wiki/ Chemical_vapor_deposition

Jaeger, Richard C. (2002). "Film Deposition". Introduction to Microelectronic Fabrication.Upper Saddle River: Prentice Hall. ISBN 0-201-44494-7.

Smith, Donald (1995). Thin-Film Deposition: Principles and Practice. MacGraw-Hill. Dobkin and Zuraw (2003). Principles of Chemical Vapor Deposition. Kluwer. ISO 3529/1-1981 Vacuum Technology - Vocabulary - part 1: General terms As quoted by

UK National Physical Laboratory (http:/ / www. npl. co. uk/ pressure/ faqs/ glossary. html)

External links Fundamental of Chemical Vapor Deposition (http:/ / www. timedomaincvd. com/

CVD_Fundamentals/ Fundamentals_of_CVD. html), by TimeDomain CVD, Inc.

Semiconductor device fabrication

NASA's Glenn Research Center cleanroom.

Semiconductor device fabricationis the process used to create chips,the integrated circuits that arepresent in everyday electrical andelectronic devices. It is a multiple-stepsequence of photographic andchemical processing steps duringwhich electronic circuits are graduallycreated on a wafer made of puresemiconducting material. Silicon isthe most commonly usedsemiconductor material today, alongwith various compoundsemiconductors.

The entire manufacturing processfrom start to packaged chips ready for shipment takes six to eight weeks and is performedin highly specialized facilities referred to as fabs.

Semiconductor device fabrication 6

WafersA typical wafer is made out of extremely pure silicon that is grown into mono-crystallinecylindrical ingots (boules) up to 300mm (slightly less than 12inches) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick andpolished to obtain a very regular and flat surface.Once the wafers are prepared, many process steps are necessary to produce the desiredsemiconductor integrated circuit. In general, the steps can be grouped into two areas:[1]

Front-end processing Back-end processing

ProcessingIn semiconductor device fabrication, the various processing steps fall into four generalcategories: deposition, removal, patterning, and modification of electrical properties. Deposition is any process that grows, coats, or otherwise transfers a material onto the

wafer. Available technologies consist of physical vapor deposition (PVD), chemicalvapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy(MBE) and more recently, atomic layer deposition (ALD) among others.

Removal processes are any that remove material from the wafer either in bulk orselectively and consist primarily of etch processes, either wet etching or dry etching. Chemical-mechanical planarization (CMP) is also a removal process used between levels.

Patterning covers the series of processes that shape or alter the existing shape of thedeposited materials and is generally referred to as lithography. For example, inconventional lithography, the wafer is coated with a chemical called a photoresist. Thephotoresist is exposed by a stepper, a machine that focuses, aligns, and moves themask, exposing select portions of the wafer to short wavelength light. The unexposedregions are washed away by a developer solution. After etching or other processing, theremaining photoresist is removed by plasma ashing.

Modification of electrical properties has historically consisted of doping transistorsources and drains originally by diffusion furnaces and later by ion implantation. Thesedoping processes are followed by furnace anneal or in advanced devices, by rapidthermal anneal (RTA) which serve to activate the implanted dopants. Modification ofelectrical properties now also extends to reduction of dielectric constant in low-kinsulating materials via exposure to ultraviolet light in UV processing (UVP).

Many modern chips have eight or more levels produced in over 300 sequenced processingsteps.

Front-end processing"Front-end processing" refers to the formation of the transistors directly on the silicon. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a "straining step" wherein a silicon variant such as "silicon-germanium" (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called "silicon on insulator" technology involves the insertion of an insulating layer


between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This methodresults in the creation of transistors with reduced parasitic effects.

Silicon dioxideFront-end surface engineering is followed by: growth of the gate dielectric, traditionallysilicon dioxide (SiO2), patterning of the gate, patterning of the source and drain regions,and subsequent implantation or diffusion of dopants to obtain the desired complementaryelectrical properties. In memory devices, storage cells, conventionally capacitors, are alsofabricated at this time, either into the silicon surface or stacked above the transistor.

Metal layersOnce the various semiconductor devices have been created they must be interconnected toform the desired electrical circuits. This "back end of line" (BEOL the latter portion of thewafer fabrication, not to be confused with "back end" of chip fabrication which refers to thepackage and test stages) involves creating metal interconnecting wires that are isolated byinsulating dielectrics. The insulating material was traditionally a form of SiO2 or a silicateglass, but recently new low dielectric constant materials are being used. These dielectricspresently take the form of SiOC and have dielectric constants around 2.7 (compared to 3.9for SiO2), although materials with constants as low as 2.2 are being offered to chipmakers.

Interconnect

Synthetic detail of a standard cell through four layers of planarizedcopper interconnect, down to the polysilicon (pink), wells (greyish)

and substrate (green).

Historically, the metal wiresconsisted of aluminum. In thisapproach to wiring oftencalled "subtractive aluminum",blanket films of aluminum aredeposited first, patterned, andthen etched, leaving isolatedwires. Dielectric material isthen deposited over theexposed wires. The variousmetal layers areinterconnected by etchingholes, called "vias," in theinsulating material anddepositing tungsten in themwith a CVD technique. Thisapproach is still used in thefabrication of many memorychips such as dynamic random access memory (DRAM) as the number of interconnectlevels is small, currently no more than four.

More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become significant prompting a change in wiring material from aluminum to copper and from the silicon dioxides to newer low-K material. This performance enhancement also comes at a reduced cost via damascene


processing that eliminates processing steps. In damascene processing, in contrast tosubtractive aluminum technology, the dielectric material is deposited first as a blanket film,and is patterned and etched leaving holes or trenches. In "single damascene" processing,copper is then deposited in the holes or trenches surrounded by a thin barrier film resultingin filled vias or wire "lines" respectively. In "dual damascene" technology, both the trenchand via are fabricated before the deposition of copper resulting in formation of both the viaand line simultaneously, further reducing the number of processing steps. The thin barrierfilm, called copper barrier seed (CBS), is necessary to prevent copper diffusion into thedielectric. The ideal barrier film is as thin as possible. As the presence of excessive barrierfilm competes with the available copper wire cross section, formation of the thinnestcontinuous barrier represents one of the greatest ongoing challenges in copper processingtoday.As the number of interconnect levels increases, planarization of the previous layers isrequired to ensure a flat surface prior to subsequent lithography. Without it, the levelswould become increasingly crooked and extend outside the depth of focus of availablelithography, interfering with the ability to pattern. CMP (chemical mechanicalplanarization) is the primary processing method to achieve such planarization although dry"etch back" is still sometimes employed if the number of interconnect levels is no more thanthree.

Wafer testThe highly serialized nature of wafer processing has increased the demand for metrology inbetween the various processing steps. Wafer test metrology equipment is used to verifythat the wafers haven't been damaged by previous processing steps up until testing. If thenumber of diesthe integrated circuits that will eventually become chips etched on awafer exceeds a failure threshold (ie. too many failed dies on one wafer), the wafer isscrapped rather than investing in further processing.

Device testOnce the front-end process has been completed, the semiconductor devices are subjectedto a variety of electrical tests to determine if they function properly. The proportion ofdevices on the wafer found to perform properly is referred to as the yield.The fab tests the chips on the wafer with an electronic tester that presses tiny probesagainst the chip. The machine marks each bad chip with a drop of dye. The fab charges fortest time; the prices are on the order of cents per second. Chips are often designed withtestability features such as "built-in self-test" to speed testing, and reduce test costs.Good designs try to test and statistically manage corners: extremes of silicon behaviorcaused by operating temperature combined with the extremes of fab processing steps. Mostdesigns cope with more than 64 corners.


Die preparationOnce tested, the wafer is scored and then broken into individual die -- wafer dicing. Onlythe good, unmarked chips go on to be packaged.

PackagingPlastic or ceramic packaging involves mounting the die, connecting the die pads to the pinson the package, and sealing the die. Tiny wires are used to connect pads to the pins. In theold days, wires were attached by hand, but now purpose-built machines perform the task.Traditionally, the wires to the chips were gold, leading to a lead frame (pronounced leedframe) of copper, that had been plated with solder, a mixture of tin and lead. Lead ispoisonous, so lead-free lead frames are now mandated by ROHS.Chip-scale package (CSP) is another packaging technology. A plastic dual in-line package,like most packages, is many times larger than the actual die hidden inside, whereas CSPchips are nearly the size of the die. CSP can be constructed for each die before the wafer isdiced [2].The packaged chips are retested to ensure that they were not damaged during packagingand that the die-to-pin interconnect operation was performed correctly. A laser etches thechips name and numbers on the package.

List of stepsThis is a list of processing techniques that are employed numerous times in a modernelectronic device and do not necessarily imply a specific order. Wafer processing

Wet cleans Photolithography Ion implantation (in which dopants are embedded in the wafer creating regions of

increased (or decreased) conductivity) Dry etching Wet etching Plasma ashing Thermal treatments

Rapid thermal anneal Furnace anneals Thermal oxidation

Chemical vapor deposition (CVD) Physical vapor deposition (PVD) Molecular beam epitaxy (MBE) Electrochemical Deposition (ECD). See Electroplating Chemical-mechanical planarization (CMP) Wafer testing (where the electrical performance is verified) Wafer backgrinding (to reduce the thickness of the wafer so the resulting chip can be

put into a thin device like a smartcard or PCMCIA card.) Die preparation

Wafer mounting Die cutting


IC packaging Die attachment IC Bonding

Wire bonding Flip chip Tab bonding

IC encapsulation Baking Plating Lasermarking Trim and form

IC testing

Hazardous materials noteMany toxic materials are used in the fabrication process. These include: poisonous elemental dopants such as arsenic, antimony and phosphorus poisonous compounds like arsine, phosphine and silane highly reactive liquids, such as hydrogen peroxide, fuming nitric acid, sulfuric acid and

hydrofluoric acidIt is vital that workers not be directly exposed to these dangerous substances. The highdegree of automation common in the IC fabrication industry helps to reduce the risks ofexposure of this sort. Most fabrication facilities employ exhaust management systems, suchas wet scrubbers, combustors, heated absorber cartridges etc, to control the risk toworkers and also the environment if these toxic materials are released into the atmosphere.

HistoryWhen feature widths were far greater than about 10 micrometres, purity was not the issuethat it is today in device manufacturing. As devices became more integrated, cleanroomsbecame even cleaner. Today, the fabs are pressurized with filtered air to remove even thesmallest particles, which could come to rest on the wafers and contribute to defects. Theworkers in a semiconductor fabrication facility are required to wear cleanroom suits toprotect the devices from human contamination.In an effort to increase profits, semiconductor device manufacturing has spread from Texasand California in the 1960s to the rest of the world, such as Europe, Israel, Japan, Taiwan,Korea, Singapore and China. It is a global business today.The leading semiconductor manufacturers typically have facilities all over the world. Intel,the world's largest manufacturer, has facilities in Europe and Asia as well as the U.S. Othertop manufacturers include STMicroelectronics (Europe), Analog Devices (US), Atmel(US/Europe), Freescale Semiconductor (US), Samsung (Korea), Texas Instruments (US),GlobalFoundries (Germany, future New York fab in construction), Toshiba (Japan), NECElectronics [3] (Japan), Infineon (Europe), Renesas (Japan), Taiwan SemiconductorManufacturing Company (Taiwan, see TSMC web site [4]), Chartered SemiconductorManufacturing Ltd (Singapore, see Chartered web site [5]), Sony(Japan), NXPSemiconductors (Europe), Micron Technology (US), Hynix (Korea) and SMIC (China, seeSMIC web site [6]).


See also Atomic layer deposition Cleanrooms Electronic design automation Foundry (electronics) GDS-II Health hazards in semiconductor manufacturing occupations International Technology Roadmap for Semiconductors Microfabrication OASIS SEMI The semiconductor industry trade association

External links Amkor Technology Semiconductor Packaging & Test [7]

Semiconductor Manufacturing [8]

Semiconductor Glossary [9]

NEC's Virtual Factory Tour [10]

Semiconductor materials processing [11]

Calculator for Silicon thermal oxidation [12]

BYU Cleanroom - semiconductor properties, calculators, processes, etc. [13]

Omron An introduction to Application Expertise - Semiconductor, Photo Voltaic &Electronics Industry [14]

References[1] Zeno Gaburro (2004). " Optical Interconnect (http:/ / books. google. com/ books?id=PgmmFRYE6a0C&

pg=PA122& dq="front+ end+ process"+ transistor& lr=& as_brr=3& ei=elK_SKqAHZDwsgPRw63YDA&sig=ACfU3U3R53OZ9F-6x6e9woPK4C3fuxQJrw)". in Lorenzo Pavesi and David J. Lockwood. Silicon Photonics.Springer. ISBN 3540210229. .

[2] http:/ / www. uic. com/ wcms/ WCMS2. nsf/ index/ Resources_26. html[3] http:/ / www. necel. com/ index. html[4] http:/ / www. tsmc. com/[5] http:/ / www. charteredsemi. com/[6] http:/ / www. smics. com/[7] http:/ / www. amkor. com[8] http:/ / www. siliconfareast. com/ manufacturing. HTM[9] http:/ / www. semiconductorglossary. com[10] http:/ / www. necel. com/ v_factory/ en/ index. html[11] http:/ / www. logitech. uk. com/ semicon. asp[12] http:/ / www. lelandstanfordjunior. com/ thermaloxide. html[13] http:/ / www. ece. byu. edu/ cleanroom/[14] http:/ / www. omron-semi-pv. eu/

Chemical-mechanical planarization 12

Chemical- mechanical planarizationChemical-mechanical planarization or Chemical-mechanical polishing, commonlyabbreviated CMP, is a technique used in semiconductor fabrication for planarizing asemiconductor wafer or other substrate.

Description

functional principle of CMP

The process uses an abrasive and corrosivechemical slurry (commonly a colloid) in conjunctionwith a polishing pad and retaining ring, typically ofa greater diameter than the wafer. The pad andwafer are pressed together by a dynamic polishinghead and held in place by a plastic retaining ring.The dynamic polishing head is rotated withdifferent axes of rotation (i.e., not concentric). Thisremoves material and tends to even out anyirregular topography, making the wafer flat orplanar. This may be necessary in order to set up thewafer for the formation of additional circuitelements. For example, this might be necessary inorder to bring the entire surface within the depth offield of a photolithography system, or toselectively remove material based on its position.Typical depth-of-field requirements are down toAngstrom levels for the latest 65 nm technology.

How it worksThe process of material removal is not simply thatof abrasive scraping, like sandpaper on wood. Thechemicals in the slurry also react with and/orweaken the material to be removed. The abrasive accelerates this weakening process andthe polishing pad helps to wipe the reacted materials from the surface. The process hasbeen likened to that of a child eating a gummy candy. If the candy sits on the tonguewithout being scraped around, the candy becomes covered with a gel coating, but themajority of the candy is not affected. Only with a vigorous scraping does the candy dissolveaway.

Another analogy is the act of brushing one's teeth. The toothbrush is the mechanical partand the toothpaste is the chemical part. Using either the toothbrush or the toothpaste alonewill get one's teeth somewhat clean, but using the toothbrush and toothpaste togethermakes a superior process.

Chemical-mechanical planarization 13

Usage in semiconductor fabricationBefore about 1990 CMP was looked on as too "dirty" to be included in high-precisionfabrication processes, since abrasion tends to create particles and the abrasives themselvesare not without impurities. Since that time, the integrated circuit industry has moved fromaluminium to copper conductors. This required the development of an additive patterningprocess, which relies on the unique abilities of CMP to remove material in a planar anduniform fashion and to stop repeatably at the interface between copper and oxide insulatinglayers (see Copper-based chips for details). Adoption of this process has made CMPprocessing much more widespread. In addition to aluminum and copper, CMP processeshave been developed for polishing tungsten, silicon dioxide, and (recently) carbonnanotubes.[1]

Key metricsKey metrics that are important for CMP are the following: Rate of removal: How quickly can the material be removed? Uniformity of removal: How uniform is the removal across the die (local) and the wafer

(global)? Planarity: How planar/flat is the surface after the removal process is complete? Defects: How many defects and of what size are left behind on the wafer? Consistency: How consistent is the performance from wafer to wafer?

References[1] Awano,Y.:(2006),"Carbon Nanotube (CNT) Via Interconnect Technologies: Low temperature CVD growth and

chemical mechanical planarization for vertically aligned CNTs". Proc. 2006 ICPT, 10

2. "Chemical Mechanical Planarization Experts". (http:/ / www. ims-expertservices. com/CaseListing. asp?KeywordID=1782) ims-expertservices.com. Retrieved on 2009-04-03.

See also RCA clean Etching (microfabrication)

Physical vapor deposition 14

Physical vapor deposition

Physical vapor deposition (PVD) is a variety of vacuum deposition and is a general termused to describe any of a variety of methods to deposit thin films by the condensation of avaporized form of the material onto various surfaces (e.g., onto semiconductor wafers).The coating method involves purely physical processes such as high temperature vacuumevaporation or plasma sputter bombardment rather than involving a chemical reaction atthe surface to be coated as in chemical vapor deposition. The term physical vapordeposition appears originally in the 1966 book Vapor Deposition by CF Powell, JH Oxleyand JM Blocher Jr, but Michael Faraday was using PVD to deposit coatings as far back as1838.Variants of PVD include, in order of increasing novelty: Evaporative deposition: In which the material to be deposited is heated to a high vapor

pressure by electrically resistive heating in "low" vacuum. Electron beam physical vapor deposition: In which the material to be deposited is heated

to a high vapor pressure by electron bombardment in "high" vacuum. Sputter deposition: In which a glow plasma discharge (usually localized around the

"target" by a magnet) bombards the material sputtering some away as a vapor. Here isan animation of a generic PVD sputter tool: PVD Animation [1]

Cathodic Arc Deposition: In which a high power arc directed at the target material blastsaway some into a vapor.

Pulsed laser deposition: In which a high power laser ablates material from the targetinto a vapor.

PVD is used in the manufacture of items including semiconductor devices, aluminized PETfilm for balloons and snack bags, and coated cutting tools for metalworking. Besides PVDtools for fabrication special smaller tools mainly for scientific purposes have beendeveloped. They mainly serve the purpose of extreme thin films like atomic layers and areused mostly for small substrates. A good example are mini e-beam evaporators which candeposit monolayers of virtually all materials with melting points up to 3500C.Some of the techniques used to measure the physical properties of PVD coatings are: Calo tester: coating thickness test Scratch tester: coating adhesion test Pin on disc tester: wear and friction coefficient testSee thin-film deposition for a more general discussion of this class of manufacturingtechnique.

Physical vapor deposition 15

References[1] http:/ / www. syngraphics. com/ whatsnew_PVD. html

Anders, Andre (editor). Handbook of Plasma Immersion Ion Implantation and Deposition.New York: Wiley-Interscience, 2000. ISBN 0471246980.

Bach, Hans, and Dieter Krause (editors). Thin Films on Glass. Schott series on glass andglass ceramics. London: Springer-Verlag, 2003. ISBN 3540585974.

Bunshah, Roitan F. (editor). Handbook of Deposition Technologies for Films andCoatings: Science, Technology and Applications, second edition. Materials science andprocess technology series. Park Ridge, N.J.: Noyes Publications, 1994. ISBN 0815513372.

Glser, Hans Joachim. Large Area Glass Coating. Dresden: Von Ardenne Anlagentechnik,2000. ISBN 3000049533.

Glocker, David A., and S. Ismat Shah (editors). Handbook of Thin Film ProcessTechnology (2 vol. set). Bristol, U.K.: Institute of Physics Pub, 2002. ISBN 0750308338.

Mahan, John E. Physical Vapor Deposition of Thin Films. New York: John Wiley & Sons,2000. ISBN 0471330019.

Mattox, Donald M. Handbook of Physical Vapor Deposition (PVD) Processing: FilmFormation, Adhesion, Surface Preparation and Contamination Control.. Westwood, N.J.:Noyes Publications, 1998. ISBN 0815514220.

Mattox, Donald M. The Foundations of Vacuum Coating Technology. Norwich, N.Y.:Noyes Publications/William Andrew Pub., 2003. ISBN 0815514956.

Mattox, Donald M. and Vivivenne Harwood Mattox (editors). 50 Years of Vacuum CoatingTechnology and the Growth of the Society of Vacuum Coaters. Albuquerque, N.M.:Society of Vacuum Coaters, 2007. ISBN 978-1878068279.

Powell, Carroll F., Joseph H. Oxley, and John Milton Blocher (editors). Vapor Deposition.The Electrochemical Society series. New York: Wiley, 1966.

Westwood, William D. Sputter Deposition. AVS Education Committee book series, v. 2.New York: Education Committee, AVS, 2003. ISBN 0735401055.

Willey, Ronald R. Practical Monitoring and Control of Optical Thin Films. Charlevoix, MI:Willey Optical, Consultants, 2007. ISBN 978-0615137605.

Willey, Ronald R. Practical Equipment, Materials, and Processes for Optical Thin Films.Charlevoix, MI: Willey Optical, Consultants, 2007. ISBN 978-0615143972.

External links Society of Vacuum Coaters (http:/ / www. svc. org/ )

Atomic layer deposition 16

Atomic layer depositionAtomic layer deposition (ALD) is a thin film deposition technique that is based on thesequential use of a gas phase chemical process. The majority of ALD reactions use twochemicals, typically called precursors. These precursors react with a surface one-at-a-timein a sequential manner. By exposing the precursors to the growth surface repeatedly, a thinfilm is deposited.[1]

IntroductionALD is a self-limiting (the amount of film material deposited in each reaction cycle isconstant), sequential surface chemistry that deposits conformal thin-films of materials ontosubstrates of varying compositions. ALD is similar in chemistry to chemical vapordeposition (CVD), except that the ALD reaction breaks the CVD reaction into twohalf-reactions, keeping the precursor materials separate during the reaction. Due to thecharacteristics of self-limiting and surface reactions, ALD film growth makes atomic scaledeposition control possible. By keeping the precursors separate throughout the coatingprocess, atomic layer control of film growth can be obtained as fine as ~0.1 (10 pm)permonolayer.ALD had been developed and introduced worldwide with the name Atomic layer epitaxy(ALE) in the late 1970s.[2] For thin film electroluminescent (TFEL) flat-panel displays, highquality dielectric and luminescent films were required on large-area substrates, thus thedeposition method of ALD was developed. Interest in ALD has increased in steps in themid-1990s and 2000s, with the interest focused on silicon-based microelectronics. ALD isconsidered as one deposition method with the greatest potential for producing very thin,conformal films with control of the thickness and composition of the films possible at theatomic level. A major driving force for the recent interest is the prospective seen for ALD inscaling down microelectronic devices.ALD can be used to deposit several types of thin films, including various oxides (e.g. Al2O3,TiO2, SnO2, ZnO, HfO2),metal nitrides (e.g. TiN, TaN, WN, NbN), metals (e.g. Ru, Ir, Pt),and metal sulfides (e.g. ZnS).

ALD processThe growth of material layers by ALD consists of repeating the following characteristic foursteps:1) Exposure of the first precursor.2) Purge or evacuation of the reaction chamber to remove the non-reacted precursors andthe gaseous reaction by-products.3) Exposure of the second precursor or another treatment to activate the surface again forthe reaction of the first precursor.4) Purge or evacuation of the reaction chamber.Each reaction cycle adds a given amount of material to the surface, referred to as the growth per cycle. To grow a material layer, reaction cycles are repeated as many as required for the desired film thickness. One cycle may take time from 0.5s to a few seconds and deposit between 0.1 and 3 of film thickness. Before starting the ALD process, the


surface is stabilized to a known, controlled state, usually, by a heat treatment. Due to theself-terminating reactions, ALD is a surface-controlled process, where process parametersother than the precursors, substrate, and temperature have little or no influence. And,because of the surface control, ALD-grown films are extremely conformal and uniform inthickness.

Advantages and limitations

AdvantagesUsing ALD, Film thickness depends only on the number of reaction cycles, which makes thethickness control accurate and simple. Unlike CVD, there is less need of reactant fluxhomogeneity, which gives large area (large batch and easy scale-up) capability, excellentconformality and reproducibility, and simplifies the use of solid precursors. Also, the growthof different multilayer structures is straight forward. These advantages make the ALDmethod attractive for microelectronics for manufacturing of future generation integratedcircuits. Another advantage of ALD is the wide range of film materials available, and highdensity and low impurity level. Also, lower deposition temperature can be used in order notto affect sensitive substrates.

LimitationsThe major limitation of ALD is its slowness; usually only a fraction of a monolayer isdeposited in one cycle. Fortunately, the films needed for future-generation ICs are very thinand thus the slowness of ALD is not such an important issue.Although the selection of film materials grown by ALD is wide, many technologicallyimportant materials (Si, Ge, Si3N4, several multi-component oxides, certain metals) cannotcurrently be deposited by ALD in a cost-effective way.ALD is a chemical technique and thus there is always a risk of residues being left from theprecursors. The impurity content of the films depends on the completeness of the reactions.In typical oxide processes where metal halides of alkyl compounds are used together withwater as precursors, impurities found in the films are at the 0.1-1 atom % level.

ALD in microelectronicsIn microelectronics, ALD is studied as a potential technique to deposit high-k (highpermittivity) gate oxides, high-k memory capacitor dielectrics, ferroelectrics, and metalsand nitrides for electrodes and interconnects. In high-k gate oxides, where the control ofultra thin films is essential, ALD is only likely to come in to wider use at the 45nmtechnology. In metallizations, conformal films are required; currently it is expected thatALD will be used in mainstream production at the 65nm node. In dynamic random accessmemories (DRAMs), the conformality requirements are even higher and ALD is the onlymethod that can be used when feature sizes become smaller than 100nm.[3]


Gate oxidesDeposition of the high-k oxides Al2O3, ZrO2, and HfO2 has been one of the most widelyexamined areas of ALD. The motivation for high-k oxides comes from the problem of hightunneling currents through the currently used SiO2 metal-oxide-semiconductor field-effecttransistor (MOSFET) gate dielectric when it is downscaled to a thickness of 1.0nm andbelow. With the high-k oxide, a thicker gate dielectric can be made for the requiredcapacitance density, thus the tunneling current can be reduced through the structure.Intel Corporation has reported using ALD to deposit high-k gate dielectric for its 45 nmCMOS technology.[4]

DRAM capacitorsThe development of dynamic random access memory (DRAM) capacitor dielectrics has beensimilar to that of gate dielectrics: SiO2 has been widely used in the industry thus far, but itis likely to be phased out in the near future as the scale of devices are decreased. Therequirements for the downscaled DRAM capacitors are good conformality and permittivityvalues above 200, thus the candidate materials are different from those explored forMOSFET gate dielectrics. (For example, Al2O3, ZrO2, and HfO2) The most extensivelystudied candidate has been (Ba,Sr)TiO3. ALD is a very promising method, which can satisfythe high conformal requirements of DRAM applications. A permittivity of 180 was measuredfor SrTiO3 and 165 for BaTiO3 when films thicker than 200nm were post-deposition annealed, but whenthe film thickness was decreased to 50nm, the permittivity decreased to only 100.

[5]

Transition-metal nitridesTransition-metal nitrides, such as TiN and TaN find potential use both as metal barriers and as gate metals.Metal barriers are used in modern Cu-based chips to avoid diffusion of Cu into the surrounding materials, such asinsulators and the silicon substrate, and also, to prevent Cu contamination by elements diffusing from theinsulators by surround every Cu interconnection with a layer of metal barriers. The metal barriers have strictdemands: they should be pure; dense; conductive; conformal; thin; have good adhesion towards metals andinsulators. The requirements concerning process technique can be fulfilled by ALD. The most studied ALD nitrideis TiN which is deposited from TiCl4 and NH3.

[6]

Metal filmsMotivations of an interest in metal ALD are1) Cu interconnects and W plugs, or at least Cu seed layers for Cu electrodeposition and Wseeds for W CVD,2) transition-metal nitrides (e.g. TiN, TaN, WN) for Cu interconnect barriers3) noble metals for ferroelectric random access memory (FRAM) and DRAM capacitorelectrodes4) high- and low-work function metals for dual-gate MOSFETs.


See also Atomic layer epitaxy Chemical vapor deposition Thin-film deposition High-k dielectric

References[1] http:/ / ald. colorado. edu/ J_Phys_Chem_100. pdf[2] T. Suntola, J. Antson, U.S. Patent 4,058,430, 1977[3] A. Ahnd, Semicond. Int. 26, 46-51, 2003.[4] http:/ / download. intel. com/ technology/ IEDM2007/ HiKMG_paper. pdf A 45nm Logic Technology with

High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100%Pb-free Packaging

[5] M. Vehkamaki et al., Electrochem. Solid-State Lett. 2, 504-506, 1999.[6] K.E. Elers et al.,Chem. Vap. Deposition 4,149, 2002

Mikko Ritala; Markku Leskel (March 1999). "Atomic layer epitaxya valuable tool fornanotechnology?". Nanotechnology 10 (1): 1924. doi: 10.1088/0957-4484/10/1/005(http:/ / dx. doi. org/ 10. 1088/ 0957-4484/ 10/ 1/ 005).

Markku Leskel; Mikko Ritala (2003). "Atomic Layer Deposition Chemistry: RecentDevelopments and Future Challenges". Angew. Chem. Int. Ed. 42: 55485554. doi:10.1002/anie.200301652 (http:/ / dx. doi. org/ 10. 1002/ anie. 200301652).

First use of ALD for DRAM applications (http:/ / www. micromagazine. com/ archive/ 05/07/ chipworks. html)

Suppliers of high quality ALD equipment (http:/ / www. cambridgenanotech. com/ ) (http:// www. picosun. com) (http:/ / www. beneq. com)

Journal articles discussing ALD (http:/ / ald. colorado. edu/ J_Phys_Chem_100. pdf) (http:// link. aip. org/ link/ ?JAPIAU/ 97/ 121301/ 1)

Academic researchers specializing in ALD (http:/ / chem. wayne. edu/ faculty/ winter/ )(http:/ / www. chem. harvard. edu/ groups/ gordon/ ) (http:/ / www. colorado. edu/ chem/people/ georges. html)

Major conferences dedicated to ALD (http:/ / www. phys. tue. nl/ ALD2008/ )

Molecular beam epitaxy 20

Molecular beam epitaxy

The Molecular Beam Epitaxy System in the William R. WileyEnvironmental Molecular Sciences Laboratory is used to grow

and characterize thin crystalline films of oxides and ceramics tounderstand in detail the chemistry that occurs on oxides and

ceramic surfaces.

Molecular beam epitaxy(MBE), is one of several methodsof depositing single crystals. It wasinvented in the late 1960s at BellTelephone Laboratories by J. R.Arthur and Alfred Y. Cho[1] .

MethodMolecular beam epitaxy takesplace in high vacuum or ultra highvacuum (108 Pa). The mostimportant aspect of MBE is theslow deposition rate (typically lessthan 1000 nm per hour), whichallows the films to growepitaxially. The slow depositionrates require proportionally bettervacuum to achieve the sameimpurity levels as other depositiontechniques.

In solid-source MBE, ultra-pure elements such as gallium and arsenic are heated inseparate quasi-knudsen effusion cells until they begin to slowly sublimate. The gaseouselements then condense on the wafer, where they may react with each other. In theexample of gallium and arsenic, single-crystal gallium arsenide is formed. The term "beam"means that evaporated atoms do not interact with each other or vacuum chamber gasesuntil they reach the wafer, due to the long mean free paths of the atoms.

During operation, RHEED (Reflection High Energy Electron Diffraction) is often used formonitoring the growth of the crystal layers. A computer controls shutters in front of eachfurnace, allowing precise control of the thickness of each layer, down to a single layer ofatoms. Intricate structures of layers of different materials may be fabricated this way. Suchcontrol has allowed the development of structures where the electrons can be confined inspace, giving quantum wells or even quantum dots. Such layers are now a critical part ofmany modern semiconductor devices, including semiconductor lasers and light-emittingdiodes.In systems where the substrate needs to be cooled, the ultra-high vacuum environmentwithin the growth chamber is maintained by a system of cryopumps, and cryopanels, chilledusing liquid nitrogen or cold nitrogen gas to a temperature close to 77 Kelvin (196degrees Celsius). Cryogenic temperatures act as a sink for impurities in the vacuum, sovacuum levels need to be several orders of magnitude better to deposit films under theseconditions. In other systems, the wafers on which the crystals are grown may be mountedon a rotating platter which can be heated to several hundred degrees Celsius duringoperation.


Molecular beam epitaxy is also used for the deposition of some types of organicsemiconductors. In this case, molecules, rather than atoms, are evaporated and depositedonto the wafer. Other variations include gas-source MBE, which resembles chemicalvapor deposition.

ATG instabilityThe ATG (Asaro-Tiller-Grinfeld) instability, also known as the Grinfeld instability, is anelastic instability often encountered during molecular beam epitaxy. If there is a mismatchbetween the lattice sizes of the growing film and the supporting crystal, elastic energy willbe accumulated in the growing film. At some critical height, the free energy of the film canbe lowered if the film breaks into isolated islands, where the tension can be relaxedlaterally. The critical height depends on Young moduli, mismatch size, and surface tensions.Some applications for this instability have been researched, such as the self-assembly ofquantum dots. This community uses the name of Stranski-Krastanov for ATG.

Notes1. Stangl, J.; V. Hol and G. Bauer (2004). "Structural properties of self-organized

semiconductor nanostructures [2]". Rev. Mod. Phys. 76 (3): 725783.doi:10.1103/RevModPhys.76.725 [3]. http:/ / link. aps. org/ doi/ 10. 1103/ RevModPhys.76. 725.

2. Shchukin, Vitaliy A.; Dieter Bimberg (1999). "Spontaneous ordering of nanostructures oncrystal surfaces [4]". Rev. Mod. Phys. 71 (4): 11251171.doi:10.1103/RevModPhys.71.1125 [5]. http:/ / prola. aps. org/ abstract/ RMP/ v71/ i4/p1125_1. Retrieved 2008-08-15.

3. Jaeger, Richard C. (2002). "Film Deposition". Introduction to MicroelectronicFabrication. Upper Saddle River: Prentice Hall. ISBN 0-201-44494-7.

See also Alfred Y. Cho Colin P Flynn Arthur Gossard Herbert Kroemer Ben G. Streetman Solar cell Wetting layer High Electron Mobility Transistor Heterojunction Bipolar Transistor Quantum cascade laser


External links Silicon and germanium nanowires by molecular beam epitaxy [6]

University of Texas MBE group [7]

Physics of Thin Films: Molecular Beam Epitaxy (class notes) [8]

References[1] A. Y. Cho and J. R. Arthur Jr., Molecular beam epitaxy, Prog. Solid State Chem., vol. 10, pp. 157-192, 1975[2] http:/ / link. aps. org/ doi/ 10. 1103/ RevModPhys. 76. 725[3] http:/ / dx. doi. org/ 10. 1103%2FRevModPhys. 76. 725[4] http:/ / prola. aps. org/ abstract/ RMP/ v71/ i4/ p1125_1[5] http:/ / dx. doi. org/ 10. 1103%2FRevModPhys. 71. 1125[6] http:/ / www. mpi-halle. mpg. de/ department2/ research-areas/ nanowires-nanoobjects/

si-ge-nanowhiskers-by-mbe/ abstract/[7] http:/ / www. ece. utexas. edu/ projects/ ece/ mrc/ groups/ street_mbe/ mbechapter. html[8] http:/ / www. uccs. edu/ ~tchriste/ courses/ PHYS549/ 549lectures/ mbe. html

Czochralski process

The Czochralski process

The Czochralski process is amethod of crystal growth usedto obtain single crystals ofsemiconductors (e.g. silicon,germanium and galliumarsenide), metals (e.g.palladium, platinum, silver,gold), salts, and syntheticgemstones. The process isnamed after Polish scientistJan Czochralski, whodiscovered the method in 1916while investigating the crystallization rates of metals.

The most important application may be the growth of large cylindrical ingots, or boules, ofsingle crystal silicon. Other semiconductors, such as gallium arsenide, can also be grown bythis method, although lower defect densities in this case can be obtained using variants ofthe Bridgman-Stockbarger technique.

Czochralski process 23

Production of Czochralski silicon

A puller rod with seed crystal forgrowing single-crystal silicon by the

Czochralski process

High-purity, semiconductor-grade silicon (only a fewparts per million of impurities) is melted down in acrucible, which is usually made of quartz. Dopantimpurity atoms such as boron or phosphorus can beadded to the molten intrinsic silicon in precise amountsin order to dope the silicon, thus changing it inton-type or p-type extrinsic silicon. This influences theelectrical conductivity of the silicon. A seed crystal,mounted on a rod, is dipped into the molten silicon. Theseed crystal's rod is pulled upwards and rotated at thesame time. By precisely controlling the temperaturegradients, rate of pulling and speed of rotation, it ispossible to extract a large, single-crystal, cylindrical ingot from the melt. Occurrence ofunwanted instabilities in the melt can be avoided by investigating and visualizing thetemperature and velocity fields during the crystal growth process.[1] This process isnormally performed in an inert atmosphere, such as argon, and in an inert chamber, suchas quartz.

Size of crystalsDue to the efficiencies that can be gained by the adoption of common waferspecifications, the semiconductor industry has for some time used wafers with standardizeddimensions. Currently, high-end device manufacturers use 200 mm and 300 mm diameterwafers. The crystal ingots from which these wafers are sliced can be up to 2 metres inlength, weighing several hundred kilograms. Larger wafers allow improvements inmanufacturing efficiency, as more chips can be fabricated on each wafer, so there has beena steady drive to increase silicon wafer sizes. The next step up, 450 mm, is currentlyscheduled for introduction in 2012[2] .Silicon wafers are typically about 0.2 - 0.75 mm thick, and can be polished to a very highflatness for making integrated circuits, or textured for making solar cells.

Impurity incorporationWhen silicon is grown by the Czochralski method, the melt is contained in a silica (quartz) crucible. During growth, the walls of the crucible dissolve into the melt and Czochralski silicon therefore contains oxygen at a typical concentration of 1018cm3. Oxygen impurities can have beneficial effects. Carefully chosen annealing conditions can allow the formation of oxygen precipitates. These have the effect of trapping unwanted transition metal impurities in a process known as gettering. Additionally, oxygen impurities can improve the mechanical strength of silicon wafers by immobilising any dislocations which may be introduced during device processing. It was experimentally shown in the 1990s that the high oxygen concentration is also beneficial for radiation hardness of silicon particle detectors used in harsh radiation environment (such as CERN's LHC/S-LHC projects).[3] [4] [5] Therefore, radiation detectors made of Czochralski- and Magnetic Czochralski-silicon are considered to be promising candidates for many future high-energy physics experiments.[6] [7] It has also been shown that presence of oxygen in silicon increases impurity trapping


during post-implantation annealing processes.[8]

However, oxygen impurities can react with boron in an illuminated environment, such asexperienced by solar cells. This results in the formation of an electrically activeboronoxygen complex that detracts from cell performance. Module output drops byapproximately 3% during the first few hours of light exposure. [9]

Mathematical expression of impurity incorporation from meltThe impurity concentration in the solid crystal that results from freezing an incrementalamount of volume can be obtained from consideration of the segregation coefficient. [10]

: Segregation coefficient: Initial volume: Number of impurities: Impurity concentration in the melt: Volume of the melt: Number of impurities in the melt: Concentration of impurities in the melt: Volume of solid: Concentration of impurities in the solid

During the growth process, volume of melt freezes, and there are impurities from themelt that are removed.


Gallery

Crucibles used in Czochralskimethod

Crucible after being used

Silicon ingot

See also Bridgman-Stockbarger technique Float-zone silicon Laser-heated pedestal growth Micro-Pulling-Down

External links Czochralski doping process [11]

References[1] J. Aleksic et al., Ann. of NY Academy of Sci. 972 (2002) 158.[2] http:/ / www. physorg. com/ news129301282. html[3] Z. Li et al., IEEE Trans Nucl. Sci. 39 (6) (1992) 1730[4] A. Ruzin et al., IEEE Trans Nucl. Sci. 46 (5) (1999) 1310[5] G. Lindstrm et al., Nucl. Instr. and Meth. A 466 (2001) 308 and cited literature therein.[6] CERN RD50 Status Report 2004, CERN-LHCC-2004-031 and LHCC-RD-005 and cited literature therein[7] J. Hrknen et al., Nucl. Instr. and Meth. A 541 (2005)202.[8] A. Polman et al., J. Appl. Phys., Vol. 75, No. 6, 15 March 1994[9] Eikelboom, J.A., Jansen, M.J., 2000. Characteristion of PV modules of new generations; results of tests and

simulations. Report ECN-C-00-067, 18.[10] James D. Plummer, Michael D. Deal, and Peter B. Griffin, Silicon VLSI Technology, Prentice Hall, 2000, p.

126-27[11] http:/ / www. articleworld. org/ index. php/ Czochralski_process

Plasma ashing 26

Plasma ashingIn semiconductor manufacturing plasma ashing is the process of removing the photoresistfrom an etched wafer. Using a plasma source, a monatomic reactive species is generated.Oxygen or fluorine are the most common reactive species. The reactive species combineswith the photoresist to form ash which is removed with a vacuum pump.Typically, monatomic (single atom) oxygen plasma is created by exposing oxygen gas (O2)to non-ionizing radiation. This process is done under vacuum in order to create a plasma. Asthe plasma is formed, many free radicals are created which could damage the wafer.Newer, smaller circuitry is increasingly susceptible to these particles. Originally, plasmawas generated in the process chamber, but as the need to get rid of free radicals hasincreased, many machines now use a downstream plasma configuration, where plasma isformed remotely and the desired particles are channeled to the wafer. This allowselectrically charged particles time to recombine before they reach the wafer surface, andprevents damage to the wafer surface.Two forms of plasma ashing are typically performed on wafers. High temp ashing, orstripping, is performed to remove as much photo resist as posible. While the "descum"process is used to remove residual photo resist in trenches. The main difference betweenthe two processes are the temperature the wafer is exposed to while in an ashing chamber.Monatomic oxygen is electrically neutral and although it does recombine during thechanneling, it does so at a slower rate than the positively or negatively charged freeradicals, which attract one another. Effectively, this means that when all of the free radicalshave recombined, there is still a portion of the active species available for process. Becausea large portion of the active species is lost to recombination, process times may take longer.To some extent, these longer process times can be mitigated by increasing the temperatureof the reaction area.

Rapid thermal processing 27

Rapid thermal processingRapid Thermal Processing (or RTP) refers to a semiconductor manufacturing processwhich heats silicon wafers to high temperatures (up to 1200 C or greater) on a timescale ofseveral seconds or less. During cooling, however, wafer temperatures must be broughtdown slowly so they do not break due to thermal shock. Such rapid heating rates are oftenattained by high intensity lamps or lasers. These processes are used for a wide variety ofapplications in semiconductor manufacturing including dopant activation, thermaloxidation, metal reflow and chemical vapor deposition.

Temperature ControlOne of the key challenges in rapid thermal processing is accurate measurement and controlof the wafer temperature. Monitoring the ambient with a thermocouple has only recentlybecome feasible, in that the high temperature ramp rates prevent the wafer from coming tothermal equilibrium with the process chamber. One temperature control strategy involvesin situ pyrometry to effect real time control.

Rapid thermal annealRapid thermal anneal (RTA) is a subset of Rapid Thermal Processing. It is a process used insemiconductor device fabrication which consists of heating a single wafer at a time inorder to affect its electrical properties. Unique heat treatments are designed for differenteffects. Wafers can be heated in order to activate dopants, change film-to-film orfilm-to-wafer substrate interfaces, densify deposited films, change states of grown films,repair damage from ion implantation, move dopants or drive dopants from one film intoanother or from a film into the wafer substrate.Rapid thermal anneals are performed by equipment that heats a single wafer at a timeusing either lamp based heating, a hot chuck, or a hot plate that a wafer is brought near.Unlike furnace anneals they are short in duration, processing each wafer in severalminutes.To achieve short time annealing time trade off is made in temperature and processuniformity ,temperature measurement and control and wafer stress as well as throughput.Recently, RTP-like processing has found applications in another rapidly growing field solar cell fabrication. RTP-like processing, in which an increase in the temperature of thesemiconductor sample is produced by the absorption of the optical flux, is now used for ahost of solar cell fabrication steps, including phosphorus diffusion for N/P junctionformation and impurity gettering, hydrogen diffusion for impurity and defect passivation,and formation of screen-printed contacts using Ag-ink for the front and Al-ink for backcontacts, respectively.

Rapid thermal processing 28

External links | IEEE RTP Conference Homepage [1]

History of RTP [2]

Semiconductor International article on RTP technology [3]

Rapid Thermal Anneal applications and components [4]

References[1] http:/ / www. ieee-rtp. org/[2] http:/ / www. ieee-rtp. org/ archiv/ rtp_history. pdf|[3] http:/ / www. reed-electronics. com/ semiconductor/ article/ CA338200|[4] http:/ / www. articleworld. org/ index. php/ Rapid_thermal_anneal

Furnace annealFurnace annealing is a process used in semiconductor device fabrication which consist ofheating multiple semiconductor wafers in order to affect their electrical properties. Heattreatments are designed for different effects. Wafers can be heated in order to activatedopants, change film to film or film to wafer substrate interfaces, densify deposited films,change states of grown films, repair damage from implants, move dopants or drivedopants from one film into another or from a film into the wafer substrate.Furnace anneals may be integrated into other furnace processing steps, such as oxidations,or may be processed on their own.Furnace anneals are performed by equipment especially built to heat semiconductorwafers. Furnaces are capable of processing lots of wafers at a time but each process canlast between several hours and a day.Increasingly, furnace anneals are being supplanted by Rapid Thermal Anneal (RTA) orRapid Thermal Processing (RTP). The reason for this is the relatively long thermal cycles offurnaces causes dopants that are being actived, especially boron, to diffuse farther than isintended. RTP or RTA fixes this by having thermal cycles for each wafer that is of the orderof minutes rather than hours for furnace anneals.

Equipment Aviza AVP [1]

Tokyo Electron alpha [2]

Kokusai [3] Vertron, Zestone, and ALDINNA ASM Advance 400 [4]

References[1] http:/ / www. aviza. net/ products/ vert. htm[2] http:/ / www. tel. com/ eng/ product/ spe/ tps/ butps. htm[3] http:/ / www. ksec. com[4] http:/ / www. asm. com/ prod_adv400. asp

Ion implantation 29

Ion implantation

An ion implantation system at LAAS technologicalfacility in Toulouse, France.

Ion implantation is a materialsengineering process by which ions of amaterial can be implanted into anothersolid, thereby changing the physicalproperties of the solid. Ion implantation isused in semiconductor device fabricationand in metal finishing, as well as variousapplications in materials science research.The ions introduce both a chemical changein the target, in that they can be a differentelement than the target, and a structuralchange, in that the crystal structure of thetarget can be damaged or even destroyed bythe energetic collision cascades.

General principle

Ion implantation setup with massseparator

Ion implantation equipment typically consists of an ionsource, where ions of the desired element areproduced, an accelerator, where the ions areelectrostatically accelerated to a high energy, and atarget chamber, where the ions impinge on a target,which is the material to be implanted. Thus ionimplantation is a special case of particle radiation. Eachion is typically a single atom or molecule, and thus theactual amount of material implanted in the target is theintegral over time of the ion current. This amount iscalled the dose. The currents supplied by implantersare typically small (microamperes), and thus the dosewhich can be implanted in a reasonable amount of timeis small. Thus, ion implantation finds application incases where the amount of chemical change required is small.

Ion implantation 30

Typical ion energies are in the range of 10 to 500 keV (1,600 to 80,000 aJ). Energies in therange 1 to 10 keV (160 to 1,600 aJ) can be used, but result in a penetration of only a fewnanometers or less. Energies lower than this result in very little damage to the target, andfall under the designation ion beam deposition. Higher energies can also be used:accelerators capable of 5 MeV (800,000 aJ) are common. However, there is often greatstructural damage to the target, and because the depth distribution is broad, the netcomposition change at any point in the target will be small.The energy of the ions, as well as the ion species and the composition of the targetdetermine the depth of penetration of the ions in the solid: A monoenergetic ion beam willgenerally have a broad depth distribution. The average penetration depth is called therange of the ions. Under typical circumstances ion ranges will be between 10 nanometersand 1 micrometer. Thus, ion implantation is especially useful in cases where the chemicalor structural change is desired to be near the surface of the target. Ions gradually lose theirenergy as they travel through the solid, both from occasional collisions with target atoms(which cause abrupt energy transfers) and from a mild drag from overlap of electronorbitals, which is a continuous process. The loss of ion energy in the target is calledstopping.

Application in semiconductor device fabrication

DopingThe introduction of dopants in a semiconductor is the most common application of ionimplantation. Dopant ions such as boron, phosphorus or arsenic are generally created froma gas source, so that the purity of the source can be very high. These gases tend to be veryhazardous. When implanted in a semiconductor, each dopant atom creates a charge carrierin the semiconductor (hole or electron, depending on if it is a p-type or n-type dopant), thusmodifying the conductivity of the semiconductor in its vicinity.

Silicon on insulatorOne prominent method for preparing silicon on insulator (SOI) substrates fromconventional silicon substrates is the SIMOX (Separation by IMplantation of OXygen)process, wherein a buried high dose oxygen implant is converted to silicon oxide by a hightemperature annealing process.

MesotaxyMesotaxy is the term for the growth of a crystallographically matching phase underneaththe surface of the host crystal (compare to epitaxy, which is the growth of the matchingphase on the surface of a substrate). In this process, ions are implanted at a high enoughenergy and dose into a material to create a layer of a second phase, and the temperature iscontrolled so that the crystal structure of the target is not destroyed. The crystalorientation of the layer can be engineered to match that of the target, even though theexact crystal structure and lattice constant may be very different. For example, after theimplantation of nickel ions into a silicon wafer, a layer of nickel silicide can be grown inwhich the crystal orientation of the silicide matches that of the silicon.

Ion implantation 31

Application in metal finishing

Tool steel tougheningNitrogen or other ions can be implanted into a tool steel target (drill bits, for example). Thestructural change caused by the implantation produces a surface compression in the steel,which prevents crack propagation and thus makes the material more resistant to fracture.The chemical change can also make the tool more resistant to corrosion.

Surface finishingIn some applications, for example prosthetic devices such as artificial joints, it is desired tohave surfaces very resistant to both chemical corrosion and wear due to friction. Ionimplantation is used in such cases to engineer the surfaces of such devices for more reliableperformance. As in the case of tool steels, the surface modification caused by ionimplantation includes both a surface compression which prevents crack propagation and analloying of the surface to make it more chemically resistant to corrosion.

Problems with ion implantation

Crystallographic damageEach individual ion produces many point defects in the target crystal on impact such asvacancies and interstitials. Vacancies are crystal lattice points unoccupied by an atom: inthis case the ion collides with a target atom, resulting in transfer of a significant amount ofenergy to the target atom such that it leaves its crystal site. This target atom then itselfbecomes a projectile in the solid, and can cause successive collision events. Interstitialsresult when such atoms (or the original ion itself) come to rest in the solid, but find novacant space in the lattice to reside. These point defects can migrate and cluster with eachother, resulting in dislocation loops and other defects.

Damage recoveryBecause ion implantation causes damage to the crystal structure of the target which isoften unwanted, ion implantation processing is often followed by a thermal annealing. Thiscan be referred to as damage recovery.

AmorphizationThe amount of crystallographic damage can be enough to completely amorphize the surfaceof the target: i.e. it can become an amorphous solid (such a solid produced from a melt iscalled a glass). In some cases, complete amorphization of a target is preferable to a highlydefective crystal: An amorphized film can be regrown at a lower temperature than requiredto anneal a highly damaged crystal.

Ion implantation 32

SputteringSome of the collision events result in atoms being ejected (sputtered) from the surface, andthus ion implantation will slowly etch away a surface. The effect is only appreciable for verylarge doses.

Ion channelling

A diamond cubiccrystal viewed from

the direction,showing hexagonal

ion channels.

If there is a crystallographic structure to the target, and especially insemiconductor substrates where the crystal structure is more open,particular crystallographic directions offer much lower stopping thanother directions. The result is that the range of an ion can be muchlonger if the ion travels exactly along a particular direction, forexample the direction in silicon and other diamond cubicmaterials. This effect is called ion channelling, and, like all thechannelling effects, is highly nonlinear, with small variations fromperfect orientation resulting in extreme differences in implantationdepth. For this reason, most implantation is carried out a few degreesoff-axis, where tiny alignment errors will have more predictableeffects. There is no relation between this effect and ion channel of acell membrane.

Ion channelling can be used directly in Rutherford backscattering and related techniques asan analytical method to determine the amount and depth profile of damage in crystallinethin film materials.

Hazardous Materials NoteIn the ion implantation semiconductor fabrication process of wafers, it is important forthe workers to minimize their exposure to the toxic materials used in the ion implanterprocess. Such hazardous elements, solid source and gasses are used, such as Arsine andPhosphine. For this reason, the semiconductor fabrication facilities are highly automated,and may feature negative pressure gas bottles safe delivery system (SDS). Other elementsmay include Antimony, Arsenic, Phosphorus, and Boron. Residue of these elements show upwhen the machine is opened to atmosphere, and can also be accumulated and foundconcentrated in the vacuum pumps hardware. It is important not to expose yourself to thesecarcinogenic, corrosive, flammable, and toxic elements. Many overlapping safety protocolsmust be used when handling these deadly compounds. Use safety, and read MSDS's.

High Voltage SafetyHigh voltage power supplies in ion implantation equipment can pose a risk of electrocution.In addition, high-energy atomic collisions can, in some cases, generate radionuclides.Operators and Maintenance personnel should learn and follow the safety advice of themanufacturer and/or the institution responsible for the equipment. Prior to entry to highvoltage area, terminal components must be grounded using a grounding stick. Next, powersupplies should be locked in the off state and tagged to prevent unauthorized energizing.

Ion implantation 33

Manufacturers of Ion Implantation Equipment Advanced Ion Beam Technology [1]

Applied Materials [2]

Axcelis Technologies [3]

Complete Ions [4]

Facilitation Centre for Industrial Plasma Technologies [5]

Global Technologies, R&D equipment and Service [6]

Ion Beam Services [7]

Nissin Ion Equipment [8]

SemEquip [9]

SEN Corporation (a SHI and Axcelis company) [10]

Tokyo Electron Limited [11]

Ulvac Technologies [12]

Varian Semiconductor Equipment [13]

External links SEMI [14] -- a semiconductor standards clearinghouse and trade organization Ion Implantation [15]

James Ziegler's code for simulating ion implantation. [16]

References[1] http:/ / www. aibt-inc. com[2] http:/ / www. appliedmaterials. com[3] http:/ / www. axcelis. com[4] http:/ / www. completeions. com[5] http:/ / www. plasmaindia. com[6] http:/ / www. global-technologies. fr[7] http:/ / www. ion-beam-services. com[8] http:/ / www. nissin-ion. co. jp[9] http:/ / www. semequip. com[10] http:/ / www. senova. co. jp/ english/ index. html[11] http:/ / www. tel. com/ eng/ about/ index. htm[12] http:/ / www. ulvac. com[13] http:/ / www. vsea. com[14] http:/ / www. semi. org[15] http:/ / www. casetechnology. com/ implant. html[16] http:/ / www. srim. org

Etching (microfabrication) 34

Etching (microfabrication)

Etching tanks used to perform Piranha, Hydrofluoricacid or RCA clean on 4-inch wafer batches at LAAS

technological facility in Toulouse, France.

Etching is used in microfabrication tochemically remove layers from the surfaceof a wafer during manufacturing. Etchingis a critically important process module,and every wafer undergoes many etchingsteps before it is complete.

For many etch steps, part of the wafer isprotected from the etchant by a "masking"material which resists etching. In somecases, the masking material is photoresistwhich has been patterned using photolithography. Other situations requirea more durable mask, such as siliconnitride.

Figures of meritIf the etch is intended to make a cavity in a material, the depth of the cavity may becontrolled approximately using the etching time and the known etch rate. More often,though, etching must entirely remove the top layer of a multilayer structure, withoutdamaging the underlying or masking layers. The etching system's ability to do this dependson the ratio of etch rates in the two materials (selectivity).

Some etches undercut the masking layer and form cavities with sloping sidewalls. Thedistance of undercutting is called bias. Etchants with large bias are called isotropic,because they erode the substrate equally in all directions. Modern processes greatly preferanisotropic etches, because they produce sharp, well-controlled features.

Selectivity Yellow: layer to be removed; blue: layer to remain1. A poorly selective etch removes the top layer, but also attacks the

underlying material.2. A highly selective etch leaves the underlying material unharmed.

Isotropy Red: masking layer; yellow: layer to be removed1. A perfectly isotropic etch produces round sidewalls.2. A perfectly anisotropic etch produces vertical sidewalls.


Etching media and technologyThe two fundamental types of etchants are liquid-phase ("wet") and plasma-phase ("dry").Each of these exists in several varieties.

Wet etchingThe first etching processes used liquid-phase ("wet") etchants. The wafer can be immersedin a bath of etchant, which must be agitated to achieve good process control. For instance,buffered hydrofluoric acid (BHF) is used commonly to etch silicon dioxide over a siliconsubstrate.Different specialised etchants can be used to characterise the surface etched.Wet etchants are usually isotropic, which leads to large bias when etching thick films. Theyalso require the disposal of large amounts of toxic waste. For these reasons, they areseldom used in state-of-the-art processes. However, the photographic developer used forphotoresist resembles wet etching.As an alternative to immersion, single wafer machines use the Bernoulli principle to employa gas (usually, pure nitrogen) to cushion and protect one side of the wafer while etchant isapplied to the other side. It can be done to either the front side or back side. The etchchemistry is dispensed on the top side when in the machine and the bottom side is notaffected. This etch method is particularly effective just before "backend" processing(BEOL), where wafers are normally very much thinner after wafer backgrinding, and verysensitive to thermal or mechanical stress. Etching a thin layer of even a few micrometreswill remove microcracks produced during backgrinding resulting in a the wafer havingdramatically increased strength and flexibility without breaking.

Anisotropic wet etching

An anisotropic wet etch on a silicon wafer creates a cavitywith a trapezoidal cross-section. The bottom of the cavity is a plane (see Miller indices), and the sides are planes. The yellow material is an etch mask, and the blue

material is silicon.

Some wet etchants etch crystallinematerials at very different ratesdepending upon which crystal face isexposed. In single-crystal materials(e.g. silicon wafers), this effect canallow very high anisotropy, as shownin the figure.

Several anisotropic wet etchants areavailable for silicon. For instance,potassium hydroxide (KOH) canachieve selectivity of 400 between and planes. Anotheroption is EDP (an aqueous solution ofethylene diamine and pyrocatechol),which also displays high selectivityfor p-type doping. Neither of these etchants may be used on wafers that contain CMOSintegrated circuits. Both of them etch aluminium, commonly used as a metallization (wiring)material. KOH introduces mobile potassium ions into silicon dioxide, and EDP is highly

corrosive and carcinogenic. Tetramethylammonium hydroxide (TMAH) presents a safer alternative, although it has even worse selectivity between and planes in


silicon than does EDP.

Plasma etchingModern VLSI processes avoid wet etching, and use plasma etching instead. Plasmaetchers can operate in several modes by adjusting the parameters of the plasma. Ordinaryplasma etching operates between 0.1 and 5 torr. (This unit of pressure, commonly used invacuum engineering, equals approximately 133.3 pascals.) The plasma produces energeticfree radicals, neutrally charged, that react at the surface of the wafer. Since neutralparticles attack the wafer from all angles, this process is isotropic.The source gas for the plasma usually contains small molecules rich in chlorine or fluorine.For instance, carbon tetrachloride (CCl4) etches silicon and aluminium, andtrifluoromethane etches silicon dioxide and silicon nitride. A plasma containing oxygen isused to oxidize (" ash") photoresist and facilitate its removal.Ion milling, or sputter etching, uses lower pressures, often as low as 10-4 torr (10 mPa). Itbombards the wafer with energetic ions of noble gases, often Ar+, which knock atoms fromthe substrate by transferring momentum. Because the etching is performed by ions, whichapproach the wafer approximately from one direction, this process is highly anisotropic. Onthe other hand, it tends to display poor selectivity. Reactive-ion etching (RIE) operatesunder conditions intermediate between sputter and plasma etching (between 10-3 and 10-1

torr). Deep reactive-ion etching (DRIE) modifies the RIE technique to produce deep,narrow features.

Common etch processes used in microfabrication Etchants for common microfabrication materials

Material to beetched

Wet etchants Plasma etchants

Aluminium (Al) 80% phosphoric acid (H3PO4) + 5% acetic acid+ 5% nitric acid (HNO3) + 10% water (H2O) at 3545C

[1]Cl2, CCl4, SiCl4, BCl3

[2]

Indium tin oxide [ITO](In2O3:SnO2)

Hydrochloric acid (HCl) + nitric acid (HNO3) + water (H2O)(1:0.1:1) at 40C[3]

Chromium (Cr) "Chrome etch": ceric ammonium nitrate((NH4)2Ce(NO3)6) + nitric acid (HNO3)

[4]

Hydrochloric acid (HCl)[4]

Gold (Au) Aqua regia

Molybdenum (Mo) CF4[2]

Organic residues andphotoresist

Piranha etch: sulfuric acid (H2SO4) + hydrogen peroxide(H2O2)

O2 ( ashing)

Platinum (Pt) Aqua regia

Silicon (Si) Nitric acid (HNO3) + hydrofluoric acid (HF)[1] CF4, SF6, NF3

[2]

Cl2, CCl2F2[2]

Silicon dioxide (SiO2) Hydrofluoric acid (HF)[1]

Buffered oxide etch [BOE]: ammonium fluoride (NH4F)and hydrofluoric acid (HF)[1]

CF4, SF6, NF3[2]


Silicon nitride (Si3N4) 85% Phosphoric acid (H3PO4) at 180C[1] (Requires SiO2

etch mask) Hydrofluoric acid (HF)[1]

CF4, SF6, NF3[2]

Tantalum (Ta) CF4[2]

Titanium (Ti) Hydrofluoric acid (HF)[1] BCl3[5]

Titanium nitride(TiN)

Nitric acid (HNO3) + hydrofluoric acid (HF) SC1

Tungsten (W) Nitric acid (HNO3) + hydrofluoric acid (HF) Hydrogen Peroxide (H2O2)

CF4[2]

SF6

References Jaeger, Richard C. (2002). "Lithography". Introduction to Microelectronic Fabrication.

Upper Saddle River: Prentice Hall. ISBN 0-201-44494-7. Ibid, "Processes for MicroElectroMechanical Systems (MEMS)"

See also Chemical-Mechanical Polishing Ingot sawing

External links BYU Cleanroom Chemical Etching [6]

References[1] Wolf, S.; R.N. Tauber (1986). Silicon Processing for the VLSI Era: Volume 1 - Process Technology. Lattice

Press. pp.531534. ISBN 0-961672-3-7.[2] Wolf, S.; R.N. Tauber (1986). Silicon Processing for the VLSI Era: Volume 1 - Process Technology. Lattice

Press. p.546. ISBN 0-961672-3-7.[3] Bahadur, Birendra (1990). Liquid Crystals: Applications and Uses. World Scientific. p.183. ISBN 9810229755.[4] Walker, Perrin; William H. Tarn (1991). CRC Handbook of Metal Etchants. pp.287291. ISBN 0-8949-3623-6.[5] Kohler, Michael (1999). Etching in Microsystem Technology. John Wiley & Son Ltd. p.329. ISBN 3527295615.[6] http:/ / www. ee. byu. edu/ cleanroom/ chemical. phtml

Dry etching 38

Dry etchingDry etching refers to the removal of material, typically a masked pattern of semiconductormaterial, by exposing the material to a bombardment of ions (usually a plasma of reactivegases such as fluorocarbons, oxygen, chlorine, boron trichloride; sometimes with additionof nitrogen, argon, helium and other gases) that dislodge portions of the material from theexposed surface. Unlike with many (but not all, see isotropic etching) of the wet chemicaletchants used in wet etching, the dry etching process typically etches directionally oranisotropically.

ExplanationDry etching is used in conjunction with photolithographic techniques to attack certainareas of a semiconductor surface in order to form recesses in material, such as contactholes (which are contacts to the underlying semiconductor substrate) or via holes (whichare holes that are formed to provide an interconnect path between conductive layers in thelayered semiconductor device) or to otherwise remove portions of semiconductor layerswhere predominantly vertical sides are desired. In conjunction with semiconductormanufacturing, micromachining and display production the removal of organic

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