Sem5 ae final ae 2014 2006

1. a) Explain two methods to create a connection to several multi-stage amplifier.

[2 marks] b) For a transformer with primary and secondary windings ratio as n1 : n2 and the

load on the secondary terminals , ZL , show that input impedance for

transformers is Li Zn

nZ

2

2

1

[4 marks]

c) Give two reasons for using a multistage amplifier over a single-stage circuit in a design.

[4 marks]

d) Figure 1 is a multi-stage amplifier circuit using coupling transformers

Figure 1

If the hybrid parameters for the transistor are hie =2K, hfe = 50, hre = hoe = 0

Calculate the voltage gain Av=vo/vi for this amplifier.

[10 marks]

2. a) Power amplifier are generally classified according to the percent of time the

output transistors are conducting or ‘turned on’. Based on the statement, how

Class-A, Class-B and Class-AB amplifier are classified? Discuss the advantage and

disadvantage between Class-A and Class-B amplifier.

[6 marks] b) Explain the following on a differential amplifier

i) common mode

ii) differential mode

iii) CMRR (common mode rejection ratio)

[6 marks]

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c) A differential amplifier with differential mode gain, Ad = 105 and CMRR = 104.

The input voltage is v1 = 105 V and v2 = 95 V. Calculate

i) common mode voltage, vc

ii) differential mode voltage, vd

iii) the magnitude of the common mode gain, AC

iv) the output voltage, vo

[8 marks]

3) a) Give four (4) main characteristics of the Operational Amplifier (Op-Amp)

[4 marks]

b) Refer to the Op-Amp circuit in Figure 3a, sketch the output voltage, vo when the

input voltage, vi = 10V sin t.

[4 marks]

c) Refer to the op-amp circuit shown in Figure 3b;

i) Which point is known as ”virtual ground” and why?

ii) Which resistor is the feedback resistor?

iii) Find the voltage gain, Av

iv) Sketch the input voltage, Vin =(2V)Sint and the output voltage, Vo for

R1=1k and R2=5k.

[8 marks]

+15V

-15V

vi

vo

7V

-

Figure 3a

+

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Figure 3b

d) Design an OP-AMP summing amplifier circuit that can produce an ouput voltage,

)5.0( 321O VVVV where V1, V2 and V3 are the input voltages. Set the

feedback resistor equal to 2k and the supply voltage equal to 15V.

[4 marks]

4) a) State de Morgan theorems. [2 marks]

Convert the following Boolean expression to their minterm and maxterm form.

i) CABAABCY

ii) ))(( DCBADACBY

[6 marks]

b) Prepare a truth table for the following Boolean expression, zyxF

[4 marks]

c) Table 1 is a part of the truth table for a 2-bit comparator circuit. The input to the

comparator is number 2 bits, A = {A1, A0} and B = {B1, B0}. Comparator output

is G and L which will show whether the two numbers A and B is greater or

smaller. If A> B then G = 1 and if B> A then L = 1. If A = B then G = L = 0.

i) Complete the truth table.

ii) Write the Boolean expression for G and L from the truth table.

iii) Simplify the expression for G and L using Karnaugh map

iii) Draw the logic circuit for the expression of G and L

[8 marks]

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Table 1

5). a) Explain the following flip-flops (Truth table, logic symbol and its operation):

i) RS Flip-Flop

ii) D Flip-Flop

iii) JK Flip-Flop

[6 marks]

b) Sketch the waveform of the output Y against the input X of figure 5(a).

[4 marks]

A1 A0 B1 B0 G L

0 0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0 1

0 1 0 0 0

0 1 0 1 0 0

0 1 1 0 1

0 1 1 1 0

1 0 0 0 1 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 0

1 1 0 0 1 0

1 1 0 1 0

1 1 1 0 0

1 1 1 1 0 0

2-bit Comparator

A=A1A0 B=B1B0

G L

Figure 5(a)

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c) Explain the followings with their truth table, logic diagram and its operation:

i) Decade counter (Modulo 10 counter)

ii) Step down counter

[6 marks]

d) Sketch the output waveforms, A, B, C and D after each clock pulse for the shift

register shown in Figure 5(b).

[4 marks]

A

B

C

D

Figure 5(b)

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1. (a) What is a cascade amplifier?

Show that the overall gain, A of an n-stages cascade amplifier is

nAAAAA ...321

[4 marks]

(b) Figure 1 shows a two-stage RC-coupled amplifier. The h-parameter of

both transistors are hie = 1 k and hfe = 100. The values of hre, hoe and the biasing network can be neglected. The amplifier is operating in its

midband region. Draw the ac equivalent circuit and the parameter-h

equivalent circuit of the amplifier.

+ V

CC

R11

R12

RC1

RE

CE

C1

C2100 k 1 k

10 k

RS

1 k

R21

R22

100 k

10 k

RC2

RE

1 k

vO

vs

CE

Figure 1

[8 marks]

(c) Calculate the voltage gain of the amplifier circuit shown in Figure 1.

[ 8 marks]

2. (a) Describe the following parameter in a differential amplifier:

(i) Common - mode gain

(ii) Differential- mode gain

(iii) Common mode rejection ratio (CMRR)

[6 marks]

(b) When the inputs to a certain differential amplifier are vi1 = 0.1sint and

vi2 = - 0.1sint, it is found that the outputs are vo1 = - 5sint and vo2 =

5sint. When both inputs are 2sint, the outputs are vo1 = - 0.05sint

and vo2 = 0.05sint. Find the CMRR in dB. [8 marks]

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(c) Figure 2 shows a differential amplifier. For transistors Q1 and Q2, hfe =

90 and hie = 1 k. Calculate the DC values of IE, IC and VC.

Q1

Q2

VEE

= - 20 V

vE

RC1 R

C2

IE

VCC

= 20 V

10 k10 k

RE 10 k

IC1

vC1

vi

Figure 2

[6 marks]

3. (a) State the condition for impedance matching between two circuits or

electronic equipments and suggest a method to solve the problem of

impedance mismatch using an operational amplifier.

[6 marks]

(b) What is meant by slew rate and explain how it affects the performance

of an operational amplifier.

[6 marks]

(c) Figure 3 shows an operational amplifier circuit. Calculate the voltages

V1 and Vo.

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+

-

+

-

V i = 3 V

V 1

V o

10 k

10 k

10 k

10 k

10 k

Figure 3

[8 marks]

4. (a) Convert the following numbers

i) binary number 1100 0011 1101 to hexadecimal number.

(ii) Hexadecimal 9A2 to binary.

(iii) Hexadecimal number ABC to decimal number.

[6 marks]

(b) Write the Boolean expression for the logic circuit shown in Figure 4 and

draw a three variable truth table of the logic function.

Figure 4

[4 marks]

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(c) A 4-input circuit has an output, Y, given by the truth table below

A B C D Y A B C D Y

0 0 0 0 0 1 0 0 0 1

0 0 0 1 1 1 0 0 1 1

0 0 1 0 1 1 0 1 0 0

0 0 1 1 1 1 0 1 1 0

0 1 0 0 1 1 1 0 0 0

0 1 0 1 1 1 1 0 1 0

0 1 1 0 1 1 1 1 0 0

0 1 1 1 1 1 1 1 1 0

i) Write down the unsimplified Boolean expression

ii) Use a Karnaugh Map to minimise the Boolean expression

iii) Draw a circuit to solve this problem using a 1-of -8 data selector.

[10 marks]

5. (a) Draw a logic symbol and truth table for the following flip-flops:

(i) J-K

(ii) Clocked R-S

[4 marks]

(b) i) List and explain two types of edge triggered flip-flops.

[2 marks]

ii) Referring to the block diagram of the JK flip-flop in Figure 5(a),

sketch the output Q corresponds to the inputs CLK, PS, J, K and

CLR given in Figure 5(b).

[4 marks]

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(c) (i) What type of flip-flops are useful in wiring counters.

(ii) Draw a logic symbol diagram for a 2-bit ripple down counter.

(iii) Redesign the 2-bit counter in (ii) to count from 11 to 00 and then

stop.

[5 marks]

Figure 5(a)

J

CLK

PS

Q

CLR

K Q

Figure 5(b)

CLK

PS

CLR

K

Q

time

Q

J

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(iv) List the binary counting sequence for counter circuit in Figure 5(c).

[5 marks]

Figure 5(c)

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1. Referring to Figure 1, the transistor has the following parameters:

hie = 1 k, hfe = 100, hoe = 0.2 mS, hre = 0.

+VCC

B

C

E

C1

C2

40 k1.5 k

10 k 300 Vo

Vi

Figure 1

(a) Draw the AC equivalent circuit for the circuit given in Figure 1.

[5 marks]

(b) Draw the hybrid equivalent circuit for the circuit given in Figure 1.

[8 marks]

(c) Determine

(i) the input resistance,

(ii) the output resistance,

(iii) the voltage gain, and

(iv) the current gain

of the amplifier

[ 12 marks]

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2. (a) What is a cascade amplifier and show that the overall gain, A of an n-

stages cascade amplifier is

nAAAAA ...321

[5 marks]

(b) Two of the amplifier stages, as shown in Figure 1, are connected in

cascade. A load resistance of 1 k is connected to the output of the second stage. Draw the small signal equivalent circuit of the cascade

amplifier together with the load.

[8 marks]

(c) Determine the total voltage gain of the cascade amplifier

[12 marks]

3. (a) State the condition for impedance matching between any two circuits or

electronic equipments.

[6 marks]

(b) Suggest a method to solve the problem of impedance mismatch

between any two circuits using an operational amplifier.

[7 marks]

+ V

- V

R2

R1

vi v

o

Figure 2

(c) Figure 2 shows an operational amplifier circuit built to operate as an

inverting amplifier. The gain is required to be fully variable between a

minimum of -1 and a maximum of -11.

(i) Suggest how this might be achieved, sketching a suitable circuit

and calculating component values.

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[8 marks]

(ii) What restrictions are there for the input signal voltage when the

amplifier is at maximum gain?

[4 marks]

4. (a) What is the difference between combinational logic circuits and

sequential logic circuits?

[5 marks]

(b) Consider an oven along with the associated input and output signals,

shown in Figure 3. The operation of the oven is as follows:

(i) The heater (H) will be ON when the power switch (P) is ON, the

door (D) is closed, and the temperature (T) is below the limit.

(ii) The fans (F) will be turned ON when the heater (H) is ON or

when the temperature (T) is above the limit and the door (D) is

closed

(iii) The light (L) will be turned ON if the light switch (S) is ON or

whenever the door (D) is opened

Write the Boolean expressions for the heater (H), the fans (F) and the

light (L) which govern the operation of the oven and construct the logic

circuit to accomplish the operation.

Figure 3

[10 marks]

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(c) Given the following Boolean expression:

DCBADCBA

DCBADCBADCBADCBAY

Simplify the Boolean expression using Karnaugh map and construct the

logic circuit for the simplified Boolean expression.

[ 10 marks]

5. (a) Describe with the aid of device symbol and truth table, the three types

of flip-flops; RS-FF, D-FF and JK-FF..

[9 marks]

(b) Referring to the block diagram of the D flip-flop in Figure 4(a), copy

the timing diagram in Figure 4(b) and sketch the output Q and Q

correspond to the inputs CLK, PS, D and CLR of the flip-flop.

Figure 4

[8 marks]

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(c) Referring to the block diagram of the JK flip-flop in Figure 5(a), copy

the timing diagram in Figure 5(b) and sketch the output Q corresponds

to the inputs CLK, PS, J, K and CLR of the flip-flop.

Figure 5

[8 marks]

Elektronik Lanjutan SSP2323

2

1. Bagi litar dalam Rajah 1, parameter transistor adalah = 100 dan VA = .

(a) Lukis litar setara isyarat kecil hybrid- . [4 markah]

(b) Tentukan:

(i) nilai gm dan r. [4 markah]

(ii) gandaan voltan isyarat-kecil, Avs = vo / vs. [4 markah]

(iii) rintangan masukan amplifier, Ri [4 markah]

(iv) gandaan arus isyarat-kecil, Ais = io / is [4 markah]

Rajah 1

2. Berpandukan litar pada Rajah 2,

(i) lukis litar setara a.u (parameter h), bagi amplifier ini, [5 markah]

(ii) kira gandaan voltan seluruh amplifier, Avs = vo/vs, [5 markah]

(iii) kira impedans masukan, Ris dan [5 markah]

(iv) kira impedans keluaran, Ro [5 markah]

Ambil nilai parameter h bagi kedua-dua transistor sebagai hie = 2K, hfe

= 100 dan hre = hoe = 0.


3

Rajah 2

3. (a) Berdasarkan lakaran graf ciri keluaran transistor, terangkan perbezaan di

antara amplifier kelas A, B dan AB. Nyatakan kebaikan dan kelemahan tiap-

tiap kelas tersebut. [6 markah]

(b) Rajah 3 adalah litar amplifier kuasa kelas A gandingan transformer. Nilai

komponen yang digunakan adalah VCC = 10 V, RL = 8 , n1 : n2 = 3 : 1, R1 =

0.73 k, R2 = 1.55 k dan RE = 20 . Parameter transistor pula adalah hie =

4.3 , hfe = 25, hre = hoe = 0 dan VBE(on) = 0.7 V. Amplitud voltan masukan

sinusoid adalah 17 mV.

(i) Lukis litar setara parameter h untuk amplifier ini. [4 markah]

(ii) Kira gandaan voltan, sov vvA di mana Vo adalah voltan keluaran ac

merentas beban, L. [4 markah]

(iii) Kira kuasa dari bekalan kuasa, PDC [3 markah]

(iv) Tentukan kuasa ulangalik (Pac) yang dihantar kebeban [3 markah]

(v) Kira nilai kecekapan amplifier. [3 markah]


4

Rajah 3

4. (a) Nilai perintang pada Rajah 4(a) adalah R1 = 20 k, R2 = 120 k, R3 =

15 k dan R4 = 75 k.

(i) Jika voltan masukan vI = 0.20 V, kira vo1, vo, i1, i2, i3 dan i4.

[6 markah]

(ii) Tentukan arah sebenar bagi semua arus. [2 markah]

Rajah 4(a)


5

b) Lakarkan bentuk gelombang voltan keluaran dari litar kamiran jika

voltan masukannya adalah seperti dalam Rajah 4(b). Jelaskan jawapan

anda. [5 markah]

Rajah 4b

c) Dua voltan masukan, tv sin5.21 V dan v2 = +2V digunakan pada

sebuah amplifier penjumlah untuk menghasilkan voltan keluaran

tvo sin15 (V).

Nilai perintang paling besar yang boleh digunakan adalah 200 k.

Bina litar penjumlah tersebut dan tentukan nilai perintang yang

digunakan. [7 markah]

5. (a) Rajah 5 merupakan sebuah litar logik yang mempunyai tiga nilai masukan A,

B dan C dan satu nilai keluaran, Y.

(i) Tuliskan pernyataan Boole untuk litar logik pada Rajah 5. [4 markah]

(ii) Buatkan jadual kebenaran untuk pernyataan Boole yang diperolehi.

[4 markah]


6

Rajah 5

(b) Ringkaskan rumus berikut dengan menggunakan aljabar Boole atau Peta

Karnaugh

(i) CABAABCY [3 markah]

(ii) ACBCAY [3 markah]

(iii) )()(________

BABAY [3 markah]

(iv) ))(( DCBADACBY [3 markah]

6. (a) Nyatakan tiga jenis flip-flop bersama simbol dan jadual kebenarannya.

[9 markah]

(b) Lukis bentuk gelombang output, Q pada Rajah 6(a), 6(b) dan 6(c)

Q

[3 markah]

Rajah 6(a)


7

Q

[4 markah]

Rajah 6(b)

Q

[4 markah]

Rajah 6(c)


8

7. (a) Terangkan dengan ringkas yang berikut:

(i) Pembilang riak (ripple counter), [2 markah]

(ii) Pembilang selari (Parallel counter), [2 markah]

(iii) Pembilang dekad (decade counter), [2 markah]

(iv) Pembilang menurun (Count-down counter). [2 markah]

(b) Lukis litar logik pembilang mod 6 (membilang 0 hingga 5 kemudian 0, 1, 2,

3,….). [4 markah]

(c) Lukiskan bentuk output C, B dan A setiap denyut jam (Clock pulse) pada

Rajah 7(a). [4 markah]

Clock

C

B

A

Rajah 7(a)


9

(d) Lukis bentuk gelombang pada output, Q dari FF1, FF2, FF3 dan FF3 pada

Rajah7(b). [4 markah]

Rajah 7(b)


10

8. (a) Dengan ringkas terangkan yang berikut:-

(i) Penambah Separuh, (Half Adder), [2 markah]

(ii) Penambah Penuh (Full Adder), [2 markah]

(iii) Penolakan Separuh (Half Substractor), [2 markah]

(iv) Penolakan Penuh (Full Substractor) dan [2 markah]

(v) terangkan bagaimana litar Penolakan Penuh (Full Substractor) dapat

dibuat dari litar Penambah Penuh (Full Adder). [2 markah]

(b) Dengan menggunakan litar pendarab (multiplier) jenis tambah dan anjak (add

and shift), senaraikan turutan kandungan pendaftar ‘accumulator’ dan

pendaftar pendarab (multiplier register) bagi menyelesaikan masalah berikut:-

[6 markah]

11102 X 1012 = ?

Accumulator Register Multiplier Register

(c) Lukis bentuk gelombang bagi D dan Bout pada Rajah 8. [4 markah]

D

Bout

Rajah 8

Sem5 ae final ae 2014 2006

Education

Transcript of Sem5 ae final ae 2014 2006