Section III: Complex system design - Wright State...

CEG 360/560; EE 451/651 Digital System Design

Dr. Travis Doom, Associate ProfessorDepartment of Computer Science and Engineering

Wright State University

Section III: Section III: Complex system designComplex system design

CEG 360/560 - EE 451/651 Section III - 2

OutlineOutlineDealing with ComplexityData unit (Datapath) design

– Registers– RTL language– Datapath Construction

Control unit (Controller) design– ASM Charts

Implementation issues– PLDs– ROM– VLSI Design


Dealing with ComplexityDealing with ComplexityPractical synchronous sequential circuits are too complex to design at the flip-flop level.

– A simple 8-bit CPU capable of storing only four values (in four GPRs) has at least 4 x 8 = 32 1-bit state devices!

– If the CPU had only 8 inputs it would still require a 232 by 28 truth table to represent the device. Each of these billion or so entries would have to contain a 32-bit next state. Storing 240 32-bit entries would require 4 TB!

K (kilo) 210 1024M (mega) 220 1048576G (giga) 230 1.07 x 109

T (tera) 240 1.10 x 1012

– Simplification would require a 40-variable K-map!

How do we manage complex design?


Complex System DesignComplex System Design

Practical sequential designs, like combinational designs, require a hierarchical approach

– Use well defined building blocksComplex blocks made of simpler blocks (hierarchy)Examples: Registers, counters

Associate a high-level of behavior with those blocks (abstraction)– Design methodologies based on abstractions can more easily encompass

complexity– Common function blocks: registers and counters

ORDER a sequence of high-level behaviors that (when executed in the proper order) solves the overall problem

– Like computer programming!


Decomposing a Design: Control and DataDecomposing a Design: Control and Data

Complex designs are generally broken down into to high-level abstractions.– The datapath is home to one or more datapath components that provide

higher-level functionality (viewable at the register transfer level)– The control unit controls the sequence in which the datapath functions are

performed in order to perform the system task

Control Unit Datapath

Control Signals

Status Signals

Control Outputs

DataInputs

ControlInputs

DataOutputs







DatapathDatapath componentscomponents

Gates and flip-flops are good building blocks for simple designsWe need more sophisticated building blocks for complex systems

Register-transfer level (RTL) components (aka Datapath components) include medium scale devices such as:

– Registers– Counters– ALUs– Multiplexers– Comparators– etc


MSI Quad/Hex RegistersMSI Quad/Hex Registers CLKCLR

4Q4Q3Q3Q2Q2Q1Q1Q

74LS175

1D

2D

3D

4D

CLKCLR

6Q5Q4Q3Q2Q1Q

74LS174

1D2D3D4D5D6D

D1Q

CLR

Q

Q /1Q

1D

D2Q

CLR

Q

Q /2Q2D

D3Q

CLR

Q

Q /3Q3D

D4Q

CLR

Q

Q /4Q4D

CLK

/CLR

74LS175

All four flip-flops use the same clock!


Octal Register with Parallel Load EnableOctal Register with Parallel Load Enable

CLKLoad

1D2D3D4D5D6D7D8D

1Q2Q3Q4Q5Q6Q7Q8Q

D Q1D

/Load

CLK

1Q

Why don’t we gate the clock?

1b-mux


Shift RegistersShift Registers

RSI 0 1 1 1

Q3 Q2 Q1 Q0RSI 0 1 1

Q3 Q2 Q1 Q0

0 1 1 1 LSI

Q3 Q2 Q1 Q0

1 1 1 LSI

Q3 Q2 Q1 Q0

Often used to rearrange bits or Multiply/Divide by 2

Multi-bit register that moves data “sideways” left/right ( 1 bit/clock )– Shift Left (or Shift Down) is towards MSB

– Shift Right (or Shift Up) is towards LSB


BiBi--directional Universal Shift Registersdirectional Universal Shift Registers

Quad Bi-directional Universal (4-bit) PIPO

CLK CLR

S1 S0

LIN D QDC QCB QBA QARIN

11

1

10

9

7

6

4

5

3

2

12

13

14

15

74x194

Modes:HoldLoadShift RightShift Left

R L

Mode Next stateFunction S1 S0 QA* QB* QC* QD*Hold 0 0 QA QB QC QDShift right/up 0 1 RIN QA QB QCShift left/down 1 0 QB QC QD LINLoad 1 1 A B C D

SRG n>S1

Q0

•••

Q1

Qn

Block symbol

D0

•••

D1

Dn

S0

RSI

LSI

(MSB)

(LSB)(SI)

(SO)


Universal SR SchematicUniversal SR SchematicRIGHT

CLK

/CLR

LIN

D

(11)

(1)

(7)

(6) D Q

CLK

CLR

10

00

11

01

(12)QD

S1 S0

SL

HO

LD

SR

LEFT74x194

D Q

CLK

CLR01

11

00

10

(15) QA

S1

S0

A

RIN

(10)

(9)

(3)

(2)


Octal TriOctal Tri--state Register/Latchstate Register/LatchCLKOE

74LS374

1D2D3D4D5D6D7D8D

1Q2Q3Q4Q5Q6Q7Q8Q

COE

74LS373

1D2D3D4D5D6D7D8D

1Q2Q3Q4Q5Q6Q7Q8Q

1Q

2Q

8Q

D

Q

D

Q

D

Q

1D

2D

8D

/OE

CLK

74LS374


Shift Register ApplicationsShift Register Applications

State Registers– Shift registers are often used as the state register in a sequential device.

Usually, the next state is determined by shifting right and inserting a primary input or output into the next position

– Very effective for finite memory machinesSerial Interconnection of Systems

– keep interconnection cost low with serial interconnectBit Serial Operations

– Bit serial operations can be performed quickly through device iteration– Iteration (a purely combinational approach) is expensive (in terms of # of

transistors, chip area, power, etc).– A sequential approach allows the reuse of combinational functional units

throughout the multi-cycle operation



SDATA

Parallel-to-serial converter

Parallel Data from A-to-D converter

Serial-to-parallel converter

Parallel Data to D-to-A converter

Control

Circuits

CLOCK

/SYNC

TransmitterControl

Circuits

Receiver

CLOCK - 1 bit per clock tick = 2.048 MHz

/SYNC - synchronization of start of “frame”

SDATA - serial data stream

DIGITAL TELEPHONY



...7 6 5 0>

x7 x6 x5 x0

...7 6 5 0>

y7 y6 y5 y0

...7 6 5 0>

FACout S

Cin A BD Q

CLK

CLR

CLK

CLEAR_Cz7 z6 z5 z0...

CTL Sequential Implementation of:Z[7..0] = X[7..0] + Y[7..0]

V


CountersCountersCounters are registers with extra functionsClocked sequential circuit with single-cycle state diagram

– Modulo-m counter = divide-by-m counter

Most Common:n-bit binary counter, where m = 2n

n flip-flops, counts 0 … 2n-1

S3

S2

S1

Sm

111110101100011010001000


CountingCounting

Common output codes for mod-8 and decimal counters

State Binary BCD Gray Excess-3 Ring Twisted-tail0 000 0000 000 0011 00000001 00001 001 0001 001 0100 00000010 00012 010 0010 011 0101 00000100 00113 011 0011 010 0110 00001000 01114 100 0100 110 0111 00010000 11115 101 0101 111 1000 00100000 11106 110 0110 101 1001 01000000 11007 111 0111 100 1010 10000000 10008 1000 10119 1001 1100


Asynchronous/Ripple CounterAsynchronous/Ripple Counter

Q

QT

Q

QT

Q

QT

Q

QT

CLKQ0

Q1

Q2

Q3

1 bit

divide-by-2

2 bit

divide-by-4

3 bit

divide-by-8

4 bit

divide-by-16

Uses Minimal Logic!

Tpd = n x Tpd,tffSetup = Tsetup,tff


Synchronous CountersSynchronous Counters

All clock inputs connected to common CLK signal– So all flip-flop outputs change simultaneously tCQ after CLK

Synchronous Counters are/have– Faster– More Complex Logic (more “expensive”)– Most Frequently Used Type of Counter

Two types of synchronous counters– Serial– Parallel

Easy to combine iteratively to build bigger counters– Combined counters have serial aspects. If the devices are parallel, then the

overall device is “mixed mode”.


Synchronous Serial CounterSynchronous Serial Counter

Flip-flops enabled when all lower flip-flops = 1.Enable propagates serially — limits speedRequires(n-1) Δ t < TCLK

All outputs change simultaneously tCQ after CLK

>T

QEN

CLK

CNTEN Q0

Q1

Q2

Q3

QEN

>T

QEN

>T

QEN

>TEquation?Delay?

Δ t

Δ t

Δ tTpd = Tpd,tffTsetup = (n-1)Δt + Tsetup,tff


Synchronous Parallel CounterSynchronous Parallel Counter

Single-level enable logic per flip-flop Fastest and most complex type of counterRequires Δ t < TCLK

All outputs change simultaneously tCQ after CLK

>T

QEN

>T

QEN

>T

QEN

>T

QEN

CLK

CNTEN Q0

Q1

Q2

Q3

Equation?Delay?

Tpd = Tpd,tffTsetup = Tpd,bigestAND + Tsetup,Tff


74163 474163 4--bit Synchronous Parallel Counterbit Synchronous Parallel Counter

>CLKCLRLDENPENTABCD

QAQBQCQD

RCO

74X163

LSB

MSBRCO = Ripple Carry Out, when Count = 1111 and ENT = 1(74161 is the same, but with an

asynchronous clear)

Common ClockSynchronous ClearSynchronous LoadCount Enable = ENP • ENT

Load Data Inputs


74163 State Table74163 State Table

Inputs Current State Next State

/CLR /LD ENT ENP QD QC QB QA QD* QC* QB* QA*

0 X X X1 0 X X1 1 0 X1 1 1 01 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 11 1 1 1

X X X XX X X XX X X XX X X X0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

0 0 0 0D C B A

QD QC QB QAQD QC QB QA

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 10 0 0 0

ClearLoadHoldHoldCount

.

.

.


74169 Up/Down Counter74169 Up/Down Counter

>CLKUP/DNLDENPENTABCD

QAQBQCQD

RCO

74X169 UP/DN = 1 = up RCO = 15UP/DN = 0 = down RCO = 0

up down upEx: 0,1,2, 1,0,15,14, 15,0,1,2

RCO RCO


Application Application -- Free Running ModuloFree Running Modulo--16 Counter16 Counter

>CLKCLRLDENPENTABCD

QAQBQCQD

RCO

74X163

CLOCK

+5 VR

Q0Q1Q2Q3


ModuloModulo--11 Counter [5,6, 11 Counter [5,6, ……, 15, 5, 6, ...], 15, 5, 6, ...]

>CLKCLRLDENPENTABCD

QAQBQCQD

RCO

74X163

CLOCK

+5 V

CNT15 /CNT15

Q0Q1Q2Q3

When Count=15 Load 5 (0101)

Any Modulus 2 16 possible

1010

RCO


ModuloModulo--11 Counter [0,1,2, 11 Counter [0,1,2, ……, 10, 0, 1, ...], 10, 0, 1, ...]

>CLKCLRLDENPENTABCD

QAQBQCQD

RCO

74X163

CLOCK

+5 V

Q0Q1Q2Q3

When Count=10 Clear

Decode Count 1x1x (10…15)Q3 • Q1

+5 V


Cascaded 74163s for 8Cascaded 74163s for 8--bit Counterbit CounterUp to ModuloUp to Modulo--256256

>CLKCLRLDENPENTABCD

QAQBQCQD

RCO

74X163

>CLKCLRLDENPENTABCD

QAQBQCQD

RCO

74X163

CLOCK/RESET/LOAD

CNTEN

D0D1D2D3

D4D5D6D7

Q0Q1Q2Q3

Q4Q5Q6Q7RCO8


44--bit, 8bit, 8--state Johnson Counterstate Johnson Counter

Also known as – twisted-ring counter– Moebius counter

2n states with n flip-flops– NOT self-correcting

RINABCDLIN

S0S1CLRCLK

+5 V

R

74X194

CLOCK

QAQBQCQD

Wired as ashift-leftshift register

Q0Q1Q2Q3

/RESET

74X04


Design DecompositionDesign Decomposition

A digital system is a sequential circuit with specified behavior.– A microprocessor is a digital system.

Specifying large digital systems with state tables may be exceptionally difficult, due to the number of states involved.

– As in computer programming, most digital systems are designed using a modular, hierarchical approach.

– The system is partitioned into modular subsystems.Each subsystem performs a well defined function with specified interface.

– Interconnection the various subsystems though data and control signals results in a digital system.


Design DecompositionDesign Decomposition

Most digital systems are partitioned into two top-level modules: – Data Unit (or Datapath): performs data-processing operations.– Control Unit: determines the sequence of these operations.

Datapaths are sequential systems.– the system state is defined by the contents of the registers.– the functionality is the set of defined operations that can be performed on

the contents of the registers. – Elementary operations are usually, but not always, performed in parallel on

a string of bits in one clock tick.A microoperation is an elementary operation performed on data stored in the datapath. They fall into four general categories:

– Transfer microoperations: transfer binary data from one register (or data input/memory) to another.

– Arithmetic microoperations: perform arithmetic on data in registers.– Logic microoperations: perform bit manipulations on data in registers.– Shift microoperations: shift data in registers.


RegisterRegister--Transfer Level DesignTransfer Level Design

An approach to specify, analyze, and design systems too complex to use the state-table based approaches commonly utilized in “simple” designs.

The Register-Transfer Level (RTL) approach is characterized by:– A digital system is viewed as divided into a data subsystem and a control

subsystem.– The state of the data subsystem consists of the contents of the registers.– The function of the system is performed as a sequence of register transfers.– A register transfer is a transformation performed on the datum while the

datum is transferred from one register to another.– The sequence of register transfers is controlled by the control subsystem.

The operation of the device can be designed as a sequence of register transfers can be designed using state diagrams, ASM charts, etc.

– Each transfer must correspond to a sequence of microoperations.– The control unit implements the RTL design through microoperations.


RTL Languages (1)RTL Languages (1)

The notation for register transfers are sufficiently complete to describe any digital system at the register-transfer level.

– known as register-transfer languages.

Registers are denoted by uppercase letters (sometimes followed by numbers) that indicate the function of the register

– e.g. R0, R1, AR, PC, MAR, et al.– The individual bits can be denoted using parenthesis and bit numbers or

labelse.g. R0(0), R0(7:0), PC(L), PC(H)

Data transfer is denoted in symbolic form by the means of the replacement operator ←.

– e.g. R2 ← R1


RTL Languages (2)RTL Languages (2)Normally we want a given transfer to occur not for every clock pulse, but only for specific values of the control signals.

– RTL conditional statements:e.g. If (K1 = 1) Then (R2 ← R1)

– Control function notation (Colon, :)e.g. K1: R2 ← R1

All RTL statements occur in response to a clock tick. A comma is used to separate two or more register transfers that are executed at the same time. A semi-colon is used for an instruction with different control

– e.g. Brake: R2 ← R1, R4 ← R3; not(Brake): R1 ← R2



Register to Memory Transfers are denoted using square brackets surrounding the memory address.

– e.g. DR ← M[AR] (Read operation)– e.g. M[AR] ← SR (Write operation)



Examples of Arithmetic Microoperations

Examples of Logic Microoperations


Designing a Designing a datapathdatapath

Design a device with two 8-bit inputs A and B, one 1-bit input START, one 8-bit output C, and one 1-bit output DONE. The device begins idle (with output DONE = 0). When START is asserted (for one clock tick) the unsigned binary inputs A and B are and held constant until the device asserts “DONE”. The device must calculate the approximate length of the hypotenuse of a right triangle with sides A and B. When the final answer is available on output C, the device will assert DONE for one clock tick. If the answer cannot be computed, assert ERR.

A

B

CC = sqrt (A2 + B2)

START

A

B

DONE

C

>

8 8

8ERR



Euler formula for Square Root Approximation:– Let x = max (|a|, |b|)– Let y = min (|a|, |b|)– Sqrt (a^2 + b^2) ~= max (x,(0.875x+0.5y))

What sort of functions do you need to process the data?


Designing a Designing a datapathdatapathSRA Circuit Model Let x = max (a, b) and y = min (a, b)

– Sqrt (a^2 + b^2) ~= max (x,(0.875x+0.5y))

Datapath

Registers: c, x, y, t

Functions: min, max, +, -, shift

Control unit…Rx ← max (A, B)Ry ← min (A, B)Ry ← Ry >> 1 # shift right 1; *0.5Rt ← Rx >> 3 # shift right 3 (1/8th)Rt ← Rx – Rt # x – 1/8x = x*0.875Rt ← Ry + RtRc ← max (Rx, Rt)C ← Rc…



Control unit…Rx ← max (A, B)Ry ← min (A, B)Ry ← Ry >> 1Rt ← Rx >> 3Rt ← Rx – RtRt ← Ry + RtRc ← max (Rx, Rt)C ← Rc…

RG8RtLD

8

8

RtIN

>Rt

RG8RxLD

8

8

RxIN

>Rx

RG8RyLD

8

8

RyIN

>Ry

RG8RcLD

8

8

RcIN

>Rc

8b-Shifter

8

8

MUXMXS

8 8Ry Rx

0 1

SR1,3

ALU8

8 8

8

ALU+-

MUXMXA1

8 8Ry Rx

0 1

Rt

8

MUXMXC2

8 8B Rt

0 1

8

MUXMXC1

8 8A Rx

0 1

Min Max8 8

MUX0 1 2 3MXF

8RcIN, RxIN, RyIN, RtIN

CBA8

8 8

2

Overflow

C



Control unit…Rx ← max (A, B)Ry ← min (A, B)Ry ← Ry >> 1Rt ← Rx >> 3Rt ← Rx – RtRt ← Ry + RtRc ← max (Rx, Rt)C ← Rc…

BA8

8

Datapath

LDRx, LDRy, LDRt, LDRc4

MXC1, MXC22

MXA1, ALU+-2

MXS, SR1,32

MXF2

C8

Overflow

Control Signals

Data Inputs

Data Outputs

Status Signals







Interaction between Data and Control UnitsInteraction between Data and Control Units

Control Signals - signals that activate data-processing functions.– To activate a sequence of such operations, the control unit sends the proper

sequence of control signals to the datapath.Status Signals - signals that describe aspects of the state of the datapath.– The control unit uses these signals in determining the specific sequence of

operations to be performed.Other Signals - allow the control unit and datapath to interact with other parts of the system, such as memory and input-output logic.

Control Unit Datapath

Control Signals

Status Signals

Control Outputs

DataInputs

ControlInputs

DataOutputs


The Control UnitThe Control Unit

The control unit generates the signals for sequencing the operations in the datapath

– A sequential circuit with states that dictate the control signals for the system

– Using status conditions and control inputs, the sequential control unit determines the next state in which additional microoperations are activated.

Hardwired Control– The control unit is implemented to provide a particular digital function

Microprogrammed Control– LATER!


Control Unit DesignControl Unit Design

Control unit

Next StateStartOverflow =

PS 00 01 10 11 RTLIDLE IDLE IDLE S1 S1S1 S2 S2 S2 S2 Rx ← max (A, B)S2 S3 S3 S3 S3 Ry ← min (A, B)S3 S4 S4 S4 S4 Ry ← Ry >> 1S4 S5 S5 S5 S5 Rt ← Rx >> 3S5 S6 S6 S6 S6 Rt ← Rx – RtS6 S7 ERR S7 ERR Rt ← Ry + RtS7 S8 S8 S8 s8 Rc ← max (Rx, Rt)S8 IDLE IDLE IDLE IDLE C ← Rc; Done ← 1ERR IDLE IDLE IDLE IDLE ERR ← 1Start

OverflowDone

LDx …


ASM for ControlASM for Control

Control unit…Rx ← max (A, B)Ry ← min (A, B)Ry ← Ry >> 1Rt ← Rx >> 3Rt ← Rx – RtRt ← Ry + RtRc ← max (Rx, Rt)C ← Rc; DONE ← 1…

Rx ← max (A,B)

Ry ← max (A,B)

Ry ← Ry >> 1

Rt ← Rx >> 3

.

.

.

LDRx, MXC1=0, MC2=0, MXF=1

LDRy, MXC1=0MC2=0, MXF=0

LDRy, MXS=0,SR1,3 = 0

LDRt, MXS=1,SR1,3 = 1

.

.

.


Algorithmic State MachinesAlgorithmic State Machines

Algorithmic State Machine (ASM) Chart– Special flowchart used to define digital hardware algorithms– Describes a sequence of events– Determines the actions which occur in the states

in response to the clock pulsein response to changes in the inputs

ASM Charts contain three basic elements:– State boxes

Rectangles, labeled with the state name and assignment, containing a register operation and/or the names of Moore outputs asserted in that state.

– Decision boxesDiamonds containing a conditional input expression and exits 1 and 0.

– Conditional output boxesOvals containing Mealy outputs asserted for the conditions leading to the box.


ASM elementsASM elements

Moore output list

state name state codestate entry path

state exit path

State box

condition

condition

Decision box

0 1

0 1

OR

condition false exit path

condition true exit path

conditional output list

from decision-boxexit path

exit path

Conditional (Mealy) output box


ASM TimingASM Timing

Each state box has a corresponding “ASM Block” that includes all decision and conditional output boxes reached from that state

– Each ASM Block has exactly one state box, all paths leaving the ASM Block lead directly to a different state box.

The current state box represents the current state.The current inputs decide a path through the decision boxes.

– Unlike state diagrams, ambiguity is easily avoided in ASM charts.– Conditional outputs along the path occur immediately in response to changes in the

inputs values.The next state box is not entered until a clock tick occurs.

– The Moore outputs in the state box and any conditional (Mealy) outputs in the new ASM Block are asserted immediately.

ASM boxes may also include Register Transfer directives!– Any changes (conditional or otherwise) to a sequential device wait until the next

positive clock edge.


ASM Example: 4-bit binary counter

Z1,Z0

STATE = Q1 Q0

00

01

10

11

A

B

C

D

Z0

Z1

Z=3

STATE = Q1 Q0

00

01

10

11

A

B

C

D

Z=1

Z=2

-or-

Z=0


ASM Example: 4-bit counter with enable

EN

EN

EN

EN

STATE = Q1 Q0

A 00

B 01

C 10

D 11

0

1

0

1

0

1

0

1

Z=3Z=1

Z=0 Z=2


ASM Example: Modulo-4 counter (Mealy)

EN

A 0001

0

1

C 0100

D 1000

B 0010

EN0

1

MAX

STATE = QD QC QB QA (one hot)

Mealy output


ASM Example: 1ASM Example: 1’’s Counters Counter

Count # of 1’s on X & Y inputs output Z if count = multiple of 4 ( 0, 4, 8 ... )

If ( X • Y ) 2 1’s ( Inc by 2 )Else if ( X+Y ) 1 1’s ( Inc by 1 )Else 0 1’s ( No Inc )


ASM chart for 1ASM chart for 1’’s Counters Counter

X•Y

X +Y

X•Y

X +Y

X•Y

X +Y

Z

X•Y

X +Y

S0 00 S1 01 S2 10 S3 11

1

0

1

0

1

0

1

0

STATE = Q1 Q2

0 0 0 0

1 1 1 1

•


Convert ASM chart to Transition ListConvert ASM chart to Transition List

Needs an extra step to find transition expressions

Trace all possible paths, from any state to all destination states

Transition expression to any given next state (= one line of the transition list) is product (AND) of all conditions along path:( condition) if 1 branch taken

– (condition)’ if 0 branch taken


Example: 1Example: 1’’s Counters Counter

Z

X•Y

X +Y

S0 00

1

0

0

1 (XY)’(X+Y)

(XY)

(XY)’(X+Y)’

PS INPUT NS00 (XY) 1000 (XY)’(X+Y) 0100 (XY)’(X+Y)’ 00


Example: 1Example: 1’’s Counters CounterQ1Q0 INPUT Q1*Q0*00 (XY) 1000 (XY)’(X+Y) 0100 (XY)’(X+Y)’ 0001 (XY) 1101 (XY)’(X+Y) 1001 (XY)’(X+Y)’ 0110 (XY) 0010 (XY)’(X+Y) 1110 (XY)’(X+Y)’ 1011 (XY) 0111 (XY)’(X+Y) 0011 (XY)’(X+Y)’ 11

Q1* = Q1’Q0’(XY) +

Q1’Q0(XY) +

Q1’Q0(XY)’(X+Y) +

Q1Q0’(XY)’(X+Y) +

Q1Q0’(XY)’(X+Y)’ +

Q1Q0(XY)’(X+Y)’

Q2* = Q1’Q0’(XY)’(X+Y) +

Q1’Q0(XY) +

Q1’Q0(XY)’(X+Y)’ +

Q1Q0’(XY)’(X+Y) +

Q1Q0(XY) +

Q1Q0(XY)’(X+Y)’ +







Programmable Logic DefinitionsProgrammable Logic Definitions

Digital integrated circuit (MSI, LSI, VLSI)– manufactured as a standard off-the-shelf component– containing “regular” array of logic gates and flip-flops– whose logic functions are determined by the application design engineer

and implemented locally

Many types of programmable logic– sometimes generically called PLDs (Programmable Logic Devices)– PAL or PLD– PROM– FPGA

output

input

Combinational

PLD


Programmable Logic DefinitionsProgrammable Logic DefinitionsPLA

– Programmable Logic Array– first PLDs– simple programmable

AND/OR array– programmed by “blowing

fuses” by hand or by mask


PAL – Programmable Array Logic– similar to a PLA, but the OR-

array is fixed– most commonly used PLD – may include input/output flip-

flops

GAL – Generic Array Logic– can be configured to emulate

the AND/OR, flip-flop, and output structure of a variety of combinational and sequential PAL devices

Programmable LogicProgrammable Logic


ReadRead--Only Memory (ROM)Only Memory (ROM)

A combinational circuit with n inputs and b outputs:

2n x bROM

AddressinputsA(n-1, ... , 0)

n b DataoutputsD(b-1, ... , 0)

Programmable ⎯ values determined by userNonvolatile ⎯ contents retained without powerUniform (Random) Access ⎯ delay is uniform for all addresses


ReadRead--Only Memory (ROM)Only Memory (ROM)

Two views:– ROM stores 2n words of b bits each, or– ROM stores an n-input, b-output truth table

Example: A1 A0 D3 D2 D1 D00 0 0 1 0 10 1 1 1 1 1 1 0 0 0 0 11 1 1 0 0 0

Stores 4 4-bit words, orstores 4 functions of 2input variables

b = 4n = 2


Using ROMs for Combinational LogicUsing ROMs for Combinational Logic

A 3-input, 4-output combinational logic function:

Function: 2-to-4 Decoder with Polarity ControlA2 = Polarity (0 = active Low, 1= active High)A1, A0 = I1, I0 (2-bit input )D3...D0 = Y3...Y0 (4-bit decoded output)

Inputs OutputsA2 A1 A0 D3 D2 D1 D00 0 0 1 1 1 00 0 1 1 1 0 10 1 0 1 0 1 10 1 1 0 1 1 11 0 0 0 0 0 11 0 1 0 0 1 01 1 0 0 1 0 01 1 1 1 0 0 0

8 × 4 ROM

A0 D0A1 D1A2 D2

D3

Y0I1

POLY1Y2Y3

I0


Internal Structure of 4Internal Structure of 4×4 Diode ROM

D0D1D2D3

2 to 4Decoder

A1

A0

Bit Lines

/w0

/w1

/w2

/w3

Diode 1

No Diode 0

0101

0001

1000

1111

1 of n Word Lines

R0R1R2R3

+5 V

Why use diodes?Why not replace them with wires?


Types Of ROMs (1)Types Of ROMs (1)

Mask ROM– Connections made by the semiconductor vendor– Expensive setup cost– Several weeks for delivery– High volume only– Bipolar or MOS technology

PROM– Programmable ROM– Connections made by equipment manufacturer– Vaporize (blow) fusible links with PROM programmer using high

voltage/current pulses– Bipolar technology– One-time programmable

Word Line

Bit Line


Internal Structure of Transistor ROMInternal Structure of Transistor ROM

R0R1R2R3

+5 V

/D3 /D2 /D1 /D0

Transistor 1

No transistor 0

w3

Replace diodes with MOS transistorsChange decoder to active-high outputs

1000


EPROM and EEPROM StructureEPROM and EEPROM StructureVDD

Floating gate

Nonfloating gate

Active-high word lines

Active-low bit lines


Types of ROMs (2)Types of ROMs (2)

EPROM– Erasable Programmable ROM– Charge trapped on extra “floating gate” of MOS

transistors– Exposure to UV light removes charge

10-20 minutesQuartz Lid = expensive package

– Limited number of erasures (10-100)

EEPROM (E2ROM)– Electrically Erasable ROM– Floating gates charged/discharged electrically– Not RAM! (relatively slow charge/discharge)– limited number of charge/discharge cycles (10,000)

Word Line

Bit Line


Types of ROMs (3)Types of ROMs (3)

Flash Memory– Electronically erasable in blocks– 100,000 erase cycles– Simpler and denser than EEPROM– Often used for firmware


ROM Type SummaryROM Type Summary

Type

Mask ROM

Mask ROM

PROM

EPROM

EEPROM

FLASH

Technology

NMOS, CMOS

Bipolar

Bipolar

NMOS, CMOS

NMOS

CMOS

Read Cycle

20-200 ns

<100 ns

<100 ns

25-200 ns

50-200 ns

25-200 ns

Write Cycle

4 weeks

4 weeks

5 minutes

5 minutes

10 μs/byte

10 μs/block

Comments

Write once; low power

Write once; high power; low density

Write once; high power; no mask charge

Reusable; low power; no mask charge

10,000 writes/location limit

100,000 erase cycles


Consider a 64 x 1 ROMConsider a 64 x 1 ROM

Very tall, narrow chip (BAD)Even worse for larger chips!

How can we make it more square?

This Decoder needs 64 6-input gates!+5 V

6-to-64Decoder

/w0

/w1

/w63

A5

A0 •••

64 x 1 Diode Array

D0


64 x 1 ROM with 264 x 1 ROM with 2--Dimensional DecodingDimensional Decoding

Almost square chip!

3 to 8Decoder

/w0

/w1

/w7

+5 V

0 78 to 1 mux

A5

A3

A2

A0D0

•••

• • •

Decoder and mux = 8 3-input gates + 8 4-input gates

8 x 8 Diode Array


64K x 8 ROM with 264K x 8 ROM with 2--D DecodingD Decoding

9 to 512Decoder

A

A

9

7

512 512×

128

128to 1Mux

• ••

• • •

D0 D1 D7

512×

128

512×

128

512×

1024Array

128to 1Mux

128to 1Mux

128 128 128

Is this a square chip?2-D Decoding / Coincident selection64k x 8 = 216 * 23 = 219

square root (219) ~= 29


Internal 2Internal 2nn x b ROM Control Structurex b ROM Control Structure

Rowdecoder

Power on

Storage array

Columnmultiplexer

A0A1

Am-1

Am

Am+1

An-1

/CS/OE

Db-1 Db-2 D0

Power on

Power on


Programmable LogicProgrammable Logic

Advantages– Design flexibility– Better design automation– Higher density, fewer packages (compared to SSI-MSI)– Less expensive– Lower power– Higher performance

Programming Technologies– Interconnections usually made by pass transistors controlled by memory

bits of some type:– Antifuse - permanent connections made electrically– EPROM - charged floating gate, UV erasable– EEPROM - charged floating gate, electrically erasable– Flash Memory - charged floating gate, electrically erasable– Programmed using CAD - Hardware Description Languages


Modern (VLSI) DesignModern (VLSI) Design

The VLSI chips that are used in most modern designs come in three varieties:

– Custom Approach: VLSI chips, or some of their parts, are designed by hand.

Full Custom Vs. Standard Cell - Using standard cell designs (same height, variable width) and routing channels simplifies the design processHighest Density, Highest Manufacturing Cost

– Semicustom Approach: The VLSI chips employ gate arrays and technology mapping.

Gate array: a partially prefabricated IC that incorporates a large number of identical gates (usually 3-input NAND or NOR gates) that are laid out in a regular two-dimensional array.Technology mapping: The process of designing a logic function as a network of available devices.Lower Density (10-25% more gates than an equivalent custom design).Inexpensive: Requires only metal deposition (define interconnections), economy of scale.


Modern (VLSI) DesignModern (VLSI) Design

The VLSI chips that are used in most modern designs come in three varieties:

– VLSI PLDsField Programmable Gate Arrays (FPGAs) A VLSI modules that can be programmed to implement a digital system consisting of tens of thousands of gates. LSI PLDs implement two-level combinational and sequential networks, FPGAs allow the realization of multilevel networks and complex systems on a single chip!Highly reprogrammable!Low costMay produce slower networkMay require a larger silicon area

Section III: Complex system design - Wright State...

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