EE143 – Ali Javey

Section 12: Intro to Devices

Extensive reading materials on reserve, includingRobert F. Pierret, Semiconductor Device Fundamentals

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Bond Model of Electrons and Holes• Silicon crystal in

a two-dimensionalrepresentation.

Si Si Si

Si Si Si

Si Si Si

Si Si Si

Si Si Si

Si Si Si

Si Si Si

Si Si Si

Si Si Si

• When an electron breaks loose and becomes a conduction electron, a hole is also created.

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Semiconductors, Insulators, and Conductors

• Totally filled bands and totally empty bands do not allow current flow. (Just as there is no motion of liquid in a totally filled or totally empty bottle.)

• Metal conduction band is half-filled.• Semiconductors have lower EG’s than

insulators and can be doped

E c

Ev

Eg=1.1 eV

E c

Eg= 9 eV empty

Si, Semiconductor SiO2

, insulator Conductor

Ecfilled

Top ofconduction band

E v

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Dopants in Silicon

Si Si Si

Si Si

Si Si Si

Si Si Si

Si Si

Si Si Si

As B

• As, a Group V element, introduces conduction electrons and creates N-type silicon,

• B, a Group III element, introduces holes and creates P-type silicon, and is called an acceptor.

and is called a donor.

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Ionized Donor

IonizedAcceptor

Immobile Chargesthey DO NOTcontribute to current flow with electric field is applied. However, they affect the local electric field

Hole

Electron

Mobile Charge Carriersthey contribute to current flow with electric field is applied.

Types of charges in semiconductors

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Fermi Function–The Probability of an Energy State Being Occupied by an Electron

f(E)0.5 1

Ef

Ef – kTEf – 2kT

Ef – 3kT

Ef + kT

EfEf + 2kTEf + 3kT

E

kTEE feEf /)(1

1)( −+= Ef is called the Fermi energy or

the Fermi level.

( ) kTEE feEf −−≈)( kTEE f >>−

( ) kTEE feEf −−−≈ 1)( kTEE f −<<−

Boltzmann approximation:

( ) kTEE feEf −−≈)(

( ) kTEE feEf −−−≈ 1)(

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Electron and Hole Concentrations

Remember: the closer Ef moves up to Ec , the larger n is; the closer Ef moves down to Ev , the larger p is.For Si, Nc = 2.8×1019cm-3 and Nv = 1.04×1019 cm-3.

kTEEc

CFeNn /)( −=

kTEEv

FVeNp /)( −=

Nc is called the effectivedensity of states.

Nv is called the effectivedensity of states of the valence band.

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Shifting the Fermi Level

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I. (i.e., N-type)

If ,

II. (i.e., P-type)

If ,

ad NNn −=

nnp i2=

iad nNN >>−

ad NN >> dNn = di Nnp 2=and

ida nNN >>− da NNp −=

pnn i2=

da NN >> aNp = ai Nnn 2=and

General Effects of Doping on n and p

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• When an electric field is applied to a semiconductor, mobile carriers will be accelerated by the electrostatic force. This force superimposes on the random thermal motion of carriers:

E.g. Electrons drift in the direction opposite to the E-fieldCurrent flows

Average drift velocity = | v | = μ ECarrier mobility

12

3

45

electron

E

123

45

electron

E =0

Carrier Drift

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• Mobile carriers are always in random thermal motion. If no electric field is applied, the average current in any direction is zero.

• Mobility is reduced by1) collisions with the vibrating atoms

“phonon scattering”

2) deflection by ionized impurity atoms “Coulombic scattering”

-

Si

-

As+

-B--

Carrier Mobility

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1E14 1E15 1E16 1E17 1E18 1E19 1E20

0

200

400

600

800

1000

1200

1400

1600

Holes

Electrons

Mob

ility

(cm

2 V-1 s

-1)

Total Im purity Concenration (atom s cm -3)Na + Nd (cm-3)

impurityphonon

impurityphonon

μμμ

τττ

111

111

+=

+=

Total Mobility

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Jp,drift = qpv = qpμp

Jn,drift = –qnv = qnμn

Jdrift = Jn,drift + Jp,drift = σ =(qnμn+qpμp)

conductivity of a semiconductor is σ = qnμn + qpμp

Resistivity, ρ = 1/ σ

∴

Conductivity and Resistivity

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N-type

P-type

ρ = 1/σ

DOPA

NT D

ENSI

TY cm

-3

RESISTIVITY (Ω⋅cm)

Relationship between Resistivity and Dopant Density

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• Rs value for a given conductive layer (e.g. doped Si, metals) in IC or MEMS technology is used– for design and layout of resistors– for estimating values of parasitic resistance in a device or

circuit

WLR

WtLR s== ρ

tRs

ρ≡

Rs is the resistance when W = L (in ohms/square)

if ρ is independent of depth x

V+ _

L

tW

I

Material with resistivity ρ

V+ _

L

tW

I

Material with resistivity ρ

V+ _

L

tW

I

Material with resistivity ρ

Sheet Resistance

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Particles diffuse from higher concentration to lower concentration locations.

Diffusion Current

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dxdnqDJ ndiffusionn =, dx

dpqDJ pdiffusionp −=,

D is called the diffusion constant. Signs explained:n p

x x

Diffusion Current

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Generation/Recombination Processes

Recombination continues until excess carriers = 0.Time constant of decay is called recombination lifetime

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A PN junction is present in almost every semiconductor device.

N- type

P- type

Donors

V

I

Reverse bias Forward bias

N P

VI

diodesymbol

– +

PN Junctions

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N-region P-region(a)

(b)

(c)

(d)

Depletionlayer

NeutralP-region

NeutralN-region

Ef

n 0 and p 0in the depletion layer

Ec

EfEv

Ec

Ev

Ef

Ec

Ev

Ef

Ev

Ec

≈ ≈

Energy Band Diagram and Depletion Layer

2lni

adbi n

NNq

kT=φ

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Qualitative Electrostatics

Band diagram

Built in-potential

From ε=-dV/dx

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Effect of Bias on Electrostatics

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Current Flow - Qualitative

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dep

depir τ

WqnAII += 0

)1(0 −= kTVqeII

⎟⎟⎠

⎞⎜⎜⎝

⎛+=

an

n

dp

pi NL

DNL

DAqnI 2

0

PN Diode IV Characteristics

Solar Cells

N P

-

+

short circuit

lightIsc

(a)

V0.7 V

–IscMaximumpower-output

Solar CellIV

IDark IV

0

(b)

Ec

Ev

Eq.(4.9.4)

Eq.(4.12.1)

p-i-n Photodiodes•Only electron-hole pairs generated in depletion region (or near depletion region) contribute to current

•Only light absorbed in depletion region contributes to generation–Stretch depletion region–Can also operate near avalanche to amplify signal

Light Emitting Diodes (LEDs)

•LEDs are typically made of compound semiconductors–Why not Si

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MOS: Metal-Oxide-Semiconductor

SiO2

metalgate

Si body

Vg

SiO2

gate

P-body

Vg

N+N+

MOS capacitor MOS transistor

MOS Capacitors

Ideal MOS Capacitor

– Oxide has zero charge, and no current can pass through it.– No charge centers are present in the oxide or at the oxide-

semiconductor interface.– Semiconductor is uniformly doped– ΦM = ΦS = χ + (EC – EF)FB

Ideal MOS CapacitorAt Equilibrium:

Ideal MOS CapacitorUnder Bias

– Let us ground the semiconductor and start applying different voltages, VG, to the gate

– VG can be positive, negative or zero with respect to the semiconductor

– EF,metal – EF,semiconductor = – q VG

– Since oxide has no charge (it’s an insulator with no available carriers or dopants), d Eoxide / dx = ρ/ε = 0; meaning that the E-field inside the oxide is constant.

Inversion conditionIf we continue to increase the positive gate voltage, the bands at the semiconductor bends more strongly. At sufficiently high voltage, Ei can be below EF indicating large concentration of

electrons in the conduction band.

We say the material near the surface is “inverted”. The “inverted” layer is not gotten by chemical doping, but by applying E-field. Where did we get the electrons from?

When Ei(surface) – Ei(bulk) = 2 [EF – Ei(bulk)], the condition is start of “inversion”, and the voltage VG applied to gate is called VT (threshold voltage). For VG > VT, the Si surface is inverted.

Ideal MOS Capacitor –n-type Si

Electrostatic potential, φ(x)Define a new term, φ(x) taken to be the potential inside the semiconductor at

a given point x. [The symbol φ instead of V used in MOS work to avoid confusion with externally applied voltage, V]

)]((bulk)[1)( ii xEEq

x −=φ

(surface)](bulk)[1iiS EE

q−=φ

](bulk)[1FiF EE

q−=φ

Potential at any point x

Surface potential

φF > 0 means p-type φF < 0 means n-type

| φF | related to doping concentration

Electrostatic potential

φS = 2φF at the depletion-inversion

transition point (threshold voltage)

φS is positive if the bands bend\ …….?

Charge Density - Accumulation

p-type silicon accumulation condition

The accumulation charges in the semiconductor are ……. , and appear

close to the surface and fall-offrapidly as x increases.

One can assume that the free carrier concentration at the oxide-semiconductor

interface is a δ-function.

M O S

VG < 0p-Si

Accumulation of holes

Charge on metal = −QM

Charge on semiconductor = − (charge on metal) |QAccumulation| = |QM|

x

Charge Density - Depletionp-type Si,

depletion conditionThe depletion charges in Si are

immobile ions - results in depletionlayer similar to that in pn

junction or Schottky diode. VG > 0

M O Sp-Si

Depletion of holes

wQM|q NA A W| = |QM|(−) (+)

If surface potential is φs, then the depletion layer width W will be

SA

Si2 φεqN

W = Does this equation look familiar?

Charge Density - Inversion

VG>>0

M O Sp-Si

Depletion of holes

wQM

Inversion electrons:δ-function-like

p-type Si, strong inversion

Once inversion charges appear, they remain close to the

surface since they are …….. Any additional voltage to the gate results in extra QM in gate and get compensated by extra inversion

electrons in semiconductor.

So, the depletion width does not change during inversion. Electrons appear as δ-function near the surface. Maximum depletion layer width W = WT

MOS C-V characteristics

•The measured MOS capacitance (called gate capacitance) varies with the applied gate voltage

– A very powerful diagnostic tool for identifying threshold voltage, oxide thickness, substrate doping concentration, and flat band voltage.

– It also tells you how close to an ideal MOSC your structure is.

•Measurement of C-V characteristics– Apply any dc bias, and superimpose a small (15 mV) ac

signal (typically 1 kHz – 1 MHz)

C-V: under accumulation

VG < 0

M O Sp-Si

Accumulation of holes

x

Consider p-type Si under accumulation.

VG < 0.Looks similar to parallelplate capacitor.

CG = Cox

where Cox = (εox A) / xox

CG is constant as a function of VG

C-V: under depletionDepletion condition:VG > 0

CG is Cox in series with Cswhere Cs can be defined as “semiconductor capacitance”

Cox= εox A / xoxCs = εSi A / W

CG = Cox Cs / (Cox + CS)s

A

Si2φ

ε=

qNW

where φs is surface potential

VG > 0

M O S

p-type Si

Depletion of holes

WQM

Cox Cs

CG decreases with increasing VG

C-V: under inversion (high frequency)

VG >>0

M O Sp-Si

Depletion of holes

WQM

Inversion electronsδ- function

Cox Cs

VG = VT and VG > VTInversion condition φs = 2 φF

FA

SiT 22

φε

==Nq

WW

At high frequency, inversionelectrons are not able to respondto ac voltage. Cox= εox A / xox

Cs = εSi A / WT

CG (ω →∞) = Cox Cs / (Cox + CS)

CG will be constant for VG ≥ VT

At low frequency, the inversion electrons will be able to respond to the ac voltage. So, the gate capacitance will be equal to the “oxide capacitance”(similar to a parallel plate capacitance).

CG (ω → 0) = Cox= εox A / xox

Ideal MOSC (p-type Si)

C-V: under inversion (low frequency)

CG increases for VG ≥ VT until it reaches Cox

CCox

accumulation depletion inversionVgVfb Vt

high frequency

low frequency

The First Transistor

1956 Physics Nobel Prize

Invention of the Field-Effect Transistor

In 1935, a British patent was issued to Oskar Heil. A working MOSFET was not demonstrated until 1955.

Today’s MOSFET Technology

Gate oxides as thin as 1.2 nm can be manufactured reproducibly.Large tunneling current through the oxide limits oxide-thicknessreduction.

Introduction to the MOSFET

Basic MOSFET structure and IV characteristics

Introduction to the MOSFET

Two ways of representing a MOSFET:

Complementary MOSFETs (CMOS)

When Vg = Vdd , the NFET is on and the PFET is off. When Vg = 0, the PFET is on and the NFET is off.

NFET PFET

Qualitative discussion: n-MOSFETVG > VT ; VDS ≈ 0ID increases with VDS

VG > VT; VDS small, > 0ID increases with VDS , but rate of increase decreases.

VG > VT; VDS ≈ pinch-offID reaches a saturation value, ID,satThe VDS value is called VDS,sat

VG > VT; VDS > VDS,satID does not increase further, saturation region.

Threshold voltage for NMOS and PMOSWhen VG = VT, φs = 2 φF; we get expression for VT.

FSi

A

ox

SioxFT 222 φ

εεε

+φ=NqxV

Ideal n-channel(p-silicon) deviceboth terms positive

⎟⎟⎠

⎞⎜⎜⎝

⎛φ

εεε

−+φ= |2|22 FSi

D

ox

SioxFT

NqxVIdeal p-channel(n-silicon) deviceboth terms negative

εSi / εox = = 11.9 / 3.9 ≈ 3

](bulk)[1FiF EE

q−=φ

φF > 0 means p-type φF < 0 means n-type

How to Measure the VT of a MOSFET

Vt is measured by extrapolating the Ids versus Vgs (at low Vds) curve to Ids = 0.

tgsdsnstgsoxedsat VVVVVCL

WI −∝−= μ)(

Vds = 10mV

Ids

Vgs

Vt

Quantitative ID-VDS Relationships – 1st attempt“Square Law”

( )⎥⎥⎦

⎤

⎢⎢⎣

⎡−−

μ=

2

2DS

DSTGoxn

DVVVVC

LZI satDS,DS0 VV << TG VV >;

ID will increase as VDS is increased, but when VG – VDS = VT, pinch-off occurs, and current saturates when VDS is increased further. This value of VDS is called VDS,sat. i.e., VDS,sat = VG – VT and the current when VDS= VDS,sat is called IDS,sat.

( )2TGox

satD, 2VV

LCZI −

μ= satDS,D VV > TG VV >;

Here, Cox is the oxide capacitance per unit area, Cox = εox / xox

ID-VDS characteristics expected from a long channel (ΔL << L) MOSFET (n-channel), for various values of VG

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N-channel MOSFET

Layout (Top View)4 lithography steps are required:1. active area2. gate electrode3. contacts4. metal interconnects

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1) Thermal oxidation(~10 nm “pad oxide”)

2) Silicon-nitride (Si3N4)deposition by CVD(~40nm)

3) Active-area definition(lithography & etch)

4) Boron ion implantation(“channel stop” implant)

Simple NMOS Process Flow

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5) Thermal oxidation to growoxide in “field regions”

6) Si3N4 & pad oxideremoval

7) Thermal oxidation(“gate oxide”)

8) Poly-Si deposition by CVD

9) Poly-Si gate-electrodepatterning (litho. & etch)

10) P or As ion implantationto form n+ source and drainregions

Top view of masks

Simple NMOS Process Flow

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11) SiO2 CVD

12) Contact definition(litho. & etch)

13) Al deposition by sputtering

14) Al patterningby litho. & etchto form interconnects

Top view of masks

Simple NMOS Process Flow