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`Lab 11

D and JK FLIP-FLOPS

OBJECTIVE

1.To investigate the operation of an edge-triggered D flip-flop, the 7474 IC.2.To investigate the operation of a pulse-triggered J-K flip-flop, the 7476 IC.3.To write a VHDL code for D Flip Flop.4.To write a VHDL code for JK Flip Flop.

EQUIPMENT REQUIRED

Altera DE2-115 circuit board with USB Download cableQuartus II Web Edition software

DISCUSSION

In this experiment, you will be introduced to a device that can sustain a given output even when its inputs are removed. Such a device is said to possess memory. Examples of memory devices include flip-flops, which are the topic for this experiment. The following classes of flip-flops are investigated in this experiment:

Pulse-triggered J-K flip-flops

Edge-triggered D flip-flops

Recall that these flip-flops have set-up and hold times that must be satisfied if the circuits that employ them are to work properly. You will be asked to compare the 7474 D flip-flop to the 7475 D latch you examined in Experiment 1.

Pulse-Triggered J-K Flip-Flops

The J-K flip-flop eliminates the ambiguous conditions of an S-R flip-flop. In place of this invalid condition, the J-K has a “toggle” condition, a characteristic of thisflip-flop. Normally, a J-K flip-flop can be operated synchronously, since

its J and K inputs need a clock input for operation. It can also be operated asynchronously and have SET and CLEAR inputs to facilitate this.

Edge-Triggered D flip-flops

The D flip-flop is a J-K flip-flop with an inverter between the J and the K inputs. This causes the flip-flop to SET or RESET with only one synchronous signal input D. Like the J-K flip-flop, the D flip-flop also has an asynchronous mode.

VHDL

We will create basic flip-flops using VHDL (Very High Speed Integrated CircuitHardware Description Language).

PROCEDURE

1)Pulse-triggered J-K flip-flop: Using QUARTUS II create Block Diagram file for basic 7476 J-K flip-flop. The 7476 is a Master- Slave Flip-flop; however its output is sensitive to negative transition. Connect the input output pins to all the I/O’s. To verify both synchronous and asynchronous operation of J-K flip-flop,make the following connections.

2)Connect the asynchronous input PRESET and CLEAR to normally high Push Button KEY [3] PIN_R24 and KEY [2] PIN_N21 respectively. Connect J, K inputs to toggle SW [1] PIN_AC28 and SW [0] PIN_AB28 the clock (CLK) input to a pushbutton Key [0] PIN_M23.

3)Connect output Q to LEDR [0] PIN_G19 and   to LEDG [7] PIN_xxx. Recompile and

download your circuit on to the DE 2 board.

4)7476 synchronous operation: In this step, you will observe that the J and K inputs can be used to change the output state of the flip-flop. You will also observe that in order for these inputs to effect a change, a clock pulse must be applied. For this reason, the J, K and CLK inputs are referred to as synchronous inputs. Verify this by performing the following steps:

5)Change the J and K input switch settings, and observe that nothing happens to Q.

6)SET J = 1 and K = 1, and apply a positive-going transition at CLK Do this by pressing and holding the CLK pushbutton key. What happens to Q?___________.

7)Repeat step 2 using a negative-going transition at CLK. Do this by releasing the pushbutton key. What happened to Q?

__________________.

8)This shows that the flip-flop responds to only negative-going transitions. Apply several more pulses to the CLK input. What happens?

_________________.

9)If Q is LOW, pulse the CLK input so that Q is HIGH. Set J = K = 0, and note that nothing happens to Q. Pulse the CLK input, observe that nothing happens to Q. WHY?

10)Set Q = 0, and note that nothing happens to Q. Pulse the CLK input momentarily. What happened to Q?

Apply several more pulses to the CLK input, and observe that Q remains in the LOW state.

11)Change J to 1 and then back to 0, and note that nothing happens to Q. Pulse the CLK input, you should observe that Q remains LOW. This shows that the J and K input states present at the time of the proper clock transition are the ones transferred to the flip-flop output.

Set J = 1, K = 0. Note that nothing happens to Q. Apply a clock pulse and observe that Q will go HIGH. Apply several more clock pulses. What happens to Q?

12) Simulation: Disable Preset and Clear input. Set flip-flop in the toggle mode and apply a 25 MHz clock signal at the CLK input. Draw the output waveform Q displayed, on timing diagram 11-1. What is the frequency of the Q waveform compared to the clock waveform? ______.

Figure 11-1

13)Set up the flip-flop in the toggle mode and apply an external 1 Hz signal to clock input. Note how the output toggles back and forth.

14)7476 asynchronous operation: The DC SET and DC CLEAR inputs are asynchronous inputs that operate independently from the

synchronous inputs (J, K, and CLK). These inputs are often labeled  and   (for preset and clear). The over bar indicates active LOW. The asynchronous inputs override the synchronous inputs when activated.

Verify this by leaving the flip-flop in toggle mode and then hold the DC CLEAR input LOW and observe that the flip-flop output stops toggling even though clock pulses are still being applied. Q will remain LOW, until the first clock pulse after the DC CLEAR pushbutton is released.

15)Now hold the DC SET input LOW. You should now observe that the flip- flop output stops toggling and remains HIGH as long as DC SET is held LOW.

16)Edge-triggered D flip-flop – 7474 IC: The 7474 IC has two individual positive edge-triggered D flip-flops with separate clock inputs and DC SET and DC CLEAR inputs. Implement a 7474 IC using Quartus II Block Diagram file. Make the following connections to the D flip-flop and then recompile and download the file to DE2 board:

1)Connect a normally HIGH pushbutton key to DC SET & DC CLEAR.2)Connect a toggle switch to the D input.3)Connect a normally HIGH pushbutton key to the CLK input.

4)Connect LED monitors to Q and .

17) 7474 synchronous operation: Monitor the Q output. Observe that nothing happens when you toggle the D input switch back and forth. This is because the D input is a synchronous input that operates with the CLK input.

Clear Q to 0 by momentarily pulsing the DC CLEAR input LOW. Set D to 1, and apply a negative-going transition at CLK. Do this by pressing and holding the CLK pushbutton LOW. What happens to Q?

Now apply a positive-going pulse at CLK by releasing the pushbutton key. What happens? ___________. This proves that the flip-flop responds only topositive-going transitions.

Make D = 0, and pulse CLK momentarily. This should clear Q back to 0.

18) 7474 asynchronous operation: For both DC SET and DC CLEAR, verify the following:

1)Inputs are active LOW and do not require a pulse at CLK to become activated.

2)The inputs override the synchronous input signals.

19)Positive Edge Triggered D Flip-Flop

-----------------------------------------------------------

--VHDL example of

--Positive Edge Triggered D Flip-Flop

----------------------------------------------------------

LIBRARY ieee;   

USE ieee.std_logic_1164.all; 

----------------------------------------------------------- 

ENTITY dff IS 

PORT (     

d, clk: IN STD_LOGIC; ---- inputs

q: OUT STD_LOGIC);---- outputs

END dff;

---------------------------------------------------------------------

ARCHITECTURE descp OF dff IS

BEGIN 

PROCESS (d, clk) --- respond to these inputs

BEGIN 

IF (clk = ‘1’ AND clk’ EVENT) THEN --- clock positive Edge

q <= d; 

END IF; 

END PROCESS; 

END descp; 

   

20) Positive Edge Triggered D Flip-Flop with Asynchronous PREset and CLeaR

-----------------------------------------------------------

--VHDL example of

--Positive Edge Triggered D Flip-Flop

--With Asynchronous Preset and Clear

----------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all; 

----------------------------------------------------------- 

ENTITY dff_asynch IS 

PORT (     

d, clk, pre, clr: IN STD_LOGIC; ---- inputs

q: OUT STD_LOGIC);---- outputs

END dff_asynch;---------------------------------------------------------------------

ARCHITECTURE beh OF dff_asynch IS

BEGINPROCESS (d, clk, pre, clr)

BEGIN 

IF pre = '0' THEN -- Don’t wait for clockq <= '1'; -- asynchronous preset

ELSIF clr = '0' THEN 

q <= '0'; -- asynchronous clear

ELSIF (Clk='1' AND Clk’ event) THEN -- Positive Edge q <= d;

END IF;

END PROCESS;

END beh;

21)Positive Edge Triggered JK Flip-Flop with Asynchronous PREset and CLeaR

--VHDL example of

--Positive Edge Triggered JK Flip-Flop

--With Asynchronous Preset and Clear

----------------------------------------------------------

LIBRARY 

ieee;   

USE 

ieee.std_logic_1164.all; 

----------------------------------------------------------- 

ENTITY jk_ff IS   

PORT (       

j, k, clk, pre, clr: IN STD_LOGIC; ---- inputs

q: 

OUT STD_LOGIC); ---- outputs

END jk_ff;     

ARCHITECTURE behv OF jk_ff IS

SIGNAL qstate: BIT; 

-- define the useful signal

BEGIN     

PROCESS (clk, pre, clr)   

--- respond to any of these signals

BEGIN     

IF pre = ‘1’ THEN     

qstate <= ‘1’; 

--- async preset

ELSIF clr = ‘0’ THEN     

qstate <= '0'; 

--- async clear

ELSIF (Clk='1' AND Clk’ event) THEN --- on Positive Edge of clock

IF j = ‘0’ AND k = ‘1’ THEN qstate <= ‘0’;

ELSIF j = ‘1’ AND k = ‘0’ THEN qstate <= ‘1’;

ELSIF j = ‘1’ AND k = ‘1’ THEN qstate <= NOT qstate;

END IF;     

END PROCESS;     

q <= qstate;     

END behv;     

QUESTIONS

1.The J and K input levels of a 7476 J-K flip-flop are transferred to the Q output on the ___________________ at CLK.

2.The DC SET and DC CLEAR inputs to a 7476 J-K flip-flop are active________ inputs and {operate with, operate independently from] the CLK signal.

3.The D input level of a 7474 D flip-flop is transferred to the Q output on the___________________ at CLK.

4.How did the D flip-flop in this experiment differ from the D Latch 7475 in Experiment 1?

5.How does a latch differ from a flip-flop?Convert PDF to HTML