Scout PCB Engineering Specification (PowerQUICC II +...

Semiconductor Products SectorMOTOROLANETWORKING & COMMUNICATION

SYSTEMS GROUP

Scout PCB Engineering Specification

AUTHOR: Bruce Parker - NSD

(PowerQUICC II + MPC750)

RevisionDate Revision Level

Revision History

Initial Draft 0.007/22/98

2nd Draft 0.211/12/98

Engineering Release 1.002/25/99

Added Appendix A (CPLD VHDL source) 1.104/14/99

Semiconductor Products SectorMOTOROLANETWORKING & COMMUNICATION

SYSTEMS GROUP

This page is intentionally left blank.

Motorola Scout PCB - Engineering Specification

TABLE OF CONTENTS

1 - General Information 11•1 Introduction 11•2 Abbreviations’ List 11•3 Related Documentation 11•4 Scout Features 2

2 - Functional Description 42•1 Reset & Hard-Reset Configuration 4

2•1•1 Power - On Reset 42•1•1•1 Power - On Reset Configuration 4

2•1•2 Manual Hard Reset 42•1•2•1 Hard Rest Configuration 5

2•1•3 Manual Soft Reset 72•1•4 PQII Internal Hard Reset Sources 7

2•2 Abort Interrupt 72•3 Clock Generator 72•4 MPC750 Backside L2 Cache 82•5 Bus Configuration 82•6 Buffering 82•7 Chip - Select Generator 92•8 Synchronous Dram DIMM (60X Bus) 9

2•8•1 SDRAM Programming 112•8•2 SDRAM Refresh 12

2•9 Flash Memory SIMM 122•10 Local Bus Synchronous Dram 13

2•10•1 Local Bus SDRAM Programming 142•10•2 Local Bus SDRAM Refresh 15

2•11 Communication Ports 162•11•1 100/10 Base - T Port 162•11•2 RS232 Ports 16

2•11•2•1 RS-232 Ports’ Signal Description 172•12 Board Control & Status Register - BCSR 18

2•12•1 BCSR0 - Board Control - Status Register 0 192•12•2 BCSR1 - Board Control - Status Register 1 202•12•3 BCSR2 - Board Control - Status Register - 2 212•12•4 BCSR3 - Board Control - Status Register 3 23

2•13 COP/JTAG Port 242•14 Switches, Jumpers and Indicators 272•15 Resistor Options 27

3 - Memory Map 28 4 - Physical 29

4•1 Power 294•1•1 5V Bus 304•1•2 3.3V Bus 304•1•3 Core Voltage for the PQII 304•1•4 Core Voltage for the MPC750 304•1•5 12V Bus 30

4•2 Connectors 314•2•1 5V Power Connector 31

Release 1.1 i


TABLE OF CONTENTS

4•2•2 12V Power Connector 314•2•3 Fast Ethernet Port Connector 314•2•4 RS232 PortS Connector 314•2•5 MPC750 COP/JTAG Port Connector 314•2•6 PQII COP/JTAG Port Connector 314•2•7 CPM Expansion Connectors 314•2•8 Logic Analyzer Connectors 31

4•3 PCB Layout 32APPENDIX A - CPLD Source File A-1

ii Release 1.1

Motorola Scout PCB - Engineering Specification LIST OF TABLES

TABLE 2-1. Hard Reset Configuration Word 6TABLE 2-2. PQII Hard Reset Configuration Word by Location 7TABLE 2-3. Scout Chip Selects’ Assignment 9TABLE 2-4. Projected SDRAM DIMM Performance 11TABLE 2-5. 66 MHz SDRAM DIMM Mode Register Programming 11TABLE 2-6. Flash Memory Performance 13TABLE 2-7. Local Bus SDRAM Performance - 66MHz 13TABLE 2-8. 66 MHz Local Bus SDRAM Mode Register Programming 14TABLE 2-9. BCSR0 Description 19TABLE 2-10. BCSR1 Description 20TABLE 2-11. BCSR2 Description 21TABLE 2-12. FLASH Presence Detect (7:5) Encoding 22TABLE 2-13. FLASH Presence Detect (4:1) Encoding 22TABLE 2-14. EXTOOLI(0:3) Assignment 22TABLE 2-15. External Tool Revision Encoding 22TABLE 2-16. Scout PCB Revision Encoding 23TABLE 2-17. BCSR3 Description 23TABLE 2-18. PQII’s COP/JTAG Port Connector’s Signal Description 25TABLE 2-19. MCP750’s COP/JTAG Port Connector’s Signal Description 26TABLE 3-1. Scout Memory Map 28

Release 1.1 iii

Motorola Scout PCB - Engineering Specification LIST OF TABLES

iv Release 1.1

Motorola Scout PCB - Engineering Specification LIST OF FIGURES

FIGURE 1-1 Scout Block Diagram 3FIGURE 2-1 Clock Generator Scheme 8FIGURE 2-2 SDRAM DIMM Connection Scheme 10FIGURE 2-3 Local SDRAM Connection Scheme 14FIGURE 2-4 RS232 Serial Ports’ Connector 17FIGURE 2-5 Debug Station Connection Schemes 24FIGURE 2-6 COP/JTAG Port Connector 24FIGURE 4-1 Scout Power Scheme 29

Release 1.1 v

Motorola Scout PCB - Engineering Specification LIST OF FIGURES

vi Release 1.1


General Information

1 - General Information

1•1 IntroductionThis document sets the engineering specifications for the Scout PCB.

The Scout PCB is a design which combines Motorola’s 750 RISC microprocessor with Motorola’s Power-QUICC II (PQII) microprocessor. The major focus of this design is to evaluate a system which utilizes thehigh performance 750 with a backside L2 cache as the system processor, and utilizes the integrated com-munication and memory controller features of the PQII. In this mode, the PPC processor inside the PQIIdevice is disabled. A configuration option will allow the user to enable the PQII processor, thus enabling amulti-processor system.

The 750, PQII, and system memory are connected via the standard PPC bus. System memory is imple-mented with a single SDRAM DIMM by multiplexing the PPC address bits appropriately. Boot memory isimplemented with FLASH SIMM modules. The PQII memory controller is used to control the SDRAM, theFLASH, and the address multiplexers. Mictor type connectors will provide logic analyzer visibility to thePPC bus. In addition, the PQII's local memory bus utilizes SDRAM devices.

Communication ports on the Scout design include a 10/100 BaseT Ethernet port, a RS232 serial port, andJTAG/COP debug ports. A communication expansion connector compatible with the type used on the ADSPQII board is included to allow additional communication devices to be added.

Scout is designed to run the PPC bus at up to 66 MHz. The L2 is designed to run at 133 MHz.

This specification is to be considered as a “living document”, and will be subjected to refinements as thedesign and development progresses.

1•2 Abbreviations’ List• PPC - PowerPC

• PQII - PowerQUICC II

• UPM - User Programmable Machine

• GPCM - General Purpose Chip-select Machine

• GPL - General Purpose Line (associated with a UPM)

• BSCR - Board Control & Status Register.

• BGA - Ball Grid Array

• SIMM - Single In-line Memory Module

• DIMM - Dual In-Line Memory Module

• PCB - Printed Circuit Board

1•3 Related Documentation• PowerQUICC II User’s Manual.

• MPC750 User’s Manual and Hardware Specifications.

• Scout Schematics.

Release 1.1 1


General Information

1•4 Scout Features

o 64 bit PowerQUICC II Communications Processor, running internally up to 166MHz withup to a 66MHz external bus frequency.

o 64 bit MPC750 Processor with 1Mbyte backside L2 Cache. The Processor will run inter-nally up to 266MHz, the L2 Cache will run up to 133MHz external bus frequency, and thePPC bus will run up to a 66MHz external bus frequency.

o 32 MByte, Unbuffered, 168 pin Synchronous Dram DIMM, residing on the 60X bus, con-

trolled by SDRAM machine 1. Automatic DIMM Identification via PQII’s I2C port andDIMM’s serial eeprom. An address latch and multiplexer is included to interface the PPCbus to the SDRAM.

o 16 MByte Flash Memory, 64-bit wide, buffered from the 60X bus. Implemented with two 80pin Flash SIMM modules. Support for up to 32 MByte, controlled by the GPCM, 5V or 12VProgrammable, with Automatic Flash SIMM identification, via the BCSR.

o 4 MByte unbuffered SDRAM on Local bus, controlled by SDRAM machine 2, soldered di-rectly on board.

o Board Control & Status Register - BCSR, Controlling Board’s Operation.

o Programmable Hard-Reset Configuration via Flash memory.

o High density (MICTOR) Logic Analyzer connectors provide PPC bus visibility and fast logicanalyzer connection.

o 100/10-Base-T Port on FCC2 with T.P. I/F, MII controlled, using Level One LXT970.

o Single RS232 port residing on SCC1.

o Module disable option for all communication transceivers (BCSR controlled) enabling useof communication ports off-board via the expansion connectors.

o Dedicated PQII communication ports expansion connectors for convenient tools connec-tion, carrying necessary bus signals for transceivers’ M/P I/F connection. Implemented with2 X 128 pin DIN 41612 receptacle connectors.

o External Tools Identification & Status read capability, via the BCSR.

o Soft / HardA Reset Push - Button

o ABORT Push - Button

o SingleB 5V Supply.

o Over Voltage Protection for Power Inputs.

o Independent, adjustable voltage regulators for the PQII and the MPC750.

A. Hard reset is applied by depressing BOTH Soft Reset & ABORT buttons.B. Unless a 12V programmable Flash SIMM is being used.

2 Release 1.1

Motorola

Scout PC

B - E

ngineering Specification

Gen

eral Info

rmatio

n

FIG

UR

E 1-1 S

cou

t Blo

ck Diag

ram

RAM DIMMingle 168 pin)

LASH SIMMDual 80 pin)

Release 1.1 3

ClockFanout

10/100 BaseT

PPC Visibility

SD(S

750 L2 Cache

COP

Latches/Muxes

Latches/BuffersF(

SDRAM(4 MB)

PPC Bus

Local Bus

PPC

COP

PowerQUICCII

OSC

RS232 UART

CPM Expansion

PowerConversion

+5V

Buffers

BCSR

+3.3VMPC750 CorePQII Core


Functional Description

2 - Functional DescriptionIn this chapter the various functional modules of the Scout design are described in detail.

2•1 Reset & Hard-Reset ConfigurationThere are several reset sources on Scout:

1) Power On Reset

2) Manual Hard-Reset

3) Manual Soft-Reset

4) PQII Internal Sources.

2•1•1 Power - On Reset

The power on reset to Scout initializes the two processors and the programmable logic after power up.When power is first applied to the system, the PORESET* signal must be asserted until the clocks arestable. This time will vary depending on the type of oscillator used. On Scout, this time has been measuredto be about 20-50 msec. The Scout design uses the programmable Altera device to guarantee a minimumPORESET* time of approximately one second. This could also be accomplished by using standard poweron reset monitor devices which provide a minimum time greater than that needed for the clocks to stabilize.

In addition to the programmable logic, a power monitor is provided on the Scout design. The power monitor,implemented with Motorola’s MC34064P-5, monitors the +5 Volt input voltage, and asserts the PORESET*input to the board when its input voltage is below 4.6 Volts.

Power On Reset may be generated during initial power up or manually by an optional dedicated push-button. The push-button must be connected to a 2 pin header provided on the board.

2•1•1•1 Power - On Reset ConfigurationAt the end of the Power - On reset sequence, MODCK(1:3) are sampled by the PQII to configure thevarious clock modes of the PQII (core, cpm, bus...). On Scout, the MODCK(1:3) pins are controlled byoption resistors. The default resistor setting will configure the PQII as follows: bus = 50MHz, CPM =100MHz, Core = 150MHz. Refer to the PQII hardware specifications for the complete table of possible set-tings.

Following the power-on reset sequence is the hard-reset sequence, within which, many other differentoptions are configured (see 2•1•2•1 "Hard Rest Configuration" on page 5). Among these options are addi-tional clock configuration bits, MODCK(4:7), which determine additional options for the clock generator.Although these bits are sampled at hard-reset configuration, i.e. whenever the hard-reset sequence isentered, they are influential only once - after power-on reset. If a hard reset sequence is entered later on,these bits although sampled, are don’t care.

2•1•2 Manual Hard Reset

To allow run-time Hard-reset, when the COP controller is disconnected from Scout and to support residentdebuggers, manual Hard reset is facilitated. Depressing both Soft-Reset and ABORT buttons assert theHRESET* signal, generating a HARD RESET sequence.

Since the HRESET* signal may be driven by the PQII, it is driven to the PQII with an open-drain gate. Ifoff-board H/W connected to Scout is to drive the HRESET* signal, then it should do so with an open-draingate to avoid contention over this line.

When Hard Reset is generated, the PQII is reset in a destructive manner, i.e., the hard reset configurationis re-sampled and all registers (except for the PLL’s) are reset, including memory controller registers, whichresults in loss of any dynamic memories’ contents.

To save on PCB real-estate, this button will not be a dedicated one, but is shared with the Soft-Reset button

4 Release 1.1



-

and the ABORT button. When both are depressed, Hard Reset will be generated.

2•1•2•1 Hard Rest ConfigurationWhen Hard-Reset is applied to the MPC750, it samples the PLLCFG(0:3) pins to set the Core-to-Bus fre-quency ratio. On Scout, the PLLCFG pins are controlled by option resistors which may be placed in eithera “pullup” or “pulldown” position. The default resistor position will set the PLLCFG bits to 0b1010, whichsets the MPC750 into 4:1 mode. Assuming a 66MHz bus frequency, the MPC750 core will run at 266MHz.Refer to the MPC750 hardware specifications for the complete table of possible ratios and the associatedPLLCFG encoding. Note, this ratio setting is completely independent of the clock ratio setting for the PQII.

When Hard-Reset is applied to the PQII (externally as well as internally), it samples the Hard-Reset con-figuration. The Scout design keeps RSTCONF* asserted (low) during HRESET* asserted, so the PQII willact as a configuration master.

During the hard reset sequence, the configuration master reads the flash memory at addresses 0x0, 0x8,0x10, 0x18,... a byte each time, to assemble the 32 bit configuration word. A total of 64 bytes of data isread from D(0:7) to acquire 8 full configuration words for systems that may have up to 8 PQII chips. Duringthis hard reset configuration, the MPC750 is held idle in its own hard reset state.

The configuration word for a singleA PQII will be stored in the flash memory simm, while the other 7 wordsare not initialized, as there are no additional PQIIs on Scout. TABLE 2-1. "Hard Reset Configuration Word"

A. Although the PQII as configuration master reads 8 configuration words, only the 1’st configuration word is influential.

Release 1.1 5



lists the required configuration for the PQII in its core disabled mode for the Scout PCB.

Using TABLE 2-1., the FLASH memory controlled by CS0* must be initialized with the PQII’s configuration

TABLE 2-1. Hard Reset Configuration Word

FieldProg Value[Bin]

Implication

ERB ’0’ Internal Arbitration Selected.

EXMC ’0’ Internal Memory Controller. CS0* active at system boot.

CDIS ’1’ Core Disabled.

EBM ’1’ 60x bus compatible

BPS ’00’ 64 Bit Boot Port Size.

Reserved ’00’ Reserved.

L2CPC ’00’ CI*/BADDR(29)/IRQ2* selected as CI*WT*/BADDR(30)/IRQ3* selected as WT*L2_HIT*/IRQ4* selected as L2HIT*CPU_BG*/BADDR(31)/IRQ5 selected as CPU_BG*

ISPS ’0’ 64 bit internal space for external master access.


ISB ’000’ IMMR initial value 0x00000000, i.e., the internal space residesinitially at this address.

BMS ’0’ Boot memory (Flash) at high memory (0xFE000000).

BBD ’0’ ABB*/IRQ2* pin is ABB*DBB*/IRQ3* pin is DBB*


LBPC ’00’ Local Bus pins function as Local bus.

APPC ’10’ MODCK1/AP(1)/TC(0) functions as BNKSEL(0)MODCK2/AP(2)/TC(1) functions as BNKSEL(1)MODCK3/AP(3)/TC(2) functions as BNKSEL(2)IRQ7*/APE* functions as IRQ7*CS11*/AP(0) functions as CS11*

CS10PC ’01’ CS10*/BCTL1/DBG_DIS* functions as BCTL1

PHE ’0’ (x) PCI configured as Agent. Don’t-care for this application.


MODCK_HI 0101 Core starts at 2x the bus frequency.

6 Release 1.1



word according to TABLE 2-2. "PQII Hard Reset Configuration Word by Location".

2•1•3 Manual Soft Reset

To allow run-time Soft-reset, when the COP controller is disconnected from Scout and to support residentdebuggers, a Soft Reset push-button is provided. When the Soft Reset push-button is depressed, theSRESET* signal will be asserted, generating a Soft Reset sequence.

Since the SRESET* signal may be driven by the PQII, it is driven by an open-drain gate, to avoid contentionover that line. If off-board H/W connected to Scout is to drive the SRESET* signal, then it should do so withan open-drain gate to avoid contention over this line.

Note, this button is implemented as a slide switch on the ENG revision of Scout.

2•1•4 PQII Internal Hard Reset Sources

The PQII has internal sources which generate Hard / Soft resets. Among these sources are:

1) Loss of Lock Reset (Hard)

2) Check-Stop Reset (Hard)

3) S/W Watch Dog Reset (Hard)

4) COP Reset (Hard / Soft)

In general, the PQII asserts a reset line HARD or SOFT for a period of 512 clock cycles after the resetsource has been identified. A hard reset sequence is followed by a soft reset sequence.

2•2 Abort InterruptThe ABORT interrupt (NMI), is generated by a push-button. When this button is depressed and released,the SMI* interrupt input to the MPC750 and the IRQ0* input to the PQII will be asserted. Refer to TABLE2-9. "BCSR0 Description" on page 19 for details on how to service this interrupt. The purpose of this typeof interrupt is to support the use of resident debuggers if any is made available to Scout.

To support external (off-board) generation of an NMI, the NMI_OUT* line is driven by an open-drain gate.If external hardware drives this signal, it is compulsory that NMI_OUT* be driven by an open-drain (or open-collector) gate.

Note, this button is implemented as a slide switch on the ENG revision of Scout.

2•3 Clock GeneratorThe clock distribution network on Scout is implemented with a 66 MHz can oscillator which feeds aMotorola MPC903 low skew buffer. This buffer drives the various clock loads, including the PQII and theMPC750. All clock nets are series terminated and routed in equal lengths to minimize system clock skew.However, the clock nets to the SDRAM DIMM connector are shortened to allow for the trace length and

TABLE 2-2. PQII Hard Reset Configuration Word by Location

Byte Address Relative to CS0* base

Byte Value

0x00000000 0x30

0x00000008 0x00

0x00000010 0x02

0x00000018 0x45

Release 1.1 7



oltage

loading on the DIMM.

The PQII requires a single clock source for the main clock oscillator. All PQII bus timings are referenced tothe main clock input. The main clock input is the same frequency as the 60X bus frequency.

FIGURE 2-1 Clock Generator Scheme

2•4 MPC750 Backside L2 Cache

The MPC750 supports an optional backside L2 cache. The Scout design will provide 1 MByte of L2Cache, implemented with two Motorola MCM69P737 devices. These are pipelined, synchronous, burstSRAM, 100 pin TQFP devices in a x36 organization. The L2 memory’s core voltage and I/O vwill both be run at +3.3 Volts.

2•5 Bus ConfigurationOn the Scout design, the PQII must be configured in the 60x Bus mode. To interface the 60x bus to theSDRAM main memory, address latching and multiplexing is provided on Scout. Address latches areincluded to allow pipelining on the 60x address bus and to provide sufficient drive to the SDRAM andFLASH modules. Multiplexing is implemented with CBT type switches. The details of address multiplexingare dependent on the type of SDRAM DIMM used. The following multiplexing scheme supports 8 columnaddress, 4 internal bank DIMMs:

60x-bus A[21-28] => DIMM A[7-0] during CAS*

60x-bus A[11-20] => DIMM A[9-0] during RAS*

60x-bus A[8-10] => DIMM A[13-11] during RAS*

PQII SDA10 => DIMM A10/AP (programmed as A9 in the PQII’s PSDMR register)

PQII BNKSEL2 => DIMM BA0

PQII BNKSEL1 => DIMM BA1

Note: BNKSEL[0-2] are programmed as A[14-16] in the PQII’s PSDMR register, making them function as60x-bus A[6-8].

2•6 BufferingIn order to achieve best performance, it is necessary to reduce the capacitive load over the 60X bus asmuch as possible. Therefore, the slower devices on the bus, i.e., the Flash Simm, the BCSR, and the CPMexpansion connectors are buffered, reducing their capacitive load from the bus, while the SDRAM DIMM

66 MHZ

CLOCK GEN.

PQII

LOWSKEWBUF.

MPC750

8 Release 1.1



will not be buffered from the 60X bus.

Latches are provided for address and control lines, while transceivers are provided for data lines. Buffersare 74ALVT type which are powered by 3.3V and provide bus hold and 5V toleranceA.

To further reduce noise and reflections, series termination resistors are used on the SDRAM DIMM’saddress and control lines.

The data transceivers open only if there is an access to a validB buffered board address or during Hard -Reset configurationC. That way data conflicts are avoided in the case of an unbuffered memory read or off-board memory is read, provided that it is not mapped to a valid address on board. It is the users’ respon-sibility to avoid such errors.

The PQII’s local bus will not be buffered at all since there is only one slave on that bus, i.e., the SDRAM.

2•7 Chip - Select GeneratorThe memory controller of the PQII is used as a chip-select generator to access memory and I/O regions.The PQII’s chip-selects assignment to the various memories / registers on Scout is shown in TABLE 2-3."Scout Chip Selects’ Assignment" below:

2•8 Synchronous Dram DIMM (60X Bus)A 32 MByte SDRAM DIMM will be provided with the Scout PCB. The SDRAM DIMM data bus is unbufferedfrom the 60X bus. The DIMM will be a SAMSUNG KMM366S424BT or compatible. The DIMM’s data sheetmay be obtained on the Internet at URL: http://www.usa.samsungsemi.com/products. Note, the Scoutdesign requires an 8 column address type DIMM. The external multiplexing must be modified for DIMMs

A. Required for FlashB. An address which is covered in a Chip-Select region that controls a buffered device.C. To allow access to the Flash memory, where the hard reset configuration word is stored.

TABLE 2-3. Scout Chip Selects’ Assignment

Chip Select: Assignment Bus Timing Machine

CS0* Flash Memory SIMM (bank 0) 60X (Buffered) GPCM

CS1* BCSR 60X (Buffered) GPCM

CS2* SDRAM (DIMM CS0 & CS2) 60X (Main) SDRAM Machine 1

CS3* SDRAM (DIMM CS1 & CS3) 60X (Main) SDRAM Machine 1

CS4* SDRAM (Soldered on board) Local SDRAM Machine 2

CS5* Unused - -

CS6* Comm. Tool M/P I/F CS 1 60X (Buffered) GPCM / UPMx

CS7* Comm. Tool M/P I/F CS 2 60X (Buffered) GPCM / UPMx

CS8* Flash Memory SIMM (bank 1) 60X (Buffered) GPCM

CS9* Unused - -

CS10*/BCTL1/DBG_DIS* BCTL1 60X All

CS11* Unused - -

Release 1.1 9



which use 9 or more column address components.

Unlike memory SIMMs which had dedicated presence detect lines for configuration reporting, the DIMM’sconfiguration information is stored in a 256 Byte Serial EEPROM residing on the DIMM, compatible withthe I2C protocol. In fact, all necessary information is in the 1’st half of the EEPROM, while the 2’nd half issystem available. On Scout, the DIMM configuration EEPROM is connected to the PQII’s I2C controller.The DIMM’s I2C address is set by resistors which may be moved to either a pullup or pulldown position.The default I2C address of the DIMM is b111.

The SDRAM’s timing is controlled by SDRAM Machine #1 associated with the 60X bus, via its assignedChip Select line (See TABLE 2-3. "Scout Chip Selects’ Assignment" on page 9).

The SDRAM connection scheme is shown in FIGURE 2-2 "SDRAM DIMM Connection Scheme" below.

FIGURE 2-2 SDRAM DIMM Connection Scheme

CS0

RAS

CAS

WE

A(13:11)

A10

CKE

CLK(1:4)

DQMB(0:7)

DQ(0:63)

CS2

PSDRAS

PSDCAS

PSDWE

+3.3V pullup

SYSCLK(1:4)

D(0:63)

PSDDQM(0:7)A(21:28)

BANKSEL(1:2)

SDA

SCL

SA(2:0)

JEDEC SDRAM DIMM

I2CDAT

I2CCLK

CS2

Serial EEPROMSlave AddressSetting Switches.

A(9:0)A(8:20)

PSDAMUX

ALE

PSDA10

SD_A(13:11)

BA(1:0)

SD_A(9:0)

CS3CS1

CS3

10 Release 1.1



The projected SDRAM performance is shown in TABLE 2-4. "Projected SDRAM DIMM Performance" onpage 11

TABLE 2-4. Projected SDRAM DIMM Performance

2•8•1 SDRAM Programming

After power-up, the SDRAM needs to be initialized by means of programming to establish its mode of op-eration. An SDRAM is programmed by issuing a Mode Register Set command. During that command ex-ecution, data is passed to the SDRAM’s Mode Register through the SDRAM’s address lines. Whenoperating in the 60X bus compatible mode, the programmer must make the mode register data appear onthe correct 60X bus address lines. Following TABLE 2-5. "66 MHz SDRAM DIMM Mode Register Program-ming" below, a programmer must force the 60X bus address lines to be 0x00000110 during the moderegister set command.:

Cycle TypeSystem Clock

Cycles @ 66MHz Bus Clock Freq.

Burst Read - Page Miss 7a,1,1,1

a. From TS~ Asserted. 1’st access may be longer due to internalpipeline delay

Burst Read - Page Hit 5a,1,1,1

Burst Write - Page Miss 5a,1,1,1

Burst Write - Page Hit 4a,1,1,1

Refresh 8b

b. Not including arbitration overhead.

TABLE 2-5. 66 MHz SDRAM DIMM Mode Register Programming

SDRAM Address

Linea

a. Actually SDRAM’s A0 is connected to the 60X Bus’ A28 and so on...

60X Bus Address

SDRAM Mode Reg Field

Value Meaning:

A11 (MSB) - Reserved ’0’

A10 - Reserved ’0’

A9 - Opcode ’0’ Burst Read & Burst Write (copy back)

A8 - Reserved ’0’

A7 A21 Reserved ’0’

A6 - A4 A22-A24 CAS Latency ’010’ Data Valid 2 Clocks cycles after CAS Asserted

A3 A25 Burst Type ’0’ Sequential Burst

A2 - A0 A26-A28 Burst Length ’010’ 4 Word Burst Length

Release 1.1 11


12


The SDRAM machine 1 of the PQII needs to be initialized as well. The following register initialization hasbeen tested and proven to work with the DIMM specified previously.

1) PSDMR == 0x004F345A

2) MPTPR == 0x2000

3) PSRT == 0x05

4) OR2 == 0xFE002CC4

5) BR2 == 0x00000041

After these registers are initialized, the programmer should initialize the SDRAM in the following sequence:

1) issue Precharge All command

2) issue 8 CBR commands

3) issue a Mode set command

4) enable refreshing and normal mode in the PSDMR

2•8•2 SDRAM Refresh

The SDRAM is refreshed using its auto-refresh mode. Using SDRAM machine 1’s periodic timer, an auto-refresh command is issued to the SDRAM every 15 µsec, so that all 2048A SDRAM DIMM rows are re-freshed within the specified 32.8 msec. This leaves an interval of 1.2 msec of refresh redundancy withinthe refresh window as a safety measure to cover for possible delays in bus availability for the refresh con-troller.

2•9 Flash Memory SIMMScout’s FLASH Memory is 64 bits wide, provided via two JEDEC 80 pin FLASH SIMM modules. Eachmodule is 32 bits wide. Scout will be provided with two 8Mbyte, 90 nsec flash memory SIMMs providing atotal of 16MBytes. The FLASH SIMMs are manufactured by Smart Modular, based on AMD flash memo-ries, with a part number of SM73228XV1JAES9. The chip select design supports up to two 16MbyteSIMMS, for a maximum of 32MBytes of FLASH memory.

To allow for proper operation in 60X bus mode, the address bus for the flashB is latched.

The design supports SIMM modules of one or two banks per SIMM only. The PQII’s CS0* selects Bank0,while CS8* selects Bank1. This method reduces any need for external logic to decode multiple FLASH chipselects, and decreases the data hold time problems associated with FLASH devices. Software mustprogram the FLASH memory region to enable the extended hold time support in the PQII.

The access time of the Flash memory provided with Scout will be 90 nsec. Slower memories may not beused due to their extended data hold time, which could result in bus contention. By reading the delaysection of the Flash SIMM Presence-Detect lines, software can establish (via ORx) the correct number ofwait-states (considering 66MHz system clock frequency) required for accessing the FLASH SIMM.

Scout supports 5V programmable modules as well as 12V programmable modules. To program 12Vmodules the user must connect a 12V power source to the 12V power input on the Scout PCB. The 12Vpower input may be left unconnected if 5V programmable modules are used or if there is no need for flashprogramming.

The flash is controlled by the GPCM. During hard - reset initializationC the debugger (or any application S/

A. In fact each SDRAM component is composed of 2 internal banks each having 2048 rows, but they are refreshed inparallel.

B. As well as all other slow static devices.

Release 1.1



W for that matter) may read the Flash Presence-Detect lines via the BCSR and decide how to program theBRx & ORx registers, within which the size and the delay of the region are determined.

The performance of the flash memory is shown in TABLE 2-6. "Flash Memory Performance" below:

2•10 Local Bus Synchronous Dram4 MBytes of SDRAM will be provided on the PQII’s Local Bus, which may be used as application specificstorage. This SDRAM is unbuffered and is configured as 2 X 512K X 32. This memory is implemented withtwo MB811171622A- 84 chips by Fujitsu or compatibles and is soldered directly to the Scout PCB.

The SDRAM’s timing is controlled by the SDRAM machine 2 of the PQII, which is dedicated for the LocalBus and is assigned to a CS line according to TABLE 2-3. "Scout Chip Selects’ Assignment" on page 9.

The local bus SDRAM performance is shown in TABLE 2-7. "Local Bus SDRAM Performance - 66MHz" onpage 13:

C. I.e., initializations that follow the hard reset sequence at system boot.

TABLE 2-6. Flash Memory Performance

Number of System Clock Cycles @ 66 MHz Bus Clock Freq.

Cycle Type \ Flash Delay [nsec] 90

Read / Writea Access [Clocks]

a. The figures in the table refer to the actual write access. Thewrite operation continues internally and the device has to bepolled for completion.

8b

b. From TS* asserted. However, due to internal activity, thesefigures may be larger.

TABLE 2-7. Local Bus SDRAM Performance - 66MHz

Cycle Type

Bus Clock Cycles @ 66

MHz Bus Clock Freq.

Burst Read - Page Miss 6a,1,1,1

a. From TS* Asserted. 1’st access may belonger due to internal pipeline delay

Burst Read - Page Hit 4a,1,1,1

Burst Write - Page Miss 4a,1,1,1

Burst Write - Page Hit 2a,1,1,1

Refresh 8b

b. Not including arbitration overhead.

Release 1.1 13



FIGURE 2-3 Local SDRAM Connection Scheme

2•10•1 Local Bus SDRAM Programming

After power-up, the local bus SDRAM needs to be initialized by means of programming, to establish itsmode of operation. The SDRAM is programmed by issuing a Mode Register Set command. During thatcommand data is passed to the Mode Register through the SDRAM’s address lines. This command is fullysupported by the SDRAM machines of the PQII.

Mode Register programming values are shown in TABLE 2-8. "66 MHz Local Bus SDRAM Mode RegisterProgramming" below:

TABLE 2-8. 66 MHz Local Bus SDRAM Mode Register Programming

SDRAM Address

Linea


Value Meaning:

A11 (MSB) Reserved ’0’

A10 Reserved ’0’

A9 Opcode ’0’ Burst Read & Burst Write (copy back)

A8 Reserved ’0’

A7 Reserved ’0’

A6 - A4 CAS Latency ’010’ Data Valid 2 Clocks cycles after CAS Asserted

A3 Burst Type ’0’ Sequential Burst

CS

RAS

CAS

W

A11

A10

A(9:8)

A(7:0)

CKE

CLK

DQMU

DQML

DQ(15:0)

CS

RAS

CAS

W

A11

A10

A(9:8)

A(7:0)

CKE

CLK

DQMU

DQML

DQ(15:0)

CS4

LSDRAS

LDCAS

LSDWE

LSDA10

+3.3V pullup

SYSCLK

LCL_D(0:15)

LCL_D(16:31)

LBS0

LBS1

LBS2

LBS3

LCL_A(22:29)

LCL_A(20:21)

LCL_A18

14 Release 1.1



d in

2•10•2 Local Bus SDRAM Refresh

The Local Bus SDRAM is refreshed using its auto-refresh mode. Using SDRAM machine 2’s periodic timer,an auto-refresh command is issued to the SDRAM every 15 µsec, so that all 2048A SDRAM DIMM rowsare refreshed within spec’d 32.8 msec, while leaving a 1.2 msec interval of refresh redundancy within thatwindow, as a safety measure, covering for possible delays in bus availability for the refresh controller.

A2 - A0(lsb)

Burst Length ’010’ 4 Word Burst Length

a. Actually SDRAM’s A0 is connected to PQII’s LCL_A29 and so on...

A. In fact each SDRAM component is composed of 2 internal banks each having 2048 rows, but they are refresheparallel.

TABLE 2-8. 66 MHz Local Bus SDRAM Mode Register Programming

SDRAM Address

Linea


Value Meaning:

Release 1.1 15



2•11 Communication PortsThe PQII on Scout is capable of supporting numerous communication ports and protocols. The Scout PCBincludes two communication ports on board and CPM expansion connectors. The CPM expansion connec-tors allow various communication boards to be connected to the PQII’s CPM ports on the Scout PCB.

The communication ports’ interfaces provided on Scout are listed below:

1) 100/10-Base-T Port on FCC2 with T.P. I/F, MII controlled.

2) Single RS232 port residing on SCC1.

2•11•1 100/10 Base - T Port

A fast Ethernet port with a T.P. (100-Base-TX) I/F is provided on Scout. This port also supports 10 Mbpsethernet (10-Base-T) via the same transceiver - the LXT970 by Level One.

The LXT970 is connected to FCC2 of the PQII via the MII interface, which is used for both the device’scontrol and data path. The initial configuration of the LXT970 is done by setting desired values at 8 config-uration signals: FDE, CFG(0:1) and MF(0:4). The MF(0:4) pins are controlled by 4 voltage levels, whichallows each pin to configure two functions. On Scout these pins are driven by factory set 0Ω resistors, con-nected to a voltage divider, allowing future option change during production.

The LXT970 reset input is driven by the HRESET* signal of the PQII, resetting the transceiver wheneverthe hard-reset sequence is taken. The LXT970 may also be reset by either asserting the FETH_RST bit inBCSR1 (see TABLE 2-10. "BCSR1 Description" on page 20) or by asserting bit 0.15 (MSB of LXT970control register) via MII I/F.

To allow external use of FCC2, its pins appear at the CPM expansion connectors and the ethernet trans-ceiver may be Disabled / Enabled at any time via the MII’s MDIO port.

The LXT970 is able to interrupt the PQII via the IRQ7* line. This signal is also connected to the CPM ex-pansion connectors. Therefore, any tool that connects to IRQ7*, or IRQ6* for that matter, should drivethese signals only with an Open Drain buffer.

2•11•2 RS232 Ports

To assist user’s applications a single RS232 port is provided on Scout, connected to the SCC1 port of thePQII. The transceiver is implemented with a MC145583 transceiver which generates RS232 levels inter-nally using a single 3.3V supply and has shutdown mode, during which receive buffers are tri-stated. Whenthe RS232EN1 bit in BCSR1 is asserted (low), the transceiver is enabled. When negated, the transceiverenters standby mode, within which the receiver outputs are tri-stated, enabling use of the correspondingport’s pins off-board via the expansion connectors.

A 9 pin, female D-Type (DB9) connector is provided, configured to be directly connected to a standard IBM-

16 Release 1.1



PC like RS232 connector.

FIGURE 2-4 RS232 Serial Ports’ Connector

2•11•2•1 RS-232 Ports’ Signal Description In the list below, the directions ’I’, ’O’, and ’I/O’ are relative to the Scout board. (I.e. ’I’ means input to Scout)

• CD (O) - Data Carrier Detect. This line is always asserted by Scout.

• TX (O) - Transmit Data.

• RX (I) - Receive Data.

• DTR (I) - Data Terminal Ready. This signal may be used by the software on Scout to detect if aterminal is connected to the Scout board.

• DSRA (O) - Data Set Ready. This line is always asserted by Scout.

• RTS (I) - Request To Send. This line is not connected in Scout.

• CTS (O) - Clear To Send. This line is always asserted by Scout.

A. Since there are only 3 RS232 transmitters in the device, DSR is connected to CD.

1

TX

2TX

3RTS

4CTS

5

DSR6

GND

7

CD

89 N.C.DTR

Release 1.1 17



2•12 Board Control & Status Register - BCSRMost of the hardware options on Scout are controlled or monitored by the BCSR, which is a 32 bit wideread / write register file. The BCSR is accessed via the PQII’s memory controller (see TABLE 2-3. "ScoutChip Selects’ Assignment" on page 9) and in fact includes 4 registers: BCSR0 to BCSR3. Since theminimum block size for a CS region is 32KBytes and only address lines A(27:28) are decoded by the BCSRfor register selection, BCSR0 - BCSR3 are duplicated multiple times inside that region. Although the reg-isters are only 32 bits wide, they are addressed on double word (64 bit) boundaries. This keeps the regis-ters all on the D(0:31) side of the data bus. See also TABLE 3-1. "Scout Memory Map" on page 28.

The following functions are controlled / monitored by the BCSR:

1) Fast Ethernet Port Control which includes:

• Transceiver Initial Enable

• Transceiver Reset

2) RS232 port 1 Enable / Disable.

3) Flash Size / Delay Identification.

4) External (off-board) tools Support which include:

• Tool Identification

• Tool Revision

• Tool Status Information

5) S/W Option Identification.

6) Scout Revision code.

Since part of Scout’s modules are controlled by the BCSR and since they may be disabled in favor ofexternal hardware, the enable signals for these modules are presented at the CPM expansion connectors,so that off- board hardware may be mutually exclusive enabled with on-board modules.

18 Release 1.1



2•12•1 BCSR0 - Board Control - Status Register 0

The BCSR0 serves as a control register on Scout. It is accessed at offset 0 from the BCSR base address.It may be read or written at any time. BCSR0 gets its defaults upon Power-On reset. BCSR0 fields are de-scribed in TABLE 2-9. "BCSR0 Description" on page 19.

TABLE 2-9. BCSR0 Description

BIT MNEMONIC FunctionPON DEF

ATT.

0 - 25 Reserved Un-implemented 0 R

26 Abort Abort Sticky Bit. This bit may be asserted (low) either by writing a 0 to thisbit position, or by the abort push-button being depressed then released.Once this bit is asserted, it will remain asserted and the SMI* input to theMPC750 will remain asserted until cleared by software. This bit is clearedby software writing a 1 to this bit position, or by a PORESET cycle. Whenread, this bit represents the logic state of the NMI_OUT* signal.

1 R,W

27 Reserved Not used on Scout. (Used as L2C_INH on VADS PCB) 0 R

28 Reserved Not used on Scout. (Used as L2C_FLUSH on VADS PCB) 0 R

29 Reserved Not used on Scout. (Used as L2C_LOCK on VADS PCB) 0 R

30 GP_BIT General Purpose bit. When this signal is active (low), a dedicated LEDilluminates. When in-active (high), this LED is not illuminated. This LED isused for S/W signalling to the user. Note, this LED is not available on theENG revision of the Scout PCB.

1 R,W

31 SIGNAL_LAMP Signal Lamp. When this signal is active (low), a dedicated LED illuminates.When in-active (high), this LED is not illuminated. This LED is used for S/Wsignalling to the user.

1 R,W

Release 1.1 19




BCSR1 serves as a control register on Scout. It is accessed at offset 8 from the BCSR base address. Itmay be read or written at any time. BCSR1 gets its defaults upon Power-On reset. BCSR1 fields are de-scribed in TABLE 2-10. "BCSR1 Description" on page 20.



ATT.

0 - 25 Reserved Un-implemented. 0 R

26 ATM_EN Not used on Scout, but is connected to the CPM expansion connector. 0 R

27 ATM_RST Not used on Scout, but is connected to the CPM expansion connector. 0 R

28 FETHIEN Fast Ethernet Port Initial Enable. When asserted (low) the LXT970’s MIIport, residing on FCC2, is enabled after Power-Up or after FETH_RST isnegated. When negated (high), the LXT970’s MII port is isolated afterPower-Up or after FETH_RST is negated and all i/f signals are tri-stated. After initial value has been set this signal has no influence over the LXT970and MII isolation may be controlled via MDIO 0.10 bit.

1 R,W

29 FETH_RST Fast Ethernet Port Reset. When active (low) the LXT970 will be reset.This line is also driven by the HRESET* signal of the PQII. Since MDDIS pinof the LXT970 is driven low with this application, the negation of this signalcauses all the H/W configuration bits to be sampled for initial values anddevice control is moved to the MDIO channel which is the control path of theMII port.

1 R,W

30 RS232EN_1 RS232 port 1 Enable. When asserted (low) the RS232 transceiver for port1 is enabled. When negated, the RS232 transceiver for port 1 is in standbymode and SCC1 pins are available for off-board use via the expansionconnectors.

1 R,W

31 Reserved Not used on Scout. (Used as RS232EN_2 on VADS PCB) 0 R

20 Release 1.1



2•12•3 BCSR2 - Board Control - Status Register - 2

BCSR2 is a status register which is accessed at offset 0x10 from the BCSR base address. It is a read onlyregister which may be read at any time. BCSR2’s various fields are described in TABLE 2-11. "BCSR2 De-scription" on page 21.



ATT.

0 - 7 TSTAT(0:7) Tool Status (0:7). This field is reserved for external tool status report. Theexact meaning of each bit within this field is tool unique and therefore will bedocumented separately per each tool.

- R

8 - 11 TOOLREV(0:3) TOOL Revision (0:3). This field may contains the revision code of anexternal tool possibly connected to Scout. The various encodings of thisfield will be described per each tool user’s manual.

R

12 - 15 EXTOOLI(0:3) External Tools Identification. These lines, which are available at the CPMexpansion connectors, are intended to serve as tools’ identifier. On-board S/W may check these lines to detect the presence of various tools (h/wexpansions) at the CPM expansion connectors. For the external tools’codes and their associated combinations see TABLE 2-14."EXTOOLI(0:3) Assignment" on page 22.

- R

16 - 17 SWOPT(0:1) Software Option (0:1). This field shows the state of dedicated jumpersproviding an option to manually change a program flow.

0 R

18 - 19 Reserved Not used on Scout. (Used as L2CSIZE(0:1) on VADS PCB) - R

20 - 23 BREVN(0:3) Board Revision Number (0:3). This field represents the revision code,hard-assigned to Scout. See TABLE 2-16. "Scout PCB RevisionEncoding" on page 23, for revisions’ encoding.

- R

24 SWOPT2 Software Option 2. This is the LSB of the field showing the state of adedicated jumper providing an option to manually change a program flow.

0 R

25 - 27 FLASH_PD(7:5) Flash Presence Detect(7:5). These lines are connected to the FlashSIMM presence detect lines, which encode the Delay of the Flash SIMMmounted on the Flash SIMM socket. For the encoding of FLASH_PD(7:5)see TABLE 2-12. "FLASH Presence Detect (7:5) Encoding" on page22.

- R

28 - 31 FLASH_PD(4:1) Flash Presence Detect(4:1). These lines are connected to the FlashSIMM presence detect lines which encode the type of Flash SIMM mountedon the Flash SIMM socket. For the encoding of FLASH_PD(4:1) seeTABLE 2-13. "FLASH Presence Detect (4:1) Encoding" on page 22.

- R

Release 1.1 21



TABLE 2-12. FLASH Presence Detect (7:5) Encoding

FLASH_PD(7:5) FLASH DELAY [nsec]

000 - 010 Not Supported

011 90

100 70

101 - 111 Not Supported

TABLE 2-13. FLASH Presence Detect (4:1) Encoding

FLASH_PD(4:1) Flash TYPE / SIZE

0000 - 0001 TBD

0010 8MByte module organized as 2Mx32 (4 devices, 16Mbit devices, one bank)

0011 - 1111 TBD

TABLE 2-14. EXTOOLI(0:3) Assignment

EXTTOOLI(0:3) [hex] External Tool

0 VCOM - PQII Communication tool

1 - E Reserved

F Tool Non Existent

TABLE 2-15. External Tool Revision Encoding

TOOLREV(0:3) [hex] External Tool Revision

0 ENGINEERING

1 PILOT

2 A

3 - F Reserved

22 Release 1.1




BCSR3 is an additional control / status register which may be accessed at offset 0x18 from BCSR baseaddress. BCSR3 gets its defaults during Power-On reset and may be read or written at any time. The de-scription of BCSR3 is shown in TABLE 2-17. "BCSR3 Description" on page 23.

Since this register has no functional bits, software can utilize this location for writing diagnostic informationout on the bus. This is sometimes useful for tracking program flow with a logic analyzer.

TABLE 2-16. Scout PCB Revision Encoding

Revision Number (0:3) [Hex]

Scout Revision

F ENG (Engineering)

E X2

D-0 Reserved



ATT.

0 - 31 Reserved Un Implemented - -

Release 1.1 23



2•13 COP/JTAG PortThe Scout design provides individual JTAG connectors for both the MPC750 and the PQII processor. EachJTAG connector is connected to it’s processor’s JTAG/COP (Common On-chip Processor) port.

Debug tools running on a host computer connect to the processors on Scout via the JTAG connectors. Thedebug station connection scheme is shown in FIGURE 2-5 below. This method is based on an Ethernet toCOP I/F as implemented by either Hewlett Packard’s or Applied Microsystems’ platform.

FIGURE 2-5 Debug Station Connection Schemes

To support a debug station connection to the COP/JTAG port, a 16 pin generic header connector isprovided on Scout, carrying the COP/JTAG signals as well as additional signals aiding in system debug.The pin-out of this connector is a general Motorola recommendation for including a COP/JTAG port in adesign. The pin-out of the COP/JTAG connector is shown in FIGURE 2-6 "COP/JTAG Port Connector" onpage 24. There are two of these connectors on the Scout PCB, one for the MPC750 and one for the PQII.TABLE 2-18. "PQII’s COP/JTAG Port Connector’s Signal Description" on page 25 describes the PQII’sconnector, while TABLE 2-19. "MCP750’s COP/JTAG Port Connector’s Signal Description" on page 26 de-scribes the MPC750’s connector.

FIGURE 2-6 COP/JTAG Port Connector

Host

EthernetPort

Scout

COPEthernet<->COP

Ethernet Network

16 Wire

Flat Cable

1

3

5

7

9

2

4

6

8

10

TDO

TRST

V3.3

TDI

HRESET

TMS

11 12

13 14

15 16

N.C.

CKSTP_OUT

TCK N.C.

N.C.

SRESET GND

“KEY”

GND

QREQ

24 Release 1.1



TABLE 2-18. PQII’s COP/JTAG Port Connector’s Signal Description

Pin #Signal

MnemonicATT.a

a. Signal attributes are with reference to Scout.

Description

1 TDO O,X Test Data Out. Standard JTAG signal. This is the scan path output,driven by the falling edge of TCK signal and sampled on the risingedge of TCK.

2, 8, 10 N.C. - No Connect.

3 TDI I,X Test Data In. Standard JTAG signal. This is the input data for thescan path. Driven by the JTAG controller on the falling edge of TCK,sampled on the rising edge of TCK by the JTAG slave.

4 TRST I,L Test Reset. Standard JTAG signal. When this signal is active (low),the JTAG logic is reset and inactive, allowing normal operation of thePQII.

5 QREQ O, L Quiescent Request. This signal is active whenever the 603e core isabout to enter low power mode.

6 V3.3 O,H This is the PQII’s I/O power supply, which indicates to the debugstation the voltage at which the target processor is powered.

7 TCK I,X Test Clock. Standard JTAG Signal. This is the clock for the JTAGmachine. JTAG signals are driven according to its falling edge andsampled over its rising edge.

9 TMS I,X Test Mode Select. Standard JTAG signal. This signal along withTCK, controls the TAP controller state machine, allowing movementbetween it’s different states. When high, causes a change in theTAP controller state, on the rising edge of TMS. When low, the TAPcontroller state machine remains in its current state.

11 SRESET I/O,L, O.D

Soft-Reset. Required to enable the debug station to either generateSoft Reset sequence, or observe the PQII taking Soft resetsequence. For signal description, see the PQII Spec.

12, 16 GND - Scout Ground Plane.

13 HRESET I/O,L, O.D

Hard-Reset. Required to enable the debug station to either generateHard Reset sequence, or observe the PQII taking Soft resetsequence. For signal description, see the PQII Spec.

14 “KEY” - This is a mechanical signal. On Scout this pin is cut, while on thereceptacle connector, connecting to the header on the m/b, it isfilled. This, to prevent miss-insertion of the connector.

15 CKSTP_OUT O,L Check-Stop Output. This active low signal, indicates that the PQIIhas taken the check-stop exception. For further detail see the PQIIspec. This signal is multiplexed with other functions on the PQII, so,there are possible SIU configurations where it is not available.On Scout, this signal will be configured as XBR3* (eXternal BusRequest 3), this since the signals XBR2* / XBG2* / XDDBG2* arerequired for the L2CACHE (BR* / BG* / DBG*) are reserved forexternal master.

Release 1.1 25



TABLE 2-19. MCP750’s COP/JTAG Port Connector’s Signal Description

Pin #Signal

MnemonicATT.a

a. Signal attributes are with reference to Scout.

Description

1 TDO O,X Test Data Out. Standard JTAG signal. This is the scan path output,driven by the falling edge of TCK signal and sampled on the risingedge of TCK.

2, 8, 10 N.C. - No Connect.

3 TDI I,X Test Data In. Standard JTAG signal. This is the input data for thescan path. Driven by the JTAG controller on the falling edge of TCK,sampled on the rising edge of TCK by the JTAG slave.

4 TRST I,L Test Reset. Standard JTAG signal. When this signal is active (low),the JTAG logic is reset and inactive, allowing normal operation of thePQII.

5 QREQ O, L Quiescent Request. This signal is active whenever the core is aboutto enter low power mode.

6 V3.3 O,H This is the MPC750’s I/O power supply, which indicates to the debugstation the voltage at which the target processor is powered.

7 TCK I,X Test Clock. Standard JTAG Signal. This is the clock for the JTAGmachine. JTAG signals are driven according to its falling edge andsampled over its rising edge.

9 TMS I,X Test Mode Select. Standard JTAG signal. This signal along withTCK, controls the TAP controller state machine, allowing movementbetween it’s different states. When high, causes a change in theTAP controller state, on the rising edge of TMS. When low, the TAPcontroller state machine remains in its current state.

11 SRESET I/O,L, O.D

Soft-Reset. Required to enable the debug station to either generateSoft Reset sequence, or observe the MPC750 taking Soft resetsequence.

12, 16 GND - Scout Ground Plane.

13 HRESET I/O,L, O.D

Hard-Reset. Required to enable the debug station to either generateHard Reset sequence, or observe the MPC750 taking Hard resetsequence.

14 “KEY” - This is a mechanical signal. On Scout this pin is cut, while on thereceptacle connector, connecting to the header on the m/b, it isfilled. This, to prevent miss-insertion of the connector.

15 CKSTP_OUT O,L Check-Stop Output. This active low signal, indicates that theMPC750 has taken the check-stop exception. For further detail seethe MPC750 User’s Manual.

26 Release 1.1



2•14 Switches, Jumpers and IndicatorsThe Power-on Reset switch on the Scout PCB is actually implemented as a 2 pin header. The Soft Resetand Abort switches on the Scout PCB are implemented with push-button switches in parallel with 2 pinheaders. This allows the actual switches to be implemented in various ways. One can mount a switch onan enclosure or panel and connect the switch to the header with a simple cable. Alternatively, one can justuse jumpers to generate the switch action. The ENG revision of the Scout PCB implements the switcheswith slide switches which fit the footprint of the headers.

The switches and jumpers on Scout include the following:

1) Power-On - Reset; 2 pin jumper/switch. This should be a SPST or momentary switch.

2) Soft - Reset; 2 pin header in parallel with a normally open momentary push-button switch.

3) Abort; 2 pin header in parallel with a normally open momentary push-button switch.

The following LEDs are provided on Scout:

1) 5V/3.3V Power - On (G)

2) Reset (R)

3) Run (based on DBB* signal activity) (G)

4) Fast Ethernet Port:

• Speed (G)

• Collision (R)

• Link Integrity (R)

• Receive (G)

• Transmit (G)

5) Signal Lamp. (R)

6) General Purpose Bit. (not on ENG revision of Scout) (G)

2•15 Resistor OptionsResistor options are provided for functions which are configurable, but are not expected to change fre-quently, or for functions for which easy changes would lead to the inevitable debug problems associatedwith jumpers.

1) MPC750’s PLLCFG(0:3) signals, which control the bus-to-core clock ratio.

2) PQII’s MODCK(0:2) signals, which control the bus-to-core and bus-to-cpm clock ratio.

3) SDRAM DIMM I2C address.

4) Scout board revision, read via the BCSR.

5) HRESET* signal; when R77 is installed, the MPC750’s and the PQII’s HRESET* signal are con-nected together. When R77 is removed, each processor has independent HRESET* signals. This is used to provide a means for independent JTAG control of the HRESET* signal. This re-sistor is installed by default.

6) SRESET* signal; when R78 is installed, the MPC750’s and the PQII’s SRESET* signal are con-nected together. When R78 is removed, each processor has independent SRESET* signals. This is used to provide a means for independent JTAG control of the SRESET* signal. This re-sistor is removed by default.

Release 1.1 27


Memory Map

3 - Memory MapAll accesses to Scout’s memory slaves are controlled by the PQII’s memory controller. Therefore, thememory map is reprogrammable to the desire of the user. After Hard Reset, software should check for theexistence, size, delay and type of the SDRAM DIMM and FLASH memory SIMM mounted on board andinitialize the memory controller accordingly. TABLE 3-1. "Scout Memory Map" on page 28 is arecommended memory map. Since it is a “soft” map, a device’s address may be moved about the map, tothe convenience of any user.

TABLE 3-1. Scout Memory Map

ADDESS RANGE

Memory Type CommentsPort Size

00000000 -00FFFFFF

SDRAMDIMM

16 MByte DIMM 64 MByte DIMM 128 MByte DIMM 64

01000000 -03FFFFFF

64

04000000 -07FFFFFF

64

08000000 -0FFFFFFF

Empty Space -

10000000 -103FFFFF

SDRAM(Local Busa)

a. The Local bus is fully transparent to the 60X bus, i.e., no mapping register. If a CS is assigned to the Localbus, its address space is completely visible to the 60X bus.

MB811171622A (4 MByte) 32

10400000 -104FFFFF

Empty Space -

10500000 -10507FFF

BCSR(0:3)b

b. The device appears repeatedly in multiples of its port-size (in bytes) X depth. E.g., BCSR0 appears at mem-ory locations 0x10500000, 0x10500020, 0x10500040..., while BCSR1 appears at 0x10500008,0x10500028, 0x10500048... and so on.

BCSR0 = 0x10500000BCSR1 = 0x10500008BCSR2 = 0x10500010BCSR3 = 0x10500018

32

10508000 -106FFFFF

Empty Space -

10700000 -1070FFFF

PQII InternalMAPc

c. Refer to the PQII spec for a complete description of the PQII’s internal memory map.

32

10710000 -FDFFFFFF

Empty Space -

FE000000 -FFFFFFFF

FLASHSIMMs

Range starts from top of memory, and moves backwards dependent onsize of modules installed. For example, for two 8Mbyte modules:16Mbytes = 0xFF000000 - 0xFFFFFFFF

64

28 Release 1.1


Physical

4 - Physical

4•1 PowerThere are 5 main power buses on Scout:

1) 5V bus

2) 3.3V bus

3) Core Voltage for the MPC750

4) Core Voltage for the PQII

5) 12V bus

The MPC750 and the PQII both require separate Core, PLL, and I/O voltages. The PLL voltage is connect-ed to the Core voltage with an RC filter, while both processors I/O voltages are connected to the boards+3.3V bus.

FIGURE 4-1 Scout Power Scheme

To support off-board application development, the +5V, +3.3V, and +12V power buses are connected tothe expansion connectors, so that external logic may be powered directly from the board. The maximumcurrent allowed to be drawn from the board on each bus is yet TBD.

To protect on-board devices against supply spikes, decoupling capacitors are provided between the

3.3V

2-2.5V

5V

Scout Logic & Peripherals

Exp

an

sio

n C

on

necto

r

PQII Core

12V

2.5-2.7VPQII

VDD

MPC750

MPC750 Core

PLLVDDCore

VDDI/O

VDDPLL

VDDCore

VDDI/O

Release 1.1 29


Physical

devices’ power leads and GND, located as close as possible to the power leads.

4•1•1 5V Bus

Some of the Scout peripherals will reside on the 5V bus, including the FLASH SIMM modules. Since theMPC750 and the PQII are not 5V tolerant, buffering is provided between 5V peripherals and the proces-sors.

To protect against over-voltage being applied to the 5V power input, a zener diode is connected betweenthe 5V bus and GND.

4•1•2 3.3V Bus

The MPC750 and PQII I/O voltage pins as well as the L2 cache, SDRAMs, and the address and databuffers are powered by the 3.3V bus. The +3.3V bus is produced from the 5V bus using a low-voltage drop,linear voltage regulator made by Linear Technology, the LT1585CT which is capable of driving up to 4.7A.Since much of the logic on Scout is powered from the +3.3V bus, only a small amount of current is availableto external boards. The actual amount will depend on several factors including the SDRAM DIMM size, L2bus frequency, and the 60x bus frequency. It is recommended external boards generate their own +3.3Vbus from the +5V bus.

4•1•3 Core Voltage for the PQII

The PQII’s internal logic and PLL is powered with an adjustable, linear power regulator, the output of whichmay be in a range of 2.0V - 2.5V. The output voltage is adjusted by changing a resistor on the PCB. Thedefault resistor will set the voltage to 2.5V. The regulator provided on the Scout design assumes the coremay be running at a high frequency. For designs which will run the PQII strictly in the core disabled mode,a much smaller regulator may be used.

Provisions will be taken to support cooling of the PQII when the core is enabled and it is working in thehigher allowed voltage range.

4•1•4 Core Voltage for the MPC750

The MPC750’s internal logic and PLL is powered with an adjustable, linear power regulator, the output ofwhich may be in a range of 2.5V - 2.7V. The output voltage is adjusted by changing a resistor on the PCB.The default resistor will set the voltage to 2.6V.

Provisions will be taken to support cooling of the MPC750. Depending on the operating frequency and theairflow, the MPC750 will require either a heatsink or a fan/heatsink combination. A 3 pin header is providedfor connection to a +5V fan/heatsink for environments which do not provide sufficient air flow.

4•1•5 12V Bus

The sole purpose of the 12V bus is to supply VPP (programming voltage) for the Flash SIMMA. It is pro-tected from over voltage in the same manner as the 5V bus.

If either the FLASH SIMM is 5V programmable or it is 12V programmable but need not be programmed the12V supply input connector of Scout may be left unconnected.

A. If necessary.

30 Release 1.1


Physical

4•2 ConnectorsScout will have connectors attached to serve the following functions:

1) 5V power input

2) 12V power input

3) MPC750 COP/JTAG Port

4) PQII COP/JTAG Port

5) 100/10-Base-T port

6) One RS232 port

7) CPM Expansion

8) Logic Analyzer connection

4•2•1 5V Power Connector

The 5V power connector is a 3-lead, two-part terminal block. The male part is soldered to the PCB, whilethe receptacle is connected to the power supply.

4•2•2 12V Power Connector

The 12V power connector is a two-lead, 2 part, terminal block connector, identical in type to the 5V con-nector.

4•2•3 Fast Ethernet Port Connector

The Ethernet connector on Scout is a Twisted-Pair (100/10-Base-T) connector and is implemented with a900 RJ45-8 connector.

4•2•4 RS232 PortS Connector

The RS232 port connector is a 9 pin, 900, female D-Type connector.

4•2•5 MPC750 COP/JTAG Port Connector

This debug port connector is a generic 16 pin (2 X 8), Male, header connector.

4•2•6 PQII COP/JTAG Port Connector

This debug port connector is a generic 16 pin (2 X 8), Male, header connector.

4•2•7 CPM Expansion Connectors

The CPM expansion connectors carry all CPM pins, i.e., Port A to Port D signals of the PQII, and a portionof the 60X signals(buffered). These two connectors are DIN 41612, 128 pin 90O, PCB connectors residingon the edge of the board, allowing convenient connection to off-board tools.

4•2•8 Logic Analyzer Connectors

To support fast connection to Hewlett Packard’s and Tektronix’s series of logic-analyzers, a set of dedicat-ed connectors are provided on board. Use is done with 38 pin, receptacle MICTOR connectors made byAMP, part # 2-767004-2.

Release 1.1 31


Physical

4•3 PCB LayoutThe Scout PCB will follow layout guidelines suitable for high-frequency operation. Following is a list ofsome of the measures which will be taken to meet this design goal:

1) Traces will be as short as possible.

2) Clock signals will be routed as equal lengths traces, except for adjustments made for capacitive load differences between nets.

3) Clocks and critical control signals will have series termination resistors as required.

4) Clocks and control signals will be routed as a chain.

5) All signals will be routed to minimize crosstalk.

6) Multilayer PCB, with ground and supply layers.

The board‘s size will be 234mm X 160mm (Double-height VMEbus card also known as Dual Euro-card).

32 Release 1.1


APPENDIX A - CPLD Source File

This appendix contains the VHDL source code used to program the Altera MAX7000 device on the Scoutboard.

-- Bruce Parker

-- 07/06/98

-- Scout PROJECT (Voyager + 750 board)

--

-- PRELIMINARY Revision; subject to change without notice

--

-- device is MAX7128 in 100pin TQFP pkg

--

-- revision history

-- 3/13/99 fixed bit reversal on flash presence detect bits in bcsr2; fl_pd(1:7)

--******************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity scout is port(

busclk: in std_logic; -- 60x bus clock

abr1, rst1: in std_logic; -- switch inputs

fl_a27, fl_a28: in std_logic; -- low order flash address lines

bcsr_cs, flash_cs1, flash_cs2, tool_cs1, tool_cs2: in std_logic; -- chip selects

bctl0: in std_logic; -- read if low, write if high

bctl1: in std_logic; -- output enable if low

-- data bus divided into bits with fflops and those read-only buffers

ro_data_bus: inout std_logic_vector(16 to 25); -- tristate controlled buffers

ff_data_bus: inout std_logic_vector(26 to 31); -- bits with flip flops

-- bcsr2 inputs

swopt: in std_logic_vector(0 to 2);

brev: in std_logic_vector(0 to 3);

fl_pd: in std_logic_vector(7 downto 1);

Release 1.1 A-1


-- outputs

poreset: inout std_logic; -- power-on reset; must be open_drain

hreset_pqii, sreset_pqii: inout std_logic; -- must be open-drain

hreset_750, sreset_750: inout std_logic; -- must be open-drain

atmrst, atmen: out std_logic;

fethrst, fethien: out std_logic;

rs232en: out std_logic;

sgllamp, reset_led, gp_bit: out std_logic;

dbufen, tdbufen: out std_logic;

bcsr2_cs: buffer std_logic;

ripctr0, por_dbnce: buffer std_logic;

nmi: inout std_logic); -- must be open-drain

end scout;

architecture arch_scout of scout is

signal bcsr0: std_logic_vector(30 to 31);



signal internal_bus: std_logic_vector(26 to 31);

signal por_ctr: std_logic_vector(0 to 13);

signal rst_depressed, rst_inactive : std_logic;

signal abrt_depressed, abrt_released, abrt_inactive : std_logic;

signal ripctr1, ripctr2, ripctr3, ripctr4, ripctr5, ripctr6, ripctr7: std_logic;

signal ripctr8, ripctr9, ripctr10, ripctr11: std_logic;

signal abr1q1, abr1q2, rst1q1, rst1q2: std_logic;

signal hreset_reg, sreset_reg, nmi_reg: std_logic;

begin

-- this process implements the reads and writes to the bcsr registers

p1 : process(por_dbnce, bcsr_cs, bctl0, fl_a27, fl_a28, nmi, bcsr0, bcsr1, bcsr2)

begin

if (por_dbnce = ’0’) then

bcsr0 <= "11";

bcsr1 <= "111111";

A-2 Release 1.1


elsif (por_dbnce = ’1’) then

if (bctl0 = ’1’) then

-- write cycle

if (bcsr_cs’event and bcsr_cs = ’1’) then

-- bcsr0 register write

if (fl_a27 = ’0’ and fl_a28 = ’0’) then

bcsr0(30 to 31) <= ff_data_bus(30 to 31);


elsif (fl_a27 = ’0’ and fl_a28 = ’1’) then

bcsr1(26 to 31) <= ff_data_bus(26 to 31);

-- note, bcsr2 is read-only register

end if;

end if;

elsif (bctl0 = ’0’) then -- read cycle

-- register read

if (fl_a27 = ’0’ and fl_a28 = ’0’) then

internal_bus(31) <= bcsr0(31);

internal_bus(27 to 30) <= "0000";

internal_bus(26) <= nmi;


internal_bus(26 to 30) <= bcsr1(26 to 30);

internal_bus(31) <= ’0’;


internal_bus(26 to 31) <= bcsr2(26 to 31);

end if;

end if;

end if;

end process;

-- this process implements the abort sticky bit

abort_sticky : process(por_dbnce, hreset_750, sreset_750, rst_inactive, abrt_released,

bcsr_cs, bctl0, fl_a27, fl_a28)

begin

if (por_dbnce = ’0’ OR hreset_750 = ’0’ OR sreset_750 = ’0’) then

nmi_reg <= ’1’;

elsif ((rst_inactive = ’1’ AND abrt_released = ’1’)) then

Release 1.1 A-3


nmi_reg <= ’0’;

elsif (bcsr_cs’event and bcsr_cs = ’1’) then


if (bctl0 = ’1’ and fl_a27 = ’0’ and fl_a28 = ’0’) then

nmi_reg <= ff_data_bus(26);

end if;

end if;

end process;

-- these statements allow data bus pins be bidirectional; to drive on writes or tri-state

ff_data_bus <= internal_bus when (bctl0 = ’0’ AND bctl1 = ’0’ AND bcsr_cs = ’0’ AND

(fl_a27 = ’0’ or (fl_a27 = ’1’ AND fl_a28 = ’0’)))

else "ZZZZZZ";

ro_data_bus <= bcsr2(16 to 25) when (bctl0 = ’0’ AND bctl1 = ’0’ AND bcsr_cs = ’0’ AND

(fl_a27 = ’1’ AND fl_a28 = ’0’) )

else "ZZZZZZZZZZ";

-- bcsr0 register bits

sgllamp <= bcsr0(31);

gp_bit <= bcsr0(30);


atmen <= bcsr1(26);

atmrst <= bcsr1(27);

fethien <= bcsr1(28);

fethrst <= bcsr1(29);

rs232en <= bcsr1(30);


bcsr2(16) <= swopt(0);


bcsr2(18) <= ’0’;

bcsr2(19) <= ’0’;

bcsr2(20 to 23) <= brev(0 to 3);


A-4 Release 1.1


--bcsr2(25 to 31) <= fl_pd(1 to 7);

bcsr2(25 to 31) <= fl_pd(7 downto 1);

-------------------------------------------------------------------------

-- driven, concurrent outputs

bcsr2_cs <= ’0’ when (bcsr_cs = ’0’ AND fl_a27 = ’1’ AND fl_a28 = ’0’) else ’1’;

dbufen <= ’0’ when (bcsr_cs = ’0’ OR flash_cs1 = ’0’ OR flash_cs2 = ’0’

OR tool_cs1 = ’0’ OR tool_cs2 = ’0’) else ’1’;

tdbufen <= ’0’ when (tool_cs1 = ’0’ OR tool_cs2 = ’0’) else ’1’;

reset_led <= ’0’ when (hreset_pqii = ’0’ OR sreset_pqii = ’0’ OR por_dbnce = ’0’) else ’1’;

-- ripple counter to divide bus clock; creates slow clock for debounce

-- (output of prior stage feeds clock of next fflop stage)

STAGE0: process (busclk)

begin

if(busclk’event and busclk = ’1’) then

ripctr11 <= not ripctr11;

end if;

end process STAGE0;

process (ripctr11)

begin

if(ripctr11’event and ripctr11 = ’1’) then


end if;

end process;

process (ripctr10)

begin



end if;

end process;

Release 1.1 A-5


process (ripctr9)

begin



end if;

end process;

process (ripctr8)

begin



end if;

end process;

process (ripctr7)

begin



end if;

end process;

process (ripctr6)

begin



end if;

end process;

process (ripctr5)

begin



end if;

end process;

A-6 Release 1.1


process (ripctr4)

begin

if (ripctr4’event and ripctr4 = ’1’) then


end if;

end process;

process (ripctr3)

begin



end if;

end process;

process (ripctr2)

begin



end if;

end process;

process (ripctr1)

begin



end if;

end process;

-- debounce slow rising poreset input signal with slow ripple counter clock

process (ripctr0)

begin


por_dbnce <= poreset;

end if;

end process;

Release 1.1 A-7


process (por_dbnce, ripctr0, abr1, rst1)

begin


abr1q1 <= ’1’;

abr1q2 <= ’1’;

rst1q1 <= ’1’;

rst1q2 <= ’1’;

elsif (ripctr0’event and ripctr0 = ’1’) then

abr1q1 <= abr1;

abr1q2 <= abr1q1;

rst1q1 <= rst1;

rst1q2 <= rst1q1;

end if;

end process;

-- switch debouncing ; uses last stage of ripple counter as slow clock for debounce

-- now, just use one input; valid after two slow clocks

rst_depressed <= ’1’ when (rst1q1 = ’0’ and rst1q2 = ’0’)

else ’0’;

rst_inactive <= ’1’ when (rst1q1 = ’1’ and rst1q2 = ’1’)

else ’0’;

abrt_depressed <= ’1’ when (abr1q1 = ’0’ and abr1q2 = ’0’) -- set on depress of switch

else ’0’;

abrt_released <= ’1’ when (abr1q1 = ’1’ and abr1q2 = ’0’) -- set on release of switch

else ’0’;

abrt_inactive <= ’1’ when (abr1q1 = ’1’ and abr1q2 = ’1’)

else ’0’;

-- to eliminate combinatorial race conditions when both buttons depressed, use clocked

-- versions of signal to be output

-- (any output of ripple clock could be used to guarantee a certain asserted time.)

process (por_dbnce, busclk)

begin


hreset_reg <= ’0’;

A-8 Release 1.1


sreset_reg <= ’0’;

elsif (busclk’event and busclk = ’1’) then

if (rst_depressed = ’1’ AND abrt_depressed = ’1’) then -- assert when both depressed


elsif (rst_inactive = ’1’ AND abrt_inactive = ’1’) then -- negate when both released


end if;

if (rst_depressed = ’1’ AND abrt_inactive = ’1’) then


else


end if;

end if;

end process;

-- assumes counter bits power up to all 0’s

-- count up to provide poreset time

process (ripctr0)

begin


if (por_ctr /= "11111111111111") then

por_ctr <= por_ctr + 1;

end if;

end if;

end process;

-------------------------------------------------------------------------

-- open drain outputs

hreset_pqii <= ’0’ when (hreset_reg = ’0’) else ’Z’; -- both buttons depressed

hreset_750 <= ’0’ when (hreset_reg = ’0’) else ’Z’; -- both buttons depressed

sreset_pqii <= ’0’ when (sreset_reg = ’0’) else ’Z’; -- rst button depressed

Release 1.1 A-9


sreset_750 <= ’0’ when (sreset_reg = ’0’) else ’Z’; -- rst button depressed

nmi <= ’0’ when (nmi_reg = ’0’) else ’Z’; -- abort button depressed and released

poreset <= ’0’ when (por_ctr /= "11111111111111" ) else ’Z’; -- drive poreset

end arch_scout;

A-10 Release 1.1

Scout PCB Engineering Specification (PowerQUICC II +...

Documents

Transcript of Scout PCB Engineering Specification (PowerQUICC II +...