SCHEM,MLB,J13 - Kythuatphancungkythuatphancung.vn/.../f20ad_Apple_Macbook_Air_A1466.pdf · 2014. 1....

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DRAWING

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PROPRIETARY PROPERTY OF APPLE INC.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

DESCRIPTION OF REVISIONCKAPPD

2 1

1245678

B

D

6 5 4 3

C

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

THE INFORMATION CONTAINED HEREIN IS THE

C

A

D

DATE

R

SHEET

Apple Inc.

THE POSESSOR AGREES TO THE FOLLOWING:

DRAWING TITLE

DSIZE

REVISION

DRAWING NUMBER

BRANCH

REV ECN

7

B

3

II NOT TO REPRODUCE OR COPY IT I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

IV ALL RIGHTS RESERVEDIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

8

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

Schematic / PCB #’s

SCHEM,MLB,J132/23/12

1 OF 73

2012-02-23

1 OF 109

2.8.0

051-9277

Voltage & Load Side Current Sensing12/02/201153

45 J11_MLB

SMBus Connections10/04/201152

44 J11_MLB

LPC+SPI Debug Connector09/08/201151

43 J11_MLB

SMC Support11/10/201150

42 J13_MLB_NON_POR

SMC10/17/201149

41 J13_MLB_NON_POR

Left I/O (LIO) Connector11/10/201147

40 J13_MLB_NON_POR

External A USB3 Connector09/30/20114639 J11_MLB

SSD CONNECTOR10/17/20114538 J13_MLB_NON_POR

X21 WIRELESS CONNECTOR10/11/20114037 J11_MLB

TBT Power Support11/10/20113836 J13_MLB_NON_POR

Thunderbolt Host (2 of 2)10/04/20113735 J11_MLB

Thunderbolt Host (1 of 2)09/30/20113634 J11_MLB

SecureDigital Card Reader11/10/20113533 J13_MLB_NON_POR

DDR3 Bypassing/Termination07/28/20113432 K21_MLB

FSB/DDR3/FRAMEBUF Vref Margining08/04/20113331 J11_MLB

DDR3 DRAM CHANNEL B (32-63)07/28/20113230 K21_MLB

DDR3 DRAM CHANNEL B (0-31)07/28/20113129 K21_MLB

DDR3 DRAM CHANNEL A (32-63)07/28/201130

28 K21_MLB

DDR3 DRAM CHANNEL A (0-31)07/28/201129

27 K21_MLB

CPU Memory S3 Support11/10/201128

26 J13_MLB_NON_POR

Clock (CK505) and Chipset Support07/29/201127

25 K21_MLB

USB HUB & MUX11/10/201126

24 J13_MLB_NON_POR

CPU & PCH XDP10/17/201125

23 J13_MLB_NON_POR

PCH DECOUPLING10/03/201124

22 J11_MLB

PCH GROUNDS07/27/201123

21 J30_MLB

PCH POWER09/30/201122

20 J11_MLB

PCH GPIO/MISC/NCTF09/16/201121

19 J11_MLB

PCH PCI/USB/TP/RSVD11/10/201120

18 J13_MLB_NON_POR

PCH DMI/FDI/PM/Graphics07/27/20111917 J30_MLB

PCH SATA/PCIe/CLK/LPC/SPI07/27/20111816 J30_MLB

CPU DECOUPLING-II07/29/20111715 K21_MLB

CPU DECOUPLING-I10/03/20111614 J11_MLB

CPU GROUNDS07/27/20111413 J30_MLB

CPU POWER11/10/20111312 J13_MLB_NON_POR

CPU DDR3 INTERFACES07/27/20111211 J30_MLB

CPU CLOCK/MISC/JTAG07/27/20111110 J30_MLB

CPU DMI/PEG/FDI/RSVD10/17/2011109 J13_MLB_NON_POR

Signal Aliases11/10/201198 J13_MLB_NON_POR

Power Aliases07/29/201187 K21_MLB

Functional Test / No Test07/29/20117

6 K21_MLB

BOM Configuration07/27/20115

5 J30_MLB

Revision History07/27/20114

4 J30_MLB

Revision History11/10/20113

3 J13_MLB_NON_POR

System Block Diagram11/10/20112

2 J13_MLB_NON_POR

PCB Rule Definitions01/11/2012

J13_CONSTRAINTS

109

73Project Specific Constraints

01/11/2012

J13_CONSTRAINTS

108

72SMC Constraints

01/11/2012

J13_CONSTRAINTS

106

71Thunderbolt Constraints

01/11/2012

J13_CONSTRAINTS

105

70PCH Constraints 2

01/11/2012

J13_CONSTRAINTS

103

69PCH Constraints 1

01/11/2012

J13_CONSTRAINTS

102

68Memory Constraints

01/11/2012

J13_CONSTRAINTS

101

67CPU Constraints

01/11/2012

J13_CONSTRAINTS

100

66LCD Backlight Driver

07/28/2011

K21_MLB

97

65Thunderbolt Connector A

10/03/2011

J11_MLB

94

64Internal DisplayPort Connector

07/28/2011

K21_MLB

90

63Power Control 1/ENABLE

11/10/2011

J13_MLB_NON_POR

7962Power FETs

07/28/2011

K21_MLB

7861Misc Power Supplies

07/28/2011

K21_MLB

7760CPU VCCIO (1.05V) Power Supply

10/17/2011

J13_MLB_NON_POR

7659CPU IMVP7 & AXG VCore Output

10/17/2011

J13_MLB_NON_POR

7558CPU IMVP7 & AXG VCore Regulator

10/14/2011

J11_MLB

74571.5V DDR3 Supply

12/02/2011

J11_MLB

73565V / 3.3V Power Supply

10/17/2011

J13_MLB_NON_POR

7255System Agent Supply

10/17/2011

J13_MLB_NON_POR

7154PBus Supply & Battery Charger

11/10/2011

J13_MLB_NON_POR

7053DC-In & Battery Connectors

11/10/2011

J13_MLB_NON_POR

6952AUDI0: SPEAKER AMP

09/30/2011

J11_MLB

62

51SPI ROM

07/28/2011

K21_MLB

61

50IPD / KBD Backlight

11/10/2011

J13_MLB_NON_POR

57

49Fan

07/28/2011

K21_MLB

56

48Thermal Sensors

08/03/2011

J11_MLB

55

47

TITLE=MLB

ABBREV=DRAWING

LAST_MODIFIED=Thu Feb 23 17:52:06 2012

CRITICAL1 PCBPCBF,MLB,J13820-3209

PageDate(.csa)

Contents Sync Page(.csa) Date

SyncContents

1 SCH051-9277 SCHEM,MLB,J13 CRITICAL

SCHEM,MLB,J13

Table of Contents07/27/20111

1 J30_MLB High Side Current Sensing10/17/2011

J13_MLB_NON_POR

54

46

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THEPROPRIETARY PROPERTY OF APPLE INC.

124578

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IV ALL RIGHTS RESERVED

R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT

PCI-E

TMDS OUT

64-bitMEMORY DDR3-1600MHZ

DUAL ChannelA

x8PG 27,28

MEMORY

B

PA_AUX

PA_DPSRC_1

x4

x4

DPC

DP0, x1 EDP

PG 9

PCI-EPG 9

PCIE1

RTC

PG 16

Xtal25MHz

EEPROM

PA_LSTX/LSRX

SPI

PA_CIO0

PA_CIO1

PA_DPSRC_3

PCIe x4

U3690

U3600

PG 34

PG 34,35 37

PG 25

TBT Host

PG 11

CONNLEFT SPEAKER

U6201

LID

I2CLEFT L/O CONN

USB PORT BJ4610

CAMERA +ALS CONN

I2C

USB CAMERA LEFT USB EXTB

PG 7

HALLJ4750

Re-DRIVER

U4700

PG 40

USB3

PG 24

U2660

EXTERNAL

(LEFT PORT)THERMAL

EFFECT

SPK

U6210

SPEAKERAMPPG 51

J6903

PG 52

CONNRIGHT SPEAKER

PG 7

MICLINE IN JACKHEADPHONE/

PG 9

Filter

J4600

SD CARD

SERIAL PORT

Boot ROMSPI

BUFFER

1

USB 3

6

47

01

43

89

23

4

Conn

CLOCK

U2700

DPMLOMUX

AUXIODISPLAY PORT

PG 64

U9420

DP OUTDPB

/ TBT

PG 64

J9400

HDMI OUT

LVDS OUT

UP TO 8 LANES

61

83

5

SPI

PG 38HDD

SATAJ4501

EDPCONN

J9000

57

Audio Codec

PG

J6700

2

J6701

SPEAKERAMPPG 10

U6620

PG 11

HDA

J4720

CONN

J6702

J4001

SNK1

SNK0

J4700

PG 11

U4650

CONN

U5700

USBPM_SLP S3/S4

U4900

43

U3500

CONTROLLER

I2C

PG 7

PG

FILTER

LIO BOARD

CONNLPC+SPI

J5100

U4730

1

MOJO SMC

DEBUG MUX

J3500

U5510

U5410

J5700

USB MUX

USB A

ADC FAN0SMB_3SMB_5 SMB_1

PG 54-60

POWER CIRCUIT

PG 52,53

SMC

PG 41

2

SD CARD

USB

(UP TO 10 DEVICES)

U6100

U2600

USB HUB

PG 6

X21

CONNPG 37

WIRELESS

PG 63

PWR

PG 17

PG 18

PG 18

SMBUS PCI HDA

Misc

PG 18

2

LINE IN

CTRL

PG 17

PG 16

PG 16

PG 16

PG 16

GPIOs

25MHz

SATA0

SATA

UP TO 6

PG 16 PG 16

JTAG

DVI OUT

RGB OUT

PG 16

J2550

PG 23XDP CONN

PCH

HEADPHONE

SYSTEM

SENSOR

PG 24

PG 35

PG 35

PG 39

PG 39

PG 40

PG 43

PG 49

SMB_2

LID

KBDLED

PG 48

FAN CONNJ5600

PG 45,46

PG 49

KBD CONNJ5715

PG 49

U5750

J4001

Bluetooth

PG 37

(ON AP)

PG 50

CPU TEMP SENSOR

PG 46,47

PG 38

U4510

MUX

LPC

1017P

U1800

PANTHER POINT - MPCH

PG 19

J6950,U7000

PG 47

TBT/MLBBOT/INLET TEMP SENSOR

VOLTAGE/CURRENT SENSOR

PG 16

PG 19

PG 23

PG 49

TRACKPAD

U1000

PG 17

DMI

CLK

32KHz

PCIE0

IVY BRIDGE 2C-35W

AXG=GT2, ULV, 1023P

INTEL CPU

PG 17

FDIPG 11

DMIPG 9PG 9

EDP

INTEL

PG 10

JTAG

FDI

MUXXHCI/EHCI2

KBD DRIVER

CHARGER

J2500

CPUXDP CONN

U3100-U3130U3200-U3230

MEMORYx8

PG 29,30

U3000-U3030U2900-U2930

SYNC_MASTER=J13_MLB_NON_POR SYNC_DATE=11/10/2011

System Block Diagram

051-9277

2.8.0

2 OF 109

2 OF 73

Apple Inc.


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3.3V

(R/H)

TPS51980

AAC

ADAPTER

AR7050

PPVBAT_G3H_CHRG_RET

1

D7005

SMC_GFX_VSENSE

PPDCIN_G3H_OR_PBUS

PP5V5_CHAR_VDDP

1SMC_DCIN_ISENSE

R7020

J6900

26

TBT_PWR_EN

PM_SLP_S3_L

RSMRST_OUT(P15)

1V05_S0_LDO_EN

U1800

PM_PCH_PWRGD

(PAGE 16~21)

(PAGE 41)

BATTERY CHARGER

CHGR_BGATE

F6901

U7000

ISL6259HRTZ

EN/UVLO

1

(PAGE 53)

LT3470A

VOUT

F7040

PPBUS_G3H

CPUIMVP_AXG_PGOOD

25-1

PPVCORE_S0_AXG_REG

(PAGE 36)

TPS22920

AVOUT

R0954

VR_ON

(PAGE 57)PGOOD

PGOODG

VLDOIN

PPVTT_S0_DDR_LDOVOUT2

SMC_SYS_KBDLED

PP3V3_S0_SSD_R

PPVOUT_SW_LCDBKLT

16

PP1V05_S0_VMON

PP1V5_S3RS0_VMON

PP5V_S0_VMON

PP5V_S0_FET

PGOOD

LCD_BKLT_EN

SMC_BATT_ISENSE

PP5V5_CHRG_VDDP

VIN

SMC_RESET_L

U7090

(PAGE 53)

PBUS SUPPLY/

VENABLE

2 ENABLE

PP3V42_G3H_REG

(PAGE 52)

LT3470A3.425V G3HOT

U6990

D6905

SMC_GFX_ISENSE

R7510

CPUVCCIOS0_PGOOD

CPUIMVP_PGOOD

PPDDR_S3_REG

Q7801SMC

J6950

2S3P

(6 TO 8.4V)

U4900

Q7840

PP5V_SUS_FET

P3V3S3_EN

P5V_3V3_SUS_EN

TPS720105

(PAGE 60)

V

P3V3S5_EN

A

PPVBATT_G3H_CONN

Q7055PPVBAT_G3H_CHGR_R

IN

DCIN(14.5V)

4

6A FUSE

Q5310

VOUT

ISL95870AH

0.75V

U7300

(PAGE 56)

TPS51916

24

1.5V

U7100

(PAGE 54)

PVCCSA_PGOOD

VCC

U7400

CPU VCORE

EN

VID1

Q5300

USB_PWR_EN

(PCH)

DDRREG_EN PG62

DELAY

RC

R7962PP1V05_SUS_LDO

U7960ISL88042IRTEZ

VDD

MIC2292OUT

PAGE49

PP3V3_S0_VMON

6

IMVP_VR_ON(P16)

R7978

PM_SLP_S3_L

CPU

U2760

8PP5V_S0_KBDLED

Q7860

14PP5V_S3_REG

V2MON

15

4

SMC_ONOFF_L

10-4

CPU_VCCSA_VID<0>

PGOOD

PVCCSA_PGOOD

PPVCCSA_S0_REG

R6906

23-1

PM_SLP_S5_L

DPWROK

SMC_DELAYED_PWRGD

ALL_SYS_PWRGDDRAMPWROK

P1V5CPU_EN

A

U2750

VOUT1

PM_S0_PGOOD

CPUVCCIOS0_PGOOD

A

P3V3S5_PGOOD

P5VS3_PGOOD

P1V8S0_PGOOD

R7550

PLTRST#16

R7350

DDRREG_PGOOD

RST*

COUGAR-POINT

SYS_RERST#

SLP_S3#(F4)

(PAGE 16~21)

SLP_S5_L(P95)

99ms DLY

P17(BTN_OUT)

(PAGE 9~13)

PWRBTN#

SMCP5VS3_PGOOD

PP3V3_S5_REG

CPU_VCCSA_VID<1>

PP5V_S0_VCCSA

VOUT1(L/H)

SMC_PBUS_VSENSE

P3V3S5_EN

CPUIMVP_VR_ON

PM_RSMRST_L

SLP_SUS#

U1800

SLP_S4#(H4)

CPUVCCIOS0_EN 21

14-1

PP3V3_S5

DDRVTT_EN

DDRREG_EN

VCC

VID0

PPVIN_S5_P5VP3V3

PPVCORE_S0_CPU_REG

V3MON

22

VIN

ENPVCCSA_EN

MAX15120CPUIMVP_VR_ON

25

PP1V05_TBTCIO_FET

SMC_CPU_ISENSE

EN

R7140

16-1

R7640

21

A

PGOOD

VIN

VOUT

VIN

SMC_CPU_FSB_ISENSE

(PAGE 59)

VIN

PP3V3_SUS_FET

A

VOUT

14-1TBTBST_EN_UVLO

Q9706

BKLT_PLT_RST_L

13-2P3V3S5_PGOOD

(PAGE 55)

VOUT2

3A 32VF9700

PBUSVSENS_EN

(PAGE 65)

PM_SLP_S4_L

14

BKL_EN

15

Q7820

LP8550

U9701

SMC_PBUS_VSENSE

Q5300

PGOOD

A

P5V_3V3_SUS_EN

(PAGE 36)

P1V8_S0_EN

17

PP3V3_T29_FET

PP1V5S0_EN

10-2

AR4599

R7831T29_PWR_EN

Q7810

Q7830

P3V3S0_EN

14

PP3V3_S3_FET

EN

VIN

U7740

10-3

14-1PP3V3_S0

R5430

P5VS3_EN

11PM_SLP_S5_L

7U7201

13

PP5V_S0_CPUVCCIOS0.

6-1SYSRST(PA2) PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

U4900

5

PPCPUVCCIO_S0_REG

29

PM_RSMRST_L

PM_PWRBTN_L

PM_SYSRST_L

PM_DSW_PWRGD

28PM_MEM_PWRGD

10P15

4

26

12

PROCPWRGD

RSMRST#

4SMC_RESET_L

22

U5010SN0903048

SMC POWER

(PAGE 42)

3

U7600CPUVCCIOS0_EN

(PCH)

U1000

RSMRST_IN(P13)

PWR_BUTTON(P90)

PWRGD(P12)

SLP_S3_L(P93)

9

PM_SLP_S4_L

V4MON

(PAGE 62)

1819

U7770

TPS72015

(PAGE 60)

TPS720105

U7780(PAGE 60)

EN

P1V8S0_PGOOD

S5

S3

VOUT

PP1V8_S0_REGU7720ISL8014A

EN

(PAGE 60)

EN

9

R6905

5VEN1

EN2

7

PG 17

PG62

VIN

ENVOUT

PP15V_T29_REG(PAGE 36)

VINLT3957U3890

Q3880

&&

13

PG62

PG 17

PG 17

T29_A_HV_EN

14-1PBUSVSENS_EN

PG62

P5V_3V3_SUS_EN

P3V3S0_EN

P5VS3_EN

6RC

DELAY

U7940

RC

SLP_S5#(E4)

SMC_PM_G2_EN

P60

PM_SLP_S3_R_L

21

22

17

19

1V05_S0_LDO_EN

PVCCSA_EN

RC

DELAY

DELAY

RC

P1V8S0_EN

P1V5S0_EN

DELAY

RC

RC

DELAY

P5VS0_EN 14-1

EN

(PAGE 41)

27

U3816/U3820

PM_DSW_PWRGD

ISL95870

1.05V

PPVIN_G3H_P3V42G3H

22-1

15A

TPS22924

U3810

PP1V05_S0_LDO.

PP1V5_S0_REG

PLT_RERST_L

CPU_PWRGD

30

SM_DRAMPWROK

UNCOREPWRGOOD

RESET*

23

PP1V5_S3RS0_FET

13-1PM_SLP_SUS_LCOUGAR-POINT

DELAY

P3V3S3_EN

PG61

10-1

J13 POWER SYSTEM ARCHITECTURE

P5VS0_ENU5750

KBDLED_ANPDE

ALL_SYS_PWRGD

S5_PWRGD

25

SLP_S4_L(P94)

Revision HistorySYNC_DATE=11/10/2011

3 OF 73

3 OF 109

2.8.0

051-9277

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

Apple Inc.


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TABLE_BOMGROUP_ITEM

BOM OPTIONSBOM NAMEBOM NUMBERTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM



TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM Variants Bar Code Labels / EEEE #’s

Sub BOM

J13_CMNPTS,EEEE:F27Q,CPU:1.8GHZ,DDR3:SAMSUNG_8GBPCBA,MLB,1.8GHZ,SA 8GB,J13639-3791

J13_CMNPTS,EEEE:F27R,CPU:2.0GHZ,DDR3:SAMSUNG_8GBPCBA,MLB,2.0GHZ,SA 8GB,J13639-3792

J13_CMNPTS,EEEE:F27V,CPU:1.7GHZ,DDR3:SAMSUNG_8GBPCBA,MLB,1.7GHZ,SA 8GB,J13639-3790

PCBA,MLB,2.0GHZ,EL 8GB,J13639-3767 J13_CMNPTS,EEEE:F25V,CPU:2.0GHZ,DDR3:ELPIDA_8GB

J13_CMNPTS,EEEE:F27W,CPU:1.7GHZ,DDR3:ELPIDA_4GBPCBA,MLB,1.7GHZ,EL 4GB,J13639-3793

PCBA,MLB,2.0GHZ,HY 4GB,J13639-3766 J13_CMNPTS,EEEE:F25R,CPU:2.0GHZ,DDR3:HYNIX_4GB

639-3765 PCBA,MLB,2.0GHZ,HY 8GB,J13 J13_CMNPTS,EEEE:F25W,CPU:2.0GHZ,DDR3:HYNIX_8GB

639-3764 PCBA,MLB,2.0GHZ,SA 4GB,J13 J13_CMNPTS,EEEE:F25N,CPU:2.0GHZ,DDR3:SAMSUNG_4GB

639-3762 PCBA,MLB,1.8GHZ,HY 4GB,J13 J13_CMNPTS,EEEE:F25Y,CPU:1.8GHZ,DDR3:HYNIX_4GB

J13_CMNPTS,EEEE:F25T,CPU:1.8GHZ,DDR3:HYNIX_8GB639-3761 PCBA,MLB,1.8GHZ,HY 8GB,J13

J13_CMNPTS,EEEE:F0TD,CPU:1.7GHZ,DDR3:ELPIDA_8GB639-3644 PCBA,MLB,1.7GHZ,EL 8GB,J13

PCBA,MLB,1.7GHZ,HY 8GB,J13639-3556 J13_CMNPTS,EEEE:DYRK,CPU:1.7GHZ,DDR3:HYNIX_8GB

085-3939 J13 MLB DEVELOPMENT BOM J13_DEVEL:ENG

J13_CMNPTS,EEEE:F25Q,CPU:1.8GHZ,DDR3:SAMSUNG_4GBPCBA,MLB,1.8GHZ,SA 4GB,J13639-3760

639-3763 PCBA,MLB,1.8GHZ,EL 8GB,J13 J13_CMNPTS,EEEE:F25P,CPU:1.8GHZ,DDR3:ELPIDA_8GB

PCBA,MLB,1.5GHZ,EL 8GB,J13639-3645 J13_CMNPTS,EEEE:F0TC,CPU:1.5GHZ,DDR3:ELPIDA_8GB

SYNC_DATE=07/27/2011SYNC_MASTER=J30_MLB

Revision History

J13_CMNPTS,EEEE:F27Y,CPU:1.8GHZ,DDR3:ELPIDA_4GBPCBA,MLB,1.8GHZ,EL 4GB,J13639-3794

J13_CMNPTS,EEEE:DYRM,CPU:1.5GHZ,DDR3:SAMSUNG_4GB639-3553 PCBA,MLB,1.5GHZ,SA 4GB,J13

CRITICAL EEEE:F25Q[EEEE_F25Q]825-7670 LBL,P/N LABEL,PCB,28MM X 6 MM1

[EEEE_F25R]1 CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM825-7670 EEEE:F25R

1 CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM825-7670 [EEEE_F27V] EEEE:F27V

LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL1825-7670 [EEEE_F27W] EEEE:F27W

[EEEE_F25W]1 CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM825-7670 EEEE:F25W

LBL,P/N LABEL,PCB,28MM X 6 MM825-7670 CRITICAL1 [EEEE_DYRQ] EEEE:DYRQ

EEEE:F25P[EEEE_F25P]825-7670 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL1

[EEEE_F25N] EEEE:F25N825-7670 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL1

[EEEE_F25V]1 CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM825-7670 EEEE:F25V

1 CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM825-7670 [EEEE_F27R] EEEE:F27R

LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL1825-7670 [EEEE_F27Y] EEEE:F27Y

1 CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM825-7670 [EEEE_F27Q] EEEE:F27Q

[EEEE_F27T]1 CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM825-7670 EEEE:F27T

[EEEE_F25T]1 CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM825-7670 EEEE:F25T

LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL1825-7670 [EEEE_F25Y] EEEE:F25Y

J13_CMNPTSCMN PTS,PCBA,MLB,J13607-9090 CMNPTS CRITICAL1

085-3939 DEVEL_BOMDEVEL1 CRITICALJ13 MLB DEVELOPMENT

825-7670 EEEE:F0TD[EEEE_F0TD]1 CRITICALLBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DYRP] EEEE:DYRP825-7670 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL1

EEEE:DYRM[EEEE_DYRM]825-7670 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL1

LBL,P/N LABEL,PCB,28MM X 6 MM EEEE:F0TC[EEEE_F0TC]825-7670 CRITICAL1

EEEE:DYRL[EEEE_DYRL]825-7670 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL1

EEEE:DYRN[EEEE_DYRN]825-7670 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL1

[EEEE_DYRK] EEEE:DYRK825-7670 LBL,P/N LABEL,PCB,28MM X 6 MM CRITICAL1

J13_CMNPTS,EEEE:DYRN,CPU:1.5GHZ,DDR3:HYNIX_4GB639-3554 PCBA,MLB,1.5GHZ,HY 4GB,J13

J13_CMNPTS,EEEE:DYRL,CPU:1.5GHZ,DDR3:HYNIX_8GB639-3555 PCBA,MLB,1.5GHZ,HY 8GB,J13

J13_CMNPTS,EEEE:DYRP,CPU:1.7GHZ,DDR3:HYNIX_4GB639-3557 PCBA,MLB,1.7GHZ,HY 4GB,J13

J13_CMNPTS,EEEE:DYRQ,CPU:1.7GHZ,DDR3:SAMSUNG_4GB639-3552 PCBA,MLB,1.7GHZ,SA 4GB,J13

CMN PTS,PCBA,MLB,J13 J13_COMMON607-9090

J13_CMNPTS,EEEE:F27T,CPU:2.0GHZ,DDR3:ELPIDA_4GB639-3795 PCBA,MLB,2.0GHZ,EL 4GB,J13

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TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

BOM OPTIONSBOM GROUPTABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Module Parts

DRAM CFG CHART

MICRON

Programmable Parts

Alternate Parts

1

0

B

A

DIE REV CFG 3

00

CFG 1 CFG 0VENDOR

HYNIX

1

1

0

0

CFG 2

1

0

1

1

ELPIDA

SIZE

4GB

SAMSUNG

8GB

PD Module Parts

J13 BOM GROUPS

371S0558371S0713 ALL

337S4196337S4236 ALL

ALL337S4198

152S1462

353S1428

372S0185

152S1307

Murata alt to Taiyo Yuden

Coilcraft alt to Murata

CPUMEM_SLG:NO,HUB_3NONREM,TBT,MPM5:YES,PP5V5_DCIN:NO,TPAD_PCH:NO,SKIP_5V3V3:INAUDIBLE,BTPWR:S4,TBTHV:P15V,LVDDR3_HW:YES,AXG_ACOUSTIC:NO

BOOTROM_PROG,SMC_PROG,TBTROM:PROG

ALTERNATE,BKLT:ENG,XDP_CONN,XDP_CPU:BPM,XDP_PCH,LPCPLUS,DDRVREF_DAC,VREFDQ:M1_M3,VREFCA:LDO_DAC,S0PGOOD_ISL,S3_S0_LED,VCCIOISNS_ENG,AIRPORTISNS_ENG,HDDISNS_ENG,LCDBKLTISNS_ENG

LPCPLUS,XDP_CONN

DEVEL_BOM,MOJO:YES,XDP

BKLT:PROD,MOJO:YES,XDP,XDP_CPU:BPM,VREFDQ:LDO,VREFCA:LDO,LPCPLUS,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB

ALTERNATE,COMMON,J13_MISC,J13_DEBUG:ENG,J13_PROGPARTS,USBHUB2514B,EDP:YES,PCH_C1

IC,SDRAM,2GBIT,DDR3L-1600,REV D.78P FBGA

IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

DRAM_TYPE:ELPIDA_4GB




333S0628

333S0628

333S0628

U3200,U3210,U3220,U3230 CRITICAL4

U3100,U3110,U3120,U3130 CRITICAL4

4 CRITICAL

CRITICAL

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA DRAM_TYPE:ELPIDA_8GBU2900,U2910,U2920,U2930 CRITICAL

IC,SDRAM,4GBIT,DDR3L-1600,REV B.78P FBGA DRAM_TYPE:ELPIDA_8GBCRITICAL4 U3000,U3010,U3020,U3030

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FGBA DRAM_TYPE:ELPIDA_8GB4 CRITICALU3100,U3110,U3120,U3130

IC,SDRAM,4GBIT,DDR3L-1600,REV B,78P FBGA DRAM_TYPE:ELPIDA_8GBCRITICALU3200,U3210,U3220,U3230

CRITICAL1806-3083 SHLD,USB,MLB,J11/J13 USBCAN

K78, mDP Spring1806-2377 CRITICALMDPSPRING NOSTUFF

MDPCAN1 CRITICAL806-3216 CAN,MDP,J11/J13

CAN,TOPSIDE_2Piece_Fence,J11/J13 CRITICAL1806-3705 TBTTOPSIDE_2P_FENCE

1 CAN,TOPSIDE,J11/J13806-3214 CRITICALTBTTOPSIDE_1P

CAN,TOPSIDE_2Piece_Cover,J11/J131 CRITICAL806-3706 TBTTOPSIDE_2P_COVER

CRITICAL1806-3215 CAN,COVER,T29,J11/J13 TBTCOVER

1 U7000IC,ISL6259,BATCHARGER,3%,4X4MM,QFN28 CRITICAL353S2929

806-3142 CRITICAL1 CAN,T29,J11/J13 TBTFENCE

GLUE946-3115 1 MLB,DYMAX UV EB 0.22GRAM,K21 CRITICAL

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB

RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FBGA4 DRAM_TYPE:HYNIX_4GB333S0622 CRITICAL

U3100,U3110,U3120,U31304 CRITICALIC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FGBA

IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE U3200,U3210,U3220,U3230 CRITICAL4

U3100,U3110,U3120,U3130

U3000,U3010,U3020,U3030 CRITICALIC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE

DRAM_TYPE:SAMSUNG_8GB4 IC,SDRAM,4GBIT,DDR3-1600,78P FBGA,C-DIE

333S0623 DRAM_TYPE:SAMSUNG_4GBCRITICAL4

4 IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE CRITICAL

DRAM_TYPE:SAMSUNG_4GB4 CRITICAL

CRITICAL333S0623 IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE

U3200,U3210,U3220,U3230IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FBGA CRITICAL4

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FPGA DRAM_TYPE:HYNIX_8GBCRITICAL4

IC,SDRAM,4GBIT,512MXB,DDR3-1600,82 FBGA U2900,U2910,U2920,U2930 DRAM_TYPE:HYNIX_8GB4

U3200,U3210,U3220,U3230 CRITICAL4 IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FBGA333S0622

NXP alt to NXPALL371S0652371S0709

376S0928376S0790 TI alt to Fairchild

138S0671 ALL Taiyo alt to Murata138S0673

TBTROM:BLANKCRITICAL1 IC,SERIAL SPI EEPROM,256KBIT,20MHZ,MLP8335S0865

376S0604 Diodes alt to FairchildALL

376S0855 ALL

ALL376S0903

197S0432197S0431 ALL

Toko alt for NEC inductor152S1295 ALL

152S1493 152S1300 ALL

353S3238 ALL Intersil alt to OPA2333

U4900 SMC_BLANKCRITICAL1 IC,SMC12,40MHZ/50DMIPS MCU, 9X9,157BGA338S1065

64 MBIT SPI SERIAL DUAL I/O FLASH,Macronix CRITICAL1 BOOTROM_BLANK335S0809 U6100

376S0855 Diodes alt to Toshiba376S0613 ALL

U3100,U3110,U3120,U3130 CRITICAL333S0622 IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FGBA4

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78P FPGA DRAM_TYPE:HYNIX_4GBCRITICAL4333S0622

CPU:1.7GHZCRITICAL1 U1000

CPU:1.5GHZU10001 CRITICAL

CPU:1.8GHZCRITICALU1000

U10001

U1000 CRITICAL1

U1800 PCH_ES11

1 U3600338S1047 TBTIC,TBT,CR-4C,ES1,288 FCBGA,12X12MM

PCH_ES2CRITICAL337S4180

CRITICALU18001 PCH_C0

IC,PCH,PPT-MB,QS77,C1,QS337S4275 PCH_C11 U1800 CRITICAL

ALL Toko alt for Cyntec152S1085

ALL Murata alt to Taiyo Yuden138S0648

ALL138S0684 138S0660

ALL372S0186

64 MBIT SPI SERIAL DUAL I/O FLASH,Numonyx CRITICAL BOOTROM_BLANKU61001335S0803

ALL376S0859 Diodes alt to Toshiba376S0977

138S0676 ALL138S0691 Murata alt to Samsung

ALL Rohm alt to Toshiba376S0972 376S0612

J13_DEBUG:PROD

J13_DEVEL:PVT

J13_DEVEL:ENG

J13_PROGPARTS

J13_MISC

J13_COMMON

J13_DEBUG:ENG

DDR3:SAMSUNG_8GB

DDR3:ELPIDA_4GB

BOM Configuration


J13_DEBUG:PVT

DDR3:HYNIX_4GB

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GBDDR3:HYNIX_8GB

DDR3:SAMSUNG_4GB

IC,EEPROM,CR,V24.1,J11/J13341S3475 TBTROM:PROG1

IC,EFI ROM,PROTO1B,J13 J11341S3482 CRITICAL BOOTROM_PROGU61001

341S3433 U4900 CRITICAL1 SMC_PROGIC,SMC,V2.1A43,Proto1B,J13

IC,SMC12-A3,40MHZ/50DMIPS MCU,9X9,157BGA SMC_BLANKCRITICAL1338S1098

DDR3:ELPIDA_8GB

376S0796

376S1053

376S0613

NXP alt to Diodes

Diodes alt to Toshiba

Fairchild alt to Siliconix

Epson alt to NDK

TDP 1.5GHZ alt to Nominal

TDP 1.7GHZ alt to Nominal

Diodes alt to ST Micro

128S0333 ALL Sanyo alt to Kemet998-4435

128S0357 Sanyo alt to POS caps998-4435 ALL

Kemet_Rect alt to POS caps998-4435998-4715 ALL

Kemet_.0045 Flute alt to POS caps998-4435998-4716 ALL

DRAM_TYPE:SAMSUNG_8GB

DRAM_TYPE:HYNIX_8GB




CRITICAL

4

333S0623

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FGBA

IC,SDRAM,2GBIT,DDR3L-1600,REV D,78P FBGA

333S0623

333S0625

333S0625

333S0625

333S0625

4

4

333S0629

333S0628

333S0642

333S0642

333S0642

333S0642

4

IC,SDRAM,2GBIT,DDR3-1600,78P FGBA,D-DIE

IC,SDRAM,2GBIT,DDR3-1600,78P FBGA,D-DIE

IC,SDRAM,4GBIT,DDR3-1600,78P FGBA,C-DIE

333S0629

333S0629

333S0629

4

4

138S0703

CRITICAL

U3000,U3010,U3020,U3030

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB

DEVEL_BOM,BKLT:PROD,MOJO:YES,XDP,XDP_CPU:BPM,VREFDQ:LDO,VREFCA:LDO,VCCIOISNS_PROD,AIRPORTISNS_PROD,HDDISNS_PROD,LCDBKLTISNS_PROD

CRITICAL

ALL

337S4197

U3690

U3690

U4900

DRAM_TYPE:HYNIX_4GB

CRITICAL

U2900,U2910,U2920,U2930

U3200,U3210,U3220,U3230

U3100,U3110,U3120,U3130

U3000,U3010,U3020,U3030

U2900,U2910,U2920,U2930

U3000,U3010,U3020,U3030

U2900,U2910,U2920,U2930

DRAM_TYPE:HYNIX_4GB

DRAM_TYPE:HYNIX_8GB


IVB,QBP8,ES2,K0,1.5,17W,2+2,0.95,4M,ULVB

U1800

CRITICAL

CPU:1.7GHZTDP

CPU:1.5GHZTDP

CPU:2.0GHZCRITICALU1000

CRITICAL

CRITICAL

IC,PCH,PPT-MB,SFF,ES2,B0

IC,PCH,PPT-MB,SFF,ES1

1

337S4235

337S4197

IC,PCH,PPT-MB,SFF,P-QS,C0

1

IVB,QBQF,ES2,K0,1.7,17W,2+2,1.0,4M,ULV,TDP

IVB,QBP8,ES2,K0,1.5,17W,2+2,0.95,4M,ULVB

IVB,QC55,QS,L0,1.7,17W,2+2,1.0,3M,ULVBGA

IVB,QC54,QS,L0,1.8,17W,2+2,1.1,3M,ULVBGA

IVB,QC52,QS,L0,2.0,17W,2+2,1.1,4M,ULVBGA1

337S4165

337S4236

337S4198

337S4296

337S4298

337S4299

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FUNC_TEST

(Need to add 2 GND TPs)

POWER SIGNALS

NO_TEST

NO_TEST Nets

FUNC_TEST

J5600: Fan Connector

(Need to add 1 GND TP)

FUNC_TEST


J5700: IPD Flex Connector


FUNC_TEST

FUNC_TEST

J5100: LPC+SPI Connector


(Need 5 TPs)

Functional Test Points

FUNC_TEST

(Need 2 TPs)

(Need to add 2 GND TP)

J5715: KB BKLT CONNECTORFUNC_TEST


(Need 5 TPs)


J4501: SATA SSD ConnectorFUNC_TEST

(Need 6 TPs)


J6900: DC-In ConnectorFUNC_TEST

(Need 4 TPs)


J6903: Speaker Connector

FUNC_TEST

FUNC_TEST

(Need 2 TPs)


FUNC_TEST

J4001: AirPort / BT Connector

J4700: LIO Connector

(Need to add 4 GND TPs near

J6950: Battery Connector

J9000: Internal DP Connector

J6950 and 1 for shield)

FUNC_TEST

(Need 2 TPs)

Misc Voltages & Control Signals


J4800: SD Card Connector

SYNC_DATE=07/29/2011SYNC_MASTER=K21_MLB

Functional Test / No Test

TRUE PPVBAT_G3H_CONN

TRUE SPKRAMP_ROUT_N

TRUE =SMBUS_BATT_SDA

TRUE USB_BT_CONN_P

TRUE NC_PCIE_CLK100M_PE7NMAKE_BASE=TRUE

TRUE PP1V5_S0

TP_PCI_CLK33M_OUT3

TP_PCI_PME_L

NC_PCIE_CLK100M_PE7PTRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4NTRUEMAKE_BASE=TRUE

AP_CLKREQ_Q_LTRUE

PCIE_AP_D2R_NTRUE

PCIE_AP_D2R_PTRUE

PCIE_CLK100M_AP_PTRUE

TRUE PCIE_CLK100M_AP_NTRUE PCIE_AP_R2D_P

AP_RESET_CONN_LTRUE

DP_INT_ML_F_N<1>TRUE

DP_INT_ML_F_P<1>TRUE

TRUE

TRUE DP_INT_ML_F_P<0>TRUE DP_INT_AUX_CH_C_P

TRUE

DP_INT_AUX_CH_C_NTRUE

LED_RETURN_1TRUE

TRUE LED_RETURN_2TRUE LED_RETURN_3TRUE

LED_RETURN_5TRUE

TRUE LED_RETURN_6I2C_TCON_SCL_RTRUE

TRUE I2C_TCON_SDA_R

PPVOUT_SW_LCDBKLTTRUE

PP3V3_SW_LCDTRUE

PP3V3_S4PP5V_S0PP5V_S3PPDCIN_G3H_ISOLPPBUS_S5_HS_OTHER_ISNSPP1V05_TBTCIOPP1V8_S0_CPU_VCCPLL_RTRUE

PP1V5_S3_CPU_VCCDQTRUE

PP1V05_S0_CPU_VCCPQETRUE

PPVCORE_S0_AXGTRUE

PPVCORE_S0_CPUTRUE

PP1V05_S0_PCH_VCCADPLLTRUE

TRUE PP1V05_TBTLCPP3V3_TBTLCTRUE

PP15V_TBTTRUE

PPVCCSA_S0_CPUTRUE

PP1V05_SUSTRUE

PP0V75_S0_DDRVTTTRUE

PPVTTDDR_S3TRUE

TRUE PP1V05_S0

PP1V5_S3RS0TRUE

PP1V5_S3TRUE

PP3V3_S0TRUE

PP1V8_S0TRUE

PP3V3_SUSTRUE

PP3V3_S3TRUE

PP3V3_S5TRUE

PP5V_SUSTRUE

TRUE PP5V_S5PPVRTC_G3HTRUE

PP3V42_G3HTRUE

PPDCIN_G3HTRUE

PPVIN_SW_TBTBSTTRUE

TRUE PPBUS_S5_HS_COMPUTING_ISNS

PPBUS_G3HTRUE

SYS_DETECT_LTRUE

=SMBUS_BATT_SCLTRUE

TRUE =PP5V_S3_LIO_CONN=PP18V5_DCIN_CONNTRUE

TRUE SSD_P3V3S0_EN

TRUE SSD_RESET_L

TRUE SATA_PCIE_SEL

TRUE SATA_SSD_R2D_P

TRUE SSD_CLKREQ_L

PCIE_SSD_D2R_N<1>TRUE

TRUE SATA_SSD_R2D_N

SMC_OOB1_TX_LTRUE

TRUE PCIE_CLK100M_SSD_P

SATA_SSD_D2R_NTRUE

SMC_OOB1_RX_LTRUE

SATA_SSD_D2R_PTRUE

PP3V3_S0_SSD_FLTTRUE

TRUE KBDLED_FB

TRUE KBDLED_ANODE

USB3_EXTB_TX_C_PTRUE

TRUE

TRUE

USB3_EXTB_TX_C_NTRUE

TRUE USB_EXTB_PUSB_EXTB_NTRUE

TRUE SPKRAMP_INR_PSPKRAMP_INR_NTRUE

AUD_GPIO_3TRUE

AUD_I2C_INT_LTRUE

AUD_IP_PERIPHERAL_DETTRUE

AUD_IPHS_SWITCH_ENTRUE

=I2C_MIKEY_SDATRUE

=I2C_MIKEY_SCLTRUE

=I2C_LIO_SCLTRUE

=I2C_LIO_SDATRUE

TRUE SMC_LIDTRUE =USB_PWR_EN

SMC_BC_ACOKTRUE

TRUE SYS_ONEWIRETRUE =PP3V3R1V5_S0_AUDIOTRUE =PP3V3_S0_AUDIOTRUE =PP3V42_G3H_ONEWIRE

TRUE

TRUE

TRUE

TRUE HDA_SDOUT

TRUE

TRUE

TRUE

TRUE USB_CAMERA_P

TRUE SMC_TDO

TRUE TP_SMC_TRST_L

SD_CMDTRUE

TRUE LPC_PWRDWN_L

PCIE_AP_R2D_NTRUE

WIFI_EVENT_LTRUE

TRUE PP3V3_WLAN_F

TRUENC_CPU_RSVD<8..27>MAKE_BASE=TRUE

TP_CPU_RSVD<8..27>

TRUE =I2C_TPAD_SCL

TP_PCIE_CLK100M_PEBN

PCIE_WAKE_LTRUE

TP_CRT_IG_DDC_CLK

TP_CRT_IG_VSYNC

TP_LVDS_IG_CTRL_CLK

TP_PCH_LVDS_VBG

TP_HDA_SDIN1

TP_HDA_SDIN2

TP_CLINK_RESET_L

TP_PCIE_CLK100M_PEBP

TP_CLINK_DATA

TP_CLINK_CLK

TP_CRT_IG_HSYNC

TP_HDA_SDIN3

TP_LVDS_IG_CTRL_DATA

TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

TP_SDVO_STALLN

TP_SDVO_INTP

TP_SDVO_INTN

TP_SDVO_STALLP

TP_XDP_PCH_OBSFN_D<0..1>

TP_XDPPCH_HOOK3

TP_XDP_PCH_OBSFN_B<0..1>

TP_XDPPCH_HOOK2

TP_XDP_PCH_OBSFN_A<0..1>

TP_XDP_PCH_HOOK4

TP_XDP_PCH_HOOK5

TP_PCH_GPIO64_CLKOUTFLEX0




SMC_BS_ALRT_L

TP_LVDS_IG_BKL_PWM

TP_LVDS_IG_B_CLKP

TP_LVDS_IG_B_CLKN

TP_PCH_TP1

TP_PCH_TP2

TP_PCH_TP3

TP_PCH_TP4

TP_PCH_TP5

TP_PCH_TP6

TP_PCH_TP7

TP_PCH_TP8

TP_PCH_TP9

TP_PCH_TP10

TP_PCH_TP12

TP_PCH_TP13

TP_PCH_TP14

TP_PCH_TP15

TP_PCH_TP16

TP_PCH_TP18

TP_PCH_TP17

TP_SATA_E_D2RP

TP_SATA_E_D2RN

TP_SATA_F_R2D_CP

TP_SATA_D_D2RP

TP_SATA_D_D2RN

TP_SATA_D_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_B_R2D_CP

TP_SATA_B_D2RP

TP_SATA_B_D2RN

TP_PSOC_P1_3

TP_PCIE_CLK100M_PE7P

TP_SATA_B_R2D_CN

TP_PCIE_CLK100M_PE7N




TP_CPU_THERMDC

TP_EDP_AUX_N

TP_EDP_TX_N<0..3>

TP_EDP_AUX_P

TP_EDP_TX_P<0..3>

TRUE LPCPLUS_GPIOTRUE SMC_RX_L

TRUE SMC_RESET_L

SMC_TDITRUE

SPI_ALT_CS_LTRUE

TRUE SPI_ALT_CLKTRUE SPIROM_USE_MLBTRUE LPC_CLK33M_LPCPLUSTRUE SMC_TX_L

TRUE LPCPLUS_RESET_L

TRUE PM_CLKRUN_L

TRUE SMC_TMS

TRUE SPI_ALT_MISO

TRUE LPC_FRAME_L

PP3V3_S3RS4_BT_FTRUE

TRUE USB_BT_CONN_N

NC_PCIE_CLK100M_PE6NMAKE_BASE=TRUETRUE

TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6P

NC_SATA_B_R2D_CNTRUEMAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_PSOC_P1_3TRUE

MAKE_BASE=TRUETRUE NC_SATA_B_D2RN

TRUEMAKE_BASE=TRUE

NC_SATA_D_R2D_CP

TRUEMAKE_BASE=TRUE

NC_SATA_F_R2D_CP

NC_SATA_F_R2D_CNTRUEMAKE_BASE=TRUE

NC_SATA_F_D2RNMAKE_BASE=TRUE

TRUE

NC_SATA_E_R2D_CPTRUEMAKE_BASE=TRUE

NC_SATA_F_D2RPTRUEMAKE_BASE=TRUE

NC_SATA_E_D2RNMAKE_BASE=TRUETRUE

NC_SATA_E_R2D_CNTRUEMAKE_BASE=TRUE

NC_SATA_E_D2RPTRUEMAKE_BASE=TRUE

MAKE_BASE=TRUENC_PCH_TP17TRUE




MAKE_BASE=TRUETRUE NC_PCH_TP14




NC_PCH_TP9TRUEMAKE_BASE=TRUE


TRUEMAKE_BASE=TRUE

NC_PCH_TP7



TRUE PCH_VSS_NCTF<15>


NC_PCH_TP3MAKE_BASE=TRUETRUE

TRUEMAKE_BASE=TRUE

NC_PCH_TP2

NC_PCH_TP1MAKE_BASE=TRUETRUE

PCH_VSS_NCTF<17>TRUE







TRUEMAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

TRUE NC_LVDS_IG_B_CLKP

MAKE_BASE=TRUETRUE NC_LVDS_IG_BKL_PWM

MAKE_BASE=TRUETRUE NC_SMC_BS_ALRT_L

PCH_VSS_NCTF<1>TRUE

PCH_VSS_NCTF<5>TRUE

PCH_VSS_NCTF<2>TRUE




TRUEMAKE_BASE=TRUE

NC_PCH_GPIO67_CLKOUTFLEX3

TRUEMAKE_BASE=TRUE

NC_PCH_GPIO66_CLKOUTFLEX2MAKE_BASE=TRUETRUE NC_PCH_GPIO65_CLKOUTFLEX1MAKE_BASE=TRUETRUE NC_PCH_GPIO64_CLKOUTFLEX0

NC_TP_XDP_PCH_HOOK5MAKE_BASE=TRUETRUE

NC_TP_XDP_PCH_HOOK4MAKE_BASE=TRUETRUE

MAKE_BASE=TRUETRUE NC_TP_XDP_PCH_OBSFN_A<0..1>

MAKE_BASE=TRUETRUE NC_TP_XDPPCH_HOOK2MAKE_BASE=TRUETRUE NC_TP_XDP_PCH_OBSFN_B<0..1>

TRUEMAKE_BASE=TRUE

NC_TP_XDPPCH_HOOK3

TRUEMAKE_BASE=TRUE

NC_TP_XDP_PCH_OBSFN_D<0..1>

MAKE_BASE=TRUETRUE NC_SDVO_STALLP

TRUEMAKE_BASE=TRUE

NC_SDVO_STALLN

MAKE_BASE=TRUETRUE NC_SDVO_INTP

MAKE_BASE=TRUETRUE NC_SDVO_TVCLKINP

TRUEMAKE_BASE=TRUE

NC_SDVO_TVCLKINN

TRUEMAKE_BASE=TRUE

NC_SDVO_INTN

XDP_AP_CLKREQ_LTRUE

XDP_PCH_AUD_IPHS_SWITCH_ENTRUE

XDP_FW_CLKREQ_LTRUE

XDP_PCH_PWRBTN_LTRUE

XDP_PCH_ISOLATE_CPU_MEM_LTRUE

XDP_PCH_S5_PWRGDTRUE

XDP_PCH_ENET_PWR_ENTRUE

TRUEMAKE_BASE=TRUE

NC_CRT_IG_VSYNCMAKE_BASE=TRUETRUE

NC_LVDS_IG_CTRL_CLKMAKE_BASE=TRUETRUE

NC_HDA_SDIN1TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUETRUE NC_HDA_SDIN3

TRUEMAKE_BASE=TRUE

NC_HDA_SDIN2

NC_CLINK_RESET_LTRUEMAKE_BASE=TRUE

MAKE_BASE=TRUETRUE NC_CLINK_CLK

NC_CLINK_DATAMAKE_BASE=TRUE

TRUE

TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBN

TRUEMAKE_BASE=TRUE

NC_PCI_CLK33M_OUT3

TRUENC_CPU_RSVD<30..45>

NC_PCIE_CLK100M_PE5NTRUEMAKE_BASE=TRUE

LPC_AD<3..0>TRUE

=PP5V_S0_LPCPLUSTRUE

SD_CD_LTRUE

TRUE SD_WP

PP5V_TPAD_FILTTRUE

TRUE USB_TPAD_CONN_P

TRUE =I2C_TPAD_SDA

TRUE

TRUE SMC_TPAD_RST_LTRUE SMC_LID

SMC_PME_S4_WAKE_LTRUE

TRUE PP3V3_TPAD_CONN

FAN_RT_TACHTRUE

=PP5V_S0_FANTRUE

TRUE FAN_RT_PWM

SPI_ALT_MOSITRUE

=PP3V42_G3H_TPADTRUE

=PP3V3_S5_LPCPLUSTRUE

TRUENC_EDP_AUXP

TRUE

MAKE_BASE=TRUE




TRUEMAKE_BASE=TRUE

TRUEMAKE_BASE=TRUE

NC_PCI_PME_L

TRUENC_CPU_THERMDCMAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4PTRUEMAKE_BASE=TRUE

MAKE_BASE=TRUETRUE NC_PCIE_CLK100M_PE5P

MAKE_BASE=TRUETRUE NC_SATA_B_D2RP

TRUEMAKE_BASE=TRUE

NC_SATA_B_R2D_CP

MAKE_BASE=TRUETRUE NC_SATA_D_D2RN

NC_SATA_D_D2RPMAKE_BASE=TRUE

TRUE

NC_SATA_D_R2D_CNTRUEMAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TP_CPU_THERMDA

TP_CPU_RSVD<30..45>

=PEG_D2R_N<15..2>

=PEG_D2R_P<15..2>

=PEG_R2D_C_N<15..2>

=PEG_R2D_C_P<15..2>

TRUENC_PEG_D2RP<15..2>

TRUE

MAKE_BASE=TRUENC_PEG_R2D_CP<15..2>

TRUE

MAKE_BASE=TRUE

TRUENC_PEG_D2RN<15..2>MAKE_BASE=TRUE

TRUEMAKE_BASE=TRUE

NC_PCIE_CLK100M_PEBP

TP_CRT_IG_DDC_DATA

TRUE LPC_SERIRQ

TRUE SMC_TCK

TRUE SMC_ROMBOOT

TRUE

XDP_PCH_SDCONN_DET_LTRUE

TRUE USB_TPAD_CONN_N

TP_SATA_E_R2D_CN

TP_SATA_E_R2D_CP

TP_SATA_F_D2RN

TP_SATA_F_D2RP

TP_SATA_F_R2D_CN

NC_PCH_LVDS_VBGMAKE_BASE=TRUETRUE

NC_LVDS_IG_CTRL_DATAMAKE_BASE=TRUETRUE

TP_CRT_IG_GREEN

TP_CRT_IG_BLUE

TP_CRT_IG_RED

NC_CRT_IG_GREENMAKE_BASE=TRUETRUE

TRUEMAKE_BASE=TRUE

NC_CRT_IG_BLUE

NC_CRT_IG_DDC_DATAMAKE_BASE=TRUETRUEMAKE_BASE=TRUETRUE

TRUEMAKE_BASE=TRUE

NC_CRT_IG_RED

TRUE XDP_PCH_SDCONN_STATE_RST_L

TRUE XDP_PCH_USB_HUB_SOFT_RST_L

TRUE VCCSAS0_SET1_RVCCSAS0_SREFTRUE

TRUE

VCCSAS0_SET1TRUE

TRUE XDP_PCH_AP_PWR_EN

TRUE TP_SMC_MD1

SD_D<7..0>TRUE

SD_CLKTRUE

TRUE SPKRAMP_ROUT_P

TRUENC_CPU_THERMDAMAKE_BASE=TRUE

PCIE_SSD_D2R_P<1>TRUE

PCIE_CLK100M_SSD_NTRUE

PCIE_SSD_R2D_N<1>TRUE

PCIE_SSD_R2D_P<1>TRUE

DP_INT_ML_F_N<0>

DP_INT_HPD_CONN

LED_RETURN_4

SMC_ONOFF_L

VCCSAS0_SET0

NC_EDP_AUXN

NC_EDP_TXN<0..3>

NC_EDP_TXP<0..3>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_CN<15..2>

NC_CRT_IG_HSYNC

NC_CRT_IG_DDC_CLK

HDA_SDIN0HDA_BIT_CLK

USB_CAMERA_NUSB3_EXTB_RX_RC_PUSB3_EXTB_RX_RC_N

HDA_RST_LHDA_SYNC

PP3V3_SW_SD_PWR

USB_EXTB_OC_L

I499

I500

I501

I502

I503

I504

I505

I506

I566

I567

I568

I569

I570

I571

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I593

I594

I595

I596

I597

I598

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051-9277

2.8.0

7 OF 109

6 OF 73

52 53

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44 52

37 68

7

18

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37

16 37 69

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16 37 69

16 37 69

37 69

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63 66

63 66

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63 66

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7

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40

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39 40 62

40 41

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7 40

7 40

7 40

16 40 69

16 69

16

16 69

16 69

18 40 68

18 40 68

41 42 43

43

33

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37 69

37 41 42

37 42

44 49

16

17 37

17

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16

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41 42 43

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25 43 69

41 42 43

25 43 69

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41 42 43

43

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37

37 68

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23

23

16 41 43 69

7 43

33

33

49

68

44 49

41 42 49

42 49

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41 42 49

49

48

7

48

43

7 49

7

16

16

9

9

9

9

17

16 41 43

41 42 43

42 43

33

68

16

16

16

16

16

17

17

17

54

54

54

54

43

33

51 52 72

8 38 66

16 38 66

38 66

38 66

42

41

44

44

40

40

68

40

40

40

69

48

43

40

33

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



1.8V/1.5V/1.2V/1.05V Rails"G3Hot" (Always-Present) Rails 3.3V Rails

TBT Rails (off when no cable)

Chipset "VCore" Rails

1V05 S0 LDO

? mA

2A max supply

5V Rails

=PP3V3_S4_TPAD=PP3V3_S4_BT

=PP3V3_SUS_PCH_VCCSUS=PP3V3_SUS_GPIO

=PP3V3_S4_SMC=PP3V3_S4_SD_HPD

=PP3V3_S5_PCH_GPIO=PP3V3_S4_P3V3S4FET

=PP3V3_S5_PWRCTL=PP3V3_S4_TBTAPWRSW

=PP3V3_S5_SYSCLK=PP3V3_S5_VMON

=PP3V3_S5_SMCBATLOW

=PP3V3_S5_PCHPWRGD

=PP3V3_S5_PCH_VCCDSW

PP3V3_S5

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM VOLTAGE=3.3V

MAKE_BASE=TRUE

=PP3V3_S5_PCH

VOLTAGE=3.3VMAKE_BASE=TRUE

PP3V3_S4MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM

=PPBUS_S0_VSENSE

=PPVIN_S5_HS_COMPUTING_ISNS_R

PPBUS_S5_HS_OTHER_ISNS

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.6 mm

VOLTAGE=8.4V

=PP3V3_SUS_SMC=PP3V3_SUS_PCH_VCC_SPI=PP3V3_SUS_PCH_GPIO


PP3V3_SW_TBTAPWRMIN_LINE_WIDTH=0.38 MM

=PP3V3_S3_BT=PP3V3_S3_CARDREADER=PP3V3_S3_MEMRESET

PP3V3_SUSMIN_LINE_WIDTH=0.50MM

MAKE_BASE=TRUEVOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

=PP3V3_SUS_PCH_VCCSUS_USB

=PP3V3_SUS_PCH

VOLTAGE=8.4V

MIN_LINE_WIDTH=0.6 mmPPBUS_S5_HS_COMPUTING_ISNS

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

=PP3V3_S3_FET

=PP3V3_S4_TBT

=PP3V3_SUS_ROM

=PPVIN_S0_CPUAXG

=PPVCCSA_S0_CPU

=PP3V3_S5_XDP

=PPVIN_S0_CPUIMVP

=PP3V3_SUS_FET

=PPVIN_S0_VCCSAS0=PPVIN_S0_CPUVCCIOS0

=PP3V3_SUS_PWRCTL

=PPVTT_S0_DDR_LDO

=PPVTT_S3_DDR_BUF

=PP3V3_S3_BMON_ISNS=PP3V3_S3_PCH_GPIO

=PP3V3_S3_WLAN

=PPBUS_S0_LCDBKLT

=PP1V5_S0_REG

=PPVCCSA_S0_REG

=PPVIN_S5_P5VP3V3

=PPVIN_S5_HS_COMPUTING_ISNS

=PPVCORE_S0_CPU_REG

=PP1V5_S3_MEM_B

=PPVIN_S0_DDRREG_LDO=PP1V5_S3_P1V5S3RS0_FET

=PPDDR_S3_MEMVREF

=PP1V5_S3_MEM_A=PP1V5_S3_MEMRESET

=PP3V3R1V5_S0_AUDIO

VOLTAGE=12.8VPPVIN_SW_TBTBST

=PPBUS_G3H

=PPVIN_S5_HS_OTHER_ISNS_R

=PP1V5_S3RS0_FET

=PP1V8R1V5_S0_PCH_VCCVRM

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP1V8_S0_P1V05S0LDO=PP1V8_S0_PCH_VCC_DFTERM

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_REG

=PP1V5_S3_CPU_VCCDDR

=PP3V3_S0_P3V3S0FET

=PPHV_SW_DPAPWRSW=PPHV_SW_TBTAPWRSW

VOLTAGE=17.8VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

PP15V_TBT

=PPVDDIO_S0_SBCLK

MIN_LINE_WIDTH=2 mm

VOLTAGE=1.5VMIN_NECK_WIDTH=0.17 mm

PP1V5_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V5_S3RS0

VOLTAGE=1.5V

=PP1V8_S0_P1V5S0

MIN_NECK_WIDTH=0.1 MMMIN_LINE_WIDTH=0.8 MM


PP1V5_S3



PP1V8_S0

=PPDDR_S3_REG

=PP15V_TBT_REG

=PP3V3_TBT_PCH_GPIO=PP3V3_TBTLC_RTR=PPVDDIO_TBT_CLK

=PP3V3_TBTLC_FET PP3V3_TBTLCMIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUEVOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V05_S0_PCH_VCCADPLLMIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MM



PPVCORE_S0_CPU

VOLTAGE=1.05V


PPVCORE_S0_AXG

MAKE_BASE=TRUE

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_LDO

=PPVCORE_S0_CPU=PPCPUVCORE_S0_VSENSE

=PPVCORE_S0_AXG_REG

=PPVCORE_S0_CPU_VCCAXG=PPGFXVCORE_S0_VSENSE

MIN_LINE_WIDTH=0.6 MMPP1V5_S3_CPU_VCCDQ

MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.5VMAKE_BASE=TRUE

=PP1V5_S3_CPU_VCCDQ

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PP1V05_S0_CPU_VCCPQE

MIN_NECK_WIDTH=0.2 MM

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_TBTLC_FET

=PP1V05_TBTLC_RTR

PP1V05_TBTLC

VOLTAGE=1.05V


MAKE_BASE=TRUE

=PP1V05_TBTCIO_RTR

PP1V05_TBTCIO

MAKE_BASE=TRUE


VOLTAGE=1.05V

=PP1V05_TBTCIO_FET

=PP1V5_S3RS0_VMON

MAKE_BASE=TRUEVOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP1V05_SUS

=PP1V05_SUS_PCH_JTAG

=PP1V05_SUS_LDO

=PPCPUVCCIO_S0_REG

=PP1V05_S0_PCH=PP1V05_S0_PCH_VCCIO=PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCC_CORE=PP1V05_S0_VMON=PPVCCIO_S0_CPUIMVP=PP1V05_S0_PCH_VCCDIFFCLK

=PPVCCIO_S0_XDP=PPVCCIO_S0_SMC=PP1V05_S0_P1V05TBTFET

MIN_LINE_WIDTH=2 mm

VOLTAGE=0.75V

PP0V75_S0_DDRVTT

MAKE_BASE=TRUE


=PP0V75_S0_MEM_VTT_A=PP0V75_S0_MEM_VTT_B=PPVTT_S0_VTTCLAMP

MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm


PPVTTDDR_S3

=PPVCCSA_S0_VSENSE

PPVCCSA_S0_CPUMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM


=PP1V05_S0_PCH_VCCIO_SATA




PP1V8_S0_CPU_VCCPLL_R

VOLTAGE=1.05V


MAKE_BASE=TRUE

=PP3V3_S3_VREFMRGN

=PP3V3_S3_WLANISNS

=PPVIN_S3_DDRREG

=PPVIN_S5_HS_OTHER_ISNS

PP5V_S5

VOLTAGE=5VMAKE_BASE=TRUE


VOLTAGE=5VMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MM

MAKE_BASE=TRUE

PP5V_SUS

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5VMAKE_BASE=TRUE


MAKE_BASE=TRUE


VOLTAGE=5V

PP5V_S0


=PP5V_S5_LDO

=PP5V_S5_P5VSUSFET=PP5V_S5_TPAD

=PP5V_SUS_FET

=PP5V_SUS_PCH

=PP5V_S3_REG

=PP5V_S3_AUDIO_AMP

=PP5V_S3_MEMRESET

=PP5V_S3_DDRREG

=PP5V_S3_P5VS0FET=PP5V_S3_RTUSB=PP5V_S3_LIO_CONN

=PP5V_S0_FET

=PP5V_S0_BKL=PP5V_S0_CPUIMVP=PP5V_S0_CPUVCCIOS0=PP5V_S0_FAN

=PP5V_S0_LPCPLUS=PP5V_S0_VCCSA=PP5V_S0_PCH=PP5V_S0_VMON=PP5V_S0_KBDLED

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6MMPP3V42_G3H

MIN_NECK_WIDTH=0.2MMVOLTAGE=3.42V

VOLTAGE=3V

PPVRTC_G3HMIN_LINE_WIDTH=0.2 MMMIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

=PP3V42_G3H_REG

=PP3V3_S5_LPCPLUS

=PP3V42_G3H_CHGR=PP3V3_S5_SMC

=PP3V42_G3H_PWRCTL=PP3V42_G3H_SMBUS_SMC_BSA=PP3V42_G3H_SMCUSBMUX

=PPVBAT_G3H_SYSCLK=PP3V42_G3H_ONEWIRE

=PPVRTC_G3_PCH

=PPVRTC_G3_OUT

=PP18V5_DCIN_ISOL

=PPDCIN_S5_VSENSE=PPDCIN_S5_CHGR_ISOL

MAKE_BASE=TRUEVOLTAGE=18.5VMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MMPPDCIN_G3H_ISOL

PPDCIN_G3HMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMVOLTAGE=18.5VMAKE_BASE=TRUE

=PP18V5_DCIN_CONN

=PPDCIN_S5_CHGR

=PP3V42_G3H_TPAD=PPVIN_S5_SMCVREF

=PP5V_S5_P1V5DDRFET

=PP3V3_SUS_P1V05SUSLDO

=PP3V3_S5_REG

=PPVIN_SW_TBTBST

PPBUS_G3H



=PP3V3_S5_CPU_VCCDDR=PP3V3_S3_P3V3S3FET

=PP1V05_S0_CPU_VCCIO

=PP3V3_S3_DBGLEDS

=PP3V3_S3_USB_RESET

=PP3V3_S4_TBTAPWR

=PP3V3_S3_USBMUX=PP3V3_S3_LCD

MIN_LINE_WIDTH=0.50MM VOLTAGE=3.3VMAKE_BASE=TRUEMIN_NECK_WIDTH=0.20MM

PP3V3_S3

SYNC_DATE=07/29/2011

Power Aliases

SYNC_MASTER=K21_MLB

PP5V_S3

=PP3V3_S3_1V5S3ISNS

=PP3V3_S3_SMBUS_SMC_MGMT


=PP3V3_S4_FET

=PP3V3_S5_P3V3SUSFET

=PP1V05_S0_PCH_VCCSSC=PP1V05_S0_PCH_V_PROC_IO=PP1V05_S0_PCH_VCC_DMI


PP1V05_S0

=PP3V3_S3_USB_HUB

=PP3V3_S3_SMBUS_SMC_A_S3

PP3V3_S0MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.20MM

=PP3V3_S0_CPUVCCIOISNS=PP3V3_S0_AUDIO=PP3V3_S0_BKL_VDDIO=PP3V3_S0_HS_COMPUTING_ISNS=PP3V3_S0_CPUTHMSNS=PP3V3_S0_DP_DDC=PP3V3_S0_FAN=PP3V3_S0_P3V3TBTFET

=PP3V3_S0_FET

=PP3V3_S0_PCH=PP3V3_S0_P1V8S0

=PP3V3_S0_PCH_GPIO=PP3V3_S0_HS_OTHER_ISNS=PP3V3_S0_PCH_VCC3_3=PP3V3_S0_PCH_VCCADAC=PP3V3_S0_PWRCTL=PP3V3_S0_RSTBUF=PP3V3_S0_SB_PM=PP3V3_S0_SMBUS_PCH=PP3V3_S0_SMBUS_SMC_0_S0=PP3V3_S0_SMBUS_SMC_B_S0=PP3V3_S0_SMC

=PP3V3_S0_SSD=PP3V3_S0_HDDISNS=PP3V3_S0_VMON=PP3V3_S0_P1V5S0=PP3V3_S0_TBTPWRCTL=PP3V3_S0_P1V05S0LDO=PP3V3_S0_IMVPISNS=PP3V3_S0_XDP=PP3V3_S0_BKLTISNS=PP3V3_S0_SYSCLKGEN

=PP3V3_S0_SAISNS=PP3V3_S0_SATAMUX

=PP3V3_S0_3V3S0ISNS=PP3V3_S0_CPU_VCCIO_SEL=PP3V3_S0_PCH_VCC3_3_CLK=PP3V3_S0_PCH_STRAPS

051-9277

2.8.0

8 OF 109

7 OF 73

49

37

22 20

42

33

19

61

62

61

64

25

62

42

25

22 20

72 6

17

6

45

8

6

42

22 20

19 18 17 16

64

37

33

26

44

44

6

22 20

22

6

61

36 35 34

50

58

22 20

15 12

23

58 57

61

61

54

59

62

56

56 31

46

25 18

37

24

65

60

54

55

8

58

32 30 29

56

61

31

32 28 27

26

40 6

36 6

53

46

61

20

25 22 20

60

22 20 19

14

60

26 15 12 10

61

64

6

25

6

67 6

60

67 6

6

56

36

19 16

36 35 34

25

36 6

6

6

6

22

60

14 12 9

45

58

15 12 9

45

6 15 12

6 14 12

14 12

36

35

36 6

35

6 36

62

6

23

60

22 16

22 20

17

22 20

22 20

62

57

22 20 16

22 20

23

22 20

42

36

6

32

32

26

6

45

6

22 16

6

6

31

46

56

46

6

6

6

6

55

61

49

61

22

55

51

26

56

61

39

52 6

61

65

57

59

48 6

43 6

54

25 22

62

49

6

6

52

43 6

53

42 41

62

44

39

25

40 6

20 17 16

25

52

45

53

6

6 52 6

53

49 6

42

61

60

55

36

52 6

26

61

14 12 10 9

52

24

24

63

6

59

18 19 25 36

61

12

46

25

45

45

38

36

60

45

60

23

44

42

46

38

62

44

25

62

25

44

22

17 16

22 16

46

20 22

60

48

36

8

47

46

40 6

65

45

72 6

22

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

IN

OUT IN

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



860-1327

USB/SD Card Pogo

870-1938

DisplayPort Pogo

870-1938

CPU Heat Sink Mounting Bosses

Fan Boss

Digital Ground

SMC Aliases

Unused PGOOD signal

4x 860-1327

Unused SMC Signals

Unused PPT

TBT DP Ports

CPU signals

Plated Board Slot

860-1327

Unused SATA ODD Signals

X21 Boss

SSD PCIE Signals

860-1327

SSD Boss

Unused USB

LVDS Aliases

SATA Aliases

EMI I/O Pogo Pins

Can Slots

2x TBT chip

2x USB Connector

2x MDP Connector

2x TBT pin diodes 61

56

16

16

16

16

46 72

46 72

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.8H-SM

TH-NSP

SL-2.3X3.9-2.9X4.5

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.9H-SMSTDOFF-4.5OD1.9H-SMSTDOFF-4.5OD1.8H-SM

SMPOGO-2.0OD-3.6H-K86-K87

CRITICAL

2.2K1/20W

5%

201MF

5%

201

2.2K1/20W

MF1/20W

201

5%

MF

2.2K

NO STUFF

2.2K

201

1/20W5%

MF

NO STUFF

100K

MF201

5%1/20W

CRITICAL

0.01MF

0612-1

0.5%1W

TH-NSP

SL-1.1X0.4-1.4X0.7

TH-NSP

SL-1.1X0.4-1.4X0.7

TH-NSP

SL-1.1X0.45-1.4X0.75

41

41

18

18

18

18

18

18

18

18

18

18

18

18

34 70

34 70

34 70

34 70

16

16

16

16

16 69

16 69

16

16

16

16

16

16

16

16

16

16

16

9

9

6 38 66

6 38 66

38 66

38 66

9

9

0.0021%MF1W

CRITICAL

0612

7 7

46 72

46 72

201

10K5%1/20WMF

RAMCFG0:LRAMCFG1:L

10K

201MF1/20W5%

201

RAMCFG2:L

10K5%1/20WMF

10K5%

MF201

1/20W

RAMCFG3:L

201

5%1/20WMF

10K 10K

MF

5%

201

1/20W5%10K

201MF1/20W

10K

201MF1/20W5%

34 70

34 70

34 70

34 70

5%

MF201

10K

1/20W

16

16

34

SL-1.1X0.45-1.4X0.75

TH-NSP

SL-1.1X0.4-1.4X0.7

TH-NSP

TH-NSP

SL-1.1X0.4-1.4X0.7SL-1.1X0.4-1.4X0.7

TH-NSP

470K1%

MF201

1/20W

470K1%

1/20W

201MF

TH-NSP

SL-1.1X0.4-1.4X0.7

CRITICAL

GND

MIN_NECK_WIDTH=0.075MMVOLTAGE=0V

MIN_LINE_WIDTH=0.6MM

DPLL_REF_CLKN

MAKE_BASE=TRUEDPLL_REF_CLK_P

MEM_B_CLK_P<1>

MAKE_BASE=TRUETP_MEM_B_CLKN<1>

DPA_IG_DDC_CLK

LVDS_IG_PANEL_PWR

LVDS_IG_A_DATA_P<3>

LVDS_IG_B_DATA_N<0..3>

NC_USB3_EXTC_TX_PMAKE_BASE=TRUE NO_TEST=TRUE

NC_USB3_EXTC_RX_PMAKE_BASE=TRUE NO_TEST=TRUE

NC_PCIE_8_D2RN

NC_PCIE_6_D2RNNC_PCIE_5_D2RNNC_PCIE_8_D2RPNC_PCIE_7_D2RP

=PP3V3_S0_DP_DDC

DPB_IG_DDC_CLKMAKE_BASE=TRUE

DP_IG_D_CTRL_CLKMAKE_BASE=TRUE

TP_DP_IG_D_CTRL_DATA

MAKE_BASE=TRUEXDP_DC3_PCH_GPIO19_SATARDRVR_EN

DPLL_REF_CLKP

MLB_RAMCFG0

MLB_RAMCFG1

DPA_IG_DDC_DATA

TP_DP_IG_C_CTRL_DATATP_DP_IG_D_CTRL_CLK

TP_MEM_A_CLKP<1>MAKE_BASE=TRUE

TP_MEM_A_CLKN<1>MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2D_C_PMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_EXCARD_D2R_P

USB_EXTD_EHCI_N

USB3_EXTD_TX_N

USB3_EXTD_RX_N

MAKE_BASE=TRUETP_P1V5S3RS0_RAMP_DONE

NO_TEST=TRUENC_USB_EXTC_P

MAKE_BASE=TRUE

PCIE_FW_R2D_C_N

PCIE_FW_D2R_P

MEMVTT_ENMAKE_BASE=TRUE

USB_EXTC_N

IR_RX_OUT_RC

=PEG_D2R_P<1..0>

=PEG_R2D_C_P<1..0>

=PEG_D2R_N<1..0>

SATA_ODD_D2R_N

SATA_ODD_R2D_C_N

TBT_B_CONFIG1_BUF

TBT_B_D2R_N<1>

LVDS_IG_B_DATA_P<0..3>

LVDS_IG_A_DATA_N<3>

LVDS_IG_BKL_PWM

NC_USB_EXTD_EHCI_PMAKE_BASE=TRUE NO_TEST=TRUE

NC_PCIE_7_D2RN

DPA_IG_HPD

TBT_B_LSTX NC_TBT_B_LSTXMAKE_BASE=TRUE NO_TEST=TRUE

NO_TEST=TRUENC_TBT_B_D2R_N<1>

MAKE_BASE=TRUE

DP_TBTPB_HPDTBT_B_CONFIG2_RC

TBT_B_LSRX

MAKE_BASE=TRUETP_LVDS_IG_B_CLKN

NC_PCIE_CLK100M_EXCARD_NMAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_CLK100M_EXCARD_P

NO_TEST=TRUEMAKE_BASE=TRUENC_PEG_CLK100M_N

NO_TEST=TRUEMAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_D2R_P

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

PEG_CLK100M_P

PCIE_CLK100M_EXCARD_P

PEG_CLK100M_N

PCIE_CLK100M_EXCARD_N

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_EXCARD_R2D_C_N

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_FW_R2D_C_P

MAKE_BASE=TRUENC_PCIE_FW_D2R_P

NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_FW_R2D_C_N

MAKE_BASE=TRUENC_PCIE_FW_D2R_N

NO_TEST=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_ENET_R2D_C_P

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_ENET_R2D_C_N

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_ENET_D2R_P

PCIE_CLK100M_FW_P

NC_PCIE_CLK100M_FW_NMAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_CLK100M_FW_P

NO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_PCIE_CLK100M_ENET_P

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

MEM_A_CLK_P<1>MEM_A_CLK_N<1>

=PEG_R2D_C_N<1..0>

DP_TBTSNK1_ML_C_N<3..0>MAKE_BASE=TRUE

MAKE_BASE=TRUEPCIE_TBT_D2R_P<1>

LCD_BKLT_ENMAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_TBT_B_R2D_C_P<1>

TBT_B_D2R_P<0>

TBT_B_D2R_N<0>

DPB_IG_HPD

TBT_B_R2D_C_N<1>NO_TEST=TRUEMAKE_BASE=TRUE

NC_TBT_B_R2D_C_P<0>MAKE_BASE=TRUE

NC_TBT_B_R2D_C_N<0>NO_TEST=TRUE

TBT_B_R2D_C_P<1>

MAKE_BASE=TRUENC_DP_TBTPB_AUXCH_C_P

DP_TBTPB_AUXCH_C_N NC_DP_TBTPB_AUXCH_C_NMAKE_BASE=TRUE

NC_DP_TBTPB_ML_C_P<3>MAKE_BASE=TRUE

DP_TBTPB_ML_C_P<1> NC_DP_TBTPB_ML_C_P<1>MAKE_BASE=TRUE

DP_TBTPB_ML_C_N<1> NC_DP_TBTPB_ML_C_N<1>MAKE_BASE=TRUE

MAKE_BASE=TRUEDP_TBTSNK0_ML_C_N<3..0> TP_DP_IG_B_MLN<3..0>

TP_DP_IG_B_MLP<3..0>

TP_DP_IG_C_MLN<3..0>

MAKE_BASE=TRUEDP_TBTSNK1_AUXCH_C_N DPB_IG_AUX_CH_N

TP_DP_IG_C_MLP<3..0>

MAKE_BASE=TRUEDP_TBTSNK1_AUXCH_C_P

DPA_IG_AUX_CH_P

DP_TBTSNK0_HPDMAKE_BASE=TRUE

DP_TBTSNK1_HPDMAKE_BASE=TRUE

NO_TEST=TRUENC_SMC_SYS_LED

MAKE_BASE=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUELCD_IG_PWR_EN

MAKE_BASE=TRUEDP_IG_D_HPD

NO_TEST=TRUENC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUENC_LVDS_IG_B_DATAN<0..3>

MAKE_BASE=TRUE

TBT_B_R2D_C_P<0>

MAKE_BASE=TRUE NO_TEST=TRUENC_TBT_B_D2R_P<0>

NO_TEST=TRUEMAKE_BASE=TRUENC_TBT_B_D2R_N<0>

NC_TBT_B_D2R_P<1>NO_TEST=TRUEMAKE_BASE=TRUE

MAKE_BASE=TRUENC_TBT_B_R2D_C_N<1>

NO_TEST=TRUE

PCIE_SSD_R2D_C_N<1..0>MAKE_BASE=TRUE

=PPVIN_S5_HS_COMPUTING_ISNS =PPVIN_S5_HS_COMPUTING_ISNS_R

ISNS_HS_COMPUTING_N

ISNS_LCDBKLT_P=PPBUS_SW_BKLMAKE_BASE=TRUEVOLTAGE=12.6V

PPBUS_SW_BKLMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.375 MM

MAKE_BASE=TRUEPCIE_TBT_D2R_N<3>

SATA_ODD_R2D_C_P

DDRREG_PGOOD

MAKE_BASE=TRUEPCIE_SSD_R2D_C_P<1..0>

MAKE_BASE=TRUE NO_TEST=TRUENC_SATA_ODD_D2RP

NC_SATA_ODD_R2DCNNO_TEST=TRUEMAKE_BASE=TRUE

USB_EXTD_EHCI_P

USB3_EXTD_TX_P

USB3_EXTD_RX_P

USB3_EXTC_TX_P

TP_DDRREG_PGOODMAKE_BASE=TRUE

NC_PCIE_6_R2D_CNNC_PCIE_5_R2D_CN

NC_PCIE_5_D2RP

PCIE_TBT_D2R_N<2>MAKE_BASE=TRUE



PCIE_TBT_D2R_P<2>MAKE_BASE=TRUE PCIE_TBT_D2R_P<3>MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<1>MAKE_BASE=TRUE


PCIE_TBT_R2D_C_P<3>MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<0>MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<1>MAKE_BASE=TRUENC_PCIE_7_R2D_CP

NC_PCIE_5_R2D_CP

NC_PCIE_8_R2D_CNNC_PCIE_7_R2D_CN


USB3_EXTC_TX_N

P1V5S3RS0_RAMP_DONE

NC_PCIE_8_R2D_CP

NC_PCIE_6_D2RP


NC_PCIE_6_R2D_CP

NO_TEST=TRUEMAKE_BASE=TRUENC_USB3_EXTC_TX_N

NO_TEST=TRUENC_USB3_EXTD_RX_P

MAKE_BASE=TRUE

NO_TEST=TRUENC_USB3_EXTD_RX_N

MAKE_BASE=TRUE

NO_TEST=TRUENC_USB3_EXTD_TX_N

MAKE_BASE=TRUE

NO_TEST=TRUENC_USB_EXTD_EHCI_N

MAKE_BASE=TRUE

NO_TEST=TRUENC_IR_RX_OUT_RC

MAKE_BASE=TRUE

LVDS_IG_B_CLK_P

MEM_B_CLK_N<1>

USB3_EXTC_RX_P

TP_MEM_B_CLKP<1>MAKE_BASE=TRUE

ENET_LOW_PWR_PCH

SATARDRVR_EN

TP_PCH_CLKOUT_DPN

SMC_SYS_LED

NO_TEST=TRUEMAKE_BASE=TRUENC_SATA_ODD_D2RN

TP_DP_IG_D_HPD

NO_TEST=TRUENC_PEG_CLK100M_P

MAKE_BASE=TRUE

NO_TEST=TRUEMAKE_BASE=TRUENC_PCIE_ENET_D2R_N

TP_DP_IG_C_CTRL_CLK

DP_TBTSNK0_AUXCH_C_NMAKE_BASE=TRUE

PPBUS_SW_LCDBKLT_PWRMAKE_BASE=TRUE

DP_TBTSNK1_ML_C_P<3..0>MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_P<3..0>MAKE_BASE=TRUE

=PP3V3_S0_DP_DDC

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML_C_N<3>

DP_TBTPB_AUXCH_C_P

DP_IG_D_CTRL_DATAMAKE_BASE=TRUE

PCIE_FW_R2D_C_P

PCIE_EXCARD_D2R_N

PCIE_SSD_D2R_N<1..0>MAKE_BASE=TRUE

MAKE_BASE=TRUEPCIE_SSD_D2R_P<1..0>

SATA_ODD_D2R_P

TP_PCH_CLKOUT_DPP

DPLL_REF_CLK_NMAKE_BASE=TRUE

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCHMAKE_BASE=TRUE

DP_TBTSNK0_DDC_CLKMAKE_BASE=TRUE

MAKE_BASE=TRUEDP_TBTSNK0_DDC_DATA

NO_TEST=TRUENC_USB3_EXTD_TX_P

MAKE_BASE=TRUE TP_LVDS_IG_B_CLKPMAKE_BASE=TRUE

TBT_B_CIO_SEL

TBT_B_D2R_P<1>

ISNS_HS_COMPUTING_P

TBT_B_R2D_C_N<0>

MAKE_BASE=TRUENC_DP_TBTPB_ML_C_N<3>

DPB_IG_AUX_CH_P

DPA_IG_AUX_CH_N

DP_TBTSNK0_AUXCH_C_PMAKE_BASE=TRUE

MAKE_BASE=TRUEPCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_P<2>MAKE_BASE=TRUE=DDRVTT_EN

MAKE_BASE=TRUEDPB_IG_DDC_DATA

ISNS_LCDBKLT_N

MLB_RAMCFG2

LVDS_IG_B_CLK_N

LVDS_IG_BKL_ON

MAKE_BASE=TRUELCD_BKLT_PWM

MAKE_BASE=TRUE NO_TEST=TRUENC_LVDS_IG_A_DATAP<3>

MLB_RAMCFG3

USB3_EXTC_RX_N NC_USB3_EXTC_RX_NMAKE_BASE=TRUE NO_TEST=TRUE

MAKE_BASE=TRUE NO_TEST=TRUENC_USB_EXTC_N

USB_EXTC_P

NO_TEST=TRUEMAKE_BASE=TRUENC_SATA_ODD_R2DCP

PCIE_CLK100M_FW_N

PCIE_FW_D2R_N

SYNC_DATE=11/10/2011SYNC_MASTER=J13_MLB_NON_POR

Signal Aliases

SMPOGO-2.0OD-3.6H-K86-K87

Z0910

1

Z0912

1

SL09001

Z0913

1

Z0911

1

Z0915

1

Z0914

1

Z0905

1

ZS0905

1

R09201

2

R09211

2

R09221

2

R09231

2

R09091

2

R0910

1 23 4

SL09011

SL09021

SL09051

R0954

1234

R09531

2

R09521

2

R09511

2

R09501

2

R09171

2

R09181

2

R09191

2

R09141

2

R09161

2

SL09071

SL09031

SL09041

SL09081

R09251

2

R09241

2

SL09061

ZS0906

1

051-9277

2.8.0

9 OF 109

8 OF 73

10 66

11 67 17

17

16

16

16

16

16

7 8

17

17

16 23

10 66

19

19

17

17

26

34

17

16

17

34

34

34

6

11 67

11 67

34 69

34 69

65

17

34 70

34 70

34 70

34 69 17

17

17

34 69 17

17

34 69

17

34

34

63

65

34 69

16

16

16

34 69

34 69

34 69

34 69

34 69

34 69

34 69

34 69

34 69

34 69

16

16

16

16

34 69

16

16

34 69

16

11 67

19

16

16

17

34 69

65

34 69

34 69

7 8

34 70

34 70

34 70

16

19 23

64

64

6

34

17

17

34 69

34 69

34 69 26 56

17

19

17

65

19

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

NC

NCNCNCNC

NCNCNCNCNCNCNCNCNCNC

NC

NCNC

NC

NC

NC

NC

NC

NCNCNCNC

NCNCNC

EDP_TX_3

EDP_TX_0EDP_TX_1EDP_TX_2

EDP_TX_2*EDP_TX_3*

EDP_TX_0*EDP_TX_1*

EDP_AUXEDP_AUX*

EDP_COMPIO

EDP_HPD

EDP_ICOMPO

FDI1_LSYNC

DMI_TX_3*

FDI0_LSYNC

FDI0_TX_3

FDI1_TX_1FDI1_TX_0

FDI1_TX_2FDI1_TX_3

FDI0_FSYNCFDI1_FSYNC

FDI_INT

FDI1_TX_3*FDI1_TX_2*

FDI0_TX_1FDI0_TX_0

FDI0_TX_2

FDI1_TX_1*

FDI0_TX_3*

FDI1_TX_0*

FDI0_TX_2*FDI0_TX_1*

DMI_TX_1*DMI_TX_2*

DMI_TX_0

DMI_TX_2DMI_TX_1

DMI_TX_3

FDI0_TX_0*

DMI_RX_2*

DMI_RX_0DMI_RX_1DMI_RX_2DMI_RX_3

DMI_TX_0*

DMI_RX_3*

DMI_RX_1*DMI_RX_0* PEG_ICOMPI

PEG_ICOMPOPEG_RCOMPO

PEG_RX_2*

PEG_RX_0*PEG_RX_1*

PEG_RX_3*PEG_RX_4*PEG_RX_5*

PEG_RX_7*PEG_RX_6*

PEG_RX_8*PEG_RX_9*

PEG_RX_10*

PEG_RX_12*PEG_RX_11*

PEG_RX_14*PEG_RX_13*

PEG_RX_15*

PEG_RX_0PEG_RX_1

PEG_RX_3PEG_RX_2

PEG_RX_4

PEG_RX_6PEG_RX_5

PEG_RX_7PEG_RX_8

PEG_RX_10PEG_RX_9

PEG_RX_11PEG_RX_12PEG_RX_13PEG_RX_14PEG_RX_15

PEG_TX_1*PEG_TX_2*

PEG_TX_0*

PEG_TX_3*PEG_TX_4*PEG_TX_5*

PEG_TX_7*PEG_TX_6*

PEG_TX_10*

PEG_TX_8*PEG_TX_9*

PEG_TX_11*PEG_TX_12*PEG_TX_13*PEG_TX_14*PEG_TX_15*

PEG_TX_1PEG_TX_0

PEG_TX_2PEG_TX_3PEG_TX_4

PEG_TX_6PEG_TX_5

PEG_TX_7PEG_TX_8PEG_TX_9PEG_TX_10PEG_TX_11PEG_TX_12

PEG_TX_14PEG_TX_13

PEG_TX_15

(1 OF 9)

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

NCNC

RSVD_26RSVD_27

RSVD_25

RSVD_23RSVD_24

RSVD_22RSVD_21

RSVD_19RSVD_18

RSVD_16RSVD_17

RSVD_15RSVD_14RSVD_13RSVD_12

DC_TEST_BG1

DC_TEST_BD1DC_TEST_BE1

DC_TEST_BG3DC_TEST_BE3

DC_TEST_BG4DC_TEST_BG58DC_TEST_BG59

DC_TEST_BE59DC_TEST_BG61

DC_TEST_BD61DC_TEST_BE61

DC_TEST_D61

DC_TEST_A61DC_TEST_C61

DC_TEST_A59DC_TEST_C59

DC_TEST_A58

DC_TEST_D3DC_TEST_D1

DC_TEST_C4DC_TEST_A4

RSVD_45

RSVD_44

RSVD_41

RSVD_43RSVD_42

RSVD_39RSVD_40

RSVD_38

RSVD_36

RSVD_33

RSVD_31RSVD_32

RSVD_30CFG_3CFG_2CFG_1CFG_0

CFG_9CFG_8CFG_7CFG_6

CFG_14

CFG_12

CFG_10

CFG_16CFG_17

VCC_VAL_SENSE

RSVD_8

RSVD_7RSVD_6

CFG_15

CFG_13

CFG_11

CFG_5CFG_4

VSS_VAL_SENSE

VAXG_VAL_SENSE

VCC_DIE_SENSE

VSSAXG_VAL_SENSE

RSVD_11

RSVD_9RSVD_10

RSVD_20

RSVD_37

RSVD_35RSVD_34

SB_DIMM_VREFDQSA_DIMM_VREFDQ

RESERVED(5 OF 9)

NCNCNC

NC

OUT

OUT

OUT

OUT

S

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Intel Doc 467283 ChiefRiver Platform design guild rev0.71 section 2.2.12 recommendation.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating

Note. VOLTAGE=1.25V

Note. VOLTAGE=0V

FOR IVYBRIDGE PROCESSOR

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

This signal can be left as no-connect if entire eDP interface is disabled.If HPD is disabled while eDP interface is still enabled,

(refer to latest Processor EDS for DC specifications).

Rise/Fall time <6ns CR SFF Intel doc #460452

connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

this alnalog sense due to accuracy concern.NOTE: Intel does not recommend to use

Note. VOLTAGE=0V

to low voltage signals for the processor

shared with other interfaces.

to convert the active high signal from Embedded DisplayPort sink deviceTherefore, an inverting level shifter is required on the motherboardNOTE: The EDP_HPD processor input is a low voltage active low signal.

even if internal Graphics is disabled since they are

Note. VOLTAGE=1.05V

NOTE: Intel validation sense lines per doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

These can be Placed close to J2500 and Only for debug access

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

8

6

6

6

6

6

6

6

6

6

6

6

6

6

6

8

8

6

6

6

8

6

6

6

6

6

6

6

6

6

6

6

8

6

6

6

8

6

6

6

6

6

6

8

6

6

8

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

6

9 23 66

9 23 66

9 23 66

9 23 66

9 23 66

9 23 66

9 23 66

9 23 66

23 66

23 66

23 66

23 66

23 66

23 66

23 66

23 66

9 23

23

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

17 66

2C-35WIVY-BRIDGE

BGA

OMIT_TABLECRITICAL

BGA

2C-35W

OMIT_TABLECRITICAL

IVY-BRIDGE

47 72

47 72

31

31

PLACE_NEAR=U1000.AG11:12.7MM

5%1K1/20W

201MF

PLACE_NEAR=U1000.G3:12.7MM

24.9

1%1/20WMF201

MF201

1/20W1%

24.9PLACE_NEAR=U1000.AF3:12.7MM

2N7002TXGSOT-523-3EDP:YES

1K

NOSTUFF

5%

MF-LF

1/16W

402

5%

1K

NOSTUFF

MF-LF

1/16W

402

NOSTUFF

1K5%

MF-LF

402

1/16W

5%

1K

MF-LF

1/16W

EDP:YES

402

5%

NOSTUFF

MF-LF

1/16W

1K

402

1/16W

MF-LF

5%

1K

402

NOSTUFF

1/16W

402

MF-LF

1K5%

NOSTUFF

402

5%

1K

1/16W

MF-LF

NOSTUFF

PLACE_SIDE=BOTTOMPLACE_NEAR=U1000.H45:50.8MM

49.9

1/16W

402

1%

MF-LF

NOSTUFF

PLACE_NEAR=U1000.H43:50.8MMPLACE_SIDE=BOTTOM

MF-LF

NOSTUFF

1%

402

1/16W

49.9

1%

PLACE_NEAR=U1000.K45:50.8MM

NOSTUFF

PLACE_SIDE=BOTTOM

MF-LF402

1/16W

49.9

1/16W

PLACE_NEAR=U1000.K43:50.8MM

1%

NOSTUFF

MF-LF402

49.9

PLACE_SIDE=BOTTOM

402

NOSTUFF

1/16W

MF-LF

5%

1K


CPU DMI/PEG/FDI/RSVD

SYNC_MASTER=J13_MLB_NON_POR

CPU_CFG<16>

CPU_PEG_COMP

=PEG_D2R_N<2>

=PEG_D2R_P<4>

=PEG_D2R_P<15>

TP_EDP_TX_P<2>

=PEG_R2D_C_P<6>

=PEG_R2D_C_P<9>

=PEG_R2D_C_N<10>

CPU_VCC_VALSENSE_P

CPU_CFG<4>CPU_CFG<5>

=PEG_D2R_N<9>

DP_INT_AUX_CH_P

CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_N

CPU_CFG<0>

CPU_CFG<3>

CPU_CFG<2>CPU_CFG<4>CPU_CFG<5>CPU_CFG<6>CPU_CFG<7>

DP_INT_HPD

EDP_HPD_L

=PEG_D2R_N<14>

=PEG_D2R_P<8>

FDI_DATA_N<7>

FDI_DATA_P<5>FDI_DATA_P<6>

PPCPU_MEM_VREFDQ_A




=PEG_R2D_C_P<14>

CPU_DC_TEST_C61_A61

=PEG_R2D_C_P<15>


=PEG_D2R_P<14>


=PEG_D2R_P<7>

=PEG_D2R_P<5>

CPU_CFG<6>

CPU_CFG<0>

=PEG_R2D_C_P<1>

=PEG_D2R_N<6>=PEG_D2R_N<5>

CPU_THERMD_NCPU_THERMD_P

=PEG_D2R_P<10>=PEG_D2R_P<11>=PEG_D2R_P<12>

CPU_DC_TEST_C59_A59

=PEG_D2R_P<13>

FDI_INT

FDI_FSYNC<0>

DMI_S2N_N<0>

=PEG_R2D_C_P<2>

CPU_CFG<17>

CPU_DC_TEST_C4_BE1_BG1

TP_CPU_DC_TEST_BD1

CPU_DC_TEST_C4_BE3_BG3TP_CPU_DC_TEST_BG4TP_CPU_DC_TEST_BG58

CPU_DC_TEST_BG59_BG61

CPU_DC_TEST_BE59_BE61TP_CPU_DC_TEST_BD61TP_CPU_DC_TEST_D61

TP_CPU_DC_TEST_D1

TP_CPU_DC_TEST_A4

CPU_CFG<3>CPU_CFG<2>CPU_CFG<1>

CPU_CFG<9>CPU_CFG<8>CPU_CFG<7>

CPU_CFG<14>

CPU_CFG<12>

CPU_CFG<10>


CPU_CFG<13>

CPU_CFG<11>

TP_CPU_VCC_DIE_SENSE

FDI_LSYNC<1>

=PEG_R2D_C_P<13>

=PEG_R2D_C_P<7>

=PEG_R2D_C_P<3>

=PEG_R2D_C_N<9>=PEG_R2D_C_N<8>


=PEG_R2D_C_N<5>=PEG_R2D_C_N<4>=PEG_R2D_C_N<3>

=PEG_R2D_C_N<0>


=PEG_D2R_P<9>

=PEG_D2R_P<6>

=PEG_D2R_P<2>=PEG_D2R_P<3>

=PEG_D2R_P<1>

=PEG_D2R_N<15>





DMI_S2N_N<1>

DMI_S2N_N<3>

DMI_N2S_N<0>

DMI_S2N_P<3>DMI_S2N_P<2>DMI_S2N_P<1>DMI_S2N_P<0>

DMI_S2N_N<2>

FDI_DATA_N<0>

DMI_N2S_P<3>

DMI_N2S_P<1>DMI_N2S_P<2>

DMI_N2S_P<0>

DMI_N2S_N<2>DMI_N2S_N<1>

FDI_DATA_N<1>FDI_DATA_N<2>FDI_DATA_N<3>

FDI_DATA_P<2>


FDI_DATA_N<6>

FDI_FSYNC<1>

FDI_DATA_P<4>

FDI_DATA_P<3>

FDI_LSYNC<0>

FDI_DATA_N<4>

=PEG_D2R_P<0>

=PEG_D2R_N<11>

PPCPU_MEM_VREFDQ_B

VOLTAGE=0.75VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MM

=PEG_R2D_C_P<10>

EDP_HPD_L

EDP_COMP

TP_EDP_TX_P<3>

TP_EDP_TX_P<1>DP_INT_ML_P<0>

TP_EDP_TX_N<3>TP_EDP_TX_N<2>

DP_INT_AUX_CH_N

DP_INT_ML_N<0>TP_EDP_TX_N<1>

=PEG_R2D_C_P<11>

DMI_N2S_N<3>

TP_CPU_DC_TEST_A58

CPU_DC_TEST_C4_D3

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<5>

FDI_DATA_P<7>

FDI_DATA_N<5>

CPU_AXG_VALSENSE_P

=PPVCORE_S0_CPU_VCCAXG

=PPVCORE_S0_CPU

=PEG_D2R_N<10>

=PEG_R2D_C_N<11>=PEG_R2D_C_N<12>=PEG_R2D_C_N<13>=PEG_R2D_C_N<14>=PEG_R2D_C_N<15>

=PEG_R2D_C_P<0>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<8>

CPU_CFG<1>

U1000

N3

M2

P7

P6

P3

P1

P11

P10

K3

K1

M7

M8

P4

N4

T3

R2

AF4AG4

AF3

AG11

AD2

AC1

AC3

AA4

AC4

AE10

AE11

AE6

AE7

AA11

AA10

U6

U7

W10

W11

W3

W1

AA7

AA6

AC12

AG8

W7

W6

T4

V4

AA3

Y2

AC8

AC9

U11

G3G1G4

K22

H22

K19

J21

F8

G8

C8

A8

C5

B6

H6

H8

F6

E5

K6

K7

C21

B22

D19

D21

C19

A19

D16

D17

C13

B14

D12

D13

C11

A11

C9

B10

F22

G22

A23

C23

K13

J14

G13

H13

K10

M10

G10

F10

D8

D9

K4

J4

D24

D23

E21

F21

G19

H19

B18

C17

K17

K15

G17

F17

E14

F14

C15

A15

U1000

B50C51

K49K53F53G53L51F51D52L53

B54D53A51C53C55H49A55H51

A4

A58A59

A61

BD1

BD61

BE1

BE3

BE59BE61

BG1

BG3BG4BG58BG59BG61

C4

C59

C61

D1D3

D61

AG13AH2

AM14AM15

AT21

AT49

AU19AU21

AV19

AY21

AY22

BA19

BA22

BB19BB21

BD21BD22BD25BD26

BE22

BE24

BE26BF23

BG22

BG26

H48

K24

K48

L42L45L47

M13M14

N42

N50

P13

U14W14

BE7BG7

H45

F48

H43K43

K45

R10311

2

R10101 2

R10301 2

Q1031

3

1

2

R10471

2

R10461

2

R10451

2

R10441

2

R10421

2

R10431

2

R10411

2

R10401

2

R10701

2

R10641

2

R10711

2

R10651

2

R10491

2

051-9277

2.8.0

10 OF 109

9 OF 73

9 23

66

6

63 66

9 23 66

9 23 66

9 23 66

9 23 66

9 23 66

9 23 66

9 23 66

63

9

7 9 10 12 14

7 9 10 12 14

7 9 10 12 14

9

66

6

6

63 66

6

6

63 66

63 66

6

7 12 15

7 12 14

9 23 66

IN

IN

IN

IN

OUT

OUT

BI

BI

BI

BI

BI

IN

BI

BI

BI

NC

SM_RCOMP_2SM_RCOMP_1SM_RCOMP_0

SM_DRAMRST*

BCLK_ITPBCLK_ITP*

DPLL_REF_CLK*DPLL_REF_CLK

BCLK*BCLK

RESET*

SM_DRAMPWROK

UNCOREPWRGOOD

PM_SYNC

PROC_SELECT*

PROC_DETECT*

PREQ*

TMSTRST*

TDITDO

DBR*

BPM_0*BPM_1*BPM_2*BPM_3*BPM_4*BPM_5*BPM_6*BPM_7*

TCK

PRDY*

THERMTRIP*

CATERR*

PROCHOT*

PECI

(2 OF 9)

CLOCKS

THERMAL

PWR MGMT

JTAG & BPM

DDR3 MISC

IN

OUT

OUT

BI

OUT

IN

IN

OUT

IN

BI

IN

IN

IN

IN

OUT

IN

IN

Apple Inc.


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(IPU)(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)(IPU)(IPU)(IPU)(IPU)(IPU)

Intel Doc 460452 ChiefRiver SFF DG rev1.0 section 2.7.11 recommendation R1115.

16 66

23 66

23 66

23 66

23 66

23 25 66

23 66

23 66

23 66

23 66

23 66

16 66

23 66

23 66

23 66

BGA2C-35W

IVY-BRIDGE

OMIT_TABLECRITICAL

201MF1/20W5%1K

NOSTUFFNOSTUFF

515%1/20WMF201

1K5%

1/20WMF201

NOSTUFF

PLACE_NEAR=U1000.B46:12.7MM

5%1/20WMF201

10K

8 66

NOSTUFF

201

1%4.99K

MF1/20W

PLACE_NEAR=U1000.BG43:12.7MM

201

2001/20WMF

1%

PLACE_NEAR=U1000.BE43:12.7MM

25.5

MF201

1/20W1%

19

41 66

19 42 66

19 42 66

19 23 66

17 66

26

16 66

PLACE_NEAR=U1000.BE45:12.7MM

130

201MF

1/20W1%

201MF1/20W5%62

56

5%1/20WMF201

PLACE_NEAR=R1121.2:1MM

201MF

1/20W1%

200

41 42 57 66

PLACE_NEAR=U1000.BF44:12.7MM

201MF1/20W1%140

201

1/20WMF

1%

43.2201MF

1/20W1%75

17 26 66

8 66

23 25

16 66

23 66

23 66

23 66

CPU CLOCK/MISC/JTAG

SYNC_MASTER=J30_MLB SYNC_DATE=07/27/2011

XDP_CPU_PRDY_L

XDP_CPU_TCK

XDP_BPM_L<7>XDP_BPM_L<6>XDP_BPM_L<5>XDP_BPM_L<4>XDP_BPM_L<3>XDP_BPM_L<2>XDP_BPM_L<1>XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TDOXDP_CPU_TDI

XDP_CPU_TRST_LXDP_CPU_TMS

XDP_CPU_PREQ_L

DMI_CLK100M_CPU_PDMI_CLK100M_CPU_N

DPLL_REF_CLKPDPLL_REF_CLKN

ITPCPU_CLK100M_NITPCPU_CLK100M_P

CPU_PECI

CPU_CATERR_L

PM_THRMTRIP_L

=MEM_RESET_L

CPU_PROCHOT_R_L

CPU_PROC_SEL_L

PM_SYNC

CPU_SM_RCOMP<0>

PLT_RESET_LS1V1_L


CPU_RESET_L


CPU_PROCHOT_L

PM_MEM_PWRGD


CPU_PWRGD

CPU_SM_RCOMP<2>CPU_SM_RCOMP<1>

PM_MEM_PWRGD_R

U1000

J3H2

N59N58

G58E55E59G55G59H60J59J61

C49

K58

AG3AG1

A48

C48

N53N55

C57

F49

C45

D44

BE45

AT30

BF44BE43BG43

L56

M60L59

D45L55J58

B46

R11021

2

R11041

2

R11001

2

R11111

2

R11151

2

R11141

2

R11131

2

R11211 2

R11011

2

R11031 2

R11201

2

R11121

2

R11251 2

R11261

2

051-9277

2.8.0

11 OF 109

10 OF 73

66

7 9 10 12 14

7 12 15 26

7 9 10 12 14

66

66

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

SA_MA_14SA_MA_15

SA_MA_12SA_MA_13

SA_MA_11

SA_MA_9SA_MA_10

SA_MA_8SA_MA_7SA_MA_6SA_MA_5SA_MA_4SA_MA_3SA_MA_2SA_MA_1SA_MA_0

SA_DQS_7

SA_DQS_5SA_DQS_6

SA_DQS_3SA_DQS_4

SA_DQS_2

SA_DQS_0SA_DQS_1

SA_DQS_7*SA_DQS_6*SA_DQS_5*SA_DQS_4*SA_DQS_3*SA_DQS_2*

SA_DQS_0*SA_DQS_1*

SA_ODT_1SA_ODT_0

SA_CS_1*SA_CS_0*

SA_CKE_1

SA_CK_1*SA_CK_1

SA_CKE_0

SA_CK_0*SA_CK_0

SA_WE*SA_RAS*SA_CAS*

SA_BS_0SA_BS_1SA_BS_2

SA_DQ_62SA_DQ_63

SA_DQ_61SA_DQ_60SA_DQ_59SA_DQ_58SA_DQ_57SA_DQ_56SA_DQ_55SA_DQ_54SA_DQ_53SA_DQ_52

SA_DQ_50SA_DQ_51

SA_DQ_49SA_DQ_48SA_DQ_47SA_DQ_46SA_DQ_45SA_DQ_44

SA_DQ_42SA_DQ_43

SA_DQ_41

SA_DQ_39SA_DQ_40

SA_DQ_38SA_DQ_37SA_DQ_36

SA_DQ_34SA_DQ_35

SA_DQ_31

SA_DQ_33SA_DQ_32

SA_DQ_29SA_DQ_30

SA_DQ_26

SA_DQ_28SA_DQ_27

SA_DQ_24SA_DQ_25


SA_DQ_19SA_DQ_20



SA_DQ_11SA_DQ_12

SA_DQ_9SA_DQ_10

SA_DQ_8SA_DQ_7SA_DQ_6SA_DQ_5SA_DQ_4SA_DQ_3SA_DQ_2SA_DQ_1SA_DQ_0

(3 OF 9)

MEMORY CHANNEL A

SB_MA_15SB_MA_14

SB_MA_12SB_MA_13

SB_MA_11SB_MA_10SB_MA_9

SB_MA_7SB_MA_8

SB_MA_6SB_MA_5SB_MA_4SB_MA_3SB_MA_2SB_MA_1SB_MA_0

SB_DQS_7SB_DQS_6SB_DQS_5SB_DQS_4SB_DQS_3SB_DQS_2SB_DQS_1SB_DQS_0

SB_DQS_7*SB_DQS_6*SB_DQS_5*SB_DQS_4*SB_DQS_3*SB_DQS_2*SB_DQS_1*SB_DQS_0*

SB_ODT_0SB_ODT_1

SB_CS_1*SB_CS_0*

SB_CKE_1

SB_CK_1SB_CK_1*

SB_CK_0*

SB_CKE_0

SB_CK_0

SB_DQ_37SB_DQ_36

SB_DQ_34SB_DQ_35

SB_DQ_33

SB_DQ_31SB_DQ_32

SB_DQ_30SB_DQ_29

SB_DQ_26SB_DQ_27SB_DQ_28

SB_DQ_24SB_DQ_25


SB_DQ_20SB_DQ_19SB_DQ_18SB_DQ_17SB_DQ_16SB_DQ_15SB_DQ_14SB_DQ_13SB_DQ_12SB_DQ_11SB_DQ_10

SB_DQ_8SB_DQ_9

SB_DQ_7SB_DQ_6

SB_DQ_4SB_DQ_5

SB_DQ_3SB_DQ_2SB_DQ_1SB_DQ_0

SB_DQ_39SB_DQ_38


SB_DQ_44SB_DQ_43

SB_DQ_46SB_DQ_45

SB_DQ_47

SB_DQ_49SB_DQ_48

SB_DQ_51SB_DQ_50

SB_DQ_52

SB_DQ_54SB_DQ_53

SB_DQ_56SB_DQ_55

SB_DQ_57

SB_DQ_59SB_DQ_58

SB_DQ_61SB_DQ_60

SB_DQ_62

SB_BS_0

SB_DQ_63

SB_BS_2SB_BS_1

SB_RAS*SB_CAS*

SB_WE*

(4 OF 9)

MEMORY CHANNEL B

Apple Inc.


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27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

27 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

28 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

29 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

30 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

27 28 32 67

27 28 32 67

27 28 32 67

8 67

8 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 67

27 67

27 67

27 67

28 67

28 67

28 67

28 67

27 67

27 67

27 67

27 67

28 67

28 67

28 67

28 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

27 28 32 67

29 30 32 67

29 30 32 67

29 30 32 67

8 67

8 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 67

29 67

29 67

29 67

30 67

30 67

30 67

30 67

29 67

29 67

29 67

29 67

30 67

30 67

30 67

30 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

29 30 32 67

2C-35W

IVY-BRIDGE

BGA

OMIT_TABLECRITICAL

BGA

IVY-BRIDGE

2C-35W

OMIT_TABLECRITICAL

CPU DDR3 INTERFACES


MEM_A_DQ<3>

MEM_A_CLK_P<0>

MEM_B_A<15>MEM_B_A<14>


MEM_B_A<11>MEM_B_A<10>MEM_B_A<9>


MEM_B_A<6>MEM_B_A<5>MEM_B_A<4>MEM_B_A<3>MEM_B_A<2>MEM_B_A<1>MEM_B_A<0>

MEM_B_DQS_P<7>MEM_B_DQS_P<6>MEM_B_DQS_P<5>MEM_B_DQS_P<4>MEM_B_DQS_P<3>MEM_B_DQS_P<2>MEM_B_DQS_P<1>MEM_B_DQS_P<0>

MEM_B_DQS_N<7>MEM_B_DQS_N<6>MEM_B_DQS_N<5>MEM_B_DQS_N<4>MEM_B_DQS_N<3>MEM_B_DQS_N<2>MEM_B_DQS_N<1>MEM_B_DQS_N<0>

MEM_B_ODT<0>MEM_B_ODT<1>

MEM_B_CS_L<1>MEM_B_CS_L<0>

MEM_B_CKE<1>

MEM_B_CLK_P<1>MEM_B_CLK_N<1>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_DQ<37>MEM_B_DQ<36>


MEM_B_DQ<33>



MEM_B_DQ<26>MEM_B_DQ<27>MEM_B_DQ<28>



MEM_B_DQ<20>MEM_B_DQ<19>MEM_B_DQ<18>MEM_B_DQ<17>MEM_B_DQ<16>MEM_B_DQ<15>MEM_B_DQ<14>MEM_B_DQ<13>MEM_B_DQ<12>MEM_B_DQ<11>MEM_B_DQ<10>




MEM_B_DQ<3>MEM_B_DQ<2>MEM_B_DQ<1>MEM_B_DQ<0>





MEM_B_DQ<47>



MEM_B_DQ<52>



MEM_B_DQ<57>



MEM_B_DQ<62>

MEM_B_BA<0>

MEM_B_DQ<63>

MEM_B_BA<2>MEM_B_BA<1>

MEM_B_RAS_LMEM_B_CAS_L

MEM_B_WE_L

MEM_A_A<14>MEM_A_A<15>


MEM_A_A<11>


MEM_A_A<8>MEM_A_A<7>MEM_A_A<6>MEM_A_A<5>MEM_A_A<4>MEM_A_A<3>MEM_A_A<2>MEM_A_A<1>MEM_A_A<0>

MEM_A_DQS_P<7>

MEM_A_DQS_P<5>MEM_A_DQS_P<6>


MEM_A_DQS_P<2>


MEM_A_DQS_N<7>MEM_A_DQS_N<6>MEM_A_DQS_N<5>MEM_A_DQS_N<4>MEM_A_DQS_N<3>MEM_A_DQS_N<2>

MEM_A_DQS_N<0>MEM_A_DQS_N<1>

MEM_A_ODT<1>MEM_A_ODT<0>

MEM_A_CS_L<1>MEM_A_CS_L<0>

MEM_A_CKE<1>

MEM_A_CLK_N<1>MEM_A_CLK_P<1>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_WE_LMEM_A_RAS_LMEM_A_CAS_L

MEM_A_BA<0>MEM_A_BA<1>MEM_A_BA<2>

MEM_A_DQ<62>MEM_A_DQ<63>

MEM_A_DQ<61>MEM_A_DQ<60>MEM_A_DQ<59>MEM_A_DQ<58>MEM_A_DQ<57>MEM_A_DQ<56>MEM_A_DQ<55>MEM_A_DQ<54>MEM_A_DQ<53>MEM_A_DQ<52>


MEM_A_DQ<49>MEM_A_DQ<48>MEM_A_DQ<47>MEM_A_DQ<46>MEM_A_DQ<45>MEM_A_DQ<44>


MEM_A_DQ<41>


MEM_A_DQ<38>MEM_A_DQ<37>MEM_A_DQ<36>


MEM_A_DQ<31>



MEM_A_DQ<26>









MEM_A_DQ<8>MEM_A_DQ<7>MEM_A_DQ<6>MEM_A_DQ<5>MEM_A_DQ<4>

MEM_A_DQ<2>MEM_A_DQ<1>MEM_A_DQ<0> U1000

BD37BF36BA28

BE39

AU36AV36

AT40AU40

AY26

BB26

BB40BC41

AG6AJ6

AU6AV9AR6AP8

AT13AU13BC7BB7

BA13BB11

AP11

BA7BA9BB9

AY13AV14AR14AY17AR19BA14AU14

AL6

BB14BB17BA45AR43AW48BC48BC45AR45AT48AY48

AJ10

BA49AV49BB51AY53BB49AU49BA53BB55BA55AV56

AJ8

AP50AP53AV54AT54AP56AP52AN57AN53AG56AG53

AL8

AN55AN52AG55AK56

AL7AR11AP6

AJ11

AL11

AR10

AR8

AY11

AV11

AU17

AT17

AW45

AV45

AV51

AY51

AT56

AT55

AK54

AK55

BG35BB34

BE37BA30BC30AW41AY28AU26

BE35BD35AT34AU34BB32AT32AY32AV32

AY40BA41

BD39AT41

U1000

BG39BD42AT22

AV43

BA34AY34

BA36BB36

AR22

BF27

BE41BE47

AL4AL1

AV4BA4AU3AR3AY2BA3BE9BD9

BD13BF12

AN3

BF8BD10BD14BE13BF16BE17BE18BE21BE14BG14

AR4

BG18BF19BD50BF48BD53BF52BD49BE49BD54BE53

AK4

BF56BE57BC59AY60BE54BG54BA58AW59AW58AU58

AK3

AN61AN59AU59AU61AN58AR58AK58AL58AG58AG59

AN4

AM60AL59AF61AH60

AR1AU4AT2

AM2

AL3

AV1

AV3

BE11

BG11

BD18

BD17

BE51

BG51

BA61

BA59

AR59

AT60

AK61

AK59

BF32BE33

BD43AT28AV28BD46AT26AU22

BD33AU30BD30AV30BG30BD29BE30BE28

AT43BG47

BF40BD45

051-9277

2.8.0

12 OF 109

11 OF 73

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

OUT

VCCIO_29VCCIO_28VCCIO_27VCCIO_26VCCIO_25VCCIO_24VCCIO_23VCCIO_22VCCIO_21VCCIO_20VCCIO_19VCCIO_18VCCIO_17VCCIO_16VCCIO_15VCCIO_14VCCIO_13VCCIO_12VCCIO_11VCCIO_10VCCIO_9VCCIO_8VCCIO_7VCCIO_6

VCCIO_49VCCIO_48

VCCIO_5VCCIO_4VCCIO_3

VCCIO_47VCCIO_46VCCIO_45VCCIO_44VCCIO_43

VCCIO_1

VCCIO_42VCCIO_41VCCIO_40VCCIO_39VCCIO_38VCCIO_37VCCIO_36VCCIO_35VCCIO_34VCCIO_33VCCIO_32VCCIO_31VCCIO_30

VCCIO_51VCCIO_50

VCC_76VCC_75VCC_74VCC_73VCC_72VCC_71VCC_70VCC_69VCC_68VCC_67VCC_66VCC_64VCC_63VCC_62VCC_61VCC_60VCC_59VCC_58VCC_57VCC_56VCC_55VCC_54VCC_53VCC_52VCC_51VCC_50VCC_49VCC_48VCC_47VCC_46VCC_45VCC_44VCC_43VCC_42VCC_41VCC_40VCC_39VCC_38VCC_37VCC_36VCC_35VCC_34VCC_33VCC_32VCC_31VCC_30VCC_29VCC_28VCC_27VCC_26VCC_25VCC_24VCC_23VCC_22VCC_21VCC_20VCC_19VCC_18VCC_17VCC_16VCC_15VCC_14VCC_13VCC_12VCC_11VCC_10VCC_9VCC_8VCC_7VCC_6VCC_5VCC_4VCC_3VCC_2VCC_1

VCCIO_SEL

VCCPQE_1VCCPQE_2

VIDALERT*VIDSCLKVIDSOUT

VCC_SENSEVSS_SENSE

VCCIO_SENSEVSS_SENSE_VCCIO

LINES

SENSE

SVID

QUIET

RAIL

PEG AND DDR

CORE SUPLLY

(6 OF 9)

(7 OF 9)

SENSE

LINE

1.8V

RAIL

SA RAIL

QUIET

RAIL

SENSE

LINE

DDR3-1.5V RAILS

GRPHICS

VDDQ_1VDDQ_2VDDQ_3VDDQ_4VDDQ_5VDDQ_6VDDQ_7VDDQ_8

VDDQ_10VDDQ_9

VDDQ_11VDDQ_12VDDQ_13VDDQ_14VDDQ_15VDDQ_16VDDQ_17VDDQ_18

VDDQ_20VDDQ_19

VDDQ_21VDDQ_22VDDQ_23VDDQ_24VDDQ_25VDDQ_26

VCCDQ_1VCCDQ_2

VDDQ_SENSEVSS_SENSE_VDDQ

VCCSA_SENSE

VCCSA_VID_0VCCSA_VID_1

SM_VREF

VAXG_1VAXG_2

VAXG_4VAXG_3

VAXG_5VAXG_6VAXG_7VAXG_8VAXG_9VAXG_10VAXG_11VAXG_12VAXG_13VAXG_14VAXG_15VAXG_16VAXG_17VAXG_18VAXG_19VAXG_20VAXG_21VAXG_22VAXG_23VAXG_24VAXG_25

VAXG_28

VAXG_26VAXG_27

VAXG_30VAXG_29

VAXG_33

VAXG_31VAXG_32

VAXG_35VAXG_34

VAXG_36VAXG_37VAXG_38VAXG_39VAXG_40VAXG_41VAXG_42VAXG_43

VAXG_45VAXG_44

VAXG_46VAXG_47VAXG_48VAXG_49VAXG_50VAXG_51VAXG_52VAXG_53VAXG_54VAXG_55VAXG_56

VAXG_SENSEVSSAXG_SENSE

VCCPLL_1VCCPLL_2VCCPLL_3

VCCSA_2VCCSA_1

VCCSA_3VCCSA_4VCCSA_5VCCSA_6VCCSA_7VCCSA_8VCCSA_9VCCSA_10VCCSA_11VCCSA_12VCCSA_13

VCCSA_15VCCSA_14

VCCSA_16

Apple Inc.


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PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V



Note. VOLTAGE=1.25V

(IPU)

(NOT controlled by VCCIO_SEL)

Note. VOLTAGE=1.05V

Note. VOLTAGE=0V

VCCIO_SEL can be NC.IVB supports 1.05V VCCIO.

Fixed at 1.05V

(IPU)

57 66

57 66

57 66

57 66

59 66

59 66

54

201MF

1%75

1/20W

PLACE_NEAR=U7400.17:2.54mm

PLACE_NEAR=U1000.A44:38mm

201 MF

43

5%1/20W

1/20W MF5%0201

201 1/20W MF5%0

57 66

57 66

57 66

201

1/20W

10K5%

MF201

1/20WMF

5%10K

54

IVY-BRIDGE

2C-35W

BGA

CRITICALOMIT_TABLE

CRITICALOMIT_TABLE

BGA

IVY-BRIDGE

2C-35W

10%16VX5R-CERM

0.1UF

0201

PLACE_NEAR=U1000.AY43:2.54mm

PLACE_NEAR=U1000.C44:2.54mm1/20WMF

1%130

201

PLACE_NEAR=U1000.F43:50.8mmPLACE_SIDE=BOTTOM

MF-LF

1001%

1/16W

402

PLACE_NEAR=U1000.AN16:50.8mm1% PLACE_SIDE=BOTTOM1/16W

402MF-LF

100

100

PLACE_SIDE=BOTTOMPLACE_NEAR=U1000.G43:50.8mm

1%

MF-LF1/16W

402MF-LF

1001%1/16W

402

PLACE_SIDE=BOTTOMPLACE_NEAR=U1000.AN17:50.8mm

PLACE_SIDE=BOTTOM 1%100

MF-LF1/16W

PLACE_NEAR=U1000.F45:50.8mm

402

1001%

PLACE_NEAR=U1000.G45:50.8mmPLACE_SIDE=BOTTOM

MF-LF1/16W

402

MF1/20W

1%100PLACE_NEAR=U1000.BC43:50.8mm

PLACE_SIDE=BOTTOM

201

201

PLACE_NEAR=U1000.U10:50.8mm100

1%

MF1/20W

PLACE_NEAR=U1000.BA43:50.8mm

201MF

1001%

1/20WPLACE_SIDE=BOTTOM

1K5%

1/20WMF201


1K5%

1/20WMF201


1/20W

NOSTUFF

201MF

5%10K


CPU POWER

CPU_VCCSENSE_N

CPU_VCCIOSENSE_N

CPU_VIDALERT_L_R

CPU_VCCIOSENSE_P

CPU_VCCSA_VID<1>

CPU_DDR_VREFVOLTAGE=0.75V

CPU_AXG_SENSE_NCPU_AXG_SENSE_P

CPU_VIDALERT_L

=PPVCCSA_S0_CPU


CPU_VIDSCLK

CPU_VIDSOUT_R


=PPVCORE_S0_CPU




CPU_VCCIO_SEL

=PP3V3_S0_CPU_VCCIO_SEL

CPU_DDR_VREF


CPU_VDDQ_SENSE_N

=PPVCCSA_S0_CPU

CPU_VCCSASENSE


CPU_VDDQ_SENSE_P

=PPVCORE_S0_CPUCPU_VCCSENSE_P

=PP1V5_S3_CPU_VCCDQ

=PP1V8_S0_CPU_VCCPLL_R


CPU_VIDSCLK_RCPU_VIDSOUT


CPU_VCCSA_VID<0>

R13001

2R13101 2

R13111 2

R13121 2

R1314 1

2

R13131

2

U1000A26A29A31A34A35A38A39A42C26C27C32C34C37C39C42D27D32D34D37D39D42E26E28E32E34E37E38F25F26F28F32F34F37F38F42G42H25H26H28H29H32H34H35H37H38H40J25J26J28J29J32J34J35J37J38J40J42K26K27K29K32K34K35K37K39K42L25L28L33L36L40N26N30N34N38

F43

AA14

AA15AB17

AB20

AC13AD16

AD18AD21

AE14

AE15AF16

AF18

AF20

AF46

AG15

AG16

AG17AG20

AG21

AG48AG50

AG51

AJ14

AJ15

AJ17

AJ21

AJ25AJ43

AJ47

AK50AK51

AL14

AL15AL16

AL20AL22

AL26

AL45AL48

AM16

AM17AM21

AM43

AM47AN20

AN42AN45

AN48

BC22

AN16

W16

W17

AM25

AN22

A44

B43C44

G43

AN17

U1000

AY43

AA46AB47

AB50

AB51AB52

AB53AB55

AB56

AB58AB59

AC61

AD47AD48

AD50

AD51AD52

AD53AD55

AD56

AD58AD59

AE46

N45P47

P48

P50P51

P52P53

P55

P56P61

F45

T48

T58T59

T61

U46V47

V48V50

V51

V52V53

V55

V56V58

V59

W50W51

W52W53

W55

W56W61

Y48

Y61

AM28

AN26

BB3BC1

BC4

L17

L21

N16N20

N22

P17P20

R16R18

R21

U10

U15V16

V17

V18V21

D48D49

W20

AJ28

AJ33AJ36

AJ40AL30

AL34

AL38AL42

AM33

AM36AM40

AN30

AN34AN38

AR26AR28

AR30

AR32AR34

AR36

AR40AV41

AW26

BA40BB28

BG33

BC43

BA43

G45

C13301

2

R13021

2

R13601

2

R13621

2

R13611

2

R13631

2

R13701

2

R13711

2

R13801

2

R13821

2

R13811

2

R13301

2

R13311

2

R13201

2

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12

7 12 15

7 9 10 12 14

7 9 10 12 14

7 9 12 14

7 9 12 15

7 9 12 15

7

12

7 10 12 15 26

7 12 15

7 10 12 15 26

7 9 12 14

7 15

7 14

7 14

54

(8 OF 9)VSS

VSS

VSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSS

VSS

VSS

VSS

VSS

VSS

VSSVSS

VSS

VSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSS

VSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSS

VSS

VSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSS

VSSVSS

VSSVSS

VSS_NCTFVSS_NCTF

VSS_NCTFVSS_NCTFVSS_NCTF

VSS_NCTFVSS_NCTF

VSS_NCTFVSS_NCTFVSS_NCTF

VSS_NCTFVSS_NCTF

VSS_NCTFVSS_NCTF

(9 OF 9)VSS

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CRITICALOMIT_TABLE

IVY-BRIDGE

2C-35W

BGA

BGA

2C-35W

OMIT_TABLECRITICAL

IVY-BRIDGE

CPU GROUNDS


U1000A13

A17

A21A25

A28

A33A37

A40A45

A49

A53

A9

AA1

AA13AA50

AA51

AA52AA53

AA55AA56

AA8

AB16

AB18AB21

AB48

AB61

AC10

AC14AC46

AC6

AD17

AD20

AD4

AD61

AE13

AE8

AF1AF17

AF21

AF47AF48

AF50AF51

AF52

AF53AF55

AF56

AF58AF59

AG10AG14

AG18AG47

AG52

AG61

AG7

AH4

AH58

AJ13

AJ16

AJ20AJ22

AJ26AJ30

AJ34

AJ38AJ42

AJ45

AJ48

AJ7

AK1

AK52

AL10AL13

AL17AL21

AL25

AL28AL33

AL36

AL40AL43

AL47

AL61

AM13AM20

AM22

AM26AM30

AM34AM38

AM4

AM42

AM45AM48

AM58

AN1AN21

AN25AN28

AN33

AN36AN40

AN43

AN47AN50

AN54

AP10

AP51AP55

AP7

AR13AR17

AR21

AR41AR48

AR61

AR7

AT14

AT19AT36

AT4

AT45

AT52AT58

AU1

AU11

AU28

AU32AU51

AU7

AV17AV21

AV22

AV34AV40

AV48

AV55

AW13

AW43AW61

AW7

AY14

AY19AY30

AY36

AY4

AY41AY45

AY49

AY55AY58

AY9

BA1BA11

BA17

BA21BA26

BA32

BA48BA51

BB53

BC13BC5

BC57

BD12

BD16BD19

BD23

BD27BD32

BD36

BD40BD44

BD48BD52

BD56

BD8

BE5BG9

U1000BG13BG17

BG21

BG24BG28

BG37BG41

BG45

BG49BG53

C29

C35C40

D10

D14D18

D22

D26D29

D35

D4

D40D43

D46

D50D54

D58

D6

E25

E29

E3

E35

E40

F13F15

F19

F29F35

F40F55

G48G51

G6

G61

H10

H14

H17H21

H4

H53H58

J1

J49J55

K11K21

K51

K8

L16L20

L22L26

L30

L34L38

L43

L48L61

M11M15

M4

M58

M6

N1N17

N21N25

N28

N33N36

N40

N43N47

N48

N51N52

N56N61

A5

A57

BC61BD3

BD59BE4

BE58

BG5BG57

C3

C58D59

E1

E61

P14P16

P18

P21P58

P59

P9

R17

R20

R4

R46

T1

T47T50

T51

T52T53

T55

T56

U13

U8

V20

V61

W13

W15

W18W21

W46

W8

Y4Y47

Y58Y59

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CPU VCORE DECOUPLINGProcessor Load Line : -2.9 mOhms

PLACEMENT_NOTE (C1640-C1645):

CPU VCCPLL DECOUPLINGCPU VCCIO/VCCPQ DECOUPLING

CPU VCCPLL Low pass filter

PLACEMENT_NOTE (C1684-C167F):


Intel recommendation (Section 6.5): 26x 1uF, 10x 10uF, 2x 330uF

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Note:The smallest 10mOhm available in the library are 0805s


Intel recommendation (section 6.4): 2x 1uF, 1x 330uF

Intel recommendation (Table 7-1): 16x 2.2uF, 12x 22uF, 3x 330uF

All INTEL recommendations from Intel doc #4439028 Huron River Platform Power Design Guide



10%

10%10%10%

10%

10%10%10%10%

10%10%10%10%10%10%10%

10%

10%10%10%10%10%10%

10%10%10%10%10%

10%10V

10V10V10V

10V

10V10V10V10V

10V10V10V10V10V10V10V

10V

10V10V10V10V10V10V

10V10V10V10V10V

10V

=PPVCORE_S0_CPU



=PP1V8_S0_CPU_VCCPLL=PP1V8_S0_CPU_VCCPLL_R

CPU DECOUPLING-I


PLACE_NEAR=U1000.BB3:2.54 mm:NO_VIA

1UF

X5R402

Place near U1000 on top side

0

402

5%MF-LF1/16W

Place near U1000 on bottom side

10UF

CERM-X5R20%6.3V0402-1

1UF

X5R402

1UF

X5R402

1UF

X5R402

1UF

X5R402

1UF

X5R402

X5R

1UF

402

1UF

X5R402

1UF

X5R402

1UF

X5R402

1UF

X5R402

1UF

X5R402

1UF

X5R402

1UF

X5R402

1UF

X5R402

1UF

X5R402

6.3V0201

20%1UF

X5R

CRITICAL

20%6.3VX5R

1UF

CRITICAL

02016.3VX5R

1UF

CRITICAL

20%

02010201

1UF

X5R6.3V20%

CRITICAL

0201X5R

1UF20%6.3V

CRITICALCRITICAL

1UF

X5R6.3V20%

0201

X5R402

1UF

1UF

X5R402

1UF

X5R402

Place on bottom side of U1000

1UF

X5R402

CERM-X5R20%

0402-1

CRITICAL

10UF6.3V

Place close to U1000 on top side.

CRITICAL

10UF20%6.3V0402-1CERM-X5R

6.3VX5R

1UF20%

CRITICAL

0201

20%X5R02016.3V

CRITICAL

1UF

X5R6.3V20%1UF

CRITICAL

0201

0201

CRITICAL

20%X5R

1UF6.3V

02016.3V1UF

X5R20%

CRITICAL

02016.3V1UF

X5R20%

CRITICAL

0201

1UF20%6.3VX5R

CRITICAL

20%

02016.3V1UF

X5R

CRITICAL

0201X5R6.3V1UF20%

CRITICAL

X5R6.3V20%

0201

1UF

CRITICAL


X5R402

1UF

0201X5R6.3V1UF20%

CRITICAL

0201

1UF20%

CRITICAL

6.3VX5R

0201

CRITICAL

6.3V1UF

X5R20%

02016.3V1UF

X5R20%

CRITICAL

0201X5R6.3V1UF20%

CRITICALCRITICAL

1UF

X5R20%

02016.3V

1UF6.3V0201X5R20%

CRITICAL

0201

CRITICAL

1UF6.3VX5R20%

CRITICAL

02016.3VX5R

1UF20%

CRITICAL

0201X5R6.3V1UF20%

X5R

Place on bottom side of U100.

1UF

402

6.3V1UF20%

CRITICAL

0201X5R

0201

1UF6.3VX5R20%

CRITICAL

20%6.3V1UF

0201X5R

CRITICAL

0201X5R20%1UF

CRITICAL

6.3V02016.3V1UF

X5R20%

CRITICAL

1UF

0201

20%6.3VX5R

CRITICALCRITICAL

0201

20%6.3V1UF

X5R

CRITICAL

20%1UF

X5R02016.3V

02016.3V1UF20%

CRITICAL

X5R0201

1UF

X5R

CRITICAL

20%6.3V

02016.3V1UF

X5R20%

CRITICAL

02016.3VX5R

1UF20%

CRITICAL

0201

20%6.3VX5R

1UF

CRITICAL

02016.3V1UF

X5R20%

CRITICAL

02016.3V1UF

X5R20%

CRITICAL

0201

20%6.3V1UF

X5R

CRITICAL

02016.3VX5R20%

CRITICAL

1UF

10UF20%CERM-X5R6.3V0402-1

CRITICAL

X5R402

1UF


CRITICAL

6.3V0402-1CERM-X5R20%10UF10UF

CRITICAL

6.3V0402-1CERM-X5R20%

6.3VCERM-X5R

CRITICAL

0402-1

20%10UF

CRITICAL

CERM-X5R20%

0402-16.3V10UF

20%10UF6.3V0402-1CERM-X5R

CRITICAL

6.3V20%CERM-X5R

CRITICAL

0402-1

10UF

CERM-X5R

CRITICAL

20%

0402-16.3V10UF

0402-1

CRITICAL

20%CERM-X5R6.3V10UF

CRITICAL

6.3V0402-1CERM-X5R20%10UF

0402-1

20%

CRITICAL

6.3V10UF

CERM-X5R

1UF

X5R402

10UF

0402-1

20%6.3V

CRITICAL

CERM-X5R

CASE-B2-SMTANT

270UF2V20%

2V20%TANT

PLACE_NEAR=U1000.BC2:5mm

CASE-B2-SM

270UF

2VTANTCASE-B2-SM

270UF20%

CASE-B2-SM

270UF

TANT20%2V

270UF

TANTCASE-B2-SM2V20%

CASE-B2-SM2V20%TANT

270UF

CASE-B2-SMTANT20%2V

270UF20%270UF2VTANTCASE-B2-SM

10UF6.3V20%CERM-X5R0402-1

CRITICAL

CERM-X5R6.3V10UF20%

0402-1

CRITICAL

1UF

X5R402

2VTANT20%270UF

CASE-B2-SM

20%2VCASE-B2-SMTANT

270UF


10UF

CERM-X5R0402-1

20%6.3V


10UF

CERM-X5R0402-1

20%6.3V


10UF

CERM-X5R0402-1

20%6.3V


10UF

CERM-X5R0402-1

20%6.3V

1UF

X5R402


10UF

CERM-X5R0402-1

20%6.3V


10UF

CERM-X5R0402-1

20%6.3V


10UF

CERM-X5R0402-1

20%6.3V


10UF

CERM-X5R0402-1

20%6.3V

CERM-X5R

10UF6.3V20%

0402-1


1UF

X5R402

X5R402

1UF

PLACE_NEAR=U1000.BC1:2.54 mm:NO_VIA

1UF

X5R402

0.010

MF0603

1%1/4W

R16011 2

C167F1

2

C16971

2

C161F1

2

C16981

2

C16991

2

C169A1

2

C169B1

2

C169C1

2

C16841

2

C16851

2

C16861

2

C16551

2

C16561

2

C16871

2

C16881

2

C16891

2

C16001

2

C16011

2

C16021

2

C16031

2

C16041

2

C16051

2

C169D1

2

C169E1

2

C169F1

2

C161A1

2

C161B1

2

C161C1

2

C161D1

2

C16901

2

C16911

2

C16921

2

C16931

2

C16941

2

C16951

2

C16961

2

R16001 2

C160X1

2

C160Y1

2

C161E1

2

C162A1

2

C162B1

2

C162C1

2

C162D1

2

C162E1

2

C167A1

2

C167B1

2

C167C1

2

C167D1

2

C16801

2

C16571

2

C16581

2

C16811

2

C16821

2

C16831

2

C167E1

2

C167G1

2

C167H1

2

C160Z1

2

C16791

2

C16591

2

C16601

2

C16611

2

C16621

2

C16631

2

C16641

2

C16651

2

C16661

2

C16671

2

C16681

2

C16691

2

C16701

2

C16061

2

C16071

2

C16081

2

C16091

2

C16101

2

C16111

2

C16121

2

C16131

2

C16141

2

C16151

2

C16161

2

C16171

2

C16181

2

C16191

2

C16201

2

C16211

2

C16221

2

C16231

2

C16241

2

C16251

2

C16261

2

C16271

2

C16281

2

C16291

2

C16301

2

C16311

2

C16321

2

C16331

2

C16341

2

C16351

2

C16361

2

C16371

2

C16381

2

C16391

2

C16401

2

C16411

2

C16421

2

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7

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Intel recommendation (section 6.3): 18x 1uF(9 no-stuff), 10x 104F(2 no-stuff), 8x 22uF(2 no stuff), 4x 470uF(2 no-stuff)



CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation (Section 6.6): 3x 1uf, 3x 10uf, 1x 330uf

VAXG DECOUPLING


Graphics Load Line : -3.9 mOhms



CPU VCCSA DECOUPLING

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

Intel recommendation (Section 6.13): 10x 1uF, 8x 10uF, 1x 330uF


10%10%

10% 10%

10%10%10%10%10%

10%10%10%

10%

10%10%10%10%10%10%

10%10%10%10%10%10%10%10%10V10V

10V 10V

10V10V10V10V10V

10V10V10V

10V

10V10V10V10V10V10V

10V10V10V10V10V10V10V10V

=PP1V5_S3_CPU_VCCDQ

=PPVCCSA_S0_CPU




CPU DECOUPLING-II

SYNC_MASTER=K21_MLB


X5R402

1UF

402X5R


1UF


X5R

1UF

402

CRITICAL

X5R402

1UF

CRITICAL

X5R

1UF

402X5R402


1UF

X5R

1UF

402


X5R402


1UF

X5R


1UF

402

402X5R

1UF

CRITICAL

X5R402

1UF

CRITICAL

X5R

1UF

CRITICAL

402

1UF

402

X5R

402X5R

1UF

CRITICALCRITICAL

X5R402

1UF

X5R402

1UF

CRITICALPlace on bottom side of U1000

1UF

402X5R

CRITICAL

X5R


402

CRITICAL

1UF1UF

X5R

CRITICAL

402


402X5R

1UF

402

1UF

X5RX5R402

1UF

6.3V20%

X5R-CERM10603

22UF

AXG_ACOUSTIC:NO

22UF20%6.3VX5R-CERM10603

AXG_ACOUSTIC:NO

22UF20%6.3VX5R-CERM10603

AXG_ACOUSTIC:NO

402

1UF

X5RX5R

1UF

402402X5R

1UF


X5R402

1UF

22UF4VX5R

20%

402

AXG_ACOUSTIC:YES

X5R4V20%22UF

402

AXG_ACOUSTIC:YES

X5R4V20%22UF

402

AXG_ACOUSTIC:YES

20%4VX5R

22UF

402

AXG_ACOUSTIC:YES

4VX5R

22UF20%

402

AXG_ACOUSTIC:YES

22UF20%6.3V

0603X5R-CERM1

AXG_ACOUSTIC:NO

20%22UF4VX5R402

AXG_ACOUSTIC:YES

Place close to U1000 on bottom side

0402-1

CERM-X5R

10UF20%6.3V

0402-1

20%6.3V

CERM-X5R

10UF


270UF

CASE-B2-SM

2V20%

TANT

270UF

TANT2V

CASE-B2-SM

20%

TANT2V20%270UF

CASE-B2-SM

10UF

CERM-X5R

6.3V20%

0402-10402-1

20%6.3V

CERM-X5R

10UF

22UF

X5R-CERM1

20%6.3V

0603

AXG_ACOUSTIC:NO

0402-1

20%6.3V

CERM-X5R

10UF20%6.3V

CERM-X5R

10UF

0402-10402-1

20%6.3V

CERM-X5R

10UF

0402-1

20%6.3V

CERM-X5R

10UF

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

10UF

CERM-X5R

6.3V20%

0402-10402-1

20%6.3V

CERM-X5R

10UF

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

10UF

CERM-X5R

6.3V20%

0402-10402-1

20%

CERM-X5R

10UF


6.3V

0603X5R-CERM1

20%6.3V

22UF

AXG_ACOUSTIC:NO

0402-1

6.3V

CERM-X5R

20%

10UF


10UF

6.3V20%

0402-1

CRITICAL

CERM-X5R

0402-1

20%6.3V

CERM-X5R

CRITICAL

10UF

6.3V

0402-1

20%

CERM-X5R

10UF

CRITICAL

CERM-X5R

0402-1

20%

10UF

6.3V

CRITICAL

0402-1

10UF

CERM-X5R

6.3V20%

CRITICAL

10UF

CRITICAL

20%6.3V

CERM-X5R

0402-1

270UF

TANT2V20%

CASE-B2-SM

2V20%

TANT

270UF

CASE-B2-SM

1UF

X5R402


MF

1/4W

1%

0.010

0603

R1702

1 2

C17571

2

C17381

2

C17391

2

C17401

2

C17171

2

C17181

2

C17191

2

C17411

2

C17421

2

C17431

2

C17441

2

C17201

2

C17211

2

C17221

2

C17451

2

C17461

2

C17471

2

C17001

2

C17011

2

C17021

2

C17041

2

C17051

2

C17061

2

C17071

2

C17081

2

C17091

2

C17581

2

C17591

2

C17601

2

C17611

2

C17621

2

C17101

2

C17031

2

C17561

2

C17681

2

C17111

2

C17121

2

C17131

2

C17141

2

C17151

2

C17161

2

C17481

2

C17491

2

C17511

2

C17521

2

C17531

2

C17551

2

C17631

2

C17641

2

C17651

2

C17661

2

C17671

2

C17231

2

C17241

2

C17251

2

C17541

2

C17501

2

C17271

2

C17281

2

C17291

2

C17301

2

C17311

2

C17321

2

051-9277

2.8.0

17 OF 109

15 OF 73

12 7

12 7

26 12 10 7

12 9 7

IN

OUT

OUT

BI

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

BI

OUT

BI

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

BI

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

OUT

BI

BI

NC

NC

IHDA

(1 OF 10)

JTAG

SATA

LPC

RTC

SPI

HDA_SDIN2

HDA_SDIN0

HDA_SYNC

SPI_CS1*

JTAG_TMS

FWH0/LAD0FWH1/LAD1FWH2/LAD2FWH3/LAD3

FWH4/LFRAME*

HDA_DOCK_EN*/GPIO33HDA_DOCK_RST*/GPIO13

HDA_SDIN1

HDA_SDIN3

HDA_SDO

JTAG_TCK

JTAG_TDI

JTAG_TDO

LDRQ0*LDRQ1*/GPIO23

RTCX2

SATA0GP/GPIO21

SATA0RXNSATA0RXPSATA0TXNSATA0TXP

SATA1GP/GPIO19



SATA3COMPISATA3RBIAS

SATA3RCOMPO




SATAICOMPISATAICOMPO

SATALED*

SERIRQ

SPI_CLK

SPI_CS0*

SPI_MISO

SPI_MOSI

HDA_RST*

SPKR

RTCX1

HDA_BCLK

INTVRMEN

INTRUDER*

SRTCRST*

RTCRST*

IN

OUT

OUT

OUT

IN

C-LINK

SMBUS

PCI-E*

CLOCKS

FLEX

CLOCKS

(2 OF 10)

XTAL25_OUTXTAL25_IN

XCLK_RCOMP

SML1DATA/GPIO75SML1CLK/GPIO58

SML1ALERT*/PCHHOT*/GPIO74

SML0DATASML0CLK

SML0ALERT*/GPIO60

SMBDATASMBCLK

SMBALERT*/GPIO11

REFCLK14IN

PETP8

PETP7

PETP6

PETP5

PETP4

PETP3

PETP1

PETN8

PETN7

PETN6

PETN5

PETN4

PETN3

PETN2

PETN1

PERP8

PERP7

PERP6

PERP5

PERP4

PERP3

PERP1

PERN8

PERN6

PERN5

PERN4

PERN3

PERN2

PERN1

PEG_B_CLKRQ*/GPIO56

PEG_A_CLKRQ*/GPIO47

PCIECLKRQ7*/GPIO46

PCIECLKRQ6*/GPIO45

PCIECLKRQ5*/GPIO44

PCIECLKRQ4*/GPIO26

PCIECLKRQ3*/GPIO25

PCIECLKRQ2*/GPIO20

PCIECLKRQ1*/GPIO18

PCIECLKRQ0*/GPIO73

CL_RST1*CL_DATA1CL_CLK1

CLKOUT_PEG_B_PCLKOUT_PEG_B_N

CLKOUT_PEG_A_PCLKOUT_PEG_A_N

CLKOUT_PCIE7PCLKOUT_PCIE7N








CLKOUT_ITPXDP_PCLKOUT_ITPXDP_N

CLKOUT_DP_PCLKOUT_DP_N

CLKOUT_DMI_PCLKOUT_DMI_N

CLKOUTFLEX3/GPIO67

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

CLKIN_SATA_PCLKIN_SATA_N

CLKIN_PCILOOPBACK

CLKIN_GND1_PCLKIN_GND1_N

CLKIN_DOT_96PCLKIN_DOT_96N

CLKIN_DMI_PCLKIN_DMI_N

PERN7

PETP2

PERP2

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

OUT

OUT

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(IPU-RSMRST#)

1.8V -> 1.1V

(IPD-PLTRST#)

(IPD-PWROK)

(IPD-PWROK)

(IPU)

(IPU)

(IPD-PWROK)

(IPU)

(IPD)

VSel strap not functional (VCCVRM = 1.8V)

(IPD)

(IPD-BOOT)

(IPD-BOOT)

(IPD)(IPD)

(IPU)

(IPU)

(IPD)

(IPD-BOOT)

(IPU)(IPU)

(IPU/IPD)(IPU/IPD)

(IPD-PWROK)

(IPU-RSMRST#)

Unused clock terminations for FCIM Mode

Controlled by PCIECLKRQ5#

DOES THIS NEED LENGTH MATCH???

If HDA = S0, must also ensure that signal cannot be high in S3.Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.

25 69

43 69

43 69

6 41 43

38 68

38 68

38 68

38 68

6 37 69

6 37 69

37 69

37 69

44 69

44 69

330K

MF

5%1/20W

201

1M

MF201

5%1/20W

20K

MF201

5%1/20W

20K

MF201

5%1/20W

37.4

MF201

1%1/20W

PLACE_NEAR=U1800.AB10:2.54mm

10K

MF201

5%1/20W

PLACE_NEAR=U1800.AC49:2.54mm

90.9

MF201

1%1/20W

44 69

44 69

16

23 69

23

69

NO STUFF

0

MF201

5%1/20W

1/20W5%

201MF

0

NO STUFF

1/20W

201MF

1K1%

25 69

25

MF201

1%

PLACE_NEAR=U1800.AH4:2.54mm

201

1%1/20W

49.9

MF

PLACE_NEAR=U1800.AF12:2.54mm

23

8 23

6 37 69

6 37 69

16 37

16

16

44 69

44 69

10 66

10 66

8

8

16 68

16 68

16 68

16 68

16 68

16 68

16 68

25 69

16

8

8

8

8

16

34 69

34 69

16 36

1/20W MF5% 2014.7K

20110K

MF5% 1/20W

1/20W5% MF10K

201

10K2011/20W5% MF

1/20W5% 201MF10K

5% 1/20W 201MF10K

5% 1/20W MF10K

201

201MF10K

5% 1/20W

1/20W5% 201MF10K10K

1/20W5% 201MF

20110K

MF5% 1/20W

1/20W5% 201MF10K

201MF1/20W5%10K

5% MF10K

1/20W 201

1/20W MF 20110K

5%

5%10K

1/20W MF 201

16 24

16

1/20W5% 201MF10K10K

1/20W5% 201MF

1/20W5% 201MF33

PLACE_NEAR=U1800.F35:1.27mm

1/20W MF33

5% 201PLACE_NEAR=U1800.K37:1.27mm

1/20W5% MF33

201PLACE_NEAR=U1800.H35:1.27mm

1/20W5% 201MF33

PLACE_NEAR=U1800.H37:1.27mm

6 40 69

6 40 69

6 40 69

6 40 69

6 41 43 69

6 41 43 69

6 41 43 69

6 41 43 69

1/20W 201MF33

5%

1/20W5% MF33

201

1/20W5% 201MF33

1/20W5% 201MF33

6 41 43 69 1/20W5% MF

33201

1/20W5% 201MF10K

1/20W 201MF10K

5%

MF1/20W5%10K

201

5% 201MF

10K1/20W

1/20W5% 201MF10K

1/20W5%10K

201MF

1/20W5% 201MF10K

1/20W5% 201MF10K

1/20W5% 201MF10K

OMIT_TABLE

PCH-PPT-MB-SFF-ES1BGA

QP8D-MM915462

43 69

43 69

23 69

16 34

6 40 69

BGA

OMIT_TABLE

PCH-PPT-MB-SFF-ES1QP8D-MM915462

1.0UF20%

X5R0201-MUR

6.3V

1.0UF20%6.3VX5R0201-MUR

6041%

MF1/20W

PLACE_NEAR=U1800.W49:5.1mm

201

8

8

8

8

8 69

8 69

8

8

8

8

8

8

8

8

8

8

8

8

6 38 66

6 38 66

6 16 38


PCH SATA/PCIe/CLK/LPC/SPISYNC_MASTER=J30_MLB


TP_SATA_C_R2D_CN

TP_SATA_E_D2RP

TP_SATA_E_R2D_CP

HDA_SYNC_R

HDA_RST_R_L

HDA_SDOUT_R

LPC_AD<0>

SML_PCH_1_DATASML_PCH_1_CLK

PEGCLKRQB_L_GPIO56

PCH_INTVRMEN_L

PCIE_CLK100M_FW_PPCIE_CLK100M_FW_N

PCIE_CLK100M_ENET_PPCIE_CLK100M_ENET_N

NC_PCIE_8_R2D_CNNC_PCIE_8_R2D_CP

FW_CLKREQ_L

PCIE_CLK100M_EXCARD_PPCIE_CLK100M_EXCARD_N

SSD_CLKREQ_L

TP_PCIE_CLK100M_PEBN

ENET_CLKREQ_LPCIE_CLK100M_SSD_P

TP_PCIE_CLK100M_PEBP

PEG_CLK100M_NPEG_CLK100M_P

PCIE_CLK100M_TBT_N

ITPXDP_CLK100M_P

PCIE_CLK100M_SSD_N

ITPXDP_CLK100M_N

PEG_CLKREQ_L

AP_CLKREQ_LPCIE_CLK100M_AP_PPCIE_CLK100M_AP_N

=PP1V05_S0_PCH

LPC_AD_R<0>LPC_AD_R<1>

NC_PCIE_7_D2RP

PCH_CLKIN_GNDN1

SML_PCH_0_DATA

LPC_AD_R<2>

NC_PCIE_5_R2D_CP

NC_PCIE_5_D2RNNC_PCIE_5_D2RP

PCIE_EXCARD_R2D_C_P

NC_PCIE_6_D2RNNC_PCIE_6_D2RPNC_PCIE_6_R2D_CN

PCH_SPKR

RTC_RESET_L LPC_AD_R<3>

PCH_SPKR

SYSCLK_CLK25M_SB_RSYSCLK_CLK25M_SB

NC_PCIE_6_R2D_CP

PCH_CLK96M_DOT_PPCH_CLK96M_DOT_N

DMI_CLK100M_CPU_P

TP_PCH_CLKOUT_DPN

HDA_BIT_CLK

HDA_SYNC

HDA_SDOUT

PCH_SRTCRST_LPCH_INTRUDER_L

PCH_CLKIN_GNDP1

PCIE_CLK100M_PCH_P

PCH_CLK100M_SATA_N

PCH_CLK96M_DOT_P

=PP3V3_S0_PCH

PCIE_CLK100M_PCH_N

PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_N

PCH_CLK14P3M_REFCLK

LPC_AD<3>LPC_AD<2>

NC_PCIE_8_D2RNNC_PCIE_8_D2RP

NC_PCIE_7_D2RN

NC_PCIE_7_R2D_CP

PCIE_AP_R2D_C_NPCIE_AP_R2D_C_P

USB_EXTB_SEL_XHCISML_PCH_0_CLK

USB_EXTD_SEL_XHCI

TP_CLINK_DATATP_CLINK_RESET_L

PEGCLKRQA_L_GPIO47TP_PCIE_CLK100M_PEGANTP_PCIE_CLK100M_PEGAP

DMI_CLK100M_CPU_N

TP_PCH_CLKOUT_DPP

PCIE_CLK100M_PCH_N

PCH_CLKIN_GNDN1PCH_CLKIN_GNDP1

PCH_CLK100M_SATA_PPCH_CLK100M_SATA_N

=PP1V05_S0_PCH_VCCDIFFCLK




HDA_BIT_CLK_R

=PPVRTC_G3_PCH

RTC_RESET_L

PCH_SRTCRST_L

PCH_INTRUDER_L

PCH_INTVRMEN_L

HDA_BIT_CLK_R

HDA_RST_R_L

SPI_MOSI_R

SPI_MISO

LPC_SERIRQ

PCH_SATALED_L

TP_SATA_F_R2D_CP

TP_SATA_F_D2RN

TP_SATA_E_R2D_CN

TP_SATA_E_D2RN

TP_SATA_D_R2D_CPTP_SATA_D_R2D_CNTP_SATA_D_D2RPTP_SATA_D_D2RN

PCH_SATA3RBIASPCH_SATA3COMP

TP_SATA_C_R2D_CP

TP_SATA_C_D2RPTP_SATA_C_D2RN

SATA_ODD_R2D_C_PSATA_ODD_R2D_C_NSATA_ODD_D2R_PSATA_ODD_D2R_N

SATA_HDD_R2D_C_PSATA_HDD_R2D_C_NSATA_HDD_D2R_PSATA_HDD_D2R_N

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

TBT_PWR_EN_PCHTP_LPC_DREQ0_L

XDP_PCH_TDI

XDP_PCH_TCK

HDA_SDOUT_R

TP_HDA_SDIN1

ENET_MEDIA_SENSE_RDIV

LPC_FRAME_R_LLPC_AD_R<3>LPC_AD_R<2>LPC_AD_R<1>LPC_AD_R<0>

XDP_PCH_TMS

TP_SPI_CS1_L

HDA_SYNC_R

HDA_SDIN0

TP_HDA_SDIN2

HDA_RST_L

ITPCPU_CLK100M_N

LPC_FRAME_L

PCIE_EXCARD_R2D_C_N

PCIE_FW_R2D_C_PPCIE_FW_R2D_C_N

PCIE_FW_D2R_NPCIE_FW_D2R_P

PCIE_EXCARD_D2R_NPCIE_EXCARD_D2R_P

PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_P

TP_SATA_F_R2D_CNTP_SATA_F_D2RP

PCIE_AP_D2R_PPCIE_AP_D2R_N

PCIE_ENET_R2D_C_NPCIE_ENET_D2R_P

LPC_AD<1>

JTAG_DPMUXUC_TRST_L

EXCARD_CLKREQ_L

TP_PCIE_CLK100M_PE4NTP_PCIE_CLK100M_PE4P

TBT_CLKREQ_L

PCH_SATAICOMP

NC_PCIE_5_R2D_CN

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

LPC_FRAME_R_L

FW_CLKREQ_L

PCH_SATALED_L

DP_AUXCH_ISOLSATARDRVR_EN

SYSCLK_CLK32K_RTC

NC_PCIE_7_R2D_CN

PCIE_CLK100M_PCH_P

PCH_CLK14P3M_REFCLK


PCIE_CLK100M_TBT_P

SSD_CLKREQ_L

PCH_CLK33M_PCIIN

SYSCLK_CLK25M_SB_R

PCH_XCLK_RCOMP

TP_CLINK_CLK

SMBUS_PCH_DATASMBUS_PCH_CLKSMBUS_PCH_ALERT_L

ENET_MEDIA_SENSE_RDIV

ITPCPU_CLK100M_P

AP_CLKREQ_L

JTAG_DPMUXUC_TRST_LENET_CLKREQ_L

PEGCLKRQA_L_GPIO47

TBT_CLKREQ_LPEG_CLKREQ_L

EXCARD_CLKREQ_L

USB_EXTD_SEL_XHCI

SMBUS_PCH_ALERT_LUSB_EXTB_SEL_XHCI

=PP3V3_S0_PCH_GPIO=PP3V3_SUS_PCH_GPIO

PEGCLKRQB_L_GPIO56

750

1/20W

TP_HDA_SDIN3

23

SPI_CS0_R_L

SPI_CLK_R

XDP_PCH_TDO

69

JTAG_ISP_TMS

R18001

2

R18011

2

R18021

2

R18031

2

R18301

2

R18201

2

R18901

2

R18401 2

R18411 2

R18861

2

R18321

2

R18311

2

R1877 1 2

R1878 1 2

R1834 1 2

R1842 1 2

R1869 1 2

R1844 1 2

R1845 1 2

R1847 1 2

R1814 2 1

R1815 1 2

R1843 1 2

R1833 1 2

R1879 1 2

R1846 1 2

R1853 1 2

R1848 1 2

R1854 1 2

R1855 1 2

R1812 1 2

R1813 1 2

R1810 1 2

R1811 1 2

R1861 1 2

R1862 1 2

R1863 1 2

R1864 1 2

R1860 1 2

R1891 1 2

R1892 1 2

R1893 1 2

R1894 1 2

R1895 1 2

R1896 1 2

R1897 1 2

R1870 1 2

R1871 1 2

U1800A37A39C39C37K40

H35

K35M35

F35

D36B36C35A35

K37

H37

K22

C21

M17

U12

M12

M15

H40F37

F19

A19C19

M2

AN3AN1AU3AU1

R1

AN6AN8AR3AR1

AD4AD2AL3AL1

AF12AH4

AF10

AD8AD6AG3AG1

AE3AE1AH8AH6

AC3AC1AJ3AJ1

AB12AB10

W10

Y4

AD12

AB8

AB6

Y2

W8

N1

A23

U1800

L3J1M8

BD17BF17

M24K24

BB26AY26

E51

AK8AK6

BB24AY24

AN10AN12

AR12AR10

AD48AD50

AE49AE51

AD40AD42

AA49AA51

Y48Y50

AB40AB42

AB44AB46

W44W46

AF44AF46

AF40AF42

H50

D48

G49

J51

M4

U8

T4

B8

M19

K8

J3

H4

R8

C4

BJ33

BJ35

BH36

BJ37

BJ39

BH40

BJ41

BJ43

BL33

BL35

BK36

BL37

BL39

BK40

BL41

BL43

BB30

BB33

BF33

BD35

AY35

BD37

AY37

AY40

AY30

AY33

BD33

BF35

BB35

BF37

BB37

BB40

J49

H12F17F10

H22K12A9

C9D12C11

AC49

W49W51

C1802 1

2

C18031

2

R18851 2

051-9277

2.8.0

18 OF 109

16 OF 73

7 22 6

6

16 69

16 69

16 25 69

16

16

8

8

8

8

16

6

6

23 66

23 66

7 22

16

16

8

16

16

8

8

8

8

8

8

16

16 16

16

16 69

8

16

16

16

16 68

16 68

16 68

7 22

16 68

16 68

16 68

16 68

8

8

8

8

6

6

16

16

16

7 20 22

6

6

6

16 69

7 17 20

16

16

16

16

16 69

16 69

16

6

6

6

6

6

6

6

6 16 69

6

16

16

16

16

16

16 69

6

10 66

6

6

6

6

68

8

16

16

16

23 25

8

8

6

6 16 38

16 69

6

16

16

10 66

16 37

16

16

16

16 36

16

16

16

16

16 24

7 17 18 19 25 36

7 17 18 19

16

6

25

IN

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

BI

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

FDI

(3 OF 10)

DMI

SYSTEM POWER

MANAGEMENT

DMI_ZCOMP

DMI3TXNDMI2TXNDMI1TXNDMI0TXN

FDI_LSYNC1

DSWVRMEN

FDI_FSYNC1FDI_FSYNC0

FDI_RXP5FDI_RXP4FDI_RXP3FDI_RXP2FDI_RXP1FDI_RXP0

APWROK

CLKRUN*/GPIO32

DMI0RXNDMI1RXNDMI2RXN

DMI2RXP

DMI3RXN

DMI3RXP

DMI3TXP

DPWROK

DRAMPWROK

FDI_INT

FDI_LSYNC0

FDI_RXN0FDI_RXN1FDI_RXN2FDI_RXN3FDI_RXN4FDI_RXN5FDI_RXN6FDI_RXN7

FDI_RXP6FDI_RXP7

PMSYNCH

PWROK

SLP_A*

SLP_LAN*/GPIO29

SLP_S3*SLP_S4*

SLP_S5*/GPIO63

SLP_SUS*

SUSACK*

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SYS_PWROK

SYS_RESET*WAKE*

RI*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

DMI1RXPDMI0RXP

DMI_IRCOMP

DMI2RBIAS

DMI0TXPDMI1TXPDMI2TXP

(4 OF 10)

LVDS

DIGITAL DISPLAY INTERFACE

CRT

LVDSA_DATA0*LVDSA_DATA1*

LVDSB_DATA3*LVDSB_DATA2*

CRT_BLUE

CRT_DDC_CLKCRT_DDC_DATA

CRT_GREEN

CRT_HSYNC

CRT_IRTN

CRT_RED

CRT_VSYNC

DAC_IREF

DDPB_0NDDPB_0PDDPB_1NDDPB_1PDDPB_2NDDPB_2PDDPB_3NDDPB_3P

DDPB_AUXNDDPB_AUXPDDPB_HPD

DDPC_0NDDPC_0PDDPC_1NDDPC_1PDDPC_2NDDPC_2PDDPC_3NDDPC_3P

DDPC_AUXNDDPC_AUXP

DDPC_CTRLCLKDDPC_CTRLDATA

DDPC_HPD

DDPD_0NDDPD_0PDDPD_1NDDPD_1PDDPD_2NDDPD_2PDDPD_3NDDPD_3P

DDPD_AUXNDDPD_AUXP

DDPD_CTRLCLKDDPD_CTRLDATA

DDPD_HPD

LVDSA_CLKLVDSA_CLK*

LVDSA_DATA2*LVDSA_DATA3*

LVDSA_DATA0LVDSA_DATA1

LVDSA_DATA3

LVDSB_CLKLVDSB_CLK*

LVDSB_DATA0*LVDSB_DATA1*

LVDSB_DATA0LVDSB_DATA1LVDSB_DATA2LVDSB_DATA3

LVD_VREFHLVD_VREFL

L_DDC_CLKL_DDC_DATA

SDVO_CTRLCLKSDVO_CTRLDATA

SDVO_INTNSDVO_INTP

SDVO_STALLNSDVO_STALLP

SDVO_TVCLKINNSDVO_TVCLKINP

L_BKLTENL_VDD_EN

L_BKLTCTL

LVD_IBGLVD_VBG

LVDSA_DATA2

L_CTRL_CLKL_CTRL_DATA

NCNCNCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NCNC

NC

NCNC

NC

NC

NC

NCNC

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



(IPD-DeepS4/S5)

(IPU)

(IPU)

(IPU)

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD)(IPD)

(IPD)(IPD)

(IPD)(IPD)

9 66

9 66

9 66

9 66

9 66

9 66

49.9

1/20W1%

201MF

PLACE_NEAR=U1800.BF19:12.7mm

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

1/20W5%

201

1K

MF

PLACE_NEAR=U1800.R51:2.54mm

750

MF

1%1/20W

201

PLACE_NEAR=U1800.BK20:2.54mm

390K

MF201

5%1/20W

1/20W5%

201MF

10K

0

MF201

5%1/20W

17 62

1/20W5%

201MF

100K

25 41

23 25 41

10 26 66

25

25

62

17 23 41

41 42 62

42

6 17 37

6 17 41 43

6 25 41 43

42 69

17 41 62

17 26 37 41 49 62

17 26 41 62

10 66

41

8

8

8

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

9 66

5% 2011/20W MF100K

1/20W5% MF1K

201

1/20W5% 2018.2K

MF

1/20W5% 201MF1K

5% 201MF100K

1/20W

5% 1/20W 201MF100K100K

1/20W5% 201MF

10K

1/20W5%

201MF

5% MF10K

2011/20W

17 56

OMIT_TABLE

QP8D-MM915462BGA

PCH-PPT-MB-SFF-ES1 PCH-PPT-MB-SFF-ES1

OMIT_TABLE

QP8D-MM915462BGA

MF5%

100K1/20W

201

PCH DMI/FDI/PM/GraphicsSYNC_MASTER=J30_MLB SYNC_DATE=07/27/2011

DMI_N2S_P<1>

PM_PWRBTN_L

PCIE_WAKE_L

PM_SLP_SUS_LPM_SLP_S5_L

PM_SLP_S3_L

FDI_INT

MEM_VDD_SEL_1V5_L

PM_SLP_S4_L

PM_CLKRUN_L

PCH_SUSWARN_L

=PP3V3_SUS_PCH_GPIO

PM_PWRBTN_L

PCH_SUSWARN_L

PCH_DMI_COMP

DMI_S2N_P<0>

DMI_S2N_P<3>

=PP1V05_S0_PCH_VCCIO_PCIE=PP3V3_SUS_PCH_GPIO

FDI_DATA_N<0>

FDI_DATA_N<2>

TP_SDVO_INTN

TP_DP_IG_C_MLP<0>

TP_DP_IG_C_MLP<1>

TP_DP_IG_C_MLP<2>

TP_DP_IG_B_MLP<0>

TP_DP_IG_B_MLP<1>

LVDS_IG_PANEL_PWRLVDS_IG_BKL_ON

LVDS_IG_BKL_PWM

TP_SDVO_INTP

DPA_IG_DDC_DATA

TP_SDVO_TVCLKINP

TP_DP_IG_D_MLP<2>

TP_DP_IG_D_MLN<1>TP_CRT_IG_DDC_DATA

PCH_SUSACK_L

=PP3V3_SUS_PCH_GPIO

=PP3V3_S5_PCH=PP3V3_S0_PCH_GPIO

TP_CRT_IG_HSYNC

TP_CRT_IG_DDC_CLK

TP_CRT_IG_RED

TP_CRT_IG_BLUE

FDI_DATA_N<5>

FDI_DATA_P<1>FDI_DATA_P<2>FDI_DATA_P<3>

FDI_DATA_N<7>

FDI_DATA_P<4>

FDI_FSYNC<0>

PCH_RI_L

PCH_DMI2RBIAS

DMI_S2N_P<2>

DMI_S2N_N<2>

FDI_DATA_P<0>

PM_DSW_PWRGD

DMI_S2N_P<1>

DMI_N2S_P<0>

PM_RSMRST_L

PM_BATLOW_L

PCIE_WAKE_LPM_SYSRST_L

PM_PCH_SYS_PWROK

LPC_PWRDWN_L

PCH_SUSACK_L

PM_SLP_SUS_L

PM_SLP_S5_LPM_SLP_S4_LPM_SLP_S3_L

TP_PM_SLP_A_L

PM_PCH_PWROK

PM_SYNC

FDI_DATA_N<6>

FDI_DATA_N<4>FDI_DATA_N<3>

FDI_DATA_N<1>

PM_MEM_PWRGD

DMI_N2S_P<3>

DMI_N2S_N<3>

DMI_N2S_P<2>

DMI_N2S_N<2>DMI_N2S_N<1>DMI_N2S_N<0>

PM_CLKRUN_L

PM_PCH_APWROK

PCH_DSWVRMEN

DMI_S2N_N<0>DMI_S2N_N<1>

DMI_S2N_N<3>

=PPVRTC_G3_PCH

FDI_LSYNC<0>FDI_LSYNC<1>

FDI_FSYNC<1>

FDI_DATA_P<5>


PM_CLK32K_SUSCLK_R

MEM_VDD_SEL_1V5_L

TP_SDVO_TVCLKINN

TP_SDVO_STALLPTP_SDVO_STALLN

DPA_IG_DDC_CLK

TP_DP_IG_D_HPD

TP_DP_IG_D_CTRL_DATATP_DP_IG_D_CTRL_CLK

TP_DP_IG_D_AUXPTP_DP_IG_D_AUXN

TP_DP_IG_D_MLP<3>TP_DP_IG_D_MLN<3>

TP_DP_IG_D_MLN<2>TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLP<0>TP_DP_IG_D_MLN<0>

DPB_IG_HPD

DPB_IG_DDC_DATADPB_IG_DDC_CLK

DPB_IG_AUX_CH_PDPB_IG_AUX_CH_N

TP_DP_IG_C_MLP<3>TP_DP_IG_C_MLN<3>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLN<1>

TP_DP_IG_C_MLN<0>

DPA_IG_HPDDPA_IG_AUX_CH_PDPA_IG_AUX_CH_N

TP_DP_IG_B_MLP<3>TP_DP_IG_B_MLN<3>TP_DP_IG_B_MLP<2>TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLN<1>

TP_DP_IG_B_MLN<0>

PCH_DAC_IREF

TP_CRT_IG_VSYNC

TP_CRT_IG_GREENSMC_ADAPTER_EN

R19001

2

R19511

2

R19201

2

R19151

2

R19051

2

R198612

R19091

2

R1923 2 1

R1925 1 2

R1991 1 2

R1985 1 2

R1922 2 1

R1921 2 1

R1924 2 1

R19831

2

R1982 1 2

U1800

H19

G3

H10

T2

BL21

BJ21

BD22

BF22

BL23

BJ23

BB22

AY22

BK20

BJ19

BL19

BB19

AY19

BL17

BJ17

BB17

AY17

BD19BF19

A21

B12

F22

BH12BK8

BB10

BK12BH8

BL13BJ15BD12BJ11AY15AY12BJ9BF10

BJ13BL15BF12BL11BB15BB12BL9BD10

BB8

K19

M22

F12

B20

C7

A7

D4K10F6

A15

G6

F15

D3

C13

M10

L1D8

U1800

M46

R49N49

R46

M50

T48

U46

N51

R51

AY48AY50AY44AY46BB44BB46BA49BA51

AW51AW49AY42

BC49BC51BD48BD50BF46BF45BE49BE51

AU51AU49

T50U44

BE46

BG51BG49BF42BD42BJ47BL47BL45BJ45

AU46AU44

M48U42

BK44

L49

M44

R42M40

L51K46

M42

AH42AH40

AG51AG49

AK46AK44

AR44

AR46

AN51

AN49

AN46

AN44

AK42

AK40

AH44AH46

AM48

AM50

AL51

AL49

AJ49

AJ51

AH48

AH50

W42R44

AT50AT48

AR51AR49

AU40AU42

R19551

2

051-9277

2.8.0

19 OF 109

17 OF 73

17 23 41

6 17 37

17 62

17 41 62

17 26 41 62

17 56

17 26 37 41 49 62

6 17 41 43

17

7 16 17 18 19

17

7

7 16 17 18 19

6

8

8

8

8

8

6

8

6

6

17

7 16 17 18 19

7

7 16 18 19 25 36

6

6

6

6

17

7 16 20

6

6

6

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

6

6

NC

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

NCNC

NC

NC

NCNCNCNCNCNCNCNCNCNCNCNCNCNC

NCNC

NC

NCNCNC

NCNCNC

NCNCNC

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

IN

BI

IN

(5 OF 10)

USB

PCI

PME*

PLTRSTB*

PIRQA*

TP2

TP5TP4

TP11

USB3RN4

USB3RN2

CLKOUT_PCI0CLKOUT_PCI1CLKOUT_PCI2CLKOUT_PCI3CLKOUT_PCI4

GNT1*/GPIO51GNT2*/GPIO53GNT3*/GPIO55

OC0*/GPIO59OC1*/GPIO40OC2*/GPIO41OC3*/GPIO42OC4*/GPIO43OC5*/GPIO9OC6*/GPIO10OC7*/GPIO14

PIRQB*PIRQC*PIRQD*

PIRQE*/GPIO2PIRQF*/GPIO3PIRQG*/GPIO4PIRQH*/GPIO5

REQ1*/GPIO50REQ2*/GPIO52REQ3*/GPIO54

RSVD

TP1

TP3

TP6TP7TP8TP9TP10

TP12TP13TP14TP15TP16TP17TP18TP19TP20TP21TP22TP23TP24

TP41TP42

USB3RN1

USB3RN3

USB3RP1USB3RP2USB3RP3USB3RP4

USB3TN1USB3TN2USB3TN3USB3TN4

USB3TP1USB3TP2USB3TP3USB3TP4

USBP0NUSBP0P

USBP10NUSBP10P

USBP11NUSBP11P

USBP12NUSBP12P

USBP1NUSBP1P

USBP2NUSBP2P

USBP3NUSBP3P

USBP4NUSBP4P

USBP5NUSBP5P

USBP6NUSBP6P

USBP7NUSBP7P

USBP8NUSBP8P

USBP9NUSBP9P

USBRBIASUSBRBIAS*

USBP13PUSBP13N

NC

NC

BI

BI

BI

OUT

OUT

OUT

OUT

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Redundant to pull-up on audio page

USB Hub (All LS/FS Devices)

Ext D (XHCI) (Mobiles: Trackpad?)

Redundant to pull-up on audio page

Ext A (XHCI/EHCI)

Ext B (XHCI)

Ext C (XHCI/EHCI)

Unused

Unused

Ext D (EHCI)

Ext B (EHCI)

Camera

RSVD: BT (HS)

RSVD: SD

RSVD: WiFi

Unused

(IPD)

(IPD)

(IPU)

(IPU-PCIERST#)

24 68

24 68

8

8

24 68

24 68

8

8

24 68

24 68

24 68

24 68

39 68

39 68

39 68

39 68

40 68

40 68

40 68

40 68

8

8

8

8

8

8

8

8

2011/20W10K

MF5%

1/20W5% 201MF10K

5% MF 2011/20W10K

MF1/20W5% 20110K

10KMF 2015% 1/20W

NO STUFF

1/20W MF10K

2015%

10KMF 2015% 1/20W

1/20W10K

MF 2015%

MF10K

2015% 1/20W

20110K

MF5% 1/20W

NO STUFF10K

MF 2015% 1/20W

5%10K

MF 2011/20W

18

18

18

18

6 18 40

18 34

6 18 40

1/20W5% 201MF10K

1/20W5% 201MF10K10K

MF1/20W5% 201

1/20W5% 201MF10K

NO STUFF10K

MF 2015% 1/20W

10KMF 2015% 1/20W

NO STUFF

18 23

18 23

18 23

18 23

18 23

23

23

39 68

23

BGAPCH-PPT-MB-SFF-ES1

QP8D-MM915462

OMIT_TABLE

39 68

6 40 68

6 40 68

1%

201MF1/20W

22.6

PLACE_NEAR=U1800.A33:2.54mm

25 26

25 69

25 69

25 69

PCH PCI/USB/TP/RSVDSYNC_DATE=11/10/2011SYNC_MASTER=J13_MLB_NON_POR

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_LXDP_DA1_PCH_GPIO40_USB_EXTB_OC_LXDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

AUD_I2C_INT_L

BLC_I2C_MUX_SEL

BLC_GPIO

PCH_GPIO54

JTAG_GMUX_TMS

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

AP_PWR_EN

TP_PCH_STRP_ESI_LPCH_STRP_TOPBLK_SWP_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

TBT_PWR_REQ_L

=PP3V3_S3_PCH_GPIO

USB_EXTD_XHCI_N

USB_EXTD_EHCI_P

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

JTAG_GMUX_TMS

PCH_GPIO54

AUD_IP_PERIPHERAL_DETTBT_PWR_REQ_LAUD_I2C_INT_L

USB3_EXTC_TX_P

PCI_INTB_L

BLC_I2C_MUX_SELUSB_EXTB_EHCI_P

USB_EXTD_EHCI_N

AUD_IP_PERIPHERAL_DET

=PP3V3_S0_PCH_GPIO

TP_USB_WLANP

TP_USB_WLANN

TP_PCH_STRP_BBS1

USB_EXTA_PUSB_EXTA_N

USB_EXTB_XHCI_PUSB_EXTB_XHCI_N

USB_EXTC_NUSB_EXTC_P

USB_EXTD_XHCI_P

TP_USB_4NTP_USB_4PTP_USB_SDN

TP_USB_SDP

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_LXDP_DA1_PCH_GPIO40_USB_EXTB_OC_LXDP_DA2_PCH_GPIO41_USB_EXTC_OC_LXDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGEXDP_DB2_PCH_GPIO10_AP_PWR_EN

PCH_USB_RBIAS

TP_USB_13NTP_USB_13P

USB_EXTB_EHCI_N

USB_CAMERA_NUSB_CAMERA_P

USB_HUB_UP_NUSB_HUB_UP_P

TP_USB_12P

TP_USB_BT_HSNTP_USB_BT_HSP

TP_USB_12N

TP_PCH_TP23

USB3_EXTC_RX_NUSB3_EXTB_RX_NUSB3_EXTA_RX_N

USB3_EXTA_RX_PUSB3_EXTB_RX_P

USB3_EXTD_RX_PUSB3_EXTC_RX_P

USB3_EXTA_TX_NUSB3_EXTB_TX_NUSB3_EXTC_TX_NUSB3_EXTD_TX_N

USB3_EXTB_TX_PUSB3_EXTA_TX_P

USB3_EXTD_TX_P

PCI_INTC_L

=PP3V3_S0_PCH_GPIOPCI_INTA_L

PCI_INTD_L

LPC_CLK33M_SMC_R

TP_PCI_CLK33M_OUT2TP_PCI_CLK33M_OUT3

LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

TP_PCI_PME_L

PLT_RESET_L

BLC_GPIO

USB3_EXTD_RX_N

=PP3V3_SUS_PCH_GPIO

R20701

2

R2067 2 1

R2068 1 2

R2061 1 2

R2062 1 2

R2033 1 2

R2060 1 2

R2030 1 2

R2018 1 2

R2016 1 2

R2017 1 2

R2014 1 2

R2031 1 2

R2010 1 2

R2011 1 2

R2012 1 2

R2013 1 2

R2054 2 1

R2069 1 2

U1800

G51E49H48J43G45

F42H42D44

C17A17A13D16A11B16C23H15

D49C48C47C45

A47C41F45F40

F7

H2

G46K44F46

AU6AU8

BB6BC1BC3BD2BD4BE1BE3BE6BF6BF7

AW1

BG1BG3BH3BH4BJ4BJ5BJ7BK6BL5

AW3AY2AY4AY6AY8BA1BA3

BH24

D20M30E3AM4AT4AT2

AD10B24D24

AD44

BK24

AD46BJ48BL7W40K30

BH20BK16

BH49BB42

BH16AN42AN40AR40AR42

BJ25BJ27BJ31BJ29

BL25BL27BL31BL29

BF26BB28BF28BF30

BD26AY28BD28BD30

F24H24

C31A31

H33F33

H30F30

M33K33

C25A25

C27A27

H28F28

M26K26

D28B28

H26F26

D32B32

M28K28

C29A29

A33C33

051-9277

2.8.0

20 OF 109

18 OF 73

18 23

18 23

18 23

6 18 40

18

18

18

18

18 23

23 37 62

18 23

18 34

7 25

6 18 40

7 16 17 18 19 25 36

68

7 16 17 18 19 25 36

6

6

7 16 17 19

OUTOUT

BI

IN

NC

IN

OUT

OUT

OUT

IN

BI

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

BI

IN

OUT

NCTF

CPU/MISC

(6 OF 10)

GPIO

GPIO1GPIO6

VSS_NCTF

VSS_NCTF

TS_VSS4TS_VSS3TS_VSS2TS_VSS1

THRMTRIP*STP_PCI*/GPIO34

SATA3GP/GPIO37SATA2GP/GPIO36

RCIN*

PROCPWRGD

PECI

NC_1

INIT3_3V*

GPIO71GPIO70GPIO69GPIO68

GPIO35

GPIO8GPIO7

DF_TVS

A20GATE

GPIO24GPIO27GPIO28

BMBUSY*/GPIO0

LAN_PHY_PWR_CTRL/GPIO12GPIO15SATA4GP/GPIO16GPIO17SCLOCK/GPIO22

SLOAD/GPIO38SDATAOUT0/GPIO39SDATAOUT1/GPIO48SATA5GP/GPIO49GPIO57

D SG

D

GS

D SG

OUT IN

IN OUT

IN OUT

NC

08

NC

OUT

NC

08OUT

NC

IN

TABLE_BOMGROUP_ITEM


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6 3



Stuff R2160 or R2574, not both

Must stuff R2197 when R2180 NO STUFFed.

Set to Vcc when HighSet to Vss when LowDF_TVS:DMI & FDI Term Voltage

(IPD)

(IPU)

(IPU-DeepS4/S5)

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

(IPU)

(IPD-PLTRST#?)

(IPU-RSMRST#)

(IPD-PLTRST#)

(IPD-PLTRST#)

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

(IPU-RSMRST#)

Systems with chip-down memory should add pull-downs on another page and set straps per software.

This has internal pull up and should not pulled low.

NOTE: TDO from CR is Push-Pull CMOS

TBT_PWR_EN goes high for JTAG Programming

NOTE: TMS/TDI from PCH is Open DrainNOTE: TCK from PCH is Push-Pull CMOS

JTAG Isolation due to glitch in and out of sleep

(TBT_CIO_PLUG_EVENT_ISOL)

SMC_RUNTIME_SCI_L

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

TBT_CIO_PLUG_EVENT_ISOL

NO STUFF

10K

TBT_CIO_PLUG_EVENT

JTAG_ISP_TMS

=PP3V3_S0_PCH_STRAPS


74LVC1G08

=PP3V3_TBT_PCH_GPIO

19

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

SSM3K15FV

=PP3V3_S0_PCH_GPIO

SSM6N15AFE

JTAG_ISP_TCK

TBT_PWR_EN

CRITICAL

PCH GPIO/MISC/NCTF

X5R-CERM

SYNC_MASTER=J11_MLB

201


JTAG_TBT_TCKSOT891

=PP3V3_S0_PCH_GPIO

1/20W

MF

PCH_RCIN_L

=PP3V3_S5_PCH_GPIO

10K

MF201

5%1/20W

1/20W5%

201MF

XDP_FC1_PCH_GPIO0

16VX5R-CERM

10%0.1UF

0201

1/20W5%

MF

10K

10KMF5% 201

16V10%

0.1UF

0201 74LVC1G08CRITICAL

SOT891

10K

1/20W

SSM6N15AFE

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

ENET_LOW_PWR_PCH

SMC_RUNTIME_SCI_L

201

JTAG_TBT_TMS

=PP3V3_TBT_PCH_GPIO

TBT_GO2SX_BIDIR

10K5%1/20WMF201

CRITICAL

JTAG_ISP_TDO

=PP3V3_TBT_PCH_GPIO

5%

JTAG_ISP_TDI JTAG_TBT_TDI

1/20W5%

201MF

10KSOD-VESM-HF

1/20W5%

201MF

10KSOT563

5%

201MF

CRITICAL

SOT563

5%

201MF

10K

1/20W5%

201MF

10K

PCH_A20GATE

MLB_RAMCFG0

MF

201

XDP_FC0_PCH_GPIO15

5%

LPCPLUS_GPIO

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCKXDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

PM_THRMTRIP_L_R

SMC_WAKE_SCI_LTBT_GO2SX_BIDIR

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_LTBT_SW_RESET_R_L

XDP_DC1_PCH_GPIO35_MXM_GOOD

JTAG_ISP_TDOJTAG_ISP_TDIFW_PWR_EN_PCH

10 23 66

SPIROM_USE_MLB

8 19

23

MF

1/20W

1/20W

1/20W

LPCPLUS_GPIO

10 42 66

5%

MF

1/20W5%

201MF

10K

RAMCFG2:H

8 23

=PP1V8_S0_PCH_VCC_DFTERM

CPU_PROC_SEL_L

=PP3V3_S0_PCH_GPIO

MLB_RAMCFG1MLB_RAMCFG2MLB_RAMCFG3

CPU_PECI

CPU_PWRGD

PM_THRMTRIP_L

PCH_INIT3V3_L

PCH_RCIN_L

PCH_PROCPWRGD

XDP_FC1_PCH_GPIO0FW_PME_LDPMUX_UC_IRQ

PCH_PECI

PCH_DF_TVS

WOL_EN

FW_PME_L

TBT_SW_RESET_L

TP_PCH_GPIO8

ODD_PWR_EN_L

WOL_EN

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:HRAMCFG_SLOT


OMIT_TABLE

PCH-PPT-MB-SFF-ES1QP8D-MM915462

BGA

19

23

66 42 10

1/20W5%201MF

390

0

MF 2015% 1/20W

1/20W5%201MF

43NO STUFF

1/20W 201MF

2011/20W5% MF10K

1/20W5% MF10K

10K1/20W5% MF

23 19

36 1/20W

0

MF 201 23

1/20W5% 201MF10K

10K5% 201MF10K5% 201

MF5%

5% 1/20W 20110K10K

5% 1/20W MF 201

10KMF1/20W5% 201

2011/20W5% MF100K 2011/20W5% MF10K

1/20W5% 201MF10K

5% 201MF100K20K

1/20W5% 201

1/20W5%

201MF

2.2K

1/20W

201MF

1K

19

41 19

8

41 19

RAMCFG0:H

10K

MF201

5%1/20W

10K

MF201

5%1/20W

RAMCFG1:HRAMCFG3:H

10K

MF201

5%1/20W

50 43 19 6

23

19

NO STUFF

1K

201

5%1/20W

19

43 19 6

23

100K

JTAG_TBT_TDO

1/20W

CRITICAL

ODD_PWR_EN_LAUD_IPHS_SWITCH_EN_PCHDPMUX_UC_IRQ

SMC_WAKE_SCI_L

SPIROM_USE_MLB

PCH_A20GATE

FW_PWR_EN_PCHTBT_SW_RESET_R_L

201

1/20W

=PP3V3_S0_PCH_GPIO=PP3V3_SUS_PCH_GPIO

10K

NO STUFF

NO STUFF

R21301

2

R21721

2

R21731

2

R21741

2

R21751

2

R217812

R21791

2

R2111 2 1

R2195 2 1

R2191 1 2

R2192 1 2

R2193 1 2

R2194 1 2

R2184 1 2

R2197 1 2

R2190 1 2

R2196 1 2

R2185 1 2

R2160 1 2

R2112 2 1

R2180 1 2

R2198 2 1

R2116 2 1

R2150 1 2

R2155 1 2

R2170 1 2

R2140 1 2

R2156 1 2

U1800

U3

W1

BC7

B40

K6

B44

K15C15G1

W12

K17

C43

K42A43

A45D40A41

H17

R6

C5

U40

AU12

AU10

U6

W6M6

AA3

AA1

W3

U10U1

N3

R3BC9

AK10AH12AK12AH10A4

A5

BJ51BL1BL3BL4

BL48BL49BL51C3C49C51

A48

D1D51E1

A49A51BH1

BH51BJ1BJ3

BJ49

Q21606

21

Q2162

3

12

Q2160

3

54

R21621

2

R21861

2

R21611

2

R21991

2

R21881

2

R21631

2

C2113 1

2

U21002

1

3

6

4

R21131

2

U21012

1

3

6

4

C2114 1

2

R21661

2

R21671

2

051-9277

2.8.0

21 OF 109

19 OF 73

5

5

16 19

19

18

34

19

43

17 16 7

7

19

19

25 23

19

22 20 7

8

10

36 25 19 18 17 16 7

8

8

8

19

19

23 19

42

50 43 19 6

19

8

23 19

41 19

19

19

19 6

41 19

19

23

19

34 19

36 25 18 17 7

19

NC

NC

VCC CORE

LVDS

(7 OF 10)

DMI

DFT/SPI

CRT

FDI

VCCIO

VCCCORE

VCC3_3

VCCADAC

VCCADMI_VRM

VCCAFDIPLL

VCCAFDI_VRM

VCCALVDS

VCCDFTERM

VCCDMI

VCCIO

VCCSPI

VCCTX_LVDS

VSSALVDS

VSSA_DAC

VCCAPLLEXP

VCCACLK

V_PROC_IO

VCCCLKDMI

VCCRTC

DCPSUSBYP

VCCDSW3_3

VCCAPLLDMI2

DCPRTC

VCCADPLLBVCCADPLLA

VCCDIFFCLKN

DCPSST

V5REF

V5REF_SUS

VCCAPLL_SATA3

VCCASW

VCCIO

VCCPUSB

VCCSSC

VCCSUS3_3

VCCSUSHDA

VCCVRM

DCPSUS

USB

SATA

PCI/GPIO/LPC

(8 OF 10)

HDA

CLK/MISC

CPU

RTC

NC

NCNC

NCNC

NCNC

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REVISION

BRANCH

6 3



AL24 left as NC per DG

PCH output, for decoupling only

NC-ed per DG

1.44 A Max, 474mA IdleVCCACLK pin left as NC per DG

PCH output, for decoupling only

55mA Max, 5mA Idle

10 mA Max, 1mA Idle

VCCAPLLDMI2 pin left as NC per DG

QP8D-MM915462

OMIT_TABLE

BGAPCH-PPT-MB-SFF-ES1PCH-PPT-MB-SFF-ES1

OMIT_TABLE

QP8D-MM915462BGA

PLACE_NEAR=U1800.N16:2.54mm

X5R-CERM

10%0.1UF16V

0201


0201

0.1UF10%16VX5R-CERM

PLACE_NEAR=U1800.U17:2.54mm16V

0.1UF10%

X5R-CERM0201

PLACE_NEAR=U1800.N16:2.54mm0201

1UF20%6.3VX5R


0.1UF10%16V

X5R-CERM0201

PCH POWERSYNC_MASTER=J11_MLB SYNC_DATE=09/30/2011

PP3V3_S0_PCH_VCC3_3_CLK_F

=PP3V3_S0_PCH_VCC3_3

=PP1V05_S0_PCH_VCC_CORE

PP3V3_S0_PCH_VCCA_DAC_F

=PP1V05_S0_PCH_VCC_DMI

=PP1V8R1V5_S0_PCH_VCCVRM=PP1V8_S0_PCH_VCC_DFTERM


=PP3V3_SUS_PCH_VCC_SPITP_1V05_S0_PCH_VCCAPLLEXP

=PP1V05_S0_PCH_VCCIO


=PP1V05_S0_PCH_VCCSSC


=PP5V_SUS_PCH_V5REFSUS


PP1V05_S0_PCH_VCCADPLLA_FPP1V05_S0_PCH_VCCADPLLB_F

MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

PPVOUT_G3_PCH_DCPRTCMIN_LINE_WIDTH=0.2 mm


TP_PPVOUT_PCH_DCPSUSBYP

=PPVRTC_G3_PCH

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V05_S0_PCH_V_PROC_IO




PPVOUT_S0_PCH_DCPSST

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mm

=PP5V_S0_PCH_V5REF

=PP3V3_SUS_PCH_VCCSUS

U1800

AB19AC19AF6BK28R40T39U37V37V39

U51

AU21

AU19

AP13AP15

AF33AG33

AP19

AB21AB23

AG25AG27AJ21AJ23AJ25AJ27AJ29AJ31AK29AK31

AC21

AK33AM33AM35

AC23AE21AE23AF21AF23AG21AG23

AJ13AJ15AK15AL13

AM23AU15AW16

AP27AR15AR23AR25AR27AR29AT13AU23AU25AU27AU29AU35AW34

AM21Y19

AF37AG37AG39AJ37

V50

AC33AE33

U1800

R15U15

U17

AR33AU31AU33V13

R10

N36

M37

AM17

AC51

BF40BD40

AM2

AW31

AB27AB29

U19U21V19V21V23V25Y21Y23Y25Y27

AB31

Y29Y31

AC27AC29AC31AE27AE29AE31R19

AP39

AC37AE37AE39

R12

AA13AB15AC13

N18R23R25U23U25

AC15AF15AG13AG15AJ17AK21

U27U29

N16

AC35

AM27N27R27R29R33R35U33U35

V31

AC39AE19AF17AW18AW21

C22321

2

C22331

2

C2222 1

2

C2231 1

2

C2210 1

2

051-9277

2.8.0

22 OF 109

20 OF 73

22

7 22

7 22

22

7 22

7 20

7 19 22

7 20

7 22

7 20 22

7 22 25

7 22

7 22

22

7 16 22

22

22

7 22

7 16 17

22

7 22

7 20 22

7 22

7 20

22

7 22

(9 OF 10)

VSSVSS

(10 OF 10)

VSSVSS

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SHEET


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DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



OMIT_TABLE

QP8D-MM915462

PCH-PPT-MB-SFF-ES1BGA

PCH-PPT-MB-SFF-ES1

OMIT_TABLE

QP8D-MM915462BGA


PCH GROUNDS

U1800AA7AA9

AB25

AP25AP29AP31AP33AP35AP37AP41AP43AP45AP48

AB33

AP50AR6AR8AR17AR19AR21AR31AR35AR37AT7

AB35

AT9AT11AT39AT41AT43AT45AU17AU37AV2AV4

AB37

AV48AV50AW7AW9AW11AW13AW23AW25AW27AW29

AB48

AW36AW39AW41AW43AW45AY10B6B10B14B18

AB50

B22B26B30B34B38B42B46BA7BA9BA11

AC7

BA13BA16BA18BA21BA23BA25BA27BA29BA31BA34

AC9

BA36BA39BA41BA43BA45BB2BB4BB48BB50BC11

AC11

BC13BC16BC18BC21

AC17

AA11

AC25AC41AC43AC45AE7AE9

AE11AE13AE15AE17

AA39

AE25AE35AE41AE43AE45AF2AF4AF8

AF19AF25

AA41

AF27AF29AF31AF35AF48AF50AG7AG9

AG11AG17

AA43

AG19AG29AG31AG35AG41AG43AG45AH2AJ7AJ9

AA45

AJ11AJ19AJ33AJ35AJ39AJ41AJ43AJ45AK2AK4

AB2

AK17AK19AK23AK25AK27AK35AK37AK48AK50AL7

AB4

AL9AL11AL39AL41AL43AL45AM15AM19AM25AM29

AB17

AM31AM37

AP2AP4AP7AP9AP11AP17AP21AP23

U1800BC23BC25BC27BC29BC31BC34BC36BC39BC41BC43BC45BD15BD24BE7BE9

BE11BE13BE16BE18BE21BE23BE25BE27BE29BE31BE34BE36BE39BE41BE43BE45BF2BF4

BF15BF24BF48BF50BH6

BH10BH14BH18BH22BH26BH28BH30BH32BH34BH38BH42BH44BH46BH48BK10BK14BK18BK22BK26BK30BK32BK34BK38BK42BK46

D6D10D14D18D22D26D30D34D38D42D46F2F4F48F50G7G9G11G13G16G18G21G23G25G27G29G31G34G36

G39G41G43J7J9J11J13J16J18J21J23J25J27J29J31J34J36J39J41J45K2K4K48K50L7L9L11L13L16L18L21L23L25L27L29L31L34L36L39L41L43L45N7N9N11N13N21N23N25N29N31N34N39N41N43N45P2P4P48P50R17R21R31R37T7T9T11T13T41T43T45U31U49V2V4V7V9V11V15V17V27V29V33V35V41V43V45V48Y15Y17Y33Y35Y37

051-9277

2.8.0

23 OF 109

21 OF 73

NC

NC

NC

NC

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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



68 mA

(PCH Reference for 5V Tolerance on PCI)

(PCH USB 1.05V PWR)

(PCH SUSPEND USB 3.3V PWR)

PCH V5REF_SUS Filter & Follower

NEED PWR CONSTRAINT

<1 MA

PCH V5REF Filter & Follower

1 mA S0-S5

1 mA

PCH VCCIO BYPASS

PCH VCCSUSHDA BYPASS

(PCH HD Audio 3.3V/1.5V PWR)

PCH VCCSUS3_3 BYPASS

PCH VCCCORE BYPASS(PCH 1.05V CORE PWR)

69 mA

(PCH DPLLA PWR)PCH VCCADPLLA Filter

PCH VCCADPLLB Filter(PCH DPLLB PWR)

(PCH Reference for 5V Tolerance on USB)

NEED PWR CONSTRAINT

10%

10%

10%

10%

10%

10%

10%

10%

10%

10% 10%

10%

10%

10%

10%

10%

10%

10%201

201

201

201

10V

10V

10V

PP1V05_S0_PCH_VCCCLKDMI_RMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MMVOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MMVOLTAGE=1.05VMAKE_BASE=TRUE

PP1V05_S0_PCH_VCCCLKDMI_F

PP3V3_S0_PCH_VCCA_DAC_FMAKE_BASE=TRUEMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V

PP1V05_S0_PCH_VCCADPLLB_FMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMVOLTAGE=1.05V

=PP3V3_S0_PCH


PP3V3_S0_PCH_VCC3_3_CLK_FMIN_LINE_WIDTH=0.4 MMVOLTAGE=3.3V


PP3V3_S0_PCH_VCC3_3_CLK_RMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V

=PP3V3_S0_PCH_VCC3_3_CLK



=PP1V05_S0_PCH_V_PROC_IO





=PP1V05_S0_PCH_VCC_DMI

=PP1V05_S0_PCH_VCC_DMI=PP5V_S0_PCH

=PP3V3_S0_PCH_VCCADAC


=PP5V_SUS_PCH=PP3V3_SUS_PCH




=PP3V3_SUS_PCH_VCC_SPI

=PP5V_SUS_PCH_V5REFSUS MIN_LINE_WIDTH=0.4 MMVOLTAGE=1.05VMIN_NECK_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCADPLLA_F


=PP1V05_S0_PCH_VCCSSC

=PP1V05_S0_PCH_VCC_CORE

PP5V_SUS_PCH_V5REFSUSMIN_NECK_WIDTH=0.25MMMAKE_BASE=TRUEVOLTAGE=5VMIN_LINE_WIDTH=0.3MM

=PP1V8_S0_PCH_VCC_DFTERM=PP1V05_S0_PCH


=PP5V_S0_PCH_V5REFMAKE_BASE=TRUE

PP5V_S0_PCH_V5REFMIN_LINE_WIDTH=0.3MMVOLTAGE=5VMIN_NECK_WIDTH=0.25MM


=PP1V05_S0_PCH_VCCADPLL

=PP3V3_S0_PCH_VCC3_3 PCH DECOUPLING


0

MF1/20W5%

1

5%MF-LF402

1/16W

10UH-0.12A-0.36OHM

0603

6.3V20%

CERM-X5R

10UF

0402-1

PLACE_NEAR=U1800.V37:2.54mmPLACE_NEAR=U1800.V37:2.54mm

X5R402

1UF

6.3V20%

0201X5R

1UF

PLACE_NEAR=U1800.AW16:2.54mm

PLACE_NEAR=U1800.AB19:2.54mm 0201X5R-CERM

0.1UF16V

PLACE_NEAR=U1800.BD40:2.54MM

0.1UF

0201

16VX5R-CERM

6.3V PLACE_NEAR=U1800.BD40:2.54MM

0201X5R

20%1UF

X5R-CERM

0.1UF

0201

16V


X5R6.3V

1UF20%

0201


0.1UF

X5R-CERM020116V

PLACE_NEAR=U1800.T39:2.54mm

0.1UF

X5R-CERM

PLACE_NEAR=U1800.BK28:2.54mm

16V0201

0201PLACE_NEAR=U1800.R40:2.54mm

X5R-CERM16V0.1UF

PLACE_NEAR=U1800.AF6:2.54mm 0201X5R-CERM

0.1UF16V

CERM20%

0.1UFPLACE_NEAR=U1800.M37:2.54mm

402

1/20W5%MF

10SOT-363BAT54DW-X-G


X5R

1UF

402

100

MF5%

1/20W SOT-363BAT54DW-X-G

0

MF1/20W5%

0402-2

10UF20%

6.3VCERM-X5R

PLACE_NEAR=U1800.U51:2.54mmPLACE_NEAR=U1800.U51:2.54mm

0.1UF

X5R-CERM16V

0201X5R-CERM

16V0201

0.01UF

PLACE_NEAR=U1800.U51:2.54mm

10UH-0.12A-0.36OHM

0603

CERM-X5RPLACE_NEAR=U1800.AP39:2.54mm

0402-2

10UF6.3V20%

PLACE_NEAR=U1800.AJ17:2.54mm 6.3V20%

0201X5R

1UF

6.3V1UF20%

0201X5R


PLACE_NEAR=U1800.AC37:2.54mm 6.3V0201X5R

1UF20%


6.3V20%

0201X5R

1UF

6.3V20%

0201X5R

1UF

PLACE_NEAR=U1800.AC35:2.54mm

PLACE_NEAR=U1800.AG13:2.54mm

6.3V20%

0201X5R

1UF


1UF

X5R0201

20%6.3V

0201X5R20%6.3V

PLACE_NEAR=U1800.AM23:2.54mm

1UF

020116V

X5R-CERM

0.1UFPLACE_NEAR=U1800.R12:2.54mm

X5R02016.3V1UF20%

PLACE_NEAR=U1800.Y19:2.54mm

020116V


0.1UF

X5R-CERM

20%6.3VX5R402

4.7UF


X5R-CERMPLACE_NEAR=U1800.AM17:2.54mm

16V0201

0.1UF


16V0201X5R-CERM

0.1UF

0.1UF


020116VX5R-CERM

16V0201X5R-CERM

0.1UFPLACE_NEAR=U1800.V31:2.54mm

X5R-CERM0201

PLACE_NEAR=U1800.AJ13:2.54mm0.1UF16V


0201

1UF

X5R20%6.3V


1UF

X5R0201

20%6.3V


1UF

X5R0201

20%6.3V


0402-2CERM-X5R

6.3V20%

10UF

1UF

X5R

PLACE_NEAR=U1800.AR25:2.54mm

0201

20%6.3V 6.3V

PLACE_NEAR=U1800.AU25:2.54mm

X5R0201

1UF20%

PLACE_NEAR=U1800.AR29:2.54mm

6.3V1UF20%

0201X5R


6.3V20%

0201X5R

1UF


10UF

0402-2

20%6.3V

CERM-X5R


1UF

X5R20%6.3V0201


X5R20%6.3V1UF

0201


1UF

X5R0201

20%6.3V


22UF20%

6.3VX5R-CERM1

0603

22UF


20%

0603X5R-CERM1

6.3V

4021/16WMF-LF

0

5%

MF-LF

0

402

5%1/16W

R24601 2

R24651 2

C2420 1

2

C2428 1

2

C24961

2

C24561

2

C24261

2

C2401 1

2

C24631

2

C24071

2

C24141

2

C24291

2

C2460 1

2

C24831

2

C24821

2

C24811

2

C24401

2

C24411

2

C24301

2

C24131

2

C24171

2

C2416 1

2

C24841

2

C24421

2

C2499 1

2

C24191

2

C24761

2

C24521

2

C24751

2

C24441

2

C24341

2

C24461

2

C24691

2

C24111

2

L24061 2

C2455 1

2

C2451 1

2

C2450 1

2

R24501 2

D24001

6

R2405

12

C2439 1

2

D24004

3

R2404

12

C2438 1

2

C24231

2

C24851

2

C24211

2

C24241

2

C24611

2

C24021

2

C24661

2

C24651

2

C24221

2

C24181

2

C24861

2

C2453 1

2

L24511 2

R24511 2

R24151 2

051-9277

2.8.0

24 OF 109

22 OF 73

5

2

20

20

20

16 7

20

20 7

7

20 7

25 20 7

20 7

22 20 7

22 20 7

20 7

22 20 7

22 20 7

22 20 7 25 7

7

22 20 7

7

7

22 20 7

16 7

20 16 7

20 7

20

20

22 20 7

20 7

20 7

20 19 7

16 7

22 20 7

20

22 20 7

7

22 20 7

IN

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

OUT

OUT

NC

IN

OUT

IN

BI

IN

OUT

OUT

OUT

IN

OUT

IN

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

IN

NC

OUT

OUT

OUTOUT

INOUT

INOUT

OUTOUT

BI

IN

IN

IN

IN

IN

BI

IN

OUT

IN

IN

IN

IN

IN

Apple Inc.


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DSIZEDRAWING NUMBER

REVISION

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6 3



NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

XDP SIGNALS

PCH Micro2-XDP

support chipset debug. Use with 921-0133 Adapter Flex to

518S0847

PCH SIGNALS

- ’Output’ non-XDP signals require pulls.

PCH/XDP Signal Isolation Notes:

- ’Output’ PCH/XDP signals require pulls.

OBSFN_B1OBSFN_B0

518S0847

CPU Micro2-XDP

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

OBSDATA_A3

OBSDATA_A0

OBSFN_C0

OBSDATA_C1

Use with 921-0133 Adapter Flex to

OBSDATA_B3

SCLTCK1

HOOK1

OBSDATA_A0

TCK0

OBSDATA_D1

OBSDATA_D2

OBSFN_C1

ITPCLK#/HOOK5

TRSTnTDO

TMSTDI

HOOK1

SDA

TCK0

HOOK3

OBSFN_D0

OBSDATA_C2

OBSDATA_C3OBSDATA_C2

OBSDATA_C1

OBSFN_D1OBSFN_D0

OBSFN_A0OBSFN_A1

OBSDATA_A1

OBSFN_B0

OBSDATA_A3

TDOTRSTn

support chipset debug.

OBSDATA_B0

OBSFN_B1

OBSFN_C1

OBSDATA_C0

OBSFN_C0

TCK1SCLSDA

HOOK3

VCC_OBS_AB

- For isolated GPIOs:

doc id 404081.

it is functional in that state, else add BOM options.

OBSDATA_B0

OBSFN_A1

OBSDATA_A1

OBSDATA_B3

VCC_OBS_CD

OBSDATA_B2

PWRGD/HOOK0

HOOK2VCC_OBS_AB

OBSDATA_A2

XDP_PRESENT#

ITPCLK/HOOK4

OBSDATA_D0

DBR#/HOOK7

OBSDATA_D3OBSDATA_D2

OBSDATA_D1

OBSDATA_B2

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3

TDITMS

OBSDATA_B1

PCH SIGNALS

OBSFN_A0

RESET#/HOOK6

OBSDATA_D3

OBSDATA_D0

OBSDATA_C3

OBSFN_D1

ITPCLK#/HOOK5VCC_OBS_CD

Non-XDP Signals

(R2560-R2563)

(R2520-R2537)

ITPCLK/HOOK4

1K series R on PCH Support Page

NOTE: This is not the standard XDP pinout.

OBSDATA_C0

XDP_PRESENT#

DBR#/HOOK7RESET#/HOOK6

and path to non-XDP signal destination.

Initially, stuffing both 33 and 0 ohms and validate whether

(R2564-R2567)

R252x, R253x, R257x and R259x should be placed where signal pathneeds to split between route from PCH to J2550

OBSDATA_A2

OBSDATA_B1

NOTE: This is not the standard XDP pinout.

HOOK2

PWRGD/HOOK0

10 25

10 66

10 66

10 66

10 66

10 66

9 23 66

9 66

9 66

25

16 23 69

16 23 69

16 23 69

9 66

16 23 69

9 66

23 44

23 44

10 23 25 66

23 41

17 25 41

10 23 66

10 23 25 66

9

10 23

16 66

16 66

10 23 66

10 23 66

1/16W5%

MF-LF

1K

NO STUFF

PLACE_NEAR=R1841.1:2.54mmXDP

5%0

1/20W MF

1/20W

PLACE_NEAR=R1840.1:2.54mm

MF0

XDP

5%

5% MF

XDP1K

1/20W

PLACE_NEAR=U1000.D44:2.54mm

XDP

5% 1/20W51

PLACE_NEAR=J2550.51:2.54mm

MF

5%51

XDP

MF1/20W


1/20W5%51

XDP

MF

PLACE_NEAR=U1800.M15:2.54mm

1/20W5%51

XDP

MF


PLACE_NEAR=U1000.B50:2.54mm MF1K

1/20W5%

XDP

0PLACE_NEAR=U4900.J3:2.54mm 1/20W5%

XDP

MF

PLACE_NEAR=U1000.B46:2.54mm

XDP

1/20W MF1K

5%

10 66

9 66

9 66

9 66

9 66

335% MF

XDP

1/20W1/20W5% MF

XDP

3333

MF

XDP

1/20W5%331/20W5% MF

XDP

331/20W5% MF

XDP

331/20W5% MF

XDP

331/20W5% MF

XDP

331/20W5% MF

XDP

33MF

XDP

1/20W5%

331/20W MF

XDP

5%335% MF

XDP

1/20W

19 23

8 19

19 23

19

9 23 66

8 16

16 23

19

19

18 23

18 23

18 23

18

18

18 23

XDP

1/20W5% MF0

PLACE_NEAR=U4900.J3:2.54mm

25 41 52 62

17 23 41

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

23

33MF

XDP

1/20W5%

33

26

16 25

19 25

01/20W5% MF

MF5%0

MF5% 1/20W0

MF5% 1/20W0

1/20W MF5%0

18 23

19 23

19 23

331/20W5% MF

XDP

331/20W5% MF

XDP33

1/20W5% MF

XDP

1/20W5% MF

XDP

33

1/20W5% MF33

XDP

331/20W MF

XDP

5%

19

18

18

0MF5%

9 66

16 23

18 37 62

18 23

8 19 19 23

1K MF5%5%

MF1/20W

1K

39 18 23

40 18 23

M-ST-SM1

CRITICALXDP_CONN

DF40RC-60DP-0.4V

DF40RC-60DP-0.4V

XDP_CONN

MF-LF

XDP_CPU:BPM

5% 1/16W0

MF-LF

XDP_CPU:BPM

05% 1/16W

PLACE_SIDE=BOTTOM1/16W

XDP_CPU:BPM

05% MF-LF

PLACE_SIDE=BOTTOM1/16W

XDP_CPU:BPM

05% MF-LF

MF-LF5%

XDP_CPU:CFG0

1/16W5%

XDP_CPU:CFG

0MF-LF1/16W

1/16W MF-LF

XDP_CPU:CFG

05%0

XDP_CPU:CFG

MF-LF1/16W5%

XDP

5% MF-LF1/16W330

511/16W MF-LF5%

XDP PLACE_NEAR=J2500.52:2.54mm

XDP

5% MF-LF1/16W51


511/16W MF-LF5%

XDP PLACE_NEAR=U1000.L55:2.54mm

PLACE_NEAR=U1000.L56:2.54mmXDP

5% MF-LF1/16W51

XDP

5% MF-LF1/16W51

PLACE_NEAR=U1000.J58:2.54mm

34 19 23

10 66

10 66

9 66

9 66

9 66

9 66

23 44

23 44

10 23 66

9 66

10 19 66

9 66

10 66

10 66

CPU & PCH XDPSYNC_DATE=10/17/2011SYNC_MASTER=J13_MLB_NON_POR

CPU_CFG<12>

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

XDP_CPU_TRST_L

=PP1V05_SUS_PCH_JTAG

XDP_PCH_TDO

XDP_DB3_SDCONN_STATE_CHANGE

XDP_FC0

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

CPU_CFG<17>

TP_XDP_PCH_HOOK5

XDP_DD1_JTAG_ISP_TCK

XDP_DC3_SATARDRVR_ENXDP_DC2_DP_AUXCH_ISOL

XDP_DC1_MXM_GOODXDP_DC0_ISOLATE_CPU_MEM_LXDP_DA0_USB_EXTA_OC_L

XDP_DA2_USB_EXTC_OC_L

TP_XDP_PCH_OBSFN_D<0>

XDP_DD0_DP_GPU_TBT_SEL

XDPPCH_PLTRST_LXDP_DBRESET_L

XDP_PCH_TMSXDP_PCH_TDI

TP_XDP_PCH_OBSFN_B<0>

XDP_DB1_USB_EXTD_OC_EHCI_L

XDP_PCH_PWRBTN_L

TP_XDPPCH_HOOK3TP_XDPPCH_HOOK2

=SMBUS_XDP_SDA=SMBUS_XDP_SCL

XDP_DA3_USB_EXTD_OC_L

TP_XDP_PCH_OBSFN_A<0>

XDP_DB2_AP_PWR_EN

XDP_CPU_CLK100M_N

CPU_CFG<5>

CPU_CFG<9>


CPU_CFG<0>

CPU_CFG<16>

XDP_BPM_L<0>XDP_BPM_L<1>

XDP_BPM_L<2>

CPU_CFG<8>

CPU_CFG<4>

CPU_CFG<6>

XDP_CPU_CLK100M_P

XDP_CPURST_LXDP_DBRESET_L

XDP_CPU_TMSXDP_CPU_TDI

XDP_CPU_PRDY_L


XDP_CPU_PWRBTN_L

=SMBUS_XDP_SDA=SMBUS_XDP_SCL

XDP_BPM_L<3>

XDP_CPU_PREQ_L

XDP_PCH_TMS

XDP_PCH_TCK

XDP_PCH_TDI

PM_PWRBTN_L

=PP3V3_S0_XDP

ITPXDP_CLK100M_P

XDP_FC0

XDP_DA3_USB_EXTD_OC_L

XDP_DB0_USB_EXTB_OC_EHCI_LXDP_DB1_USB_EXTD_OC_EHCI_L

XDP_DC1_MXM_GOOD

XDP_DD0_DP_GPU_TBT_SEL

XDP_FC1

XDP_DB2_AP_PWR_EN

ALL_SYS_PWRGD


XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

CPU_PWRGD

CPU_RESET_L

ITPXDP_CLK100M_N

XDP_BPM_L<7>

XDP_BPM_L<5>XDP_BPM_L<4>

XDP_VR_READY

PM_PCH_SYS_PWROK

XDP_DD2_AUD_IPHS_SWITCH_EN

TP_XDP_PCH_HOOK4

XDP_DD3_ENET_LOW_PWR

TP_XDP_PCH_OBSFN_D<1>

XDP_DB3_SDCONN_STATE_CHANGE

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_DA1_USB_EXTB_OC_L

=PPVCCIO_S0_XDP

XDP_PCH_TCK

CPU_CFG<7>

XDP_CPU_TDO

XDP_CPU_TDI

=PPVCCIO_S0_XDP

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_TRST_L

XDP_PCH_TDOTP_XDP_PCH_TRST_L

USB_EXTA_OC_LUSB_EXTB_OC_L

AP_PWR_EN

ISOLATE_CPU_MEM_L

DP_AUXCH_ISOL

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

XDP_DB2_PCH_GPIO10_AP_PWR_ENXDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL


XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

TP_XDP_PCH_OBSFN_A<1>

TP_XDP_PCH_OBSFN_B<1>

XDP_PCH_S5_PWRGD

CPU_CFG<13>

XDP_DA1_USB_EXTB_OC_LXDP_DA0_USB_EXTA_OC_L

XDP_DA2_USB_EXTC_OC_L

XDP_DC0_ISOLATE_CPU_MEM_L

XDP_DC2_DP_AUXCH_ISOLXDP_DC3_SATARDRVR_EN

XDP_DD1_JTAG_ISP_TCK

XDP_DD2_AUD_IPHS_SWITCH_ENXDP_DD3_ENET_LOW_PWR

=PP3V3_S5_XDP

XDP_FC1

SDCONN_STATE_RST_L

XDP_BPM_L<6>

XDP_OBSDATA_B<2>CPU_CFG<14>CPU_CFG<15>

XDP_CPU_TCK

CPU_CFG<1>

XDP_OBSDATA_B<1>XDP_OBSDATA_B<0>

XDP_OBSDATA_B<3>

CPU_CFG<0>

PM_PWRBTN_L

M-ST-SM1

CRITICAL

XDP_CPU_CFG<0>

XDP_CPU_PWRGD

1/20W

9

402

402402402402

402402402402

402

402

402

402

402

402

XDP XDP

XDPXDP

X7R-CERM0402

0.1UF

X7R-CERM0402

0.1UF

X7R-CERM0402

0.1UF

X7R-CERM0402

0.1UF

16V 16V

16V16V

201

201

201

201

201

201

201

201

201

201

201201201201

201

201201201201

201201

201

201

201201

201

201

201

201

201

201

201201

201

201

201201

10% 10%

10%10%

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_CPU_TDO

201

XDP

MF5% 1/20W1K


201MF5% 1/20W1KXDP_FC1_PCH_GPIO0

23

17

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_LXDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_LXDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DB2_PCH_GPIO10_AP_PWR_ENXDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_FC0_PCH_GPIO15

XDP_FC1_PCH_GPIO0

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SELXDP_DC3_PCH_GPIO19_SATARDRVR_ENXDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_DC1_PCH_GPIO35_MXM_GOODXDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

19 23

TBT_CIO_PLUG_EVENT_ISOL

1/20W

66

AUD_IPHS_SWITCH_EN_PCH

JTAG_ISP_TCK

1/20W2015% 1/20W MF

0201

0

MF1/20W5%

C25011

2

C2500 1

2

C2580 1

2

C25811

2

R25401

2

R2515 1 2

R2516 1 2

R2505 1 2

R2550 2 1

R2551 2 1

R2552 2 1

R2556 2 1

R2501 1 2

R2502 1 2

R2500 1 2

R2524 1 2

R2525 1 2

R2526 1 2

R2527 1 2

R2530 1 2

R2532 1 2

R2533 1 2

R2534 1 2

R2535 1 2

R2536 1 2

R2537 1 2

R2584 1 2

R2585 1 2

R2521 1 2

R2597 1 2R2596 1 2

R2572 1 2

R2570 1 2

R2576 1 2

R2528 1 2

R2529 1 2

R2520 1 2

R2522 1 2

R2523 1 2

R2531 1 2

R2575 1 2

R25801 2

R25811 2

R2590 1 2

R2592 1 2

J2500

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

78

9

J2550

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

6162

6364

78

9

R2560 1 2

R2561 1 2

R2562 1 2

R2563 1 2

R2564 1 2

R2565 1 2

R2566 1 2

R2567 1 2

R2504 1 2

R2510 1 2

R2511 1 2

R2512 1 2

R2513 1 2

R2514 1 2

R2574 1 2

051-9277

2.8.0

25 OF 109

23 OF 73

7

16 23 69

23

6

23

23

23

23

23 23

23

6

23

6

23

6

6

6

23

6

23

66

66

66

16 23 69

16 23 69

16 23 69

7

23

6

23

6

23

23

23

7 23

10 23 66

10 23 66

7 23

10 23 66

10 23 66

10 23 66

6

6

6

7

23

66

66

66

66

BI

BI

IN

VCC

GND

SELOE*

D+D-

Y+Y-

M+M-

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

NCNC

BI

BI

BI

BI

VDD33

PLLFILT

CRFILT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

XTALIN/CLKINXTALOUT

TEST

RESET*

THRM_PAD

USBDP_UP

NC

OSC3*

OCS1*OCS2*

USBDM_UP

RBIAS

VBUS_DET

NC

NCNC

USBDP_DN3/PRT_DIS_P3USBDM_DN3/PRT_DIS_M3



PRTPWR3/BC_EN3*

PRTPWR1/BC_EN1*PRTPWR2/BC_EN2*

SYM VER 1

Apple Inc.


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SHEET


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REVISION

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6 3



TABLE_5_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM


TABLE_5_ITEM

CRITICAL BOM OPTIONTABLE_5_HEAD

PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

1 1 Port 1, 2, and 3 are non removable

SMC Port

PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE

SDCARD(NA to K78)

IPUIPUIPU

TO LIO CONNECTOR

SEL=0 CHOOSE USB EHCI2 PORT

PCH GPIO60

BlueTooth

SEL=1 CHOOSE USB XHCI PORT

0 1 Port 1 is non removable0 0 All ports are removable

BOM TABLE

TO PCH XHCI

Trackpad/Keyboard

TO USB HUB

PCH PORT 1 (XHCI)

PCH PORT 9 (EHCI2)

TO TP/KB

TO CONNECT TP/KB TO PCH XHCI

LIO External D

1 0 Port 1 and 2 are non removable

NON_REM1 NON_REM0 DESCRIPTION

IPU

NOSTUFF R2611 & R2615, STUFF R2621 & R2622,R2616 & R2617

USB XHCI/EHCI2 PORT MUX FOR EXT B

NC_USB_HUB1_PRTPWR2

USB_SDCARD_P

USB_BT_P

USB_TPAD_HUB_P

USB_SMC_PUSB_SMC_N

USB_SDCARD_N

TP_USB_HUB1_PRTPWR1

NC_USB_HUB1_OCS2

NC_USB_HUB1_PRTPWR3

USB_HUB1_RBIAS

NC_USB_HUB1_OCS4NC_USB_HUB1_OCS3

USB_HUB_UP_N

USB_HUB1_CFG_SEL0

USB_HUB1_CFG_SEL1

USB_BT_N

USB_HUB_UP_P

USB_HUB1_TEST

USB_HUB_RESET_L

USB_EXTB_P

USB_TPAD_HUB_N

USB_EXTB_N

USB_EXTB_SEL_XHCI

USB_EXTB_EHCI_P

USB_HUB1_VBUS_DET

USB_HUB_RESET_L

=PP3V3_S3_USB_HUB

USB_EXTB_XHCI_N

=PP3V3_S3_USB_RESET

USB_SMC_N

USB_EXTB_EHCI_N

USB_EXTB_XHCI_P

USB_HUB1_NONREM0

USB_HUB1_NONREM1

USB_HUB1_XTAL1USB_HUB1_XTAL2

USB_SMC_P

USB_TPAD_HUB_P

=PP3V3_S3_USB_HUB

TP_USB_HUB1_OCS1

NC_USB_HUB1_PRTPWR4

PPUSB_HUB1_CRFILTMIN_LINE_WIDTH=0.4MMMIN_NECK_WIDTH=0.2MMVOLTAGE=1.8V

=PP3V3_S3_USB_HUB

USB_TPAD_HUB_N USB_TPAD_R_N

USB_EXTD_XHCI_PUSB_TPAD_R_P

USB_EXTD_XHCI_N

MIN_NECK_WIDTH=0.2MMVOLTAGE=1.8V

PPUSB_HUB1_PLLFILTMIN_LINE_WIDTH=0.4MM

=PP3V3_S3_USB_HUB

=PP3V3_S3_USBMUX

IC,USB2513B,USB 2.0,HUB CNTRL,3PRT,36QFN CRITICAL USBHUB2513B338S0923 1 U2600

USBHUB2512BCRITICALIC,USB2512B,USB 2.0 HUB CNTRL,36-QFN U26001338S0983

HUB_ALLREM HUB_NONREM1_0,HUB_NONREM0_0

HUB_1NONREM HUB_NONREM1_0,HUB_NONREM0_1

HUB_NONREM1_1,HUB_NONREM0_1HUB_3NONREM

HUB_2NONREM HUB_NONREM1_1,HUB_NONREM0_0

IC,USB2514B,USB 2.0,HUB CNTRL,4PRT U2600 USBHUB2514BCRITICAL338S0824 1

USB HUB & MUXSYNC_DATE=11/10/2011SYNC_MASTER=J13_MLB_NON_POR

HUB_NONREM1_0

5%10K

1/20WMF

201

1/20W

10K

HUB_NONREM0_0

5%

MF201

HUB_NONREM1_1

10K

MF

5%1/20W

201

HUB_NONREM0_1

5%10K

1/20WMF201

1/20W

10K

201MF

5%

5%1/20WMF

10K

201

1/20W5%10K

201MF

0.1UF

0201X5R-CERM16V10%

CRITICALOMIT_TABLE

QFNUSB2513B

NP0-C0G-CERM

CRITICAL

201

6.0PF+/-0.1PF

25V CRITICAL

1M

1/20W5%

MF 201

201

CRITICAL

25V

6.0PF+/-0.1PF

NP0-C0G-CERM

5%

100

1/20WMF201

68 37

4.7UF20%6.3V

X5R-CERM1402

BYPASS=U2600.23::5mm

BYPASS=U2600.5::5mm

20%4.7UF

6.3V

402X5R-CERM1

0201


16V10%

X5R-CERM

0.1UF

BYPASS=U2600.5::2mm

0.1UF10%

0201X5R-CERM

16V


X5R-CERM

0.1UF10%16V

0201

X5R-CERM


0.1UF16V10%

0201


0201

16V10%

X5R-CERM

0.1UF


10%

0201

16V

0.1UF

X5R-CERM

68 37

1UF

0201

20%6.3VX5R

X5R-CERM

0.1UF10%16V

0201

68 18

CRITICAL

MF201

12K1%1/20W

68 18

24.000MHZ-50PPM-6PF2.50X2.00MM-SM

CRITICAL

1/20WMF

5%

201

NOSTUFF

10K

NOSTUFF

10K

1/20W

201MF

5%

68 18

TPAD_PCH:YES

1/20W5%

0

201MF

68 18

TPAD_PCH:YES

201

0

5%1/20WMF

68 33

PLACE_NEAR=U2600.26:2.5MM0201

10%16V

X5R-CERM

0.1UF

10K

201

1/20W5%

MF

MF201

5%10K1/20W

TPAD_PCH:YES

201MF

10K5%

1/20W

TPAD_PCH:YES

68 24

68 24

MF

0

5%1/20W

201

TPAD_PCH:NO

MF

5%1/20W

0

201

TPAD_PCH:NO

68 33

10%0.1UF

X5R-CERM16V

0201

68 24

68 41 24

68 41 24

68 18

68 18

68 18

68 18

68 24

PI3USB102ZLETQFN

CRITICAL

16

68 40 6

68 40 6

0201

20%6.3VX5R

1UFC26181

2

C26171

2C26161

2

C26151

2

R26201

2

R26001

2

C2612 1

2

C2611 1

2

C2603 1

2

C2610 1

2

C2609 1

2

C2608 1

2

C2602 1

2

C2607 1

2

R26051 2

C26201

2R26301 2

C2619 1

2

U2600

14

25

89

20

21

131719

34

121618

35

26

24

22

28

11

37

1

3

6

30

2

4

7

31

27

5 1015232936

3332

R26071

2

R26061

2

R26031

2

R26011

2

R26041

2

R26021

2

U2660

67

3

45

8 10

9

21

C2663 1

2

R26151 2

R2611

1 2

R26171

2

R26161

2

R26121

2

C2604 1

2

R2621

1 2

R26221 2

R26191

2

R26181

2

Y2600

2 4

1 3

051-9277

2.8.0

26 OF 109

24 OF 73

24

24

24 7

7

68 41 24

68 41 24

24 7

24 7

68 49

24 7

7

OUT

OUT

OUT

PAD

+3.42V

VDD_25M

+V3.3A

VDDIO_25M_CVDDIO_25M_BVDDIO_25M_A

25MHZ_C25MHZ_B25MHZ_A

X1X2

VDD_RTC_OUT

THRMGND

32KHZ_A

NCNC

OUT

OUT

OUT

OUT

OUT

IN

NC

NC

OUT

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

IN

IN

BIIN

NC

OUT

OUT

08

Y1

Y2

GNDB2

VCC

A1B1A2

IN

IN

IN

OUT

D SG

D

SG

IN

OUT

D

G S

IN

OUT

OUT

OUT

OUT

OUT

IN

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GPIO Glitch Prevention

System RTC Power Source & 32kHz / 25MHz Clock Generator

No Coin-Cell: 3.3V S5

For SB RTC Power

Ground VDDIO of unused CLK

Buffered

DP_AUXIO_EN Inversion

Coin-Cell: VBAT (300-ohm & 10uF RC)

VTT voltage divider on CPU page

PCH Reset Button

Platform Reset ConnectionsUnbuffered

GreenClk 25MHz Power

create VDD_RTC_OUT.

Powered in S0

SB XTAL Power

TBT XTAL Power

available ~3.3V power

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.42V G3Hot (no RC)

No bypass necessary

Coin-Cell & No G3Hot: 3.3V S5

IPD = 9-50k

SMC controls strap enable to allow in-field control of strap setting.Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.

If high, ME is disabled. This allows for full re-flashing of SPI ROM.PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

VBAT and +V3.3A are

internally ORed to

+V3.3A should be first

to reduce VBAT draw.

outputs for power savings

PCH ME Disable Strap

Buffered

scrub for layout optimization

NOTE: 30 PPM crystal required

PCH S0 PWRGD

5%

12PF

0201

NP0-C0G-CERM

25V

5%

12PF

0201

NP0-C0G-CERM

25V

5%

5%

5%

5%

5%

5%

5% 5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

201

201

201

201

201

201

201 201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

CRITICAL

SMC_DELAYED_PWRGD

25.000MHZ-12PF-20PPM

AUD_IPHS_SWITCH_EN

=PP3V3_S0_SYSCLKGEN

=PPVDDIO_TBT_CLK

SYSCLK_CLK25M_TBT

=PP3V3_S5_PCHPWRGD

MAKE_BASE=TRUE

PM_PCH_PWROK

=PP3V3_S0_RSTBUF

PLT_RST_CPU_BUF_LMAKE_BASE=TRUE

=PP3V3_S0_RSTBUF

=PPVBAT_G3H_SYSCLK

XDP_DBRESET_L PM_SYSRST_L

=PP3V3_S0_SB_PM

=PPVRTC_G3_OUT

SPI_DESCRIPTOR_OVERRIDE_LS5V

BKLT_PLT_RST_L

SPI_DESCRIPTOR_OVERRIDE

MAKE_BASE=TRUE

LPCPLUS_RESET_L

CPU_RESET_L

DP_AUXIO_EN

DP_AUXCH_ISOL

SYS_PWROK_R

PCH_CLK33M_PCIOUT

LPC_CLK33M_LPCPLUS

PCH_CLK33M_PCIIN

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SB

LPC_CLK33M_SMC

SMC_LRESET_L

=PP5V_S0_PCH


HDA_SDOUT_R

SPI_DESCRIPTOR_OVERRIDE_L

AUD_IPHS_SWITCH_EN_PCH

=PP3V3_S0_SB_PM

=PP3V3_S5_SYSCLK

=PPVDDIO_S0_SBCLK

PM_PCH_APWROK

LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

=PP3V3_S0_PCH_GPIO

SYSCLK_CLK25M_X2_R

PM_S0_PGOOD

PM_PCH_SYS_PWROK

SYSCLK_CLK25M_X2

SYSCLK_CLK25M_X1

CPUIMVP_PGOOD

ALL_SYS_PWRGD

SDCARD_PLT_RST_L

=TBT_RESET_LTBT_RESET_LMAKE_BASE=TRUE

PLT_RESET_L

AP_RESET_L

PCA9557D_RESET_L

PLT_RST_BUF_L

XDPPCH_PLTRST_L

SSD_RESET_L

LPC_PWRDWN_L

PM_PCH_PWROK

=PP3V3_S5_PCHPWRGD

SYNC_MASTER=K21_MLB SYNC_DATE=07/29/2011

Clock (CK505) and Chipset Support25 17

MF1/20W

037

1K

1/20WMF

XDP

23

0

1/20WMF

36

0

1/20WMF

31

XDP

0

1/20W

MF

10K

MF1/20W

0201

X5R

1UF20%6.3V

6.3V

0201

20%

X5R

1UF

0201

0.1UF10%

X5R-CERM16V MF

1/20W

100K38 6

0

MF1/20W

SC70-HFMC74VHC1G08

CRITICAL

23 16

NO STUFF

1/20W

10K

MF

CRITICAL

SSM3K15FVSOD-VESM-HF

1/20WMF

10K

0.1UF

0201

10%16V

X5R-CERM

64

41

SSM6N37FEAPESOT563

SOT563SSM6N37FEAPE

69 16

1/20WMF

1K

1/20WMF

100K

23 19

43 41 17 6

16

40 6

34

MF-LF1/16W

0

NO STUFF

SILK_PART=SYS RESET402

0

1/20WMF

MF

1M

NO STUFF

1/20W

0

MF

1/20W

0201

X5R-CERM

0.1UF10%16V

0.1UF

0201

16V10%

X5R-CERM

66 23 10 41 17

57

62 52 41 23

1K

1/20W

MF

PLACE_NEAR=U1800.P12:7mm

MC74VHC1G08SC70-HF

16VX5R-CERM

10%0.1UF

0201

MC74VHC1G08

SC70-HF

0.1UF10%16V

0201X5R-CERM

0

MF1/20W

1/20WMF

3.0K

0

NO STUFF

MF1/20W


NO STUFF

1/20W

MF

0

17

25 17

41 23 17

69 18

69 18

69 18

PLACE_NEAR=U1800.G45:2.54MM:5.1mm

MF1/20W

22

MF1/20W

22PLACE_NEAR=U1800.E49:5.1mm

MF

22

1/20W

PLACE_NEAR=U1800.G51:5.1mm

69 16

69 43 6

69 41

0.1UF

16V

0201

10%

X5R-CERM

SC7074LVC1G07

100K

1/20WMF

0

1/20WMF

26 18

MF1/20W

33

1/20WMF

33

23 10

65

33

41

69 43 6

SM-3.2X2.5MM

SLG3NB148A

CRITICALTQFN

69 34

69 16

69 16

CRITICAL

74LVC2G08GT

SOT833

TBT_PWR_EN_PCH TBT_PWR_EN0201

0.1UF10%

X5R-CERM16V

=PP3V3_S3_PCH_GPIO

U2700

9

8

15

12

7 10

16

13

2

17

5

1

11

6

14

4

3

Y270524

13

C2705

12

C2706

1 2

R2783

1 2

R2781

1 2

R2793

1 2

R27801

2

U2780

2

3

5

4

C2780 1

2

R2727

1 2

R2726

1 2

R2729

1 2

R27611

2

R2763

1 2

R2762

1 2

R2760

1 2

C27601

2

U2760

3

2

1

4

5

C27501

2

U2750

3

2

1

4

5

R27501

2

C2722 1

2

C2724 1

2

R2705

1 2

R27061

2

R2782

1 2

R27971

2

U27521

52

6

4

8

7

3

R27201

2

R27211

2

Q2720

3

54

Q2720 6

2 1

C2739 1

2

R27301 2

Q2730 3

1 2

R27311

2

U2771

3

2

1

4

5

R2772

1 2R27701

2

C2771 1

2

C27521

2

C27021

2

C27101

2

R27951

2R2796

1 2

R2771

1 2

R2773

1 2

R2789

1 2

R2788

1 2

051-9277

2.8.0

27 OF 109

25 OF 73

1

7

7

25 7

25 7

25 7

7

25 7

7

22 7

22 20 7

25 7

7

7

36 19 18 17 16 7

69

42 41 36

69

69

18 7

25 7

IN

IN

D

SG

D

S G

D

SG

D

SG

OUT

OUT

DSG

D SG

IN

IN

OUT

G

D

S

D

SG

IN

D

SG

IN

S0_READY

ISOL*

S0_EN

S3_EN

RST_IN*

GNDTHRM

VDD

VTT_EN

VDDIO_EN

RST_OUT*

PAD

OUT

OUT

IN

IN

IN

IN

OUT

IN

D

SG

D

S G

OUT

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Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

3 0 0 0 1 X 1 0 0

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

S3

S0

2 0 0 1 1 1 1 0 1

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well1V5 S0 "PGOOD" for CPU

75mA max load @ 0.75V

60mW max power

to

to

S0

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

MEMVTT ClampEnsures CKE signals are held low in S3

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

6 0 1 1 1 1 1 1 1

5 0 1 1 1 0 (*) 1 1 1

4 0 0 1 1 X 1 0 1

1 0 1 1 1 1 1 1 1

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

26 37 41 49 62

10K5%1/20WMF

CPUMEM_SLG:NO

18 25 26

SOT563SSM6N37FEAPE

CPUMEM_SLG:NO

SSM6N37FEAPE

MF

100K1/20W

5%

CPUMEM_SLG:NO

SOT563SSM6N37FEAPE

CPUMEM_SLG:NO

CPUMEM_SLG:NO

100K5%

1/20WMF

SSM6N37FEAPE

CPUMEM_SLG:NO

SOT563

26 61

26 27 28 29 30

SOT563SSM6N37FEAPE

CPUMEM_SLG:NO

SOT563SSM6N37FEAPE

CPUMEM_SLG:NO

23 26

5%MF

100K

CPUMEM_SLG:NO

1/20W

10

10 17 66

10K5%1/20WMF

CPUMEM_SLG:NO

MF-LF603

5%1/10W

10

SOT-563

CRITICAL

DMB53D0UV

MF1/20W5%10K

SOT-563DMB53D0UV

SSM6N37FEAPESOT563

100K5%MF

1/20W

17 26 41 62

SOT563SSM6N37FEAPE

MF1%

27.4K1/20W

8 56

0.1UF

0201

X5R-CERM

0

5%1/20WMF

CPUMEM_SLG:NO

TQFNSLG4AP022

CPUMEM_SLG:YES

8 26

26 27 28 29 30

23 26

18 25 26

17 26 41 62

17 26 37 41 49 62

26 61

10 26

X5R6.3V

0.1UFCPUMEM_SLG:YES

SOT563

CPUMEM_SLG:NO

SSM6N37FEAPE

43.2K1%

MF

1K5%1/20WMF

SOT563SSM6N37FEAPE

CPUMEM_SLG:NO

8 26

CPU Memory S3 Support


ISOLATE_CPU_MEM_L_R

VTTCLAMP_EN

=PP1V5_S3_MEMRESET

MEM_RESET_L

PM_MEM_PWRGD_L

PM_MEM_PWRGD


=PPVTT_S0_VTTCLAMP

=PP3V3_S3_MEMRESET

MEM_RESET_L

P1V5CPU_EN

=DDRVTT_EN

=PP5V_S3_MEMRESET

VTTCLAMP_LPLT_RESET_L

ISOLATE_CPU_MEM_L

P1V5CPU_EN

PM_SLP_S4_L

=PP5V_S3_MEMRESET

MEMVTT_EN_L

P1V5CPU_EN_L

MEMVTT_EN

MEMVTT_EN

PM_SLP_S3_L

CPU_MEM_RESET_LMAKE_BASE=TRUE

PM_SLP_S3_L

ISOLATE_CPU_MEM_L

=MEM_RESET_L


P1V5_S0_DIV

PM_SLP_S4_L

CRITICAL

1/20W

201

201

201201

201

201

201

201

201

201

201

201

NO STUFF

NO STUFF

X7R-CERM0201

1000PF

X7R-CERM0201

1000PF

=MEM_RESET_L

MEMRESET_ISOL_LS5V_L

PLT_RESET_L

CPUMEM_SLG:NO

SOT563

=PP3V3_S3_MEMRESET

26

17

16V

16V

16V

10%

10%

10%

10%

NO STUFF

16V

X7R-CERM

0402

0.047UF10%

R28051

2

Q2805 6

2 1

Q28053

54

R28101

2

Q2810 6

2 1

Q28103

54

R28011

2

Q2800 3

5 4

R28021

2

Q2800 6

2 1

Q2815

3

54

Q2815

6

21

R28151

2

R28501

2

Q28206

2

1

R28221

2

Q28205

3

4

C2820 1

2

Q2850 6

2 1

C2851 1

2

R28511

2

Q2850 3

5 4

R28201

2

C2816 1

2

C2817 1

2

R289012

U2800

5

9

7

8

3

1

6

11

10

4

2

C2800 1

2

R28211

2

R28161

2

051-9277

2.8.0

28 OF 109

26 OF 73

31

7

7

7

7 26

7 26

7 26

7 26

7 10 12 15

NF_DQ6NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3A4

A6

A10/AP

A11

A12/BC*A13

A14

BA0

BA1BA2

CKE1

RAS*

WE*CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3A4

A6

A10/AP

A11

A12/BC*A13

A14

BA0

BA1BA2

CKE1

RAS*

WE*CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0ODT1

RESET*

ZQ0

A0

A2A3

A4

A6

A10/AP

A11A12/BC*

A13A14

BA0BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0DQ1

DQ2DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2A3

A4

A6

A10/APA11

A12/BC*

A13A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*CS0*

ZQ1DQ0

DQ1

DQ2DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

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NCNC

NC

NCNC

NC

NC

NC

A14/A15 FOR 2G/4G MONO ONLYCS1 IS FOR 2G DDP RANK CONTROL

240

MF 1% 1/20W 2012011/20W1%MF

240

1/20WMF

240

2011%

240

2011/20W1%MF

MT41K1G4

512MX8-4GBIT-DDR3-1600

OMIT_TABLEFBGA-9P5X11P65-COMBO

MT41K1G4



MT41K1G4





MT41K1G4

201

4VCERM-X5R-1

0.47UF20%

201

4VCERM-X5R-1

0.47UF20%

201

4VCERM-X5R-1

0.47UF20%

201

4VCERM-X5R-1

0.47UF20%

201

20%0.47UF

CERM-X5R-14V

201

4VCERM-X5R-1

0.47UF20%

201

20%0.47UF

CERM-X5R-14V

201

4VCERM-X5R-1

0.47UF20%

201

4VCERM-X5R-1

0.47UF20%

201

20%0.47UF

CERM-X5R-14V

201

4VCERM-X5R-1

0.47UF20%

201

4VCERM-X5R-1

0.47UF20%

201

240

1/20W1%MF

201

240

1/20W1%MF

201

240

1/20W1%MF

201

240

1/20W1%MF


DDR3 DRAM CHANNEL A (0-31)

MEM_A_A<15>

MEM_A_A<15>

MEM_A_A<14>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_CLK_P<0>

MEM_A_BA<0>


MEM_A_A<9>

MEM_A_A<0>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_CLK_P<0>

MEM_A_DQS_P<0>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_DQS_N<0>

MEM_A_DQ<4>

MEM_A_CS_L<0>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CKE<1>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<6>

MEM_A_A<3>

MEM_A_A<2>

MEM_RESET_L

MEM_A_ODT<0>

MEM_A_A<1>

MEM_A_DQ<5>

MEM_A_DQ<0>

MEM_A_DQ<6>

MEM_A_A<7>

MEM_A_A<9> MEM_A_DQS_P<1>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_DQS_N<1>

MEM_A_DQ<12>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<8>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CKE<1>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<0>

MEM_RESET_L

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_A<1>

MEM_A_DQ<10>

MEM_A_DQ<13>

MEM_A_DQ<9>

MEM_A_DQ<11>

MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_CLK_P<0>

MEM_A_DQS_P<2>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_DQS_N<2>

MEM_A_DQ<20>

MEM_A_DQ<23>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CKE<1>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<0>

MEM_RESET_L

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_A<1>

MEM_A_DQ<22>

MEM_A_DQ<16>

MEM_A_DQ<21>

MEM_A_DQ<18>

MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_CLK_P<0>

MEM_A_DQS_P<3>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_DQS_N<3>

MEM_A_DQ<30>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CKE<1>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<0>

MEM_RESET_L

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_A<1>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<31>

MEM_A_DQ<29>

MEM_A_DQ<2> MEM_A_DQ<17>

MEM_A_DQ<19>

=PP1V5_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A =PP1V5_S3_MEM_A


PP0V75_S3_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A =PP1V5_S3_MEM_A


=PP1V5_S3_MEM_A

MEM_A_DQ<26>

MEM_A_DQ<7>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<8>

MEM_A_A<10>

MEM_A_CS_L<1>


MEM_A_ZQ0

MEM_A_ZQ4MEM_A_ZQ1

MEM_A_ZQ5MEM_A_ZQ2

MEM_A_ZQ6

MEM_A_ZQ3

MEM_A_ZQ7

MEM_A_ODT<1>

MEM_A_DQ<1>

MEM_A_DQ<3>

MEM_A_ZQ5

MEM_A_ZQ6

MEM_A_ZQ7

MEM_A_ZQ4

R29301 2R29201 2R29101 2

R29001 2

U2930

K3L7

H7

M7K7

N3

N7J7

L3

K2L8

L2M8

M2

N8M3

J2K8

J3

G3

F7G7

G9F9

H2H1

B7

B3C7

C2

C8

C3

D3

A3

79

8081

82

E3

E8

D2E7

A7

G1

F1

F3

N2

A2A9

D7

G2G8

K1

K9M1

M9

B9

C1E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U2920

K3L7

H7

M7K7

N3

N7J7

L3

K2L8

L2M8

M2

N8M3

J2K8

J3

G3

F7G7

G9F9

H2H1

B7

B3C7

C2

C8

C3

D3

A3

79

8081

82

E3

E8

D2E7

A7

G1

F1

F3

N2

A2

A9D7

G2

G8K1

K9M1

M9

B9

C1

E2E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U2910

K3

L7

H7M7

K7

N3N7

J7

L3K2

L8L2

M8

M2N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2H1

B7

B3

C7

C2C8

C3

D3

A3

7980

81

82

E3

E8D2

E7

A7

G1

F1

F3

N2

A2

A9

D7G2

G8K1

K9

M1M9

B9C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U2900

K3

L7

H7

M7

K7N3

N7

J7

L3

K2

L8L2

M8M2

N8

M3

J2

K8J3

G3

F7

G7

G9

F9

H2H1

B7

B3

C7C2

C8

C3

D3

A3

79

80

8182

E3E8

D2

E7

A7

G1

F1

F3

N2

A2

A9D7

G2

G8K1

K9

M1M9

B9C1

E2E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8H9

C2900 1

2

C2901 1

2

C2902 1

2

C2910 1

2

C2911 1

2

C2912 1

2

C2920 1

2

C2921 1

2

C2922 1

2

C2930 1

2

C2931 1

2

C2932 1

2

R29011 2

R29111 2

R29211 2

R29311 2

27 OF 73

29 OF 109

051-9277

2.8.0

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67 11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 67

11 27 28 32 67

11 27 28 32 67

11 67

11 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 27 28 32 67

11 67

11 67

11 67

11 27 28 32 67

11 27 28 32 67 11 67

11 27 28 32 67

11 27 28 32 67

11 67

11 67

11 67

11 67

11 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 67

11 67

11 67

11 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 67

11 27 28 32 67

11 27 28 32 67

11 67

11 67

11 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 67

11 67

11 67

11 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 67

11 27 28 32 67

11 27 28 32 67

11 67

11 67

11 67

11 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 67

11 67

11 67

11 67

11 67 11 67

11 67

7 27 28 32

27 28 31 67

27 28 31 67 7 27 28 32

27 28 31 67

27 28 31 67 27 28 31 67 7 27 28 32

27 28 31 67

7 27 28 32

11 67

11 67

27 28 31 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

27 28 31 67

11 27 28 32 67

11 67

11 67

27

27

27

27

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0ODT1

RESET*

ZQ0

A0

A2A3

A4

A6

A10/AP

A11A12/BC*

A13A14

BA0BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0DQ1

DQ2DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8A9

A5

A7

A15

NF_DQ6NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3A4

A6

A10/AP

A11A12/BC*

A13

A14

BA0

BA1BA2

CKE1

RAS*

WE*CAS*

CS1*

CS0*

ZQ1

DQ0DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3A4

A6

A10/AP

A11A12/BC*

A13

A14

BA0

BA1BA2

CKE1

RAS*

WE*CAS*

CS1*

CS0*

ZQ1

DQ0DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/APA11

A12/BC*A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*CS0*

ZQ1DQ0

DQ1DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



NC

NC

NCNC

NC

NCNC

A14/A15 FOR 2G/4G MONO ONLY

NCNC

CS1 IS FOR 2G DDP RANK CONTROL

NC

NC

NC

2011/20W1%MF

240

1/20W1%MF

240

201

1/20W1%MF

240

201

OMIT_TABLE

MT41K1G4


FBGA-9P5X11P65-COMBO

MT41K1G4



MT41K1G4



MT41K1G4



OMIT_TABLE

201

4VCERM-X5R-1

0.47UF20%

1/20W1%MF

240

201

20%0.47UF

CERM-X5R-14V

201

4VCERM-X5R-1

0.47UF20%

2014V

CERM-X5R-1

0.47UF20%

201

4VCERM-X5R-1

0.47UF20%

201

4VCERM-X5R-1

0.47UF20%

2014V

CERM-X5R-1

0.47UF20%

201

4VCERM-X5R-1

0.47UF20%

201

4VCERM-X5R-1

0.47UF20%

201

20%0.47UF

CERM-X5R-14V

201

4VCERM-X5R-1

0.47UF20%

201

20%0.47UF

CERM-X5R-14V

201

MF 1% 1/20W

240

201

MF 1% 1/20W

240

201

MF 1% 1/20W

240

201

MF 1% 1/20W

240

201

DDR3 DRAM CHANNEL A (32-63)


MEM_A_ZQ12

MEM_A_ZQ8

MEM_A_A<15>

MEM_A_A<7>

MEM_A_A<5>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_CLK_P<0>

MEM_A_DQS_P<4>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_DQS_N<4>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_DQ<39>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CKE<1>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<6>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<0>

MEM_RESET_L

MEM_A_ODT<1>

MEM_A_ODT<0>

=PP1V5_S3_MEM_A


PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<1>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<32>

MEM_A_DQ<38>

MEM_A_ZQ15

MEM_A_ZQ11

MEM_A_ZQ14

MEM_A_ZQ10MEM_A_ZQ13

MEM_A_ZQ9

MEM_A_A<14>

MEM_A_ZQ15

MEM_A_ZQ14

MEM_A_ZQ13

MEM_A_ZQ12


=PP1V5_S3_MEM_APP0V75_S3_MEM_VREFDQ_A=PP1V5_S3_MEM_APP0V75_S3_MEM_VREFDQ_A


MEM_A_A<2>

MEM_A_CLK_P<0>

MEM_A_BA<2>

MEM_A_BA<1>


=PP1V5_S3_MEM_APP0V75_S3_MEM_VREFDQ_A

MEM_A_ODT<1>

MEM_A_A<14>

MEM_A_BA<1>

MEM_A_DQ<47>

MEM_A_DQ<40>

MEM_A_DQ<45>

MEM_A_A<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_RESET_L

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_CKE<1>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQS_N<5>

MEM_A_CLK_N<0>

MEM_A_DQS_P<5>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<7>MEM_A_DQ<54>

MEM_A_DQ<49>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_A<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_RESET_L

MEM_A_A<0>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<14>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<55>

MEM_A_DQ<48>

MEM_A_DQS_N<6>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_DQS_P<6>

MEM_A_CLK_P<0>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<7>

MEM_A_CKE<0>

MEM_A_BA<0>


MEM_A_DQ<46>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<62>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<58>

MEM_A_A<1>

MEM_A_ODT<0>

MEM_RESET_L

MEM_A_A<0>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<6>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_BA<0>

MEM_A_BA<2>

MEM_A_CKE<1>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_DQ<59>

MEM_A_DQ<57>

MEM_A_DQ<63>

MEM_A_DQ<56>

MEM_A_DQS_N<7>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_DQS_P<7>

MEM_A_CLK_P<0>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<5>

MEM_A_A<7>

MEM_A_A<15>

R30301 2R30201 2R30101 2

R30001 2

U3010

K3

L7

H7M7

K7

N3N7

J7

L3K2

L8L2

M8

M2N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2H1

B7

B3

C7

C2C8

C3

D3

A3

7980

8182

E3

E8D2

E7

A7

G1

F1

F3

N2

A2

A9

D7G2

G8K1

K9

M1M9

B9C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3020

K3L7

H7

M7K7

N3N7

J7

L3K2

L8

L2M8

M2

N8M3

J2K8

J3

G3

F7G7

G9F9

H2H1

B7

B3C7

C2C8

C3

D3

A3

79

8081

82

E3

E8

D2E7

A7

G1

F1

F3

N2

A2

A9D7

G2

G8K1

K9M1

M9

B9

C1

E2E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3030

K3L7

H7

M7K7

N3N7

J7

L3K2

L8

L2M8

M2

N8M3

J2K8

J3

G3

F7G7

G9F9

H2H1

B7

B3C7

C2C8

C3

D3

A3

79

8081

82

E3

E8

D2E7

A7

G1

F1

F3

N2

A2

A9

D7G2

G8

K1K9

M1

M9

B9C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3000

K3

L7

H7

M7

K7N3

N7J7

L3

K2L8

L2

M8M2

N8

M3

J2

K8J3

G3

F7

G7

G9

F9

H2H1

B7

B3

C7C2

C8

C3

D3

A3

79

80

8182

E3E8

D2

E7

A7

G1

F1

F3

N2

A2

A9D7

G2

G8K1

K9

M1M9

B9C1

E2E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8H9

C3000 1

2

C3001 1

2

C3002 1

2

C3010 1

2

C3011 1

2

C3012 1

2

C3020 1

2

C3021 1

2

C3022 1

2

C3030 1

2

C3031 1

2

C3032 1

2

R30011 2

R30111 2

R30211 2

R30311 2

051-9277

2.8.0

30 OF 109

28 OF 73

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 67

11 27 28 32 67

11 27 28 32 67

11 67

11 67

11 67

11 67

11 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 27 28 32 67

7 27 28 32

27 28 31 67

27 28 31 67

11 27 28 32 67

11 67

11 67

11 67

11 67

11 27 28 32 67

28

28

28

28

27 28 31 67

7 27 28 32 27 28 31 67 7 27 28 32 27 28 31 67

27 28 31 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

27 28 31 67

7 27 28 32 27 28 31 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 67

11 67

11 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 67

11 67

11 67

11 27 28 32 67

11 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67 11 67

11 67

11 67

11 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 67

11 67

11 67

11 67

11 67

11 27 28 32 67

11 27 28 32 67

11 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67 11 27 28 32 67

11 67

11 67

11 67

11 67

11 67

11 67

11 67

11 27 28 32 67

11 27 28 32 67

26 27 28 29 30

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 67

11 67

11 67

11 67

11 67

11 27 28 32 67

11 27 28 32 67

11 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

11 27 28 32 67

NF_DQ6

NF_DQ7

NF_DQ5NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3

A4

A6

A10/APA11

A12/BC*A13

A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*CS0*

ZQ1DQ0

DQ1DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0ODT1

RESET*

ZQ0

A0

A2A3

A4

A6

A10/AP

A11A12/BC*

A13A14

BA0BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0DQ1

DQ2DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8A9

A5

A7

A15

NF_DQ6NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3A4

A6

A10/AP

A11A12/BC*

A13

A14

BA0

BA1BA2

CKE1

RAS*

WE*CAS*

CS1*

CS0*

ZQ1

DQ0DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3A4

A6

A10/AP

A11A12/BC*

A13

A14

BA0

BA1BA2

CKE1

RAS*

WE*CAS*

CS1*

CS0*

ZQ1

DQ0DQ1

DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




NC

NCNC

NC NCNC

NCNC

NCNC

NCNC


MF 1% 1/20W

240

2011%MF

240

1/20W 2011%MF

240

1/20W 2011/20WMF 1%

240

201



MT41K1G4 FBGA-9P5X11P65-COMBO

MT41K1G4

OMIT_TABLE


MT41K1G4

OMIT_TABLE



MT41K1G4


FBGA-9P5X11P65-COMBOOMIT_TABLE

20%0.47UF

CERM-X5R-14V

201

20%0.47UF

CERM-X5R-14V

201

20%0.47UF

CERM-X5R-14V

201

20%0.47UF

CERM-X5R-14V

201CERM-X5R-1

4V20%

0.47UF

201 201

4VCERM-X5R-1

0.47UF20%

4VCERM-X5R-1

0.47UF20%

201CERM-X5R-1

0.47UF

4V20%

201

20%0.47UF

CERM-X5R-14V

201 CERM-X5R-14V

20%

201

0.47UF

4V20%

0.47UF

CERM-X5R-1201

20%0.47UF

4VCERM-X5R-1

201

1/20WMF 1% 201

240

1/20W

240

1% 201MF

240

1% 1/20W 201MF

240

MF 2011/20W1%

DDR3 DRAM CHANNEL B (0-31)


MEM_B_ZQ7

MEM_B_ZQ3

MEM_B_ZQ6

MEM_B_ZQ2MEM_B_ZQ5

MEM_B_ZQ1MEM_B_ZQ4

MEM_B_ZQ0

MEM_B_DQ<7>

MEM_B_DQ<1>

MEM_B_CS_L<1>

MEM_B_ZQ6

MEM_B_ZQ5

MEM_B_ZQ7

MEM_B_ZQ4

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<14>

MEM_B_A<10>

MEM_B_ODT<0>

=PP1V5_S3_MEM_BPP0V75_S3_MEM_VREFDQ_B



PP0V75_S3_MEM_VREFDQ_B

MEM_B_DQ<16>

MEM_B_DQ<18>

MEM_B_DQ<20>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<23>

MEM_B_DQ<17>

MEM_B_DQ<19>

MEM_B_DQS_N<2>

MEM_B_A<9>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_DQS_P<2>MEM_B_A<10>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_RESET_L

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<30>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<25>

MEM_B_DQ<31>

MEM_B_DQ<24>

MEM_B_DQS_N<3>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_DQS_P<3>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<7>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_RESET_L

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<12>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<0>

MEM_B_DQ<9>

MEM_B_DQ<15>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<8>

MEM_B_DQS_N<1>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_DQS_P<1>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_ODT<1>

MEM_RESET_L

MEM_B_A<2>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<5>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<6>

MEM_B_DQ<0>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<14>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_A<15> MEM_B_A<15>

MEM_B_A<13>

MEM_B_A<15>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<11>

MEM_B_A<9>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_CKE<1>

MEM_B_DQ<2>

MEM_RESET_L

MEM_B_DQ<29>

MEM_B_DQ<26>


MEM_B_A<11>


=PP1V5_S3_MEM_B


MEM_B_DQ<10>

R3130 1 2R3120 1 2R3110 1 2

R3100 1 2

U3100

K3

L7

H7

M7

K7N3

N7J7

L3

K2L8

L2

M8M2

N8

M3

J2

K8J3

G3

F7

G7

G9

F9

H2H1

B7

B3

C7C2

C8

C3

D3

A3

79

80

8182

E3E8

D2

E7

A7

G1

F1

F3

N2

A2

A9D7

G2

G8K1

K9

M1M9

B9C1

E2E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8H9

U3110

K3

L7

H7M7

K7

N3N7

J7

L3K2

L8L2

M8

M2N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2H1

B7

B3

C7

C2C8

C3

D3

A3

7980

8182

E3

E8D2

E7

A7

G1

F1

F3

N2

A2

A9

D7G2

G8K1

K9

M1M9

B9C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3120

K3L7

H7

M7K7

N3N7

J7

L3K2

L8

L2M8

M2

N8M3

J2K8

J3

G3

F7G7

G9F9

H2H1

B7

B3C7

C2C8

C3

D3

A3

79

8081

82

E3

E8

D2E7

A7

G1

F1

F3

N2

A2

A9D7

G2

G8K1

K9M1

M9

B9

C1

E2E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3130

K3L7

H7

M7K7

N3N7

J7

L3K2

L8

L2M8

M2

N8M3

J2K8

J3

G3

F7G7

G9F9

H2H1

B7

B3C7

C2C8

C3

D3

A3

79

8081

82

E3

E8

D2E7

A7

G1

F1

F3

N2

A2A9

D7

G2G8

K1

K9M1

M9

B9

C1E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

C3100 1

2

C3101 1

2

C3102 1

2

C3110 1

2

C3111 1

2

C3112 1

2

C3120 1

2

C3121 1

2

C3122 1

2

C3130 1

2

C3131 1

2

C3132 1

2

R31011 2

R31111 2

R31211 2

R31311 2051-9277

2.8.0

31 OF 109

29 OF 73

11 67

11 67

11 29 30 32 67

29

29

29

29

11 67

11 67

29 30 31

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

7 29 30 32 29 30 31

29 30 31

7 29 30 32 29 30 31

29 30 31

11 67

11 67

11 67

11 67

11 67

11 67

11 67

11 67

11 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 67 11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 67

11 67

11 67

11 67

11 67

11 67

11 67

11 29 30 32 67

11 29 30 32 67

11 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 67

11 67

11 67

11 67

11 67

11 67

11 67

11 67

11 29 30 32 67

11 29 30 32 67

11 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 67

11 67

11 67

11 67

11 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67 11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 67

26 27 28 29 30

11 67

11 67

7 29 30 32 29 30 31

11 29 30 32 67

29 30 31

7 29 30 32

29 30 31

11 67

NF_DQ6NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3A4

A6

A10/AP

A11

A12/BC*A13

A14

BA0

BA1BA2

CKE1

RAS*

WE*CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2A3

A4

A6

A10/APA11

A12/BC*

A13A14

BA0

BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*CS0*

ZQ1DQ0

DQ1

DQ2DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

NF_DQ6

NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0ODT1

RESET*

ZQ0

A0

A2A3

A4

A6

A10/AP

A11A12/BC*

A13A14

BA0BA1

BA2

CKE1

RAS*

WE*

CAS*

CS1*

CS0*

ZQ1

DQ0DQ1

DQ2DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8A9

A5

A7

A15

NF_DQ6NF_DQ7

NF_DQ5

NF_DQ4

A1

VREFDQ

VREFCA VDD VDDQ

ODT0

ODT1

RESET*

ZQ0

A0

A2

A3A4

A6

A10/AP

A11

A12/BC*A13

A14

BA0

BA1BA2

CKE1

RAS*

WE*CAS*

CS1*

CS0*

ZQ1

DQ0

DQ1DQ2

DQ3

DQS*

DM/TDQS

NF_TDQS*

NC

VSS

CK*

CKE0

DQS

CK

VSSQ

A8

A9

A5

A7

A15

Apple Inc.


124578

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PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




NCNC

NC

NCNC NC

NCNC

NC NC

NCNC


MF 1% 201

240

1/20W201

240

1/20W1%MF2011/20W1%MF

240

OMIT_TABLE

MT41K1G4





MT41K1G4

OMIT_TABLE


MT41K1G4

FBGA-9P5X11P65-COMBOOMIT_TABLE

OMIT_TABLE

MT41K1G4



201CERM-X5R-1

4V

0.47UF20%

240

1%MF 1/20W 201

201

4VCERM-X5R-1

0.47UF20%

0.47UF

201

20%

CERM-X5R-14V

201

0.47UF20%

CERM-X5R-14V

201

0.47UF20%

CERM-X5R-14V

0.47UF

CERM-X5R-1201

4V20%

CERM-X5R-1201

0.47UF

4V20%

201

0.47UF

4VCERM-X5R-1

20%CERM-X5R-1

201

20%0.47UF

4V

201

20%0.47UF

CERM-X5R-14V

201

20%4V

CERM-X5R-1

0.47UF

201

20%0.47UF

CERM-X5R-14V

MF 2011/20W

240

1%

240

2011%MF 1/20W

2011%MF 1/20W

240

2011/20W

240

MF 1%


DDR3 DRAM CHANNEL B (32-63)

MEM_B_CLK_N<0>

MEM_B_DQ<39>

=PP1V5_S3_MEM_B

MEM_B_DQ<55>


MEM_B_DQ<41>



MEM_B_ZQ15

MEM_B_ZQ11MEM_B_ZQ13

MEM_B_ZQ9MEM_B_ZQ12

MEM_B_ZQ8

MEM_B_ZQ15

MEM_B_ZQ14

MEM_RESET_L

MEM_B_ODT<1>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_ZQ13

MEM_B_ZQ12

MEM_RESET_L

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_A<9>


MEM_B_A<1>

MEM_B_A<4>

MEM_B_A<7>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_CLK_P<0>

MEM_B_CKE<0>

MEM_B_DQ<32>

MEM_B_DQ<34>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<33>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CKE<1>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<0>

MEM_B_ODT<0>

MEM_B_A<7>

MEM_B_A<9> MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MEM_B_DQ<56>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<63>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CKE<1>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

MEM_RESET_L

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_A<7>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_CLK_P<0>

MEM_B_DQS_P<5>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_DQS_N<5>

MEM_B_DQ<46>

MEM_B_DQ<42>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CKE<1>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<6>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<0>

MEM_B_A<1>

MEM_B_DQ<47>

MEM_B_DQ<45>

MEM_B_DQ<40>

MEM_B_DQ<43>

MEM_B_A<14>


MEM_B_A<15>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

=PP1V5_S3_MEM_B

MEM_B_DQ<54>

MEM_B_DQ<52>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_A<1>



MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_RESET_L

MEM_B_A<0>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_CKE<1>

MEM_B_RAS_L

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<53>

MEM_B_DQ<51>

MEM_B_DQ<48>

MEM_B_DQS_N<6>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_DQS_P<6>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<5>

MEM_B_A<7>

MEM_B_A<15>

MEM_B_ZQ10

MEM_B_ZQ14


MEM_B_DQ<44>MEM_B_A<3>

MEM_B_A<8>

=PP1V5_S3_MEM_B


R3230 1 2R3220 1 2R3210 1 2

R3200 1 2

U3230

K3L7

H7

M7K7

N3

N7J7

L3

K2L8

L2M8

M2

N8M3

J2K8

J3

G3

F7G7

G9F9

H2H1

B7

B3C7

C2

C8

C3

D3

A3

79

8081

82

E3

E8

D2E7

A7

G1

F1

F3

N2

A2A9

D7

G2G8

K1

K9M1

M9

B9

C1E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3200

K3

L7

H7

M7

K7N3

N7

J7

L3

K2

L8L2

M8M2

N8

M3

J2

K8J3

G3

F7

G7

G9

F9

H2H1

B7

B3

C7C2

C8

C3

D3

A3

79

80

8182

E3E8

D2

E7

A7

G1

F1

F3

N2

A2

A9D7

G2

G8K1

K9

M1M9

B9C1

E2E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8H9

U3210

K3

L7

H7M7

K7

N3N7

J7

L3K2

L8L2

M8

M2N8

M3

J2

K8

J3

G3

F7

G7

G9

F9

H2H1

B7

B3

C7

C2C8

C3

D3

A3

7980

81

82

E3

E8D2

E7

A7

G1

F1

F3

N2

A2

A9

D7G2

G8K1

K9

M1M9

B9C1

E2

E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

U3220

K3L7

H7

M7K7

N3

N7J7

L3

K2L8

L2M8

M2

N8M3

J2K8

J3

G3

F7G7

G9F9

H2H1

B7

B3C7

C2

C8

C3

D3

A3

79

8081

82

E3

E8

D2E7

A7

G1

F1

F3

N2

A2

A9D7

G2

G8K1

K9M1

M9

B9

C1

E2E9

J8

E1

A1

A8

N1

N9

B1

D8

F2

F8

J1

J9

L1

L9

B2

B8

C9

D1

D9

H3

H8

H9

C3200 1

2

C3201 1

2

C3202 1

2

C3210 1

2

C3211 1

2

C3212 1

2

C3220 1

2

C3221 1

2

C3222 1

2

C3230 1

2

C3231 1

2

C3232 1

2

R32011 2

R32111 2

R32211 2

R32311 2051-9277

2.8.0

32 OF 109

30 OF 73

11 29 30 32 67

11 67

7 29 30 32

11 67

29 30 31

11 67

29 30 31

29 30 31

30

30

26 27 28 29 30

11 29 30 32 67

11 67

11 67

30

30

26 27 28 29 30

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

29 30 31

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 67

11 67

11 67

11 67

11 67

11 67

11 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67 11 67

11 67

11 67

11 67

11 67

11 67

11 67

11 67

11 67

11 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 67

11 29 30 32 67

11 29 30 32 67

11 67

11 67

11 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 67

11 67

11 67

11 67

11 29 30 32 67

11 29 30 32 67 11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

7 29 30 32

11 67

11 67

11 67

11 67

11 29 30 32 67

29 30 31

29 30 31

11 29 30 32 67

11 29 30 32 67

26 27 28 29 30

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 67

11 67

11 67

11 67

11 29 30 32 67

11 29 30 32 67

11 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

11 29 30 32 67

7 29 30 32 29 30 31

11 67 11 29 30 32 67

11 29 30 32 67

7 29 30 32

29 30 31

OUT

V-

V+

V-

V+

V-

V+

IN

NC

NC

DSG

DSG

V-

V+

NC

RESET*

A0A1A2

SCLSDA

P0P1P2

P5P6P7

P3P4

THRM

VCC

GNDPAD

NC

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTASCL

SDA

A0

A1

GND

IN

BI



Apple Inc.


124578

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SHEET


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6 3



NOTE: MEMVREG and FRAMEBUF share

NOTE: CPU DAC output step sizes:

DDR3L (1.35V) 6.99mV per step DDR3 (1.5V) 7.70mV per step

RST* on ’platform reset’ so that system

watchdog will disable margining.

NOTE: Margining will be disabled across all

Addr=0x30(WR)/0x31(RD)

Addr=0x98(WR)/0x99(RD)

both at the same time!

8.59mV / step @ output

+61uA - -61uA (- = sourced)

1.5V (DAC: 0x3A)


1.267V (DAC: 0x8B)

MEM VREG

PCA9557D Pin:

0.000V - 3.300V (0x00 - 0xFF)

Nominal value

DAC range:

VRef current:

DAC Channel:

MEM A VREF DQ

1

A B

2 3 4

C

5

D

0.000V - 3.000V (0x00 - 0x74)

1.056V - 1.442V (+/- 180mV)

+6.0mA - -5.0mA (- = sourced)


6

D

- =I2C_PCA9557D_SCL

VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.

(OD)Page Notes

a DAC output, cannot enable

MEM B VREF DQ

Margined target:

10mA max load

1.000V - 2.000V (+/- 500mV)

GPU Frame Buffer (1.8V, 70% VRef)

VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.

DAC step size:

soft-resets and sleep/wake cycles.

VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.

Signal aliases required by this page:

MEM B VREF CA

0.300V - 1.200V (+/- 450mV)

0.000V - 1.501V (0x00 - 0x74)

+3.4mA - -3.4mA (- = sourced)

VREFCA:LDO - LDO outputs sent to CA inputs.

VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.

- =I2C_VREFDACS_SDA- =I2C_VREFDACS_SCL

- =PPDDR_S3_MEMVREF- =PPVTT_S3_DDR_BUF- =PP3V3_S3_VREFMRGNPower aliases required by this page:

- =I2C_PCA9557D_SDA

BOM options provided by this page:

VREFDQ:LDO - LDO outputs sent to DQ inputs.

DDRVREF_DAC - Stuffs Apple margining circuit.

MEM A VREF CA

C

0.75V (DAC: 0x3A)

Required zero ohm resistors when no VREF margining circuit stuffed

NOTE: Must not enable more than two SO-DIMM margining

buffers at once or VRef source may be overloaded.

56

0.1UF

6.3VX5R201

10%

DDRVREF_DAC

1%

33.2K

1/20WMF201

PLACE_NEAR=R7315.2:1mm

DDRVREF_DAC

100K5%

1/20W

MF

201

DDRVREF_DAC

UCSPMAX4253

DDRVREF_DAC

MAX4253UCSP

DDRVREF_DAC

MAX4253UCSP

DDRVREF_DAC

1/20WMF201

1%

PLACE_NEAR=U2900.J8:2.54mm200

VREFCA:LDO_DAC

SHORT

NONE402

NONE

OMIT

NONE

OMIT

SHORT

402

NONENONE

NONE

25

200

1/20W

PLACE_NEAR=U2900.E1:2.54mm

201MF

1%

VREFDQ:LDO_DAC

201MF

133

1%

VREFDQ:LDO_DAC

PLACE_NEAR=R3303.2:1mm1/20W

201

1/20W

DDRVREF_DAC

100K5%

MF

1K1%1/20W

201MF

VREFDQ:M1_M3PLACE_NEAR=Q3320.6:1mm

0201

16V10%0.1UF


X5R-CERM

201MF1/20W

1K1%

VREFDQ:M1_M3


CRITICALVREFDQ:M1_M3

SSM6N15AFESOT563

SSM6N15AFE

SOT563

CRITICALVREFDQ:M1_M3

MF

1%

201


1K

1/20W

X5R-CERM16V10%0.1UF

VREFDQ:M1_M3

0201

PLACE_NEAR=Q3320.3:2mm

MF1/20W

VREFDQ:M1_M3

1K1%


201

VREFDQ:LDO_DACPLACE_NEAR=Q3310.3:1mm

5%1/20WMF201

0

DDRVREF_DAC

MAX4253UCSP

1%

201MF

1/20W

200 PLACE_NEAR=U3100.J8:2.54mm

VREFCA:LDO_DAC

201MF

1/20W1%

133

VREFCA:LDO_DAC


MF

1/20W

100K5%

201

DDRVREF_DAC

0

NOSTUFF

5%1/20WMF201

PLACE_NEAR=R3309:1mm

5%

100K

1/20W

MF

201

DDRVREF_DAC

1%1/20W

201

133

MF


VREFCA:LDO_DAC

CRITICAL

QFN

PCA9557

DDRVREF_DAC

44

44

DAC5574

MSOP

DDRVREF_DAC

CRITICAL

44

44

16VX5R-CERM0201

10%0.1UF

DDRVREF_DAC

6.3V20%

402-LFCERM

2.2UF

DDRVREF_DAC

DDRVREF_DAC

0.1UF

X5R-CERM0201

10%16V

0.1UF10%16V

X5R-CERM0201

DDRVREF_DAC


FSB/DDR3/FRAMEBUF Vref Margining

RES,MF,332OHM,1,1/20W,0201118S0303 R33041 VREFDQ:M1_DAC

VREFDQ:M1_DACRES,MF,1KOHM,1,1/20W,0201118S0012 4 R3321,R3322,R3311,R3312

VREFCA:LDOR3309,R33052 RES,MF,1/20W,0.0 OHM,5,0201,SMD117S0002

1117S0002 VREFDQ:LDORES,MF,1/20W,0.0 OHM,5,0201,SMD R3303,R3360

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_MEMVREG_EN

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_SODIMMS_CA

VREFMRGN_DQ_SODIMMA_EN

=PP3V3_S3_VREFMRGN

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_SODIMMA_DQ

VOLTAGE=3.3V

PP3V3_S3_VREFMRGN_DACMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mm

VREFMRGN_MEMVREG_BUFPP0V75_S3_MEM_VREFDQ_A

PCA9557D_RESET_L

PP3V3_S3_VREFMRGN_CTRLMIN_LINE_WIDTH=0.3 mm

VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mm



VREFMRGN_DQ_SODIMMA_BUF

=PPVTT_S3_DDR_BUF



=I2C_PCA9557D_SDA


PP0V75_S3_MEM_VREFDQ_BPPCPU_MEM_VREFDQ_B


PPCPU_MEM_VREFDQ_A

=I2C_PCA9557D_SCL

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

PP0V75_S3_MEM_VREFDQ_BMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0.75V

DDRREG_FB

=PPDDR_S3_MEMVREF

=PPDDR_S3_MEMVREF

PP0V75_S3_MEM_VREFDQ_AMIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=0.75V

U3301

3

4

5

8

6

7

9

10

11

12

13

14

15

1

2

17

16

C3303 1

2

C3302 1

2

R3301

12

R3310

1 2

U3300

9

10

3

6

7

8

1

2

4

5

C33011

2

C3300 1

2

C3305 1

2 R3314

1 2

R33131

2

U3302

C3

C2

C1

C4

B1

B4

U3302

A3

A2

A1

A4

B1

B4

U3304

C3

C2

C1

C4

B1

B4

R3309

1 2

R3318

1 2

R3319

1 2

R3303

1 2

R3304

1 2

R33071

2

R33211

2

C33201

2

R33221

2

Q3320

6

21

Q3320

3

54

R33111

2

C33101

2

R33121

2

R33601

2

U3304

A3

A2

A1

A4

B1

B4

R3305

1 2

R3306

1 2

R33151

2

R33611

2

051-9277

2.8.0

33 OF 109

31 OF 73

7

27 28 31 67

27 28 67

7 56

29 30

26 31

29 30 31 9

26 31

9

29 30 31

7 31

7 31

27 28 31 67

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



COLUMN OF THREE CAPS BETWEEN PACKAGES


2 CAPS ALONG PACKAGE EDGE






Place RC end termination after last DRAMMEM CLOCK TERMINATION

Place Source Cterm at neckdown at first DRAM

JEDEC recommends 30 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

MEM_B_RAS_L

MEM_A_A<8>MEM_A_A<14>MEM_A_A<13>MEM_A_A<6>

MEM_A_A<11>

MEM_A_BA<2>MEM_A_A<9>MEM_A_A<15>

MEM_A_A<7>MEM_A_BA<0>MEM_A_A<1>

MEM_A_CS_L<1>MEM_A_A<2>MEM_A_CS_L<0>

MEM_A_A<12>

MEM_A_ODT<1>MEM_A_CKE<0>

=PP0V75_S0_MEM_VTT_B

MEM_B_BA<0>

=PP1V5_S3_MEM_B MEM_B_A<1>

MEM_B_A<3>MEM_B_ODT<0>MEM_B_A<6>MEM_B_A<12>

MEM_B_A<15>

MEM_B_CS_L<1>

=PP1V5_S3_MEM_A

MEM_B_A<8>

=PP1V5_S3_MEM_B

MEM_B_A<10>

MEM_B_CKE<0>

=PP1V5_S3_MEM_A

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

VOLTAGE=0V

MEM_B_CLK_TERM_R

VOLTAGE=0V

MEM_B_CS_L<0>MEM_B_A<13>

MEM_B_A<7>MEM_B_CKE<1>

MEM_B_A<9>MEM_B_CAS_L

MEM_B_A<0>

MEM_B_BA<1>MEM_B_A<14>


MEM_B_A<5>

MEM_B_ODT<1>

MEM_B_A<11>

MEM_B_WE_L

MEM_B_BA<2>

=PP0V75_S0_MEM_VTT_A

MEM_A_A<5>MEM_A_CAS_L

MEM_A_BA<1>

MEM_A_CKE<1>

MEM_A_RAS_LMEM_A_A<0>MEM_A_A<3>

MEM_A_ODT<0>

MEM_A_WE_LMEM_A_A<10>MEM_A_A<4>

DDR3 Bypassing/Termination


20%0.47UF

201

4VCERM-X5R-1

20%0.47UF

201

4VCERM-X5R-1

365%1/32W 4X0201

365% 4X02011/32W

4X02015%1/32W36

6.3V

2.2UF

402-LFCERM

20%

4X02011/32W5%3636

4X02011/32W5% 20%0.47UF

201CERM-X5R-14V

20%

201

4V

0.47UF

CERM-X5R-1

6.3V20%

402-LFCERM

2.2UF

2.2UF

402-LF

6.3V20%

CERM

CERM6.3V

2.2UF20%

402-LF

CERM402-LF

20%2.2UF6.3V

CERM402-LF

20%6.3V

2.2UF

CERM402-LF

20%2.2UF6.3V

6.3V

2.2UF20%

402-LFCERM

6.3V

2.2UF

402-LF

20%

CERM

CERM

20%6.3V

2.2UF

402-LF

402-LF

6.3V20%

CERM

2.2UF

6.3V

2.2UF20%

402-LFCERM

CERM6.3V20%

402-LF

2.2UF

2.2UF6.3V20%

402-LFCERM

2.2UF

CERM402-LF

20%6.3V

CERM402-LF

20%2.2UF6.3V

6.3V

2.2UF20%

402-LFCERM

CERM

20%2.2UF6.3V

402-LF

CERM402-LF

20%2.2UF6.3V

CERM402-LF

20%2.2UF6.3V

CERM402-LF

20%2.2UF6.3V

2.2UF20%

CERM402-LF

6.3V

6.3V

2.2UF20%

402-LFCERM

2.2UF6.3VCERM402-LF

20%

CERM

20%2.2UF6.3V

402-LF

CERM402-LF

20%6.3V

2.2UF

20%6.3VCERM

2.2UF

402-LF

6.3V20%

CERM

2.2UF

402-LF

20%

CERM402-LF

6.3V

2.2UF

20%6.3VCERM402-LF

2.2UF

20%2.2UF6.3VCERM402-LF

2.2UF20%6.3VCERM402-LF

2.2UF

402-LF

6.3V20%

CERM

CERM402-LF

20%2.2UF6.3V

20%6.3V

402-LFCERM

2.2UF

6.3V

2.2UF20%

402-LFCERM

1/32W5%36

4X0201

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

402-LFCERM6.3V

2.2UF20%

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

4X020136

1/32W5%

4X02015%36

1/32W

361/32W5% 4X0201

4X020136

1/32W5%

4X02011/32W5%36

402-LF

2.2UF20%6.3VCERM

4X02015%1/32W36

361/32W5% 4X0201

4X02015%1/32W36

4X02015%1/32W36

365%1/32W 4X0201

4X02011/32W5%36

5%1/32W36

4X0201

5%1/32W 4X020136

4X020136

1/32W5%

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

67 28 27 11

CERM6.3V

2.2UF20%

402-LF

67 28 27 11

67 28 27 11

67 28 27 11

365%1/32W 4X0201

4X02015%36

1/32W

5%1/32W36

4X0201

364X02011/32W5%

4X02015%1/32W36

4X020136

5%1/32W

402-LFCERM

20%2.2UF6.3V

4X020136

1/32W5%

5% 4X020136

1/32W

5%1/32W 4X020136

5%1/32W 4X020136

4X02015%1/32W36

364X02011/32W5%

4X020136

5%1/32W

20%4V

201CERM-X5R-1

0.47UF

67 30 29 11

67 30 29 11

6.3V

2.2UF20%

402-LFCERM

67 30 29 11

67 30 29 11

0.47UF

CERM-X5R-1

20%4V

201

6.3V

2.2UF20%

402-LFCERM

1/32W 4X02015%36 4X02015%1/32W36 5%1/32W36

4X0201

361/32W5% 4X0201

67 30 29 11 5%

364X02011/32W

67 30 29 11

20%2.2UF6.3V

402-LFCERM

6.3V20%

CERM402-LF

2.2UF

402-LF

20%6.3VCERM

2.2UF

2.2UF20%6.3VCERM402-LF

CERM6.3V20%2.2UF

402-LF

6.3V20%2.2UF

402-LFCERM

CERM6.3V20%2.2UF

402-LF

2.2UF6.3V

402-LF

20%

CERM

365%1/32W 4X0201

CERM6.3V

2.2UF20%

402-LF

4X020136

5%1/32W

365% 4X02011/32W

5%36

4X02011/32W

5%36

4X02011/32W

1/32W36

5% 4X0201

5% 4X02011/32W36

2.2UF

CERM402-LF

20%6.3V

365% 4X02011/32W

5%36

1/32W 4X0201

4X020136

5%1/32W

4X02011/32W36

5%

20%2.2UF6.3V

402-LFCERM

CERM402-LF

6.3V20%2.2UF

6.3V

2.2UF20%

402-LFCERM

6.3V

2.2UF20%

402-LFCERM

30

201

1/20WMF

5%

201CERM25V5%

3.3PF

30

201

5%1/20WMF

MF1/20W5%

30

201

CERM25V5%

3.3PF

201

201

30

5%1/20WMF

0.1UF

201

10%X5R

6.3V

0.1UF

MEM_A_CLK_TERM_R

10%X5R

6.3V201

2.2UF20%

402-LFCERM6.3V

2.2UF20%

CERM6.3V

402-LF

20%2.2UF

402-LFCERM6.3V

4VCERM-X5R-1201

0.47UF20%

2.2UF6.3V20%

402-LFCERM

CERM-X5R-1

20%4V

201

0.47UF

0.47UF

201

20%

CERM-X5R-14V

0.47UF20%

201CERM-X5R-14V

402-LF

2.2UF6.3V20%

CERM

402-LF

2.2UF6.3V20%

CERM

201

4V

0.47UF20%

CERM-X5R-1

20%0.47UF

201CERM-X5R-14V

0.47UF4VCERM-X5R-1

20%

201

20%

201CERM-X5R-14V

0.47UF

CERM-X5R-1

0.47UF

201

4V20%

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

6.3V

2.2UF

CERM

20%

402-LF

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

67 30 29 11

4X02015%1/32W36

1/32W5%36

4X0201

4X02011/32W5%36

1/32W 4X02015%3636

5%1/32W 4X0201

CERM402-LF

20%2.2UF6.3V

364X02015%1/32W

4X02011/32W36

5%

20%0.47UF

201CERM-X5R-14V

20%0.47UF

201CERM-X5R-14V

20%4V

0.47UF

CERM-X5R-1201

20%

201CERM-X5R-14V

0.47UF

0.47UF20%4VCERM-X5R-1201

C34201

2

C34211

2

C34101

2

C34111

2

C34121

2

C34001

2

C34011

2

C34241

2

C34251

2

C34141

2

C34151

2

C34161

2

C34041

2

C34051

2

C34501

2

C34511

2

C34401

2

C34411

2

C34421

2

C34301

2

C34311

2

C34541

2

C34551

2

C34441

2

C34451

2

C34461

2

C34341

2

C34351

2

C34221

2

C34231

2

C34701

2

C34711

2

C34721

2

C3402

C34031

2

C34261

2

C34271

2

C34741

2

C34751

2

C34761

2

C34061

2

C34071

2

C34521

2

C34531

2

C34901

2

C34911

2

C34921

2

C34321

2

C34331

2

C34561

2

C34571

2

C34941

2

C34951

2

C34961

2

C34361

2

C34371

2

C34811

2

C34601

2

RP3410 3 6

RP3409 3 6

RP3411 2 7

RP3408 4 5

RP3411 3 6

C34621

2

C34641

2

C34671

2

C34611

2

C34631

2

C34651

2

C34661

2

RP3408 3 6

RP3410 4 5

RP3408 1 8RP3410 2 7

RP3414 2 7

RP3413 2 7

RP3414 1 8

C34831

2

C34851

2

C34801

2

C34821

2

C34841

2

C34871

2

C34861

2

C34881

2

C34891

2

C3469

1 2

C3479

1 2

R34681 2

C3468 1

2 R34691 2

R34781 2

C3478 1

2 R34791 2

RP3413 1 8RP3410 1 8RP3409 1 8

RP3413 3 6

RP3413 4 5

RP3409 4 5RP3408 2 7

RP3409 2 7

RP3414 4 5

RP3411 1 8

RP3414 3 6

C34081

2

C34091

2

C34181

2

C34191

2

C34281

2

C34291

2

C34381

2

C34391

2

RP3411 4 5

RP3412 1 8RP3412 2 7RP3412 3 6RP3412 4 5

C34931

2

C34771

2

RP3406 2 7

RP3402 2 7

RP3401 4 5

RP3401 2 7

RP3402 1 8

RP3403 1 8

RP3406 1 8

RP3407 3 6

RP3404 3 6

RP3402 3 6

RP3406 4 5

RP3404 1 8

RP3403 4 5

RP3407 2 7

RP3407 4 5

RP3407 1 8

RP3403 3 6

RP3402 4 5

RP3401 1 8

RP3401 3 6

RP3404 4 5

RP3404 2 7

RP3406 3 6

RP3405 1 8RP3405 2 7RP3405 3 6RP3405 4 5

RP3403 2 7

051-9277

2.8.0

34 OF 109

32 OF 73

7

32 30 29 7

32 28 27 7

32 30 29 7

32 28 27 7

67 30 29 11

67 30 29 11

67 28 27 11

67 28 27 11

7

VDD

WRITE_PROTECT_SW

CARD_DETECT_SWCARD_DETECT_GND

DAT6DAT7

DAT1

CD/DAT3

DAT2

DAT4DAT5

VSS

VSS

CLK

CMDDAT0

SHLD_PIN

SHLD_PINSHLD_PIN

SHLD_PIN

GPIO2

RSTZ*

THRM_PADTEST

SD_WP

D7D6D5

D0

SD_CLK

D3D2

GPIO1

DVDD

IOVDD

MS_INSSD_CDZSD_CMD

PLLVDD

AVDD

D4

D1

PMOS

RREF

GPIO0

DPDM

NC

NC

DET_OUT

DET_IN

RST_IN*

DET_CHNGD*

LOW_PWRRST_OUT*

VDD

THRMGND PAD

(IPU) (OD)

(OD)

DLY

XOR

LOGICRST

NC

INOUT

OUT

OUT

IN

BI

BI

D

SG

D

SG

IN

IN

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



SD Detect & Reset LogicSDCONN_DETECT Debounce, Inversion, Detect-Changed PCH GPIO Latch Circuit Converts SDCONN from active-low level signal to active-high pulses

516-0237

PDMOD: POWER DOWN MODES

10K LOW = POWER SAVING MODE ENABLE10K HIGH = REMOTE WAKE UP ENABLE

NC = DISABLE (DEFAULT)

(IPD)

(IPD)

*** Need to confirm with SW weather LATCH is required.

Connector shorts GND with Card_Detect_SW signalwhen SD card inserted.

DLY block is 20ms nominalWhen LOW_PWR gated dessarts, RST_OUT# deassserts for >80ms, then asserts for 10ms

Max Current = 800 mA

Keep this net short!

R3505 is for rail discharge. GL822 may cycle PMOS torecover from card error. Off duration is 100ms and cardvoltage must be less than 0.5V for at least 1ms per spec.

(IPU)

(IPU)

(IPU)

regardless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#

(SDCONN_STATE_RST_L will be required with LATCH)

-> To GL822 Chip

(Low active pulse signal)-> To SMC & Isolation Circuit (then to PCH GPIO)

From SD CONN ->

RESET_IN* musts be pulled to GND if not used. SD detect logic will only function if Reset logic is low.

CRITICAL

0805-10.22UH

CRITICAL

F-RT-THSD-CARD-K16

CRITICAL

GL822QFN

X5R201

BYPASS=U3500.8:5 mm

0.1UF6.3V6.3V

0.1UF

201X5R

BYPASS=U3500.8:5 mm

201

10K

MF1/20W

X5R-CERM16.3V

4.7UF20%

4.7UF

X5R-CERM16.3V20%

20133MF1/20W

MF-LF1/16W0

1/16W0

MF-LF

1/16W0

MF-LF

0MF-LF1/16W

MF-LF1/16W0

1/16W0

MF-LF

MF-LF0

1/16W

1/16W0

MF-LF

01/16W MF-LF

1/16W0

MF-LF

1/16W

MF-LF

0

NO STUFF

1/16W MF-LF0

47NH-1.3OHM0402

TDFNSLG4AP014V

6 33 42

33

6 33

33

201 MF

0

1/20W

X5R6.3V20%0.22UF

0201

201MF1/20W

10K

201X5R6.3V

0.1UF

0.1UF

X5R6.3V

BYPASS=U3500.1:16:5 mm

201

201

6.3V

0.1UF

BYPASS=U3500.3:5:5 mm

X5R

24 68

24 68

MF

47K

1/20W

201

1%

MF1/20W

201

715

NO STUFF

10K

MF1/20W

201

MF201

10K

1/20WNO STUFF

25VNPO201

SOT563SSM6N37FEAPE

SOT563SSM6N37FEAPE

23

25

SecureDigital Card Reader


SD_CD_L

GL137_RESET_L_RGL137_RESET_L

GL137_RREF

GL137_GPIO0

=PP3V3_S3_CARDREADER

GL137_GPIO1SD_WP

SD_D_R<6>SD_D_R<5>

SD_D_R<0>

SD_CLK_R

SD_D_R<2>

SDCARD_IOVDD

SD_CMD_R

SDCARD_PLLVDD

VOLTAGE=3.3VMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.40MMPP3V3_S3_CARDREADER_AVDD

SD_D_R<4>

SD_D_R<1>


VOLTAGE=3.3V

PP3V3_SW_SD_PWR


MAKE_BASE=TRUE

USB_SDCARD_PUSB_SDCARD_N

SD_CD_L

SD_D<7>SD_D<6>SD_D<5>

SD_D<3>SD_D<2>

SD_CMDSD_D<0>

SD_CLK_R1 SD_CLK_R2

SD_D<1>

SD_CLK

SD_D<4>

SD_CLK_L

SDCONN_STATE_CHANGE_SMC

SDCONN_DETECT_L

=PP3V3_S4_SD_HPD

SDCARD_PLT_RST_L

SDCARD_PLT_RSTSDCONN_STATE_RST_L

SDCONN_DETECT_L

SD_D_R<7>

SD_D_R<3>

10PF

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

C0G-CERM0402

10PF5%

C0G-CERM0402

10PF5%

C0G-CERM0402

10PF5%

C0G-CERM0402

10PF5%

C0G-CERM0402

10PF5%

C0G-CERM0402

10PF5%

C0G-CERM0402

10PF5%

C0G-CERM0402

10PF5%

C0G-CERM0402

10PF5%

50V

50V

50V

50V

50V

50V

50V

50V

50V

402

402

402

402

402

402

402

402

402

402

402

402

402

402

10%10%

10%

10%

10% C35051

2

C35031

2

C35041

2

R35051

2

R35061

2

R35071

2

R35091

2 C3515 1

2

Q3500 3

54

Q3500 6

21

L3500

2

1

J3500

15

14

1

5

2

7

8

9

10

11

12

13

17

18

19

20

4

3

6

16

U3500

5

131491018192021

23

1 7 16

22617

8

25

28

15

4

26 23

12

1124

27

29

C35011

2

C35021

2

R35101

2

C3514 1

2C3507 1

2

C35201

2

C35211

2

C3522 1

2

C35231

2

C3524 1

2

C35251

2

C3526 1

2

C35271

2

R35201 2

R3521 1 2

R3522 1 2

R3523 1 2

R3524 1 2

R3525 1 2

R3526 1 2

R3527 1 2

R3528 1 2

R35191 2

C35191

2

R3529 1 2

R35301

2

R3531 1 2

L35041 2

U3510

86

7

5

2

3

4

9

1

R3513

1 2

C35131

2

R35901

2

051-9277

2.8.0

35 OF 109

33 OF 73

7

6

6

6

6

6

6

6

6

6

6

6

6

7

OUT

OUT

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

IN

IN

IN

IN

OUT

PETN_3

PETN_2PETP_2

PETP_1PETN_1

PETP_0PETN_0

MONOBS_N

MONDC0MONDC1

PERN_3PERP_3

PERN_2PERP_2

PERN_1PERP_1

PERP_0PERN_0

MONOBS_P

TMU_CLK_INTMU_CLK_OUT

DPSRC_3_P

DPSRC_2_P

DPSRC_3_N

DPSRC_1_P

DPSRC_2_N

DPSRC_1_N

DPSRC_0_P

DPSRC_AUX_P

DPSRC_0_N

DPSRC_HPD_OD

DPSRC_AUX_N

GPIO_2/GO2SX

GPIO_15

GPIO_9/OK2GO2SX_OD*GPIO_14

GPIO_8/EN_CIO_PWR_OD*GPIO_7/CIO_SCL_ODGPIO_6/CIO_SDA_OD

GPIO_5/CIO_PLUG_EVENTGPIO_4/WAKE_N_OD

GPIO_3

PB_CIO3_TX_N/DP_SRC_2_N

PB_CONFIG2/CIO_2_LSOE

PB_CIO2_RX_N

PB_CONFIG1/CIO_2_LSEO

PB_CIO2_RX_P

PB_CIO2_TX_P/DP_SRC_0_PPB_CIO2_TX_N/DP_SRC_0_N

PB_CIO3_TX_P/DP_SRC_2_P

PB_DPSRC_3_N

PB_DPSRC_1_NPB_DPSRC_1_P

PB_LSRX/CIO_3_LSOE

PB_CIO3_RX_N

PB_LSTX/CIO_3_LSEO

PB_CIO3_RX_P

PB_DPSRC_3_P

GPIO_11/PB_CIO_SEL/BYP1GPIO_13/PB_DP_PWRDN/BYP2

GPIO_1/PB_HV_EN/BYP0

PB_DPSRC_HPD

PB_AUX_NPB_AUX_P

THERMDA

EE_DIEE_DOEE_CS_N

TDI

EE_CLK

TDO

DPSNK0_2_P

DPSNK0_3_N

DPSNK0_1_P

DPSNK0_2_N

DPSNK0_0_P

DPSNK0_1_N

DPSNK0_AUX_P

DPSNK0_0_N

DPSNK0_HPD

DPSNK0_AUX_N

DPSNK1_3_NDPSNK1_3_P




DPSNK1_AUX_NDPSNK1_AUX_P

DPSNK1_HPD

PA_CIO0_TX_N/DP_SRC_0_NPA_CIO0_TX_P/DP_SRC_0_P

PA_CIO0_RX_NPA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOEPA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_N/DP_SRC_2_NPA_CIO1_TX_P/DP_SRC_2_P

PA_CIO1_RX_NPA_CIO1_RX_P

PA_LSRX/CIO_1_LSOEPA_LSTX/CIO_1_LSEO

PA_DPSRC_1_NPA_DPSRC_1_P

PA_DPSRC_3_NPA_DPSRC_3_P

PA_AUX_P

PA_DPSRC_HPD

PA_AUX_N

GPIO_10/PA_CIO_SEL/BYP1GPIO_0/PA_HV_EN/BYP0

GPIO_12/PA_DP_PWRDN/BYP2

PETP_3

RSENSE

REFCLK_100_IN_PREFCLK_100_IN_N

XTAL_25_INXTAL_25_OUT

TMSTCK

TEST_ENTEST_PWR_GOOD

DPSNK0_3_P

PWR_ON_POC_RSTN

PERST_N

NC

RBIAS

PCIE_RST_0_NPCIE_RST_1_N

PCIE_RST_3_NPCIE_RST_2_N

PCIE_CLKREQ_OD_N

EN_LC_PWR

PCIE RESET

PCIE GEN2

MISC

(SYM 1 OF 2)

CLOCKS

JTAG/TEST PORT

RECEIVE

TRANSMIT

EEPROM

SINK PORT 0

SINK PORT 1

SOURCE PORT 0

PORT3

PORT2

PORT0

PORT1

DISPLAYPORT

PORTS

OUT

NC

IN

IN

IN

OUT

OUT

OUT

IN

BI

BI

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

BI

BI

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

D

C

Q

S*

W*

HOLD*

PADVSS THM

VCC

IN

OUT

IN

OUT

BI

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

(TBT_SPI_MOSI)

(TBT_SPI_CLK)

DEBUG: For monitoring current/voltage

DEBUG: For monitoring clock

(TBT_SPI_MISO)

SNK1 AC Coupling

SNK0 AC Coupling

Not used in host mode.

(TBT_SPI_CS_L)

DEBUG: For monitoring current/voltage

Use AA8 GND ball for THERM_DN

DEBUG: For monitoring clock

8 - GPIO_159 - GPIO_1110 - GPIO_1411 - GPIO_012 - GPIO_1213 - GPIO_1014 - PB_LSTX15 - PB_LSRX

NOTE: The following pins require testpoints:

1 - GPIO_10 - GPIO_13

3 - GPIO_32 - GPIO_2

4 - GPIO_5

7 - PCIE_RST_3_N6 - PCIE_RST_2_N5 - PCIE_RST_1_N

(FORCE_PWR)

if necessary.Stuff one of R3861/2.

of GPIO_2/GPIO_9allows separationR3681 for CYA,

(TBT_EN_CIO_PWR_L)

TP_DP_TBTSRC_AUXCH_CP

TP_DP_TBTSRC_ML_CN<0>TP_DP_TBTSRC_ML_CP<0>

TP_DP_TBTSRC_ML_CN<1>TP_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CN<2>

TP_DP_TBTSRC_ML_CN<3>

TP_DP_TBTSRC_ML_CP<2>

TBT_PCIE_RESET_L

SYSCLK_CLK25M_TBT_RTP_TBT_XTAL25OUT

TBT_TMU_CLK_OUT

TP_DP_TBTSRC_ML_CP<3>

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

201201

201

201

201 201

201

201201

201

201

201

201 201

201

201

201

201

201

201

201

201

201

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

402

402X5R

=PP3V3_TBTLC_RTR

TBT_B_R2D_C_P<1>TBT_B_R2D_C_N<1>

TBT_B_D2R_P<1>TBT_B_D2R_N<1>

TBT_B_LSRXTBT_B_LSTX

DP_TBTPB_ML_C_P<1>

=PP3V3_S4_TBT

DP_TBTPA_HPD

TBT_B_CONFIG1_BUF

DP_TBTPB_ML_C_P<3>

TBT_EN_LC_PWR

TBTROM_HOLD_L

TBTROM_WP_L

=PP3V3_TBTLC_RTR

TBT_PWR_ON_POC_RST_L

PCIE_TBT_R2D_C_P<3>=PP3V3_S4_TBT

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK1_ML_P<2>

TP_DP_TBTSRC_AUXCH_CN

TBT_SPI_CS_LTBT_SPI_CLK

DP_TBTSNK0_ML_N<2>

=PP3V3_TBTLC_RTR

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_P<0>

DP_TBTSNK0_ML_C_P<3>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_N<3>

PCIE_TBT_R2D_C_N<1>




DP_TBTSNK0_ML_C_N<0>




DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_N


DP_TBTSNK1_AUXCH_C_P



DP_TBTSNK1_AUXCH_N

DP_TBTSNK0_ML_P<1>

DP_TBTSNK1_ML_P<3>



DP_TBTSNK0_ML_C_N<2> DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<1>

PCIE_TBT_D2R_P<3>

DP_TBTSNK1_ML_P<0>

PCIE_TBT_R2D_C_P<2>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<3>

PCIE_TBT_D2R_N<2>

SYSCLK_CLK25M_TBT


TP_TBT_PCIE_RESET2_LTP_TBT_PCIE_RESET3_L

TP_TBT_PCIE_RESET1_L

TBT_RBIAS

DP_TBTSNK0_ML_P<3>

JTAG_TBT_TCKJTAG_TBT_TMS

TBT_RSENSE

PCIE_TBT_D2R_C_P<3>

TBT_A_DP_PWRDN

TBT_A_HV_ENTBT_A_CIO_SEL

DP_TBTPA_AUXCH_C_NDP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_P<3>DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<1>DP_TBTPA_ML_C_N<1>

TBT_A_LSTXTBT_A_LSRX

TBT_A_D2R_N<1>

TBT_A_R2D_C_P<1>TBT_A_R2D_C_N<1>

TBT_A_CONFIG2_RC

TBT_A_D2R_P<0>

TBT_A_R2D_C_P<0>

DP_TBTSNK1_HPD

DP_TBTSNK1_ML_P<0>DP_TBTSNK1_ML_N<0>


DP_TBTSNK1_ML_N<2>


DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_HPD

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<2>

JTAG_TBT_TDO

JTAG_TBT_TDI

TBT_SPI_MISO

TP_TBT_THERM_DP

DP_TBTPB_AUXCH_C_PDP_TBTPB_AUXCH_C_N

DP_TBTPB_HPD

TBT_B_HV_EN

TBT_B_DP_PWRDNTBT_B_CIO_SEL

TBT_B_R2D_C_P<0>

PCIE_TBT_R2D_N<0>PCIE_TBT_R2D_P<0>

PCIE_TBT_R2D_P<1>PCIE_TBT_R2D_N<1>



TP_TBT_MONDC1

PCIE_TBT_D2R_C_N<0>PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_C_N<1>PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<2>PCIE_TBT_D2R_C_N<2>

PCIE_TBT_D2R_C_N<3>

TBT_MONOBSNTBT_MONOBSP

DP_TBTSNK1_AUXCH_N

TBT_B_CONFIG2_RC

DP_TBTSNK1_AUXCH_P

TBT_A_D2R_P<1>

TBT_B_R2D_C_N<0>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_N<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_P<2>


DP_TBTSNK1_AUXCH_C_N

TBT_A_CONFIG1_BUF

TBT_A_D2R_N<0>

TBT_A_R2D_C_N<0>

TBT_B_D2R_P<0>TBT_B_D2R_N<0>

=TBT_WAKE_L

TBT_TEST_ENTBT_TEST_PWR_GOOD

TP_TBT_PCIE_RESET0_L

=TBT_CLKREQ_L

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_N<3>

TBT_A_HV_ENTBT_B_HV_EN

TBT_GPIO_14TBT_GPIO_9

TBT_GO2SX_BIDIRTBT_DDC_XBAR_EN_L

TBT_SPI_MOSI

PCIE_CLK100M_TBT_PPCIE_CLK100M_TBT_N

TBT_TMU_CLK_IN

TBT_PWR_EN

TBT_B_DP_PWRDNTBT_A_DP_PWRDN

TBT_PWR_REQ_L

TBT_DDC_XBAR_EN_LTBT_GPIO_14TBT_GPIO_9

MAKE_BASE=TRUETBT_EN_CIO_PWR_L

DP_TBTSRC_HPD

Thunderbolt Host (1 of 2)


69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

X5R-CERM0201

X5R-CERM0201

0201X5R-CERM

X5R-CERM0201

X5R-CERM0201

3.3K5%

MF1/20W

0201X5R-CERM

0201X5R-CERM

X5R-CERM0201

0201X5R-CERM

0201X5R-CERM

X5R-CERM0201

X5R-CERM0201

5%3.3K

MF1/20W

X5R-CERM0201

X5R-CERM0201

0201X5R-CERM

X5R-CERM0201

36

05%1/20WMF

MF

5%1/20W

10K

MF

5%1/20W

10K

NO STUFF

10K1/20W5%

MF

34 19

23

34

1/20W

10K5%

MF

10K1/20W5%

MFMF

5%1/20W

10K

10K1/20W

5%

MF

MF

5%1/20W

100K

34

18

44

44

42

25 100K

5%1/16WMF-LF

36

MF

47K

1/20W5%

NO STUFF

0201X5R-CERM

36

NONENOSTUFF

NONENONE

OMIT

OMIT_TABLE

M95256-RMC6XGMLP

CRITICAL6.3V20%

1UF

0201

70 8

70 8

70 8

70 8

8

8

70 8

70 8

70 8

70 8

8

8

70 8

70 8

70 8

70 8

70 8

70 8

8

34

8

34

70 64

70 64

70 64

70 64

64

64

70 64

70 64

70 64

70 64

64

64

70 64

70 64

70 64

70 64

70 64

70 64

64

64 36 34

64

64 34

69 16

69 16

5%1/20W

MF

10K

NO STUFF

MF1/20W5%1K

806

1%

MF1/20W

10K5%

MF1/20W

69 25

36

CACTUSRIDGE4CFCBGA

OMIT_TABLE

CRITICAL

8

8

16

19 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

0201X5R-CERM

0201X5R-CERM

0201X5R-CERM

0201X5R-CERM

X5R-CERM0201

0201X5R-CERM

0201X5R-CERM

0201X5R-CERM

0201X5R-CERM

0201X5R-CERM

0201X5R-CERM

0201X5R-CERM

1K1%

MF1/20W

0201X5R-CERM

0201X5R-CERM

X5R-CERM0201

0201X5R-CERM

0201X5R-CERM

0201X5R-CERM

0201X5R-CERM

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

69 8

0201X5R-CERM

5%

MF1/20W

3.3K

5%0

MF1/20W

MF

5%1/20W

100K

100K

MF

5%1/20W

5%0

MF1/20W

8

8

5%3.3K

MF1/20W

36

TP_TBT_MONDC0

TBT_GO2SX_BIDIR

=I2C_TBTRTR_SCL=I2C_TBTRTR_SDATBT_CIO_PLUG_EVENT

R36901

2

R36921

2

R36911

2

R36551

2

C3601 1 2

C3600 1 2

C3602 1 2

C3603 1 2

C3604 1 2

C3605 1 2

C3606 1 2

C3607 1 2

C3640 1 2

C3641 1 2

C3642 1 2

C3643 1 2

C3645 1 2

C3644 1 2

C3646 1 2

C3647 1 2

R36251

2

R36301

2

R36311

2

R36291

2

R36931

2

C3629 1 2

C3628 1 2

C3627 1 2

C3626 1 2

C3625 1 2

C3624 1 2

C3623 1 2

C3622 1 2

C3621 1 2

C3620 1 2

C3630 1 2

C3631 1 2

C3632 1 2

C3633 1 2

C3634 1 2

C3635 1 2

C3636 1 2

C3637 1 2

C3638 1 2

C3639 1 2

U3600

D19

E20

D17

E18

D15

E16

D13

E14

B5

A6

U6

D11

E12

D9

E10

D7

E8

D5

E6

B3

A4

T5

B9

A8

B11

A10

B13

A12

B15

A14

D3

C2

V3

W4

AD3

R4

P5

K5

G2

M3 L2

H3 L4

T3

V5

M1

Y1

W2

J4

AA2

AB1

AC2

P3

M5

AD23

AC24

W16

W18

F1

F3

E22

G22

E24

G24

J22

L22

J24

L24

K1

G4

B17

A16

B19

A18

H1

J6

N2

E2

D1

N22

R22

N24

R24

U22

W22

U24

W24

P1

H5

B21

A20

B23

A22

K3

G6

L6

W6

N6

T1

Y5

U2

AA10

AB13

AA16

AB19

AB9

AA12

AB15

AA18

R6

AD7

AD11

AD15

AD19

AD5

AD9

AD13

AD17

J2W20

AD21

AB21

U20

AA6

V1

R2

N4

AB5

Y7

AB3

Y3

AA4

AA24

AB23

R36981

2 R36951 2

R36961

2

R36991

2

C36901

2

U36906

5

7

2

1

9

8

4

3

R36151

2

C3610 1

2

R36101

2

R36321

2

R36971

2

R36851

2

R36881

2

R36871

2

R36861

2

R36821

2

R36831

2

R36801

2

R36811

2

051-9277

2.8.0

36 OF 109

34 OF 73

U4

36 35 34 7

36 35 34 7

36 35 34 7

36 35 34 7

69 34

69 34

69 34

70

70

69 34

36 35 34 7

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

69 34

70

47

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69

69 34

69 34

69 34

69 34

64 36 34

34

34

34

34 19

34

70

69

34

64 34

34

VSSPEVSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPE

VSSPEVSSPE

VSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPE

VSSPEVSSPE

VSSVSS

VSSVSS

VSS

VSSVSS

VSSVSSVSSVSSVSSVSS

VSSVSS

VSSVSS

VSS

VSSVSS

VSSVSS

VSSVSS

VSS

VCC1P0_DPAUXVCC1P0_DPAUX

VCC3P3_POC

VSSPE

VCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PE

VCC1P0_PEVCC1P0_PE

VCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PEVCC1P0_PE

VCC1P0VCC1P0

VCC3P3_DPVCC3P3_DP

VCC3P3_DP

VCC3P3_CIOVCC3P3_CIOVCC3P3_CIO

VCC3P3VCC3P3

VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0

VCC1P0VCC1P0

VCC1P0VCC1P0VCC1P0VCC1P0VCC1P0

VCC1P0_ON

VCC1P0_ON

VCC1P0_ONVCC1P0_ON

VCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ONVCC1P0_ON

VCC3P3

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPEVSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPE

VSSPEVSSPE

VSSPEVSSPEVSSPEVSSPEVSSPEVSSPEVSSPE

VSSPEVSSPE


VSSPEVSSPE


VSSPEVSSPE

VCC3P3_DP

VCC3P3_DPAUX

(SYM 2 OF 2)

VCC

GND

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6 3



EDP: 240 mA250 mA (Dual-Port)??? mA (Single-Port)

EDP: 3000 mA2700 mA (Dual-Port)???? mA (Single-Port)

250 mA (Dual Port)???? mA (Single Port)

EDP: 10 mA

EDP: 1000 mA

20%

X5R6.3V

1.0UF

0201-MUR

6.3VCERM-X5R0402-1

10UF20%

20%

X5R6.3V

1.0UF

0201-MUR

20%

X5R6.3V

1.0UF

0201-MUR

6.3V20%1.0UF

X5R0201-MUR

1.0UF20%

X5R0201-MUR

6.3VCERM-X5R

20%6.3V

0402-1

10UF

20%10UF

0402-1CERM-X5R

6.3V

X5R6.3V20%1.0UF

0201-MUR

CRITICAL

OMIT_TABLE

CACTUSRIDGE4CFCBGA

6.3VCERM-X5R0402-1

10UF20%20%

X5R6.3V

1.0UF

0201-MUR

20%

X5R6.3V

1.0UF

0201-MUR

0201-MURX5R

20%6.3V

1.0UF

20%

X5R

1.0UF

0201-MUR

6.3V

X5R6.3V

0201-MUR

20%1.0UF

X5R6.3V

1.0UF20%

0201-MUR

1.0UF

0201-MUR

6.3VX5R

20%

6.3VX5R0201-MUR

1.0UF20%

X5R0201-MUR

1.0UF20%6.3V

20%6.3V

1.0UF

0201-MURX5R

20%

X5R6.3V

1.0UF

0201-MUR

20%

X5R6.3V

1.0UF

0201-MUR

20%

X5R6.3V

1.0UF

0201-MUR

20%

X5R6.3V

1.0UF

0201-MUR

Thunderbolt Host (2 of 2)


=PP3V3_TBTLC_RTR

=PP1V05_TBTCIO_RTR

=PP1V05_TBTLC_RTR

=PP3V3_S4_TBT

C37141

2

C37101

2

C37121

2

C37181

2

C37131

2

C3700 1

2

C3701 1

2

U3600K11

K15

R10

R14

T11

U10

V11

W10

L10

L14

M11

M15

N10

N14

P11

P15

G8

H9

J10

J12

J14

J16

J8

K17

T15

U14

V7

W8

G10

G12

V15

V19

W12

W14

G14

G16

G18

H19

K19

M19

P19

T19

M7

P7

T7

L18

N18

R18

H11

H13

H15

H17

H7

K7

AD1

K13

N16

N8

P13

P17

P9

R12

R16

R8

T13

T17

K9

T9

U12

U16

U8

V9

L12

L16

L8

M13

M17

M9

N12

A2

A24

AC12

AC14

AC16

AC18

AC20

AC22

AC4

AC6

AC8

B1

AA14

B7

C10

C12

C14

C16

C18

C20

C22

C24

C4

AA20

C6

C8

D21

D23

E4

F11

F13

F15

F17

F19

AA22

F21

F23

F5

F7

F9

G20

H21

H23

J18

J20

AA8

K21

K23

L20

M21

M23

N20

P21

P23

R20

T21

AB11

T23

U18

V13

V17

V21

V23

Y11

Y13

Y15

Y17

AB17

Y19

Y21

Y23

Y9

AB7

AC10

C37601

2

C3772 1

2

C3771 1

2

C3770 1

2

C3790 1

2

C37291

2

C37321

2

C37301

2

C3744 1

2

C3743 1

2

C3742 1

2

C3741 1

2

C3740 1

2

C3745 1

2

C37051

2

C3773 1

2

C3774 1

2

051-9277

2.8.0

37 OF 109

35 OF 73

7 34 36

7

7

7 34 36

IN

D

G S

D

S G

D

S G

IN

SG

D

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND GND

NC

SNS1

SNS2

OUT

IN

RESET*

OUTEN

MR*

GNDTHRM

IN

VDD

SENSE+-

PAD

(OD)

0.7V

DLY

IN

OUT

IN

GND

VOUT

ON

VIN

GND

VOUT

ON

VIN

D SG

OUTSENSE

THRM

RESET*

CT

GND

MR*

VDD

PAD

VOUT

GNDON

VIN

D

SG

IN

IN

D

GS

Apple Inc.


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6 3



Part

Type

R(on)@ 2.5V

Max Current = 2A (85C)

3.3V TBT "LC" Switch

18.5 mOhm Typ

TPS22924C

Load Switch

25.8 mOhm Max

U3810

1.05V TBT "LC" Switch

@ 1.05V

Load Switch

Freq = 300KHzMax Current = 1.0AVout = 15.1V

UVLO(falling) = 1.22 * (R1 + R2) / R2

UVLO = 4.55V (falling), 4.95 (rising)UVLO(rising) = UVLO(falling) + (2uA * R1)

1.05V TBT "CIO" Switch

Vt = 2.33V +/- 2%

8 mOhm Typ

U3815Part

GND inside package,

Max Vgs: 10V

Vgs(max): +/-12VVds(max): -30V

- =PP18V_TBT_REG (18V Boost Output)

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

Signal aliases required by this page:

BOM options provided by this page:

8-13V InputChanges requiredfor 2S.

Id(max): 3.7A @ 70C

TPS22924C

- =PP1V05_TBT_FET (1.05V FET Output)

Type

28.6 mOhm Max

Page Notes

TBTBST:Y - Stuffs 18V boost circuitry.

- =TBT_CLKREQ_L- =TBT_RESET_L

- =PPVIN_SW_TBTBST (8-13V Boost Input)

<Ra>

add property on another page.

- =PP3V3_S0_TBTPWRCTL

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

<R1>

<Rb>

SI8409DB:

R(on)

TPS22920

U3820

11.5 mOhm Max

Type

R(on)

(IPU)

Delay = 27.3ms

Part

20.3 mOhm Typ

Pull-up: R3610

Supervisor & CLKREQ# Isolation

@ 1.0V


WF: C value may need tuning.

Rds(on): 46mOhm @ 4.5V Vgs

Voltage not specified here,

Vgs(th): -1.4V

<R2>

SGND shorted to Vout = 1.6V * (1 + Ra / Rb)

TBT 15V Boost Regulator

Pull-up provided by SB page.

RC guarantees minimum 5ms to reach 0.5V


Load Switch

C3816 must be 10%

- =PP3V3_TBT_FET (3.3V FET Output)

Power aliases required by this page:

TPS3808G25

Platform (PCIe) Reset

TBT "POC" Power-up ResetIntel investigating whether RC is sufficient.

no XW necessary.

DLY = 60 ms +/- 20%

0201

CSP

1/20W

201MF

5%0

NO STUFF

100PF


22PF

MF

34 64

1/20W5%

MF

470K

25VX5R

0.1UF

SOD-VESM-HF

1/20WMF

1%73.2K

1/20WMF

5%330K

SOT563SSM6N37FEAPE

SOT563

6.3V

0.33UF

CERM-X5R

330K5%1/20W

25 41 42

MF-LF1/16W

15.8K

CRITICAL

SI8409DBBGA

MF

1%200K

1/20W

QFN

LT3957SM

DFLS230L

CRITICAL

150K5%

MF1/20W

10K1/20W

MF

1%MF-LF1/16W

1%133K

6.8UH-4.0A

CRITICAL

34

100K5%1/20WMF

TDFN

CRITICAL

0201X5R-CERM

0.1UF

25

16

34

X5R-CERM

6.3V

1.0UF

0201

6.3V

0201

100K5%1/20WMFSOT563

SSM6N37FEAPE

34

TPS3808QFN

X5R-CERM

CRITICAL

TPS22920

6.3V

X5R-CERM

1.0UF

0201

MF

5%100K

SSM6N37FEAPE

34

19

49.9K

1/16W1%

MF-LF

VESM MF1/20W5%10K

10UF

0603X5R-CERM

25V20%

X5R-CERM0603

25V20%10UF

805X5R

4.7UF

TBT Power Support


=TBT_RESET_L

TBTBST_EN_UVLO

TBTPOCRST_MR_L

TBT_SW_RESET_L

TBT_PWR_ON_POC_RST_L

TBT_PCIE_RESET_L

=PP3V3_S0_PCH_GPIO

=PP3V3_S4_TBT

=PP3V3_S0_P3V3TBTFET

TBT_EN_CIO_PWR_L

=PP3V3_TBTLC_RTR

TBTBST_FBX



TBTBST_RT


=PP3V3_TBTLC_RTR

=TBT_CLKREQ_L

MAKE_BASE=TRUE

TBT_EN_LC_ISOL

TBTBST_PWREN_L

TBTBST_BOOSTMIN_LINE_WIDTH=0.5 mm

DIDT=TRUESWITCH_NODE=TRUE


PPVIN_SW_TBTBSTMIN_LINE_WIDTH=0.5 mm

=PPVIN_SW_TBTBST

TBTBST_VCMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

TBTBST_INTVCCMIN_LINE_WIDTH=0.2 mm

VOLTAGE=0V

SMC_DELAYED_PWRGD



PIMB062D-SM


1%

TBTBST_SS

20%25V

10UF25V20%

X5R-CERM

20%25V

X5R-CERM

20%25V

25V20%

0603

0603

0603

0603

0603

X5R-CERM

PP1V05_TBTLC

SSM3K15FV

TBT_A_HV_EN

TBTBST_PWREN_DIV_L

GND_TBTBST_SGNDMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

25V5%47PF

0201

SSM6N37FEAPE

TBTBST_SNS2

CRITICAL


CERM

5%

5%

CERM

TBTBST_VSNS_RC

SOT563


TBTBST_SNS1

10UF

10UF


TBTPOCRST_CT

CRITICAL

=PP1V05_TBTCIO_FET

0.1UF

X7R-CERM0201

330PF

16V

16V

16V

50V

50V

402

402 402

402

402

402

402

41.2K1%

1/20WMF

TBTBST_VC_RC

NP0-C0G-CERM

10V

201

201

201

201

201

201

201

201

201

201

201

201

10%

10%

10%

10%

10%

10%

10%

10%

10%

10VX7R-CERM0201

3300PF10%

TBTBST_SHDN_DIV


CERM25V10%0.0047UF

0402

10UF

X5R-CERM25V20%

0603

0603

20%25VX5R-CERM

10UF

0603

20%25VX5R-CERM

10UF0.001UF50V10%

=PP15V_TBT_REG

PLACE_NEAR=C3895.1:2 mm

10UF

X5R-CERM

10UF

POWERDI-123

X5R-CERM

TBTBST_VSNS

0402X7R-CERM

34 TBT_CLKREQ_L

201

1/20WMF

1%

1/20W

10%

0201

X5R-CERM

6.3V

36.5K

SSM3K15AMFVAPE

TBT_EN_LC_PWR

CSPTPS22924

TBT_EN_CIO_PWR

TBT_CLKREQ_ISOL_L

SLG4AP016V

=PP3V3_S0_TBTPWRCTL

CRITICAL

X5R-CERM

1.0UF

1.0UF

=PP1V05_TBTLC_FET

TBT_EN_LC_1V05

TPS22924

CRITICAL

CSP

10%

NO STUFF

1.0UF

6.3V

X5R-CERM

0201

=PP3V3_TBTLC_FET

201MF

1/20W5%

0TBT_EN_LC_3V3

R38801

2

C38801

2

Q38053

12

R38921

2

R38871

2

Q38883

54

Q38886

21

R38941

2

C38941

2

R38881

2

C38891

2

R38961

2

Q3880

23

1

4

R38911

2

U389025

31

12

13

14

15

16

17

28

1

2

10

35

36

33

6

3

4 23

24

37

32

8 9

20

21

38

34

30

27

XW3895

12

R38891

2

D3895A

K

C38991

2

C38931

2

R38811

2

R38931

2

R38951

2

L38951 2

R38071

2

U3800

6

5

7

3

8

4

2

9

1C3800 1

2

U3810

C1

C2

A2

B2

A1

B1

C3810 1

2

U3815

C1

C2

A2

B2

A1

B1

C3815 1

2

C3816 1

2

R38301

2

Q3825

3

54

U3830

3

5

4

62

7

1

C3830 1

2

U3820

D1

D2

A2

B2

C2

A1

B1

C1

C3820 1

2

R38201

2

Q3825 6

2 1

R38901 2

R38161

2

Q3840

3

12

R38401

2

C38251

2

C3890 1

2

C38911

2

C38921

2

C38951

2

C38971

2

C38841

2

C3883 1

2

C3896 1

2

C3898 1

2

C38871

2

C38881

2

C38311

2

C38821

2

C38811

2

C38111

2

R381112

051-9277

2.8.0

38 OF 109

36 OF 73

7

7

7

7 16 17 18 19

7 34 35

7

7 36

36

7 34 35 36

7 34 35

6 7

6 7

7

36

7

7

25

7

OUT

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

RESET*

OUTEN

MR*

GNDTHRM

IN

VDD

SENSE +-

PAD

(OD)

0.7V

DLYOUT

IN

IN

OUT

BI

BI

VCC

GND

SEL OE*

D+

D-

Y+

Y-

M+

M-

OUT

D

G S

IN

G

SD

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6 3



DLY = 60 MS +/- 20%

BLUETOOTH

LOADING

H USB_BTL USB_BT_WAKE

20-30 MOHM @2.5V

SEL OUTPUT

514S0335

CHANNEL

0.750 A (EDP)

P-TYPE

3V S3 WLAN FET

TPCP8102MOSFET

RDS(ON)

AIRPORT

6 17

62

0.1UFX5R6.3V

PLACEMENT_NOTE=Place close to J4001.

16 69

16 69

PLACEMENT_NOTE=Place close to J4001.

0.1UF 6.3V X5R

6 16 69

6 16 69

X5R6.3V

0.1UF

PLACEMENT_NOTE=Place close to Q4050.

6 16 69

6 16 69

0.020

MF-LF

CRITICAL

1%0.25W805

46 72

46 72

SLG4AP016VTDFN

CRITICAL 6.3VX5R

0.1UF

16

25

18 23 62

5%MF

100K1/20W

100K

MF1%

1/20W

232K1/20W

1%MF

0.1UF6.3VX5R

SSD-K99

CRITICAL

F-RT-SM1

6 41 42

603

10UF

X5R

PLACEMENT_NOTE=Place close to Q4050.

20%

0.1UF

0201X5R-CERM

16V

5%

0

MF1/20W

NOSTUFF

MF1/20W1%15K

1%1/20W

15K

MF

NOSTUFFBTPWR:S4

15K

MF1/20W1%

24 68

24 68

0.1UF6.3VX5R

TQFN

CRITICAL

PI3USB102ZLE

42 BTPWR:S4

SOD-VESM-HF

SSM3K15FV

BTPWR:S4

0

1/20W5%

17 26 41 49 62

MF1/20W

5%0

BTPWR:S3

MF

15K

1/20W1%

NOSTUFF

NOSTUFF

15K1%1/20WMF

15K

1/20W

NOSTUFF

BTPWR:S4

MF-LF

5%

0

402

1/16W

BTPWR:S3

1/16W

0

5%

MF-LF402

DFN2563-6

CRITICAL

DMP2018LFK

40216V

0.033UF

X5R

100K

1/20W5%MF

5%1/20WMF

10K


X21 WIRELESS CONNECTOR

PP3V3_WLAN_RVOLTAGE=3.3V

MIN_LINE_WIDTH=20 mmMIN_NECK_WIDTH=0.2 mm

=PP3V3_S3_WLAN

P3V3WLAN_SS

PP3V3_S3RS4_BT_FMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V

USB_BT_CONN_PUSB_BT_CONN_N

PCIE_WAKE_L

AP_RESET_CONN_L

AP_CLKREQ_Q_L

PCIE_AP_D2R_N

USB_BT_WAKE_P

PP3V3_S3RS4_BT_F

=PP3V3_S3_WLAN

BTMUX_SEL

USB_BT_WAKE_N


MIN_LINE_WIDTH=20 mm

PP3V3_WLAN_F

PCIE_CLK100M_AP_N

PCIE_CLK100M_AP_P

USB_BT_N

=BT_WAKE_L

USB_BT_P

PCIE_AP_R2D_C_N

PCIE_AP_R2D_C_P

WIFI_EVENT_L

PP3V3_WLAN_F

=PP3V3_S4_BT

PM_SLP_S4_L

AP_CLKREQ_LAP_CLKREQ_L_RP3V3WLAN_VMON

AP_RESET_L

PCIE_AP_R2D_N

AP_PWR_EN

PCIE_AP_R2D_P

PM_WLAN_EN_L

ISNS_AIRPORT_PISNS_AIRPORT_N

=PP3V3_S3_BT


1%

MF

PCIE_AP_D2R_P

MFNOSTUFF

0.01UF16V

X7R-CERM0402

10V

201

201

201

201

201

201

201

201

201

201

201201

201

201

201201

201

201

201

201

10%

10%

10%

10%

10%

10%

10%

10%

10%

C4021 1

2

C4051 1

2R40501 2

R40511

2

C4030

1 2

C40311 2

R4052

1 23 4

U4002

6

5

7

3

8

4

2

9

1

C4053 1

2

R40531

2

R40551

2

R40541

2

C40321

2

J4001

19

20

21

1

10

11

12

13

14

15

16

17

18

2

3

4

5

6

7

8

9

C40201

2 C40501 2

R409012

R40141

2

R40131

2

R40121

2

C40101

2

U4010

6

7

3

4

5

810

9

2

1

Q40103

12

R40111 2

R40181

2

R40171

2

R40161

2

R40151

2

R40011 2

R40021 2

Q4050

4

3

12

C4011 1

2

051-9277

2.8.0

40 OF 109

37 OF 73

7 37

6 37

6 68

6 68

6

6

68

6 37

7 37

68

6 37 42

6 37 42

7

6 69

6 69

7

OUT

OUT

OUT

OUT

IN

IN

A1_PA1_N

SEL

XSD

B0_P

B1_P

B0_N

B1_N

C0_P

C1_P

C0_N

C1_N

VDD

VDD

VDD

VSS

VSS

VSS

THRM

A0_PA0_N

PAD

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

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REVISION

BRANCH

6 3



PCIE/SATA GUMSTICK2 CONNECTOR

353S3361

514S0393

Per PCIe Spec, only TX side should have AC cap

FERR-70-OHM-4A

CRITICAL

0603

PLACE_NEAR=J4501.1:3mm

46 72

46 72

0.1UF

X5R-CERM02010201

0.1UF

X5R-CERM

8 66

8 66

8 66

8 66

0.1UF

PLACE_NEAR=U4510.1:2 mm

0201X5R-CERM


0.01UF16VX5R-CERM0201

VQFNCBTL02043ABQ

CRITICAL

16 68

16 68

16 68

16 68

6 41 42

6 41

10K5%

MF1/20W

16V 0201X5R-CERM

0.1UF

6 8 66

6 8 66

8 66

8 66 0.1UF

X5R-CERM 16V 0201

5%

MF1/20W

470K

16V 0201X5R-CERM

0.1UF

0201

0.1UF

16VX5R-CERM

X5R-CERM020116V

0.1UF

020116VX5R-CERM

0.1UF

0.01UF

16V 0201X5R-CERM

0.01UF

16V 0201X5R-CERM

0.01UF

16V 0201X5R-CERM

0.01UF

16V 0201X5R-CERM

X5R-CERM0201


0.1UF

CRITICAL

GND_VOID=TRUEGND_VOID=TRUE

F-RT-SMSSD-J5

GND_VOID=TRUE


GND_VOID=TRUE


6 25

6 16

6 16 66

6 16 66

61 62

MF1/20W

0

5%

6.3V

100UF20%

1206-1CERM-X5R

MF1W1%

0.002

CRITICAL

0612

CERM-X5R

100UF

1206-1

20%6.3V

NOSTUFF


SSD CONNECTOR


VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6mmMIN_NECK_WIDTH=0.150mm

PP3V3_S0_SSD_FLT MIN_NECK_WIDTH=0.150mmMIN_LINE_WIDTH=0.6mm

VOLTAGE=3.3V

PP3V3_S0_SSD_R

PCIE_SSD_R2D_MUX_IN_P

SATA_SSD_R2D_N

ISNS_SSD_NISNS_SSD_P

=PP3V3_S0_SSD

SATA_SSD_R2D_P

PCIE_SSD_D2R_MUX_OUT_N

SATA_SSD_D2R_MUX_OUT_P

PCIE_SSD_R2D_C_P<1>

=PP3V3_S0_SATAMUX

SMC_OOB1_TX_LSMC_OOB1_RX_L

SSD_RESET_L

PCIE_SSD_R2D_N<1> PCIE_SSD_R2D_C_N<1>

SSD_P3V3S0_EN =P3V3S0_EN

SATA_SSD_R2D_MUX_IN_P

SATAMUX_EN_L

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_HDD_R2D_C_NSATA_SSD_R2D_MUX_IN_N

PCIE_SSD_D2R_N<0>

PCIE_SSD_D2R_P<0>

SATA_SSD_D2R_MUX_OUT_N

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_R2D_C_N<0>

PCIE_SSD_D2R_MUX_OUT_P

SATA_HDD_R2D_C_P

PCIE_SSD_R2D_MUX_IN_N

SATA_SSD_D2R_N

PCIE_SSD_R2D_P<1>

PCIE_CLK100M_SSD_PPCIE_CLK100M_SSD_N

SATA_PCIE_SEL

SATA_SSD_D2R_P

SSD_CLKREQ_L

PCIE_SSD_D2R_N<1>

PCIE_SSD_D2R_P<1>

10V10V

10V10V

201

201

201

10%10%

10% 10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

L4500

1 2

C45021

2

C45011

2

C45141

2

C45191

2

U4510

43

87

1819

1617

1415

1213

9

21

1 610

511

20

2

R45101

2

C4521 1 2

C4520 1 2

R45051

2

C4518 1 2

C4517 1 2

C4513 1 2

C4512 1 2

C4516 1 2

C4515 1 2

C4511 1 2

C4510 1 2

C45051

2

J4501

272829303132333435

1

101112131415161718

19

2

20212223242526

3456789

R45201 2

C45031

2

R4599

1234

C45041

2

051-9277

2.8.0

45 OF 109

38 OF 73

6

66

6 68

7

6 68

66

68

7

6 66

6

68

68

68

66

66

6 68

6 66

6

6 68

OUT

OUT

IN

IN

L2

L1

L2

L1

NC

NC

GND

VBUS IO

IO

NC

NC

GNDSSRX-SXRX+GNDD+

GND

SSTX+SSTX-

D-

VBUS

SYM_VER-1

BI

BI

IN

OUT

IN

OUT

GNDTHRM

OUT2OUT1

ILIM

IN_0IN_1

EN2

FAULT1*FAULT2*

EN1

PAD

VCC

GND

SELOE*

D+D-

Y+

Y-

M+

M-

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6 3



Mojo SMC Debug Mux

SEL=0 Choose SMCSEL=1 Choose USB

Right USB Port A

Current limit per port (R4600): 2.18A min / 2.63A max

USB Port Power Switch

10%

10%

10%

10%

10%

201

201

201

201

201

201

10V

PP5V_S3_RTUSB_A_ILIM

VOLTAGE=5V


USB2_EXTA_MUXED_N

USB2_EXTA_MUXED_F_NUSB2_EXTA_MUXED_P USB2_EXTA_MUXED_F_P

USB3_EXTA_RX_F_NUSB3_EXTA_RX_F_P

USB3_EXTA_TX_F_N

USB3_EXTA_RX_P

USB3_EXTA_TX_F_P

USB3_EXTA_RX_N

USB3_EXTA_TX_C_N

USB3_EXTA_TX_C_P

PP5V_S3_RTUSB_A_FMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.375 mmVOLTAGE=5V

SMC_DEBUGPRT_RX_L

USB_EXTA_PUSB_EXTA_N

=PP3V42_G3H_SMCUSBMUX

SMC_DEBUGPRT_EN_L

USB3_EXTA_TX_N

USB3_EXTA_TX_P

SMC_DEBUGPRT_TX_L

USB_EN2

USB_EXTA_OC_L

=PP5V_S3_RTUSB

=USB_PWR_EN

USB_ILIM


External A USB3 Connector

FERR-120-OHM-3A

0603

CRITICAL

CRITICAL

220UF-35MOHM6.3V20%

CASE-B2-SM1POLY-TANT

1/16W

402MF-LF

1%23.2K

PI3USB102ZLE

CRITICALTQFN

MOJO:YES

SIGNAL_MODEL=MOJO_MUX

SON

TPS2561DR

CRITICAL

0402-2CERM-X5R

10UF6.3V20%

23

MOJO:NO

5%

0

MF1/20W

MOJO:NO

0

5%1/20WMF

41

68 42 41

68 42 41

MF1/20W

10K

MOJO:YES

5%

0201X5R-CERM

0.1UF

MOJO:YES

68 18

68 18

0201

16VX5R-CERM

0.1UF 10UF

0402-2CERM-X5R

6.3V20%

DLP0NS90-OHM

CRITICAL

TSSLP-2-1ESD0P2RF-02LS

CRITICAL


CRITICAL

ESD0P2RF-02LSTSSLP-2-1

CRITICAL

CRITICAL


CRITICAL

F-RT-THUSB3.0-J11-J13

1/20WMF

05%

SLP1210N6CRITICAL

RCLAMP0582N

80OHM-25%-100MA

GND_VOID=TRUECRITICAL

0504

CRITICAL

80OHM-25%-100MA0504

GND_VOID=TRUE

X5R6.3V

0.1UF

GND_VOID=TRUE

0.1UF

GND_VOID=TRUE

6.3VX5R

68 18

68 18

68 18

68 18

0201X5R-CERM

0.01UF16V

C4695 1

2

C46911

2

C4650 1

2

R46501

2

R46511 2

R46521 2

C4690 1

2

U4600

4

5

10

6

1

7

2

3

9

8

11

U4650

6

7

3

4

5

8 10

9

2

1

R46001

2

C46961

2

L4605

1 2

C4605 1

2

C4620

1 2

C4621

1 2

L4610

1 2

34

L4620

1 2

34

D4600

1

452 3

6

R46011

2

J4600

56

4

7

10

1112131415161718

9

32

8

1

D4610

1

2

D4620

1

2 D4621

1

2

D4611

1

2

L4600

1 2

34

051-9277

2.8.0

46 OF 109

39 OF 73

68

68

68 68

68

68

68

68

68

68

7

7

62 40 6

IN

IN

BI

BI

BI

BI

OUT

OUT

IN

OUT

IN

IN

OUT

BI

BI

BI

OUT

IN

OUT

BI

BI

IN

IN

IN

IN

IN

OUT

OUT

Apple Inc.


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REVISION

BRANCH

6 3



(Right Speaker Enable)

ON MLB SIDE AS LIO CAN’T FIT CAPS

998-4617

10%16V

0201X5R-CERM


0.1UF

6 41 42 49

6 16 69

X5R-CERM0201

10%16V


0.1UF

6 18 68

6 18 68

6 24 68

6 24 68

6 18

6 25

6 51 72

6 51 72

6 41 42

6 39 62

6 18

6 41

6 44

6 44

23

6 16 69

6 44

6 44

6 16 69

6 16 69

6 16 69

GND_VOID=TRUE

1/20W

0

MF5% 201

16V10%

GND_VOID=TRUE

0.1UF0201

X5R-CERM

NOSTUFF

0201

0.1UF

GND_VOID=TRUE

16V

X5R-CERM10%

NOSTUFF

0.1UF020116V

10%X5R-CERM

GND_VOID=TRUE

GND_VOID=TRUE

2015%1/20WMF

0

GND_VOID=TRUE

020110%16V 0.1UF

X5R-CERM

18 68

18 68

18 68

18 68

DF40CG3.0-48DS-0.4V

CRITICAL

F-ST-SM

ESD0P2RF-02LS

CRITICAL

TSSLP-2-1

CRITICAL


CRITICAL


CRITICAL


X5R-CERM


0.1UF

0201

16V10%

Left I/O (LIO) Connector


USB3_EXTB_RX_RC_N

=PP3V42_G3H_ONEWIRE

USB_CAMERA_N

USB3_EXTB_RX_RC_P

USB3_EXTB_TX_C_N

USB3_EXTB_TX_C_P

USB3_EXTB_RX_P

USB3_EXTB_RX_N

USB3_EXTB_TX_P

USB3_EXTB_TX_N

SPKRAMP_INR_N

AUD_IPHS_SWITCH_EN

=PP3V3_S0_AUDIO

=PP3V3R1V5_S0_AUDIOAUD_I2C_INT_L=USB_PWR_ENSMC_BC_ACOK

=I2C_LIO_SCL

SYS_ONEWIRE

=I2C_LIO_SDA

AUD_GPIO_3SMC_LIDHDA_RST_LUSB_EXTB_OC_L

=I2C_MIKEY_SCLHDA_SYNC

=I2C_MIKEY_SDA

HDA_SDIN0HDA_BIT_CLKHDA_SDOUT

USB_EXTB_PUSB_EXTB_N

USB_CAMERA_P

AUD_IP_PERIPHERAL_DET

SPKRAMP_INR_P

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

C47001

2

C4710 1

2

C4720 1

2

R47101 2

C4731

1 2

C47321 2

C4722

1 2

R47201 2

C4721

1 2

J4700

1

1011 1213 1415 16

19

2

2021 2223 2425 2627 2829

3

3031 32

35 3637 3839

4

4041 4243 4445 4647 48

49

5

50

51 52

67 89

D4711

1

2D4710

1

2

D4720

1

2 D4721

1

2

051-9277

2.8.0

47 OF 109

40 OF 73

6 68

6 7

6 68

6 68

6 68

6 7

6 7

LPC0AD3LPC0CLKLPC0FRAME*

LPC0AD1LPC0AD2

AIN08AIN07

LPC0CLKRUN*LPC0PD*

AIN13AIN14

PM7/FAN0TACH0PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RXPECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DPUSB0DM

AIN03AIN02

T0CCP1/PB7T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18AIN19

WT4CCP0/PH6WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119PP4/IRQ120

C0-

WT2CCP0/PH0WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+T3CCP1/PJ5/C2-

PF4PF5

T1CCP0/PJ0

T2CCP0/PJ2T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDOTDI

RST*

HIB*WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCKSWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

IN

BI

BI

BI

BI

IN

IN

IN

BI

OUT

IN

OUT

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

OUT

IN

NC

OUT

NC

BI

OUT

IN

OUT

OUT

IN

OUT

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

BI

IN

IN

OUT

IN

NC

OUT

IN

IN

OUT

OUT

IN

IN

IN

IN

OUT

BI

IN

OUT

BI

BI

BI

IN

BI

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NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR ENG PKG

1.2V FOR ENG PKG

(OD)

NC FOR ENG PKG

NC FOR ENG PKG

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

(OD)

(OD)

NC FOR ENG PKG

(OD)

(OD)

(OD)

(OD)

(OD)

(OD)

NC FOR STACK BRD

(OD)

(OD)

(OD)

NOTE:

NOTE:

(OD)

(OD)

NC FOR ENG PKG

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR STACK BRD

NC FOR ENG PKG

(OD)

NC FOR STACK BRD

those designated as inputs require pull-ups.pins designed as outputs can be left floating,

(OD)

SMS Interrupt can be active high or low, rename net accordingly.

Unused pins have "SMC_Pxx" names. Unused

If SMS interrupt is not used, pull up to SMC rail.

SMC_VCCIO_CPU_DIV2CPU_PROCHOT_L

SMC_ADC21

SMC_ADC18

CPU_THRMTRIP_3V3CPU_CATERR_LSPI_DESCRIPTOR_OVERRIDE_LSMC_S5_PWRGD_VIN

=PP3V3_S5_SMC

PP1V2_S5_SMC_VDDCMIN_LINE_WIDTH=0.25MMMIN_NECK_WIDTH=0.1MMVOLTAGE=1.2V

PM_SYSRST_L

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_0_S0_SCL

LPC_CLK33M_SMC

LPC_AD<2>

SMC_ADC8SMC_ADC7

SMC_FAN_0_CTL

SMC_ADC4

SMC_ADC9

SMC_ADC11

SMC_ADC15

SMC_ADC6

SMC_ADC10

SMC_ADC12

SMC_ADC1

SMC_ADC3SMC_ADC2

SMC_ADC16

SMC_ADC19

SMC_BATLOW_L

SMC_THRMTRIP

SPI_SMC_CLK

SMBUS_SMC_4_ASF_SCL

SMBUS_SMC_2_S3_SCL

S5_PWRGDPM_PCH_SYS_PWROK

SMC_TDO

SMC_RESET_L

WIFI_EVENT_L

SMC_TCKSMC_TMS

SMC_CLK32K

SMC_WAKE_L

SMC_DELAYED_PWRGD

SPI_SMC_CS_L

SPI_SMC_MISO

SYS_ONEWIRE

SMC_ADC13

SMC_BIL_BUTTON_L

SMC_T25_EN_L

SMBUS_SMC_4_ASF_SDA

SMC_RUNTIME_SCI_L

LPC_SERIRQ

LPC_AD<3>

SMBUS_SMC_2_S3_SDA

SMBUS_SMC_1_S0_SDA

LPC_PWRDWN_LPM_CLKRUN_L

LPC_FRAME_L

LPC_AD<1>

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_5_G3_SDASMBUS_SMC_5_G3_SCL

SMC_PECI_L

SMC_XTAL

NC_SMC_XOSC1

NC_SMC_HIB_L

SMC_EXTAL

SMC_TDI

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.25MMPP3V3_S5_SMC_VDDA

VOLTAGE=3.3V

SMC_ADC22

SMC_ADC20

SMC_ADC17

LPC_AD<0>

SMC_LRESET_L

SMBUS_SMC_3_SCL

SMC_WAKE_SCI_L

SMC_ADC14

SPI_SMC_MOSI

SMC_OOB1_TX_LSMC_OOB1_RX_L

SMC_ADAPTER_EN

SMC_GFX_OVERTEMPSMC_DEBUGPRT_EN_L

SMBUS_SMC_3_SDA

SMC_PROCHOT

SMC_DEBUGPRT_RX_LSMC_DEBUGPRT_TX_LSMC_SYS_LED

PP3V3_S5_AVREF_SMC

GND_SMC_AVSS

MEM_EVENT_L

SMC_FAN_0_TACHSMC_FAN_1_CTLSMC_FAN_1_TACHSMC_MPM5_LED_PWR

SMC_SYS_KBDLED

HISIDE_ISENSE_OC

CPU_PECI_R

SMC_MPM5_LED_CHG

PM_DSW_PWRGD

SMC_S4_WAKESRC_EN

SMC_LID

USB_SMC_P

PM_SLP_S5_L

SMC_PM_G2_EN

SMC_GFX_THROTTLE_L

ALL_SYS_PWRGD

BDV_BKL_PWM

SMC_DP_HPD_L

SMC_ONOFF_L

PM_PWRBTN_L

SMC_ADC23

SYS_TDM_ONEWIRE

SMC_ODD_DETECT

USB_SMC_N

SMC_TX_LSMC_RX_L

PM_SLP_S4_LPM_SLP_S3_LG3_POWERON_LSMC_BC_ACOKSMS_INT_LENET_ASF_GPIO

SMC_PME_S4_DARK_LSMC_PME_S4_WAKE_L

IR_RX_OUT_RC

SMC_ADC5

SMC_ADC0


SMC

PLACE_NEAR=U4900.D1:1MMPLACE_NEAR=U4900.D2:1MM

1UF6.3V0201X5R20%

42

PLACE_NEAR=U4900.D2:1MM

0.01UF

X5R

PLACE_NEAR=U4900.D1:1MM

1.0UF

0201-1X5R-CERM

20%1.0UF

0201-1X5R-CERM

20%

NOSTUFF

20%

X5R-CERM0201-1

1.0UF

42

42

68 24

68 24

42

8

42

20%1UF6.3VX5R0201

0.1UF

X5R-CERM0201

0.1UF

X5R-CERM0201

0.1UF

0201X5R-CERM

0.1UF

X5R-CERM0201

0.1UF

X5R-CERM0201

X5R-CERM0201

0.1UF

42

42

66 10

25 23 17

40 6

42 38 6

42

38 6

66 57 42 10

30-OHM-1.7A

0402

25

62

42

42

42

42 37 6

62 42

62 42

42

49 42 6

62 17

62 49 37 26 17

62 26 17

42

42 40 6

42

49 42 40 6

49 42 6

42

48

48

49

42

42

42

43 42 6

43 42 6

42

42

19

62 42 17

25 17

23 17

42

62 52 25 23

42

39

69 42

69 42

69 42

69 42

8

68 42 39

68 42 39

42

42 36 25

17

62

42

42

42

42

42

42

42

42

42

42

42

42

42

42

42

42

42

42

42

42

42

42

42

42

71 44

71 44

42

42

71 44

71 44

71 44

71 44

71 44

71 44

71 44

71 44

19

43 25 17 6

43 17 6

43 16 6

25

69 43 16 6

69 25

69 43 16 6

69 43 16 6

69 43 16 6

69 43 16 6

X5R-CERM

0.1UF

0201

0.1UF

0201X5R-CERM

0201X5R-CERM

0.1UF

0201

0.1UF

X5R-CERM0201X5R-CERM

0.1UF

0.1UF

0201X5R-CERM

0201

0.1UF

X5R-CERM

1M

MF5%1/20W

69 42

53 43 42 6

PLACE_NEAR=U4900.A1:4MM

SM

OMIT_TABLE

LM4FSXAH5BBBGA

OMIT_TABLE

BGALM4FSXAH5BB

10V

10V10V10V

10V

10V 10V 10V 10V 10V

10V

10V 10V

10V 10V

10V 10V

201

201

10%

10%

10% 10% 10% 10% 10%

10%

10% 10%

10% 10%

10% 10%

U4900

E2E1F2F1B3A3B4A4B5A5B6A6C1C2B1B2G2G1H1H2B7A7B8A8

K2K1L2

E10D13M4N2N8M8L8K8N7M7N4N3

B13A13C12D11H12

G11

D12

F13

C13

F12

H13

L1

C4C6

L9K9

J4J2

B12

C11A12

H11L13

G3

D10

L11N12N11M11

M13L12M5J12

J13L5D8K6

D4E4F5N5N6K5M6L6

M2M3L4N1

L10K10

M9N9

F4F3

C9B9A9C8

D5C5

L3M1

F11E11

E13E12

K7L7

K3K4

J3H4H3G4

H10

U4900

A1C7

K11

D9E5F9H5H9J5J8J11

C3E3

M12

G12G13

B11

G10 C10A10A11B10

K12

D7E6E8E9F10J7J9J10

D3

J1J6

K13D6

D1D2

N13

M10

N10

XW490012

R49021

2

C49061

2

C49051

2

C49091

2

C49081

2

C49041

2

C49031

2

C49071

2

L49011 2

C49171

2

C49161

2

C49151

2

C49141

2

C49131

2

C49011

2

C49021

2

C49101

2

C49111

2

C49121

2

C49201

2

C49211

2

051-9277

2.8.0

49 OF 109

41 OF 73

A2

42

42

42 7

42

43 42 6

43 42 6

43 42 6

42

42

43 42 6

42

46 45 42

IN

OUT

BI

IN

IN

IN

REFOUT

MR1*

THRMGND

RESET*

DELAY

MR2*

VINV+

SN0903048

PAD

OUT

IN OUT

OUT

IN OUT

OUTIN

OUTIN

OUTIN

OUTIN

OUT

IN

D

GS

D

G S

D

S G

D

S G

BIOUT

IN

OUT

IN

Apple Inc.


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SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



SMC12 SPI Supporttopology of 2 SPI Masters are verified.

SMC12 Eng Pkg Support

Module has 3.3K PU

SMC Crystal CircuitSMC USB Clock require these crystalvalues:5,6,8,10,12,16,18,20,24,25 MHz

From SMC

with comparators on Stack Board.

MR1* and MR2* must both be low to cause manual reset.

Mobiles: 3.42VDesktops: 5V

SMC Reset "Button", Supervisor & AVREF Supply

From/To CPU/PCH

(IPU)

PM_BATLOW_L in PCH.

To SMC

Internal 20K pull-up on

(IPU)

Debug Power "Buttons"

Used on mobiles to support SMC reset via keyboard.NOTE: Internal pull-ups are to VIN, not V+.

Eng Package requires 1.2V ON SMC_ADC23 pin.

BATLOW# Isolation

ADC10 and ADC11 are shared

SMC12 PECI Support

Note:

Series resistors are no stuffed until the

MF10K

1/20W

MF100K

1/20W1/20W

10KMFMF

100K1/20W

10K1/20W MF10K1/20W MF

MF10K

1/20W10K1/20W MF

1/20W MF10K

41 42

19

PLACE_SIDE=BOTTOM

1/10W

0

SILK_PART=PWR_BTN

OMIT

MF-LF603

10 41 57 66

41

NO STUFF

1/20W MF10K

10K1/20W MF

1/20W MF100K

MF10K

1/20W

PLACE_SIDE=TOP

1/10W

0

OMIT

MF-LF603

SILK_PART=PWR_BTN

SILK_PART=SMC_RST

PLACEMENT_NOTE=Place R5001 on BOTTOM side

0

OMIT

1/10W603MF-LF

6 41 42 49

6 49

0.01UF

X5R

CERM-X5R

0.47UF6.3V402 VREF-3.3V-VDET-3.0V

CRITICAL

DFN

0.01UF

X5R

MF1/20W

100K

6 41 43 53

17 69

221/20WPLACE_NEAR=U1800.D3:5.1mm MF

41 69

100K1/20W MF

6 41 49

100K

MF1/20W

41 62 17

100K

MF1/20W

NOSTUFF

0

MF-LF402

1/16W

10KMF1/20WMF1/20W

100K

10K1/20W MF

1/20WMF

1K

100K1/20W MF

NO STUFF

43 50 69 69

43 50 69 41

43 50 69 41

43 50 69 41

01/20W

SMC_PACKAGE:ENG

MF

1%MF1/20W

100K

MF1/20W1%100K

MF1/20W10K

6 41 42 49

41

MF

NOSTUFF

1/20W

1.6K

0

1/20WMF

1/20WMF

330

NO STUFF10K1/20W MF

MF100K

1/20W

VESM

SSM3K15AMFVAPE

CRITICAL

VESM

CRITICAL

SSM3K15AMFVAPE

CRITICALSOT563SSM6N15AFE

SSM6N15AFE

CRITICALSOT563

100K1/20W MF

NO STUFF33K

1/20W MF

10 19

66 41


43

MF1/20W

10 19 66

DFN1006-3

CRITICAL

MMBT3904LP-7

41 42

10UF

X5R-CERM0402-1

20%

1/20W

3.3K

MF

34

1/20W100K

MF

100KMF1/20W

12.000MHZ-30PPM-10PF3.2X2.5MM-SM

CRITICALMF

1/20W1%

2.49K


SMC SupportSYNC_DATE=11/10/2011

PM_CLK32K_SUSCLK_R

SMC_PECI_L

CPU_PECI_R

PM_THRMTRIP_R_L

SMC_ONOFF_L

MEM_EVENT_LCPU_THRMTRIP_3V3

SMC_THRMTRIP

MAKE_BASE=TRUESMC_LCDBKLT_ISENSE

MAKE_BASE=TRUESMC_3V3S0_ISENSE

NC_SMC_ADC20MAKE_BASE=TRUE

G3_POWERON_L

SMC_BC_ACOK

SMC_DEBUGPRT_RX_L

SMC_TX_L

SMS_INT_LSMC_S5_PWRGD_VIN

SMC_TCKSMC_TDI

SMC_ROMBOOT

SMC_ONOFF_L

SMC_DP_HPD_L NC_SMC_DP_HPD_LMAKE_BASE=TRUESMC_BC_ACOKMAKE_BASE=TRUE

=CHGR_ACOK

=TBT_WAKE_L

ENET_ASF_GPIO

SMC_ADC17

SMC_ADC19

SMC_ADC21

SMC_GFX_OVERTEMP

=PP3V3_S0_SMC=PP3V3_S4_SMC

SMC_PME_S4_DARK_L

MAKE_BASE=TRUESMC_GFX_VSENSE

SMC_BIL_BUTTON_L

SMC_TDO

SMC_DEBUGPRT_TX_L

SMC_TMS

SMC_LID

SMC_OOB1_TX_L

SMC_ODD_DETECT

=PPVIN_S5_SMCVREF

=PP3V3_SUS_SMC

=PP3V3_S4_SMC

SMC_ADC6

SMC_ADC3

SMC_ADC15

CPU_PECI

SMC_PECI_L_R

=PPVCCIO_S0_SMC

MAKE_BASE=TRUENC_SMC_ADC21

NC_SCM_ADC17MAKE_BASE=TRUE

SMC_ADC5

SMC_DCIN_ISENSEMAKE_BASE=TRUE

SMC_ADC14

MAKE_BASE=TRUESMC_OTHER_HI_ISENSEMAKE_BASE=TRUESMC_HS_COMPUTING_ISENSESMC_ADC8

SMC_ADC4MAKE_BASE=TRUESMC_DCIN_VSENSE

SMC_ADC2

SMC_HDD_ISENSEMAKE_BASE=TRUE

SMC_ONOFF_L

=PPVCCIO_S0_SMC

PP3V3_WLAN_F

WIFI_EVENT_L

=PP3V3_S5_SMC

=PP3V3_S5_SMCBATLOW

PM_BATLOW_L

SMC_TPAD_RST_LSMC_PROCHOT

SMC_BATLOW_L

SMC_PBUS_VSENSEMAKE_BASE=TRUE

SMC_ADC9

SMC_CPU_ISENSEMAKE_BASE=TRUE

SMC_ADC23SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUESMC_CPUVCCIO_ISENSE

NC_SMC_GFX_OVERTEMPMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_CPU_SA_ISENSE

SMC_ADC23

SMC_ADC12

SMC_ADC10

SMC_ADC11

SMC_RESET_L

SMC_ADC13

SMC_ADC16

SMC_VCCIO_CPU_DIV2

MAKE_BASE=TRUENC_HISIDE_ISENSE_OC

MAKE_BASE=TRUENC_SMBUS_SMC_4_ASF_SDAMAKE_BASE=TRUENC_SMBUS_SMC_4_ASF_SCL

SMC_MANUAL_RST_L MIN_LINE_WIDTH=0.4 mmVOLTAGE=3.3VMIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.4 mmGND_SMC_AVSSMIN_NECK_WIDTH=0.1 mmVOLTAGE=0V

SMC_ADC0

MAKE_BASE=TRUESMC_WLAN_ISENSE

SMC_1V5S3_ISENSEMAKE_BASE=TRUE

MAKE_BASE=TRUESMC_BMON_ISENSESMC_ADC7

SMC_GFX_ISENSEMAKE_BASE=TRUE

PP1V2_S5_SMC_VDDC

PM_THRMTRIP_LSMC_ADC22

SMC_ADC20

SMC_ADC18

SMC_CLK32K

HISIDE_ISENSE_OC

SMBUS_SMC_4_ASF_SDA

MAKE_BASE=TRUENC_SMC_ADC22

NC_SMC_ADC19MAKE_BASE=TRUE

MAKE_BASE=TRUESMC_ADC23

MAKE_BASE=TRUENC_SMC_GFX_THROTTLE_L

NC_ENET_ASF_GPIOMAKE_BASE=TRUENC_SMC_MPM5_LED_PWRMAKE_BASE=TRUE

SDCONN_STATE_CHANGE_SMC

NC_BDV_BKL_PWMMAKE_BASE=TRUE

BDV_BKL_PWM

SMC_PME_S4_DARK_LMAKE_BASE=TRUE

SMC_T25_EN_L

MAKE_BASE=TRUESMC_PME_S4_WAKE_L=BT_WAKE_L

MAKE_BASE=TRUENC_SYS_TDM_ONEWIREMAKE_BASE=TRUENC_SMC_MPM5_LED_CHG

SMC_FAN_1_TACH

SMC_GFX_THROTTLE_L

SMC_FAN_1_CTL

NC_SMC_T25_EN_LMAKE_BASE=TRUE

SMC_ADC1

SMC_CPU_VSENSEMAKE_BASE=TRUE

SMC_VCCSA_VSENSEMAKE_BASE=TRUE

=PP3V3_S5_SMC

SMC_RX_L

SMC_S4_WAKESRC_EN

SMC_ADAPTER_EN

SMC_DELAYED_PWRGD

SMC_THRMTRIP

SMC_XTAL

SMC_EXTAL

SMC_XTAL_R

CPU_PROCHOT_L

PM_THRMTRIP_L_R

CPU_THRMTRIP_3V3

PP3V3_S5_AVREF_SMC

69

SPI_SMC_MOSI SPI_MLB_MOSI

MF1/20W

15PLACE_NEAR=U6100.5:1MM

SPI_MLB_CLK15

1/20WMF

PLACE_NEAR=U6100.6:1MM

15 SPI_MLB_CS_LPLACE_NEAR=U6100.1:1MM

69

69

SPI_SMC_CS_L

1/20WMF

41 24.9

MF

SPI_SMC_MISO SPI_MLB_MISO

SYS_TDM_ONEWIRE

SMC_MPM5_LED_CHG

SMC_MPM5_LED_PWR

MAKE_BASE=TRUENC_SMC_FAN_1_TACHMAKE_BASE=TRUENC_SMC_FAN_1_CTL

1%1/20W

SPI_SMC_CLK


5%

5%5%5%

5%5%5%5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%5%

5%

5%

5%

5%

5%

5%

5%

5%

5%5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

25VNP0-C0G-CERM0201

12PF5%

25VNP0-C0G-CERM0201

12PF5%

10V10V10V

201

201201201

201201201201

201

201

201

201

201

201201

201

201

201

201

201

201201

201

201

201201

201

201

201

201

201

201

201201

201

201

201

201

201

201

201

201

201

201

201

10%

10%

10%

R5070 1 2

R5071 1 2R5073 1 2R5074 1 2

R5077 1 2R5078 1 2R5079 1 2R5080 1 2

R5085 1 2

R50151

2

R5089 1 2

R5081 1 2

R5092 1 2

R5072 1 2

R50161

2

R50011

2

C5001 1

2

C5020 1

2 U5010

4

2

67

8

5

9

1 3

C50261

2

R50001

2

R50121 2

R5090 1 2

R50821

2

R50401

2

R50411 2

R5075 1 2R5076 1 2

R5086 1 2

R50881

2

R5068 1 2

R50991

2

R50971

2

R50961

2

R5093 1 2

R50531

2

R50521 2

R50511

2

R5014 1 2R5017 1 2

Q5040

3

12

Q50503

1 2

Q50596

21

Q50593

54

R5067 1 2

R5066 1 2

R50341 2

Q50581

3

2

C5025 1

2

R50581 2

R5087 1 2

R5091 1 2

Y5010

2 4

1 3

R50101 2

C50101

2

C50111

2

R50221 2

R50231 2

R50241 2

R50211 2

051-9277

2.8.0

50 OF 109

42 OF 73

41

41 42

46

45

41

6 40 41 42

39 41 68

6 41 43

41

41

6 41 43

6 41 43

6 43

6 41 42 49

41

6 40 41 42 45 53

41

41

41

41

41

41

7

7 42

41 42

45

41

6 41 43

39 41 68

6 41 43

6 40 41 49

6 38 41

41

7

7

7 42

41

41

41

41

7 42 41

46

41

46

46 41

41

45

41

46

7 42

6 37

6 37 41

7 41 42

7

45

41

45

41 42

41

41

45

45

41 42

41

41

41

41

41

41

41

41 45 46

41

46

46

46 41

45

41

41

41

41

41

41

41 42

33

41

41 42

41

37

41

41

41

41

45

45

7 41 42

6 41 43

41 62

17 41 62

25 36 41

41 42

41

41

OUTIN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

OUT

IN

BI

BI

OUT

IN

BI

IN

IN

OUT

BI

BI

IN

OUTIN

OUTIN

INOUT

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LPC+SPI Connector

998-4235

SPI Bus Series Termination

42 50 69

1/20W

201

5%

MF

16 69

6 41 42

6 41 42

6 41 42

6 41 42

6 42

6 41 42 53

6 41 42

6 19

6 25 69

6 16 41 69

6 16 41 69

6 43

6 16 41 69

6 25 69

6 16 41 69

6 41 42

6 17 25 41

6 16 41

6 43

6 43

6 17 41

6 19 50

6 16 41 69

6 43

LPCPLUSCRITICAL

M-ST-SMDF40C-30DP-0.4V

42 50 69

5%

MF

16

42 50 69

PLACE_NEAR=U1800.AD12:5mm

5%

MF

1569

42 50 69 16 69


LPC+SPI Debug Connector

SMC_TDOTP_SMC_TRST_LTP_SMC_MD1SMC_TX_L

SMC_TMSSMC_RX_LSMC_ROMBOOTSMC_RESET_LSMC_TCKSMC_TDI

LPC_AD<0>LPC_CLK33M_LPCPLUS

=PP3V3_S5_LPCPLUS

SPI_ALT_MISO

SPI_ALT_CLK

LPC_SERIRQLPC_PWRDWN_L

SPI_ALT_MOSI

LPC_AD<1>LPC_AD<3>

SPI_MISO

SPI_CLK

SPI_MOSISPI_MOSI_R

SPI_ALT_CLK

PM_CLKRUN_L

SPIROM_USE_MLBLPC_FRAME_L

SPI_ALT_CS_L

=PP5V_S0_LPCPLUS

LPC_AD<2>

SPI_ALT_MISOSPI_ALT_MOSI

LPCPLUS_GPIOLPCPLUS_RESET_L

SPI_CLK_R

PLACE_NEAR=U1800.AB8:5mm

15

1/20W

SPI_CS0_L

PLACE_NEAR=U1800.W8:5mm

16

69 SPI_CS0_R_L15

SPI_ALT_CS_L

LPCPLUS

435%1/20WMF

LPCPLUS

435%1/20WMF

PLACE_NEAR=J5100.14:5mmPLACE_NEAR=J5100.12:5mm

MF1/20W5%

LPCPLUS

43PLACE_NEAR=J5100.9:5mm

SPI_MLB_CS_L

PLACE_NEAR=R5125.2:5mm5%

MF

43

SPI_MLB_CLK43

1/20WMF

5%

43

1/20WMF

5%PLACE_NEAR=R5127.2:5mm

SPI_MLB_MOSI

1/20W


SPI_MLB_MISO

MF1/20W1%24.9

LPCPLUS

PLACE_NEAR=U6100.2:5mm

24.9

1%1/20WMF

1/20W

201

201

201

201

201

201

201 201201201

R51101 2

R51111 2

R51121 2

J5100

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

23 24

25 26

27 28

29

3

30

31 32

33 34

4

5 6

7 8

9

R51251

2

R51261

2

R51271

2

R51201 2

R51211 2

R51221 2

R51231 2

R51281

2

051-9277

2.8.0

51 OF 109

43 OF 73

6

6

6 7

69

69

69

6 43

6 7

6 43

6 43

43 6

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6 3



PCH S0 SMBus "0" Connections

Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88) N Y * Y *

U3600

(Write: 0x72 Read: 0x73)

(* = Multiple options)

Battery Manager - (Write: 0x16 Read: 0x17)

ISL6258 - U7000


EMC1414-A: U5570

U9701

(WRITE: 0x58 READ: 0x59)

LED BACKLIGHT

Left I/O Board

(See Table)J4700

CPU Temp

U4900

U4900

(MASTER)

VRef DACs

U1800

Battery

J6955

U4900

(MASTER)

(MASTER)

Battery

U1800

SMC

(See Table)

(MASTER)

U4900

SMC

(MASTER)

U1800

Cougar-Point

U4900

Margin Control

SMC

(MASTER)

XDP Connectors

SMLink 1 is slave port to

Cougar-Point

Battery ChargerSMC

(MASTER)

U3301


U3300


J5700

Trackpad

EMC1704: U5400


Internal DP

(See Table)J9000

K21 K78 Samsung LGD Samsung LGD AUO

TBT & Inlet Temp

Cougar-Point



TBT

(Write: 0xXXX Read: 0xXXX)

ALS - (write: 0x72 Read: 0x73)Finstack Temp - (Write: 0x92 Read: 0x93)

SMC S0 "1" SMBus Connections

Parade T-con - (0x10-0x1F or 0x30-0x3F) Y N * N *

NOTE: SMC RMT bus remains powered and may be active in S3 state

DVR - (Write: 0x4E Read: 0x4F) Y Y Y Y N

SMC

SMC "0" SMBus S0 Connections


SMC "5" SMBus G3H Connections


Mikey

U6800

Left I/O Board

J2600 & J2650

(MASTER)

Internal DP

PCH S0 "SMLink 0" Connections


PCH S0 "SMLink 1" Connections

access PCH

201

4.7K5%1/20WMFMF

4.7K

201

5%1/20W

2.0K1/20W

MF201

5%2.0K

MF

5%1/20W

201

1/20W

1K

201

5%

MF201

5%

MF

1K1/20W

201MF

5%1/20W

4.7K

201

4.7K

MF1/20W

5%

201MF

1/20W5%

8.2K

201MF

8.2K1/20W5%

1K

MF201

5%1/20W1/20W

MF

1K5%

201

201MF

5%2.0K

1/20W

2.0K

1/20W5%

MF201


SMBus Connections

=PP3V3_S0_SMBUS_PCH

MAKE_BASE=TRUE

SMBUS_PCH_CLK

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

=I2C_LIO_SDA

=I2C_LIO_SCL

=SMBUS_CHGR_SCL

=I2C_BKL_1_SDA

=PP3V3_S3_SMBUS_SMC_MGMT

SML_PCH_0_DATAMAKE_BASE=TRUE

=SMBUS_BATT_SDA

=SMBUS_BATT_SCL

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V3_S0_SMBUS_PCH

=I2C_VREFDACS_SCL

=SMBUS_CHGR_SDA

=I2C_VREFDACS_SDA

=SMBUS_XDP_SDA

=I2C_PCA9557D_SDA

=I2C_TBT_INLET_THMSNS_SDA

=I2C_TPAD_SDA

=I2C_BKL_1_SCL

=PP3V3_S3_SMBUS_SMC_A_S3

=I2C_TBT_INLET_THMSNS_SCL

=I2C_TPAD_SCL

SMBUS_SMC_2_S3_SCLMAKE_BASE=TRUE

SMBUS_SMC_2_S3_SDAMAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_SMC_3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

SMBUS_SMC_5_G3_SCLMAKE_BASE=TRUE

=I2C_PCA9557D_SCL

=I2C_TBTRTR_SCL

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCLMAKE_BASE=TRUE

=PP3V3_S0_SMBUS_SMC_B_S0

=I2C_TCON_SDA

=I2C_TCON_SCL

=I2C_TBTRTR_SDA

=I2C_MIKEY_SCL

=SMBUS_XDP_SCL

MAKE_BASE=TRUE

SMBUS_PCH_DATA

=PP3V3_S0_SMBUS_SMC_0_S0

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

=I2C_MIKEY_SDA

SML_PCH_1_CLK

SML_PCH_0_CLKMAKE_BASE=TRUE

SML_PCH_1_DATA

R52611

2

R52601

2

R52801

2

R52811

2

R52701

2

R52711

2

R52511

2

R52501

2

R52101

2

R52111

2

R52011

2

R52001

2

R52911

2

R52901

2

051-9277

2.8.0

52 OF 109

44 OF 73

7 44

16 69

47

47

6 40

6 40

53

65

7

16 69

6 52

6 52

7

7 44

31

53

31

23

31

46

6 49

65

7

46

6 49

41 71

41 71

41 71

41 71

41 71

41 71

31

34

41 71

41 71

7

63

63

34

6 40

23

16 69

7

41 71

41 71

6 40

16 69

16 69

16 69

OUT

IN

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUTIN

IN

V+

REFIN+

IN- OUT

GND

OUT

OUT

IN

IN

IN

IN

V+

V-THRM

V+

V-THRM

OUT

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

IN

IN

OUT

IN

IN

V-

V++

-

V-

V++

-

OUT

IN

IN

OUT

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



divider when SUS present.

divider when AC present.

Enables DC-In VSense

Enables DC-In VSense

divider when in S0.

GFX/IG Vcore Voltage Sense / Filter

GFX/IG VCore Load Side Current Sense / Filter

Max VOut: 3.3V at 19.77V Input

DC-In Voltage Sense Enable & Filter

PBUS Voltage Sense Enable & Filter

Sense R is R7510 Sense R is 0.75mOhm

(200V/V)

CPU 1.05V VCCIO Current Sense / Filter

VCCSA Voltage Sense / Filter

RTHEVENIN = 4573 Ohms

CPU VCore Load Side Current Sense / Filter

EDP: 33A TDP :28.05A

Max VOut: 2.73V at 39.934AScale: 12.1A / V

Scale: ???A / V

3.3V S0 FET Current Sense / Filter

Gain: 200x

Gain:161.765x

EDP: 8.5A TDP :7.225A

Enables PBUS VSense

RTHEVENIN = 4573 Ohms

Max VOut: 3.3V at 19.77V Input

Scale: 8.24A / V

Max VOut: 3.3V at 8.25A

Sense R is R7640, 2mOhm

Sense R is 1mOhm

Max VOut: ???V at ???A

Gain:???

Max VOut: ???V at ???A

Gain:110.181x

Sense R is R7550

EDP: 5A Gain:???

Scale: ???A / V

Sense R is 0.75mOhmEDP: 18A TDP: 15.3A

CPU SA Current Sense / Filter

Scale: 2.5A / V

Sense R is R7831

Sense R is 1mOhmEDP: 6A

Sense R is R7140

CPU Vcore Voltage Sense / Filter


42

0.22UF

02016.3V20%X5R

PLACE_NEAR=U4900.C1:5MM

4.53K

1%


201MF

1/20W

62 1%

MF201

100K1/20W

100K1%

1/20WMF201

42

20%

0201X5R6.3V0.22UF


PLACE_NEAR=U4900.A3:5MM27.4K1/20W

MF201

1%


201

5.49K1%MF

1/20W

NTUD3169CZSOT-963

42

1/20W201MF

4.53K

1%

VCCIOISNS_ENGPLACE_NEAR=U4900.A6:5MM

VCCIOISNS_ENG6.3V0201

20%X5R

0.22UF


6.3VX5R

0.1UF10%

201

VCCIOISNS_ENG

59 72

59 72

SC70

VCCIOISNS_ENG

CRITICAL

INA210PLACE_NEAR=R7640.3:5MM


PLACE_NEAR=U4900.E1:5MM

1%

4.53K

MF1/20W201

42

42

PLACE_NEAR=U4900.E1:5MMPLACE_NEAR=U4900.M11:5MM

0.22UF6.3V20%X5R0201

PLACE_NEAR=U4900.H1:5MMPLACE_NEAR=U4900.M13:5MM

02016.3VX5R20%0.22UF


10%X5R6.3V201

0.1UF

PLACE_NEAR=U4900.H1:5MM

4.53K

201MF

1/20W1%

58 72

58 72

57 58 72

58 72

CRITICAL

OPA2333DFN

CRITICAL

OPA2333DFN

42

1%

MF201

1/20W PLACE_NEAR=U4900.F1:5MM

27.4K

20%

0201

0.22UF6.3VX5R

PLACE_NEAR=U4900.F1:5MM

1%

MF1/20W

5.49K

201


100K1%

MF1/20W

201

NTUD3169CZSOT-963

MF

1%

201

1/20W

100K

42

20%0.22UF

X5R6.3V0201

PLACE_NEAR=U4900.C2:5MM201

1/20WMF1%

4.53K


0.1UF10%


X5R2016.3V

54 72

54 72

42

0.22UF

PLACE_NEAR=U4900.B1:5MM

20%X5R6.3V0201


MF201

1%1/20W

4.53K

61 72

61 72

SC70-5OPA333DCKG4

CRITICAL

CRITICAL

SC70-5OPA333DCKG4


0.1UF

201X5R6.3V10%

42

1%

PLACE_NEAR=U4900.F2:5MM201

4.53K

MF1/20W

0.22UF


20%6.3VX5R0201

SM

PLACE_NEAR=R7140.2:5 MM

0201

1/20W

4.42K

0.1%

MF


MF0201

1/20W


4.42K

0.1%


0201MF

1/20W0.1%

4.42K

PLACE_NEAR=R7550.4:5MM MF0201

1/20W

4.42K

0.1%

0201

487K0.1%

MF1/20W

MF

715K

0.1%1/20W

0201

SIGNAL_MODEL=EMPTY

0201

0.1%

MF

487K

1/20WSIGNAL_MODEL=EMPTY

715K

MF1/20W0.1%

0201


1.82K

0201MF

0.1%1/20W


0201

1.82K

0.1%1/20WMF


1.82K

0201

0.1%1/20WMF


0201

1.82K

0.1%1/20WMF

MF0201

1/20W0.1%1.00M

0201

SIGNAL_MODEL=EMPTY

1.00M

1/20WMF

0.1%

0201 SIGNAL_MODEL=EMPTY

1.00M

1/20WMF

0.1%

1.00M

0201MF1/20W0.1%

NOSTUFF

201

05%

MF1/20W

42 53

62

201

1/20WMF

5%0

SM

PLACE_NEAR=R7550.2:5 MM

42 4.53K

1/20W201MF1%

PLACE_NEAR=U4900.E2:5MM

0.22UF20%6.3VX5R0201

PLACE_NEAR=U4900.E2:5MMPLACE_NEAR=R7510.2:5 MM

SM


Voltage & Load Side Current Sensing

DCINVSENS_EN

PM_SUS_EN

=PPDCIN_S5_VSENSE

PDCINVSENS_EN_L_DIV

=CHGR_ACOK

DCIN_S5_VSENSE

CPUIMVP_ISUM_IOUT

CPUIMVP_ISUM_R_N

CPUIMVP_ISUM_R_P

CPUIMVP_ISUMG_R_PCPUIMVP_ISUMG_IOUT

CPUIMVP_ISUMG_R_N

GND_SMC_AVSS

GND_SMC_AVSS

SMC_VCCSA_VSENSE

=PP3V3_S0_SAISNS

VCCSAISNS_R_N

VCCSAISNS_R_P

SMC_CPUVCCIO_ISENSE

CPUVSENSE_IN

DCINVSENS_EN_L

SMC_DCIN_VSENSE

GND_SMC_AVSS

=PBUSVSENS_EN

PBUSVSENS_EN_L

PBUS_S0_VSENSE

GND_SMC_AVSS

=PPBUS_S0_VSENSE

SMC_PBUS_VSENSE

GFXVSENSE_IN SMC_GFX_VSENSE

GND_SMC_AVSS

GND_SMC_AVSS

SMC_CPU_SA_ISENSE

SMC_GFX_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS

CPUVCCIOS0_CS_N

CPUVCCIOS0_CS_P GND_SMC_AVSS

CPUIMVP_ISNS1_N

CPUIMVP_ISNS1G_N

=PPGFXVCORE_S0_VSENSE

SMC_3V3S0_ISENSE

=PP3V3_S0_IMVPISNS

CPUIMVP_ISNS1_P

=PPCPUVCORE_S0_VSENSE

=PP3V3_S0_3V3S0ISNS

GND_SMC_AVSS

=PP3V3_S0_CPUVCCIOISNS ISNS_3V3S0_P

ISNS_3V3S0_N

ISENSE_3V3S0_IOUT

ISNS_3V3S0_R_N

ISNS_3V3S0_R_P

CPUVCCIO_IOUT

CPUIMVP_ISNS1G_P

ISENSE_SA_IOUT

PBUSVSENS_EN_L_DIV

VCCSAS0_CS_N

VCCSAS0_CS_P=PPVCCSA_S0_VSENSE VCCSAVSENSE_IN

SMC_CPU_VSENSE

SMC_CPU_ISENSE

C53301

2

R53301 2

XW53301 2

R53201 2

C53201

2

XW53201 2

R53021

2

R53011

2

C53041

2

R53031

2

R53041

2

Q5300

6

3

2

5

1

4

R53611 2

C53611

2

C53601

2U5360

2

5

4

6

1

3

R53411 2

C53411

2

C53511

2

C53401

2

R53511 2

U53403

2

1

94

8

U53405

6

7

94

8

R53131

2

C53141

2

R53141

2

R53121

2

Q5310

6

3

2

5

1

4

R53111

2

C53711

2

R53711 2

C53701

2

C53811

2

R53811 2

U53701

3

4

2

5

U53801

3

4

2

5

C53801

2

R53401 2

C53501

2

XW53401 2

R53421 2

R53431 2

R53521 2

R53531 2

R53441

2

R53551 2

R53451 2

R53541

2

R53721 2

R53731 2

R53821 2

R53831 2

R53741

2

R53751 2

R53851 2

R53841

2

R53151

2

R53161

2

051-9277

2.8.0

53 OF 109

45 OF 73

72

72

72

72

41 42 45 46

41 42 45 46 72

72

41 42 45 46

41 42 45 46

7

41 42 45 46

41 42 45 46

41 42 45 46

41 42 45 46

41 42 45 46

7

7

7

7

41 42 45 46

7

72

7

OUT

OUTIN

OUT

OUT

OUT

OUT

IN

IN

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

IN

IN

IN

IN

IN

IN

OUTIN

IN

OUTIN-

IN+ REF

V+

GND

BI

BI

BI

BI

BI

BI

OUT

IN

OUT

ALERT*

THERM*/ADDRDP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3GND

IN

V+

REFIN+

IN- OUT

GND

V+

REFIN+

IN- OUT

GND

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



DDR3 1V5R1V35 Current Sense / Filter

AirPort Current Sense / Filter

GAIN: 200X(200V/V)

(200V/V)Scale: 0.25A / VMAX VOUT: 3V AT 0.825A

PLACEMENT_NOTEs:

SCALE: 5A / V

Max Vdiff: 15 mV

Max Vdiff: 31 mV

TBT/Inlet Temp Sensor



OTHER High Side Current Sense / Filter

DC-IN (AMON) Current Sense Filter

EDP Current: 15.5 A


Read Address: 0x99

MAX VOUT: 3.1V at 16.5A


Max Vdiff: 31 mV

SCALE: 0.667A / VMAX VOUT: 3.3V AT 2.2A

(For R and C)


(500V/V)

MAX VOUT: 3.3V AT 0.66ASCALE: 0.2A / V


GAIN: 500X

ISL6259 Gain: 20x

DC-In AMON

Scale: 2.5A / V

EDP Current: 3.5A


(500V/V)

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

EDP Current: 12 A

PLACEMENT_NOTEs:

MAX VOUT: 2.4V AT 16.5A

Gain: 200x

Max Vdiff: 7.0 mV

EDP Current: 0.67 AMax Vdiff: 6.7 mV

(For R and C)

EDP Current: 0.750 A

(For R and C)

EDP Current: 2.36A


GAIN: 500X

(100V/V)

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

GAIN: 50X

MAX VOUT: 3.1V at 16.5A

GAIN: 100X

EDP Current: 15.5 A

SCALE: 5A/ V

Charger BMON (Production) Solution

EDP Current: 310A

ISL6259 Gain: 36x


Scale: 2.78A / V

From charger

CHARGER BMON High Side (BATTERY DISCHAEGE) Current Sense, MUX & Filter

LCD Backlight Driver Input Current Sense / Filter

Write Address: 0x98

COMPUTING High Side Current Sense / Filter

(For R and C)

SCALE: 5A/ V

Max Vdiff: 24 mV

HDD Current Sense / Filter

(50V/V)

42

42 PLACE_NEAR=U4900.B3:5MM

0.22UF20%6.3VX5R0201


4.53K

MF

1%1/20W

53

42

42

42

42

PLACE_NEAR=U4900.B6:5mm

Place close to SMC

X5R

20%6.3V

0.22UF

0201


4.53K

1%

Place close to SMC

MF1/20W

0.1UF6.3VX5R

56 72

56 72


Place close to SMC

0.22UF

X5R

20%6.3V

AIRPORTISNS_ENG

0201


Place close to SMC

1%1/20WMF

4.53K

AIRPORTISNS_ENG


HDDISNS_ENG

Place close to SMC

6.3V20%0.22UF

X5R0201


1/20W

HDDISNS_ENG

Place close to SMC

1%

4.53K

MF

X5R

0.1UF6.3V

AIRPORTISNS_ENGAIRPORTISNS_ENG

INA210SC70

HDDISNS_ENG

INA211SC70

PLACE_NEAR=U4900.G2:5mm

LCDBKLTISNS_ENG

6.3V

0.22UF20%

X5R0201

Place close to SMC

PLACE_NEAR=U4900.G2:5mm

4.53K

1%1/20WMF

LCDBKLTISNS_ENG

LCDBKLTISNS_ENG

6.3VX5R

0.1UF

SC70INA211

LCDBKLTISNS_ENG

37 72

37 72

38 72

38 72

8 72

8 72


1/20WMF

1%

300K

42


0201

Place close to SMC

6.3V20%

X5R

0.22UF


MF

Place close to SMC

1/20W

4.53K

1%

X5R6.3V

0.1UF

8 72

8 72

SC70INA214

X5R6.3V

HDDISNS_ENG

0.1UF

5%1/20WMF

10K10K5%

1/20WMF

44

44

6.3VX5R

0.1UFMF

5%1/20W

47

PLACE_NEAR=U5410.3:5mmPLACE_NEAR=U5410.2:5mm

0201

2200PF

X7R-CERM

SIGNAL_MODEL=EMPTY47 72

47 72


SIGNAL_MODEL=EMPTY

X7R-CERM0201

2200PF

47

47

42

Place close to SMC


0.22UF

0201X5R

20%6.3V


1/20W1%

MF

4.53K

Place close to SMC

6.3VX5R

0.1UF

MF

1%

CRITICAL

1W

0.005

0612

7

7

EMC1414-1-AIZL

CRITICAL

MSOP

53

INA210SC70

CRITICAL

SC70INA213

High Side Current Sensing


=PP3V3_S3_1V5S3ISNS

ISNS_1V5_S3_P

ISNS_1V5_S3_N ISNS_1V5S3_IOUT

ISNS_P5VWLAN_IOUT

=PP3V3_S0_HDDISNS

=TBTTHMSNS_D2_P

=TBTTHMSNS_D2_N

SMC_1V5S3_ISENSE

ISNS_HS_COMPUTING_P

INLET_THMSNS_D1_N

SMC_DCIN_ISENSE

TBT_INLET_THM_L

=PP3V3_S0_HS_COMPUTING_ISNS

GND_SMC_AVSS

TBT_INLET_ALERT_L

=I2C_TBT_INLET_THMSNS_SDA

ISNS_SSD_N

ISNS_SSD_P

GND_SMC_AVSS

ISNS_P5VHDD_IOUT

ISNS_AIRPORT_P

GND_SMC_AVSS

SMC_LCDBKLT_ISENSE

SMC_HDD_ISENSE

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

GND_SMC_AVSS

SMC_WLAN_ISENSE

ISNS_LCDBKLT_IOUT

=PP3V3_S0_BKLTISNS

CHGR_AMON

ISNS_AIRPORT_N

GND_SMC_AVSS

=PP3V3_S3_WLANISNS

GND_SMC_AVSS

SMC_HS_COMPUTING_ISENSE

SMC_OTHER_HI_ISENSE

=PPVIN_S5_HS_OTHER_ISNS_R

ISNS_HS_COMPUTING_IOUT

=PP3V3_S0_HS_COMPUTING_ISNS

ISNS_HS_COMPUTING_N

=I2C_TBT_INLET_THMSNS_SCL

INLET_THMSNS_D1_P

GND_SMC_AVSS

SMC_BMON_ISENSECHGR_BMON

=PPVIN_S5_HS_OTHER_ISNS

VOLTAGE=3.3VMIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.5 mmPP3V3_S0_HS_COMPUTING_ISNS_R

GND_SMC_AVSS

HS_OTHER_IOUTISNS_HS_OTHER_N

ISNS_HS_OTHER_P

=PP3V3_S0_HS_OTHER_ISNS

10V

10V

201

201

201

201

201

201

201

201

201

201

201

201

201201

201

201

201

201

10%

10%

10%

10%

10%

10%

10%

10%

10%


10VX7R-CERM0201

3300PF10%

C54311

2

R5431

1 2

C54651

2

R54651 2

C54601

2

C54751

2

R54751 2

C54851

2

R54851 2

C54701

2U5470

2

5

4

6

1

3

U5480

2

5

4

6

1

3

C54951

2

R54951 2

C54901

2U5490

2

5

4

6

1

3

R5422

1 2

C54221

2

C54551

2

R54551 2

C54501

2U5450

2

5

4

6

1

3

C54801

2

R54121

2

R54111

2

C54101

2

R54101 2

C5411 1

2

C5412 1

2

C54331

2

R54331 2

C54301

2

R5430

12

34

U5410

83

5

2

4

6

10

9

7

1

U5460

2

5

4

6

1

3

U5430

2

5

4

6

1

3

051-9277

2.8.0

54 OF 109

46 OF 73

7

7

7 46

41 42 45 46

41 42 45 46

41 42 45 46

41 42 45 46

7

41 42 45 46

7

41 42 45 46

7 46

41 42 45 46

41 42 45 46

72

72

7

BI

BI THRM_PADDN2/DP3

DP2/DN3

VDD

SMDATA

SMCLKGND

DN1

DP1 THERM*/ADDR

ALERT*

BI

BI

BI


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Place Q5510 next to DDR/5V/3.3V supply on TOP sidePlacement note:

Detect DDR/5V/3.3V Proximity Temperature

TBT,MLB Bottom & Inlet Proximity Sensors

Placement note:

To connect Proximity Sensor, Stuff R5540 & R5541, No Stuff R5550,R5551

TBT Die

Write Address: 0x98

Detect TBT Die Temperature

Placement note:Place Q5520 close to TBT on TOP side

Place Q5530 between near rear vent on bottom side

Use GND pin B1 on U3600 for N leg

To connect Die Sensor, Stuff R5550 & R5551, No stuff R5540 & R5541

Placement note:

Place U5510 under CPUPlacement note:

Read Address: 0x99

CPU Proximity Sensor

Detect CPU Die Temperature

Replacing caps with 100K PD on ISENSE SMC inputs

Place Q5540 on MLB bottom side opposite U5400

10K

MF1/20W5%

MF1/20W

5%10K


SIGNAL_MODEL=EMPTY

X7R-CERM

2200PF

0201

9 72

9 72

DFNEMC1413

CRITICAL

34

SM


5%

0

MF1/20W

5%

MF1/20W

0

1/20W5%

MF

0

NO STUFF

NO STUFF

1/20W5%

MF

0

DFN1006H4-3BC846BLP

BC846BLPDFN1006H4-3

BC846BLPDFN1006H4-3

BC846BLPDFN1006H4-3

44

44

6.3VX5R

0.1UF

47

5%

MF1/20W

X7R-CERM

SIGNAL_MODEL=EMPTY


0201

2200PF

Thermal Sensors


AIRPORTISNS_PRODRES,MF,1/20W,100K OHM,5,0201,SMD C54751117S0008

117S0008 RES,MF,1/20W,100K OHM,5,0201,SMD1 VCCIOISNS_PRODC5361

C5485 HDDISNS_PROD1 RES,MF,1/20W,100K OHM,5,0201,SMD117S0008

C5495 LCDBKLTISNS_PROD117S0008 1 RES,MF,1/20W,100K OHM,5,0201,SMD

=MLBBOT_THMSNS_D3_N

=MLBBOT_THMSNS_D3_P

TBTTHMSNS_D2_R_P

TBTTHMSNS_D2_R_N

INLET_THMSNS_D1_P

INLET_THMSNS_D1_N

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 mmPP3V3_S0_CPUTHMSNS_R


=TBTTHMSNS_D2_P

=I2C_CPUTHMSNS_SCL

TBT_THERMD_N =TBTTHMSNS_D2_N

TBT_THERMD_PMAKE_BASE=TRUE

=TBTTHMSNS_D2_N TBT_MLBBOT_THMSNS_NMAKE_BASE=TRUE

CPUTHMSNS_THM_L

CPUTHMSNS_ALERT_L

=I2C_CPUTHMSNS_SDA

CPU_THERMD_P

CPU_THERMD_N

=PP3V3_S0_CPUTHMSNS

=TBTTHMSNS_D2_P

TP_TBT_THERM_DP

TBT_MLBBOT_THMSNS_PMAKE_BASE=TRUE

=MLBBOT_THMSNS_D3_P

=MLBBOT_THMSNS_D3_N

=TBTTHMSNS_D2_P

=TBTTHMSNS_D2_N

10V

10V

201201

201

201

201

201

201

201

10%

10%

10%

C55101

2

R55101 2

C5512 1

2

R55121

2

R55111

2

C5511 1

2

U5510

83

5

2

4

6

10

9

7

11

1

XW55201 2

R55401 2

R55411 2

R55501 2

R55511 2

Q5510 1

3

2

Q5530 1

3

2

Q5520 1

3

2

Q5540 1

3

2

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47 OF 73

47

47

72

72

46 72

46 72

72

72

46 47

72 46 47

72

46 47 72

7

46 47 72

47

47

46 47

46 47

D

GS

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NCGNDMOTOR CONTROLTACH5V DC

NC

FAN CONNECTOR

518S0793

47K

201MF

1/20W5%

201

47K1/20W

5%MF

100KMF

1/20W5%

201SOD-VESM-HFSSM3K15FV

FF14A-4C-R11DL-B-3HF-RT-SM

CRITICAL


Fan

FAN_RT_PWM

FAN_RT_TACH

SMC_FAN_0_CTL

SMC_FAN_0_TACH

=PP3V3_S0_FAN=PP5V_S0_FAN

R56651 2

R5660 1

2

R5661 1

2

Q5660

3

12

J5600

5

6

1

2

3

4

051-9277

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48 OF 73

6

6

41

41

7

6 7

IN

BI

BI

VIN

SW

OUTFB

EN

NC

THRMGND PAD

NC

NC

NC

VCC

GND

SELOE*

D+D-

Y+

Y-

M+

M-

BI

BI

OUT

IN

OUT

OUT

BI

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Keyboard Backlight Driver & Detection

Keyboard Backlight Connector

IPD Flex Connector

grounded when KB BL flex connected.

SEL=0 Choose pull up/downSEL=1 Choose USB

518S0794

tristate and read SMC_SYS_KBDLED:

518S0793If HIGH, keyboard backlight not present If LOW, keyboard backlight present

R5853 always stuffed, R5854 only

on keyboard backlight flex J5815 pin 1 is grounded

To detect Keyboard backlight, SMC will

MF

10K5%

1/20W

1/20WMF

10K5%

17 26 37 41 62

1/20W

0

5% MF

24 68

24 68


CRITICAL

NOSTUFF

16V

0201

MLFMIC2292

CRITICAL

50V

0603-1X5R-CERM

0.22UF

0603-1X5R-CERM

50V

0.22UF

X5R-CERM0201

0.1UF

16V

TQFNPI3USB102ZLE

CRITICAL

PLACE_NEAR=J5700.13:1.5MM

0.1UF

6.3VX5R

6 44 49


CRITICAL

6.3V

0.1UF

X5R


6 44 49

6 41 42 49

6 40 41 42 49

6 42 49

PLACE_NEAR=J5700.10:1.5MM0402-LF

FERR-120-OHM-1.5A

1/20W5% MF

0

6 41 42

402

4.75%1/16WMF-LF

10UH-0.58A-0.35OHM

1098AS-SM

CRITICAL

BYPASS=U5750.1:2:2 MM

402-1X5R

1UF

41

0201

0.1UF

X5R-CERM16V


IPD / KBD Backlight


=I2C_TPAD_SDA

SMC_TPAD_RST_L

KBDLED_SW


SWITCH_NODE=TRUE

SMC_SYS_KBDLED

SMC_ONOFF_LSMC_LID

SMC_ONOFF_L

=I2C_TPAD_SCL

SMC_PME_S4_WAKE_L

SMC_LID

=I2C_TPAD_SDA=I2C_TPAD_SCL

=PP3V3_S4_TPAD

PP5V_TPAD_FILTVOLTAGE=5V MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20mm

MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20mmVOLTAGE=3.3V

=PP5V_S5_TPAD


KBDLED_ANODEMIN_LINE_WIDTH=0.25 MM


KBDLED_FB

=PP5V_S0_KBDLED

PM_SLP_S4_L

USB_TPAD_M_NUSB_TPAD_M_P

USB_TPAD_NUSB_TPAD_P

USB_TPAD_MUX_SEL

=PP3V3_S4_TPAD

USB_TPAD_R_NUSB_TPAD_R_P


0.1UF

X5R-CERM

=PP3V42_G3H_TPAD

PP3V3_TPAD_CONN

100PF5%

25VNP0-CERM


NP0-CERM25V5%

100PF

100PF5%

25VNP0-CERM

100PF5%

25VNP0-CERM

SMC_TPAD_RST_L0201

0201

0201

0201





0201

100PF5%

25VNP0-CERM

10V

201

201

201

201

201

201

10%

10%10%

10%

10%

10%

10%

10%

C5700 1

2

C5720 1

2

J5700

15

16

1

10

11

12

13

14

2

3

4

5

6

7

8

9

L5720

1 2

R57301 2

R57551

2

L5750

1 2

C5750 1

2

C5701 1

2R57031

2

R57021

2

R57041 2

J5715

5

6

1

2

3

4

C5704 1

2

U5750

3

6

4 81

7

9

2

C57561

2

C5755 1

2

C5710 1

2

U5700

67

3

45

8 10

9

21

C5732 1

2C5733 1

2 C5734 1

2 C5735 1

2 C5736 1

2

57 OF 109

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5

6 7

6 44 49

6 40 41 42 49

6 41 42 49

6 44 49

7 49

6

6

7

6 6

7

68

68

68

68

7 49

6 42 49

OUTIN

IN IN

IN RST*/HOLD*

CE*WP*

SCK

VSS THRM_PAD

SI/SIO0

SO/SOI1

VDD

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High Speed CLK Frequency - 50MHz for fast read dual I/ODUAL I/O MODE (MODE 0 & 3) SUPPORTED

ROM will ignore SPI cycles.NOTE: If HOLD* is asserted

=PP3V3_SUS_ROM

SPI_MLB_CLK

SPI_MLB_CS_LSPI_WP_L

SPI_MLB_MISO

SPIROM_USE_MLB

SPI_MLB_MOSI

SPI ROM


X5R-CERM

10%0.1UF

16V

0201

SST25VF064COMIT_TABLE

64MBITWSON

CRITICAL

43 19 6

69 43 42 69 43 42

69 43 42 69 43 42

3.3K5%

201

1/20WMF

R61011

2

U6100

1

7

6 5

2

9

84

3

C6100 1

2

051-9277

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50 OF 73

7

IN

IN

ININ-IN+ OUT+

OUT-

GAINSHDN*

PVDD

NC

PGND

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ALIAS OF PP5VLT_S3, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.25MM

6DB

SPEAKER LOWPASS

GAIN

APN:353S2888

80 HZ < FC < 132 HZ

SPEAKER AMPLIFIERS

SPKRAMP_ROUT_N



SPKRAMP_ROUT_P

SPKRAMP_INR_N

SPKRAMP_INR_P

AUD_GPIO_3

R_AMP_GAINR_SPKRAMP_SHDN

MAX98300_R_P

=PP5V_S3_AUDIO_AMP

MAX98300_R_N

PP5V_S3_U6210


VOLTAGE=5V


AUDI0: SPEAKER AMP

CRITICAL

0201X5R-CERM

16V10%

0.1UF 0201

16V10%

0.1UF

CRITICAL

X5R-CERM

0

5%1/20WMF201

100K

MF

5%

201

NOSTUFF

1/20W

1/20W5%

201MF

100K

1/20WMF

5%

201

100K

CRITICAL

WLPMAX98300

72 40 6

40 6

5%

201MF

0

1/20W

20%6.3VPOLY-TANT

47UF

2012-LLP

CRITICAL

6.3V10%

X5R

0.1UF

201

72 40 6

C6207 1

2

C62011

2

R62101 2

U6210

C3

B3

A3

C1

B1

A2

A1

C2

R62121

2R62111

2

R62131

2

R62141 2

C6210

1 2

C6211

1 2

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B2

72 52 6

72 52 6

72

7

72

IN

BI

D

GS

IN

IN

IN

NC

SW

BOOSTVIN

BIASSHDN*

GND

NCFB

PADTHRM

G

D

S

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DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL5.1V Zener

Supply needs to guarantee 3.31V delivered to SMC VRef generator

3.425V "G3Hot" Supply

<Rb>

60MA MAX OUTPUT

Vout = 3.425V

(Switcher limit)

Battery Connector

K16-Specific

Vout = 1.25V * (1 + Ra / Rb)

<Ra>

Debug LEDs(For development only)

Right Speaker Connector

518S0519

518S0540

518S0508

MLB to LIO Power Cable Connector

10%

10%

10%10%

10%

10%

10%

10%

201

201

201

201

X7R

10V

10V

10V

402

402

402

402

402

50V

50V

16V

16V

6

6 44

SC-75

CRITICAL

MF1/20W

5%10K

1UF

X5RM-RT-SM

CRITICAL

M-RT-SMWTB-PWR-M82

CRITICAL

MF-LF1/16W5%1K

S3_S0_LEDS3_S0_LED

1/20WMF

5%1K

S3_S0_LED

SSM3K15FV

S3_S0_LED

SOD-VESM-HF

2.0X1.25MM-SMGREEN-3.6MCD

23

M-RT-SM78171-0002

CRITICAL

6 51 72

6 51

CRITICAL

DP418C-SM

CERM

0.22UF

BAT30CWFILMSOT-323

CRITICAL

805

5%

MF-LF1/8W

4.7

1/8W5%

805MF-LF

10

1%348K

1/20WMF

1/20WMF

200K1%

DFN

CRITICAL

LT3470A

MF

603-1

0.1UF

0201

CRITICAL

1UF25VX5R

1UF25VX5R

CRITICAL

5.6UF20%

POLY-TANTCASE-B2-SM

25V

CRITICAL

0402-1X5R-CERM

20%10UF

0402-1X5R-CERM

20%10UF

X5R35V

1UF

CRITICAL

1UF35V

603

DC-In & Battery Connectors


=PP18V5_DCIN_CONN

=PP5V_S3_LIO_CONN


PPVIN_G3H_P3V42G3HMIN_LINE_WIDTH=0.4 mm

SPKRAMP_ROUT_P

=SMBUS_BATT_SCL

PPBUS_G3H

P3V42G3H_BOOST


PPVBAT_G3H_CONN

SYS_DETECT_L=SMBUS_BATT_SDA

SPKRAMP_ROUT_N

DBGLED_S3

DBGLED_S0

DBGLED_S0_D




VOLTAGE=18.5V

ALL_SYS_PWRGD

VOLTAGE=18.5V

PPBUS_G3H_R

=PP3V42_G3H_REG


41

CRITICAL


=PP3V3_S3_DBGLEDS

72

GREEN-3.6MCD2.0X1.25MM-SM

33UH-20%-0.39A-0.435OHM

CRITICALCRITICAL

P3V42G3H_FB

PPDCIN_G3H_OR_PBUS_R

P3V42G3H_SW

WTB-PWR-M82

NO STUFF

NO STUFF

RCLAMP2402B


22PF5%

NP0-C0G-CERM0201

X5R

201

603

0.1UF

X5R-CERM


40.2K1%1/20W

44

0.1UF

X5R25V

402

10%

GDZ-0201

100K

MF1/20W5%

S3_S0_LED

NO STUFF

62

SI5419DUPOWERPAK

=PP18V5_DCIN_ISOL

10%

402

25VX5R

0.1UF

DIDT=TRUE

25

201

GDZT2R6.8

CRITICAL

CRITICAL

DCIN_ISOL_GATE

1 RES,MF,1/20W,90.9KOHM,1,0201,SMD118S0560 MPM5:YESR6912

MPM5:YES1 R6911117S0008 RES,MF,1/20W,100KOHM,1,0201,SMD

MPM5:NO

MPM5:YES

0

1/20WMF

5%

201

MPM5:NO

DCIN_ISOL_GATE_R

D6950

3

1 2R69501

2

C69501

2

C6951 1

2

J6950

1

2

3

4

5

6

7

8

9

J6900

1

2

3

4

5

6R69411

2

R69401

2

D6911A

K

Q69403

12

D6910A

K

J6903

3

4

1

2

L6995

1 2

C6994 1

2

D6905

1

2

3

R69061 2

R69051 2

R69951

2

R69961

2

U6990

2

3

1

5

8 4

9

6

R69101

2

Q6910

1

4

5

5A

R69121

2

D6912

A

K

C6905 1

2

C69061

2

C6991 1

2

C69901

2C69921

2

C6999 1

2

C69981

2

C69081

2

C6907 1

2

C69951

2

C6912 1

2 R69111 2

051-9277

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7

6 7

6 7

6 7

6 53

6

7

7

OUT

OUT

IN

BI

OUT

AMONBMONACOK

LGATE

PHASE

BOOT

SGATEAGATECSIPCSIN

DCIN

VNEGCSOPCSON

THRM_PAD

PGND

VDDPVDD

BGATE

UGATEICOMPVCOMP

ACIN

SDAVFRQCELL

VHST

SCLSMB_RST_N

IN

SG

D

IN

G

D

S

G

D

S

SW

BOOSTVIN

BIASSHDN*

GND

NCFB

PADTHRM

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<Ra>

FROM ADAPTER

(AGND)

Reverse-Current Protection

(CHGR_AGATE)

DIVIDER SETS ACIN THRESHOLD AT 12.18V

through body diodes:

Need to stuff R7092 if either PP5v5_DCIN:Yes or PP5v5_VDDP are used

For Erp Lot6 spec

Q7055.

(CHGR_DCIN)

TO SYSTEM

5.5v "G3Hot" Supply

(Switcher limit)

* R7051 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE

(GND)

.

36V/V

(CHGR_CSO_P)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

20V/V

Input impedance of ~40K meets

(CHGR_BGATE)

(PPVBAT_G3H_CHGR_R)

Inrush Limiter

(OD)

<Rb>

(CHGR_SGATE)

This node is powered

DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)

f = 400 kHz

Vout = 5.50V200MA MAX OUTPUT

Float CELL for 1S

30mA max load

Vout = 1.25V * (1 + Ra / Rb)

TO/FROM BATTERY

* DCIN through Q7080.* PBUS through Q7085, Charger TOP FETs and

Max Current = 8A

sparkitecture requirements

ACIN pin threshold is 3.2V, +/- 50mV

10%

10%

10%

10%

10%

10%

10% 10%10%

10%

10%

10%

10% 10%

10% 10% 10%10%

10%10%

10%

10%

10%

10%

201

201

201

201

201201

201

201

201

201201

201

201

201

201

201

201

201

201

X7R

10V

10V

10V

10V

10V

10V10V

10V

X5R-X7R-CERM0201

0201

16V

470PF

16V


1%220

0.01UF

0.01UF

402

402

402402

402

402

402 402

402

402

402

402

50V

50V

0.047UF

0402X7R-CERM16V

16V

16V

6.3VX5R

0.1UF

1UF

X5R

402-1X5R

1UF

5%

4.7

1/16WMF-LF

SM


1UF

X5R

0.1UF25V

0.1UF25VX5R

0.22UF

CERM


1/20W

10

MF

5%

5%

10

MF1/20W

25V20%

CASE-D3L

33UF-0.06OHM

CRITICAL

25V20%

CASE-D3L

33UF-0.06OHM

POLY-TANT

CRITICAL

1206

8AMP-24V

1/20WMF

332K1%

62K5%1/20WMF

46

44

44

X5R

42 45

0.010.5%

1W

MF

0612-3

TQFN

ISL6259HRTZ

CRITICALOMIT_TABLE

MF

100K5%

1/20W

62

CRITICAL

SI7615DNPWRPK-1212-8

1%100

1/20WMF

BAT30CWFILM

CRITICAL

SOT-323

X5R25V

0.1UF1/20WMF

5%100K

MF1/20W1%470K

1UF25VX5R603-1

X5R603-1

25V

1UF

0

1/20WMF

5%

6 41 42 43

POWERPAK

CRITICAL

SI5419DU

CRITICAL

25VX5R603-1

1UF25V

0.1UF

X5R25V25V

X5R805

10UF

1/20W5% MF

MF5%0

1/20W

255K1%1/20WMF

MF1/20W

CASE-B

62UF

POLY11V20%

CRITICAL

62UF

CASE-BPOLY11V20%

CASE-B

CRITICAL

62UF20%11VPOLY

WPAKRJK03P0DPA

CRITICAL

CRITICAL

PIMC104T4R7MN-SM

0.5%

0612

0.020

1W

MF-LF

CRITICALMF-LF

5%

603

20

1/10W

603X5R

10UF

CRITICAL

20%

603

CRITICAL

X5R

10UF20%

1%

MF

1/20W

681K

MF

1%

1/20W

200K

0.22UF

CERMLT3470A

CRITICAL

MF-LF 5%

0

PP5V5_DCIN:YES

1/16W

PP5V5_VDDP

MF-LF1/16W5%

0

NO STUFF

0

5%1/16W

MF-LF

25V

0603X5R-CERM

4.7UF CRITICAL

10UH-30%-0.85A-460MOHM

2520

X5R-CERM0603-1

0.22UF

66.5K1%1/20WMF

23.7K1/20WMF

1%


PBus Supply & Battery Charger

CHGR_SGATE


P5V1_FB

PPDCIN_G3H_CHGR

=PPDCIN_S5_CHGR



DIDT=TRUE GATE_NODE=TRUE

CHGR_UGATE

DIDT=TRUE

P5V1_BOOST

VOLTAGE=5.5V

PP5V5_CHGR_VDDPMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUEDIDT=TRUE

P5V1_SWMIN_LINE_WIDTH=0.5 mm


CHGR_CSO_N

CHGR_DCIN


CHGR_VNEG_R


CHGR_VNEG

=PP3V42_G3H_CHGR

CHGR_CSO_R_P



CHGR_CSO_R_N

VOLTAGE=8.4VMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CHGR_REG

CHGR_BGATE



PPCHGR_DCIN_D_R CHGR_DCIN_D


PPDCIN_G3H_INRUSH

VOLTAGE=18.5V



CHGR_CSI_R_P

CHGR_BMON=CHGR_ACOK

CHGR_LGATE MIN_NECK_WIDTH=0.2 mm


GATE_NODE=TRUE

DIDT=TRUE

PPVBAT_G3H_CONNMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.15 mmVOLTAGE=8.4V

SMC_RESET_L

=PPBUS_G3H

CHGR_RST_L=SMBUS_CHGR_SCL=SMBUS_CHGR_SDA

CHGR_DCIN

PP5V1_CHGR_VDDP



PPCHGR_DCIN_D_R

VOLTAGE=18.5V

CHGR_SGATE_DIVMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.2 mm

CHGR_CSI_P



CHGR_AGATE

MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=5.1V

PP5V1_CHGR_VDDP

CHGR_CSI_N


MIN_LINE_WIDTH=0.5 mm DIDT=TRUE

CHGR_BOOT

DIDT=TRUE

SWITCH_NODE=TRUE

CHGR_PHASE

VOLTAGE=8.4VMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmCHGR_VCOMP


CHGR_AMON

PP5V1_CHGR_VDD

VOLTAGE=5.1V



CHGR_CSO_P


PPVBAT_G3H_CHGR_R


CHGR_VCOMP_R

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

CHGR_ICOMP

=PPDCIN_S5_CHGR_ISOL

GND_CHGR_AGND


VOLTAGE=0V

CHGR_ACIN

POLY-TANT

DFN

NP0-C0G-CERM

5%22PF

0201

PLACE_NEAR=Q7030.5:1.5mm

X7R-CERM0402

0.001UF

PLACE_NEAR=L7030.2:1.5mm

X7R-CERM0201

1000PF

X7R-CERM0201

1000PF

46

CHGR_VFRQCHGR_CELL

470PF

X5R-X7R-CERM

0.47UF10%

X5R10V

0402

SI5419DUPOWERPAK


CRITICAL

2.2




CHGR_CSI_R_N

402

4.7UH-17A

CHGR_AGATE_DIV

X5R

PP5V5_DCIN:NO

CRITICALMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.15 mmVOLTAGE=18.5V

50V

NO STUFF

NO STUFF

25VX5R-CERM

0603

4.7UF10%

PPDCIN_G3H_OR_PBUSVOLTAGE=18.5V


C70421

2

C70021

2

C70001

2

R70011 2

XW7000

1 2

C7001 1

2

C70211

2

C7022 1

2

C70201

2

C70251

2

R70221 2

R70211 2

C7030 1

2

C7031 1

2

F7040

1 2

R70861

2

R70811

2

C7011 1

2

C7026 1

2

R7050

21

43

C70371

2

C70451

2

U7000

3

14

1

9

16

15

25

627

28

17

18

2

5

21

22

23

11

10

2613

29

24

7

19

20

4

12

8

R70021

2

Q7055

5

4

12

3

R70131

2

D7005

1

2

3

C7085 1

2

R70801

2

R70851

2

C70351

2

C70361

2

R70001 2

Q7080

1

4

5

5A

Q7085

1

4

5

5A

C70141

2

C70131

2

C70121

2

C7017 1

2

R7051 1 2

R7052 1 2

R70151

2

R70161

2

C7040 1

2

C7043 1

2

C7041 1

2

Q70302

1

6

7

3 4 5

L70301 2

R70201

2

3

4

R70051 2

C70991

2

C70981

2

R70951

2

R70961

2

C7094 1

2U7090

2

3

1

5

8 4

9

6

R7090

1 2

R7091

1 2

R7092

1 2

C7090 1

2 L7095

1 2

C7005 1

2

R70101

2

R70111

2

C70951

2

C7015 1

2

C70161

2

C70501

2

C7084 1

2

051-9277

2.8.0

70 OF 109

53 OF 73

7

71

7

71

53

7

71

71

53

6 52

7

53

53

53

71

53

71

71

7

71

OUT

IN

IN

IN FB

EN

PVCCVCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

PGNDGND

SET0

SET1

VID0

VID1

IN

Apple Inc.


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6 3



(VCCSAS0_OCSET)

0 1 0.725V

VID1 VID0 Voltage

0 0 0.9V

1 0 0.8V

(ENDIAN SWAP)

(VCCSAS0_VO)

6A Max Output

f = 300 kHz

OCP = 8.5A

OCP = R7141 x 8.5uA / R7140

INTEL TABLE:

1 1 0.675V

1000PF

0402

0.022UF

X5R-X7R-CERM


1/20W

0201-10201-1COG-CERM

5%10PF

COG-CERM

5%10PF


=PPVIN_S0_VCCSAS0

MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.1 mm VCCSAS0_FSEL

=PVCCSA_EN

VCCSAS0_DRVL

GATE_NODE=TRUE


DIDT=TRUE

VOLTAGE=5V

PP5V_S0_VCCSAS0_VCCMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm


VCCSAS0_VBST

DIDT=TRUE

VCCSAS0_DRVH

GATE_NODE=TRUEMIN_NECK_WIDTH=0.2 mm

DIDT=TRUE


PVCCSA_PGOOD


CPU_VCCSASENSE

MIN_LINE_WIDTH=0.6 mmPPVCCSA_S0_REG_R

VOLTAGE=1.05V

=PPVCCSA_S0_REG

=PP5V_S0_VCCSA


VCCSAS0_BOOT_RC

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mmSWITCH_NODE=TRUE

VCCSAS0_LL

DIDT=TRUE


VCCSAS0_CS_P

VCCSAS0_CS_N

VCCSAS0_SET0



VCCSAS0_SET1

VCCSAS0_OCSET


VCCSAS0_SET1_R



VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mmVCCSAS0_AGND


VCCSAS0_VO


VCCSAS0_SREFMIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mmVCCSAS0_RTN

CPU_VCCSASENSE_RMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.1 mm

System Agent Supply


FDV0630H-SM

1.0UH-7.7A

CRITICALSIZ710DT

MF

3.24K1/20W1% 1%

3.24K

MF1/20W

2.2UF20%

0402X5R-CERM

MF1%

VCCSAS0_RTN_R

1/20W

1.62K

1.62K

MF1%

1/20W

56K

MF1/20W1%

1%MF1/20W

511K

1%49.9K

MF

1%MF1/20W

20K

12

CRITICAL

ISL95870AHUTQFN

MF

05%

1/20W

62UF20%

CASE-B

CRITICAL

POLY11V

270UF

CASE-B2-SMTANT2V20%

SM

PLACE_NEAR=C1763.2:3mm

0805

10UF

12

12

X5R-CERM

10UF

CRITICAL

0805

0.0011%

MF-10612

1W

CRITICAL

5%25V

1%1K

MF1/20W

MF1/20W

1%1K

NP0-C0G

5%25V

0.22UF

CERM1/16W

5%0

MF-LF

0402-1X5R-CERM

10UF20%

CRITICAL

2.2

MF-LF1/16W

5%

SM


62

62

16V

16V 16V

50V 50V

402

402

402

402

CPU_VCCSA_VID<0>


CPU_VCCSA_VID<1>


402NP0-C0G

1000PF


CRITICAL

X5R-CERM

CRITICAL

0.1UF

16VX7R-CERM

0402

POWERPAK-6X3.7

10V

10V

10V

201 201

201

201

201

201

201

201

201

201

201

10%

10%

10%

10% 10%

R71031

2

C71021

2

XW7100

1 2

R71011

2

C71011

2

R71301

2

C71301

2

C7140

12

R71411

2

R71421

2

C7122 1

2

R7140

1 2

3 4

C7120 1

2

C7119 1

2

XW7101

1

2

C71411

2

C7123 1

2

U7100

1815

10

13

3

1

11

2

14

16

20

4

8

9

7

17

19

6

5

12

R71471

2

R71481

2

R71491

2

R71501 2

R71511 2

R71531 2

R71521

2

R71541

2

Q7100

1

6

4 5

2 3 7

8

L7100

1 2

C71051

2

C71061

2

C7103 1

2

C7121 1

2

051-9277

2.8.0

71 OF 109

54 OF 73

7

7

7

72 45

72 45

6

6

6

6

OUT

IN IN

EN

EN2EN1

DRVL2

SKIPSEL1SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

OUT

IN

Apple Inc.


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6 3



F=400KHZ

F=400KHZ

Vout = 3.3V

6.5A MAX OUTPUT7.2A MAX OUTPUT

Vout = 5.0V

353S2678

152S1424

P5VP3V3_VREF2

P5VS3_PGOOD

10%10%

0201-1X7R-CERM

16V

270PF


NO STUFF

P3V3S5_PGOOD


MF

10% 10%

10%

10%

10% 10%

10%

10%

10%10%

10%

10% 10%

10%

201

201201

201

201201

201

201

201

201

201

201201

201

201

201 201

201

201

201

201

201

X7R X7R

10V 10V

10V

10V

10V 10V

10V

402

402402

402

402

402 402

402

402

16V16V

16V

16V16V

16V

16V 16V

16V


P5VS3_CSN1


DIDT=TRUEMIN_NECK_WIDTH=0.2 mm

P5VS3_VBST_R

P5VS3_EN_R

=P3V3S5_EN=P5VS3_EN

P5VS3_VFB1-R


P5VP3V3_VREG3


P3V3S5_VFB2_RMIN_LINE_WIDTH=0.2 mm

=PP3V3_S5_REG=P5V3V3_REG_EN

P5VS3_COMP1

P3V3S5_COMP2_R

P5VP3V3_VREF2

P5VS3_COMP1_R

P5VS3_FUNC P3V3S5_RF

P3V3S5_COMP2MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.1 mm

DIDT=TRUE GATE_NODE=TRUEP5VS3_DRVH


GATE_NODE=TRUEDIDT=TRUEP5VS3_DRVL


P5VS3_CSP1

=PP5V_S3_REG

P5VS3_LLDIDT=TRUE SWITCH_NODE=TRUE



P5VS3_VFB1

P5VS3_CSP1_RMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.1 mm

P3V3S5_EN_R

=PP5V_S3_REG

P5VP3V3_SKIPSEL

MIN_LINE_WIDTH=0.6 mmP3V3S5_VBST_R

MIN_NECK_WIDTH=0.2 mmDIDT=TRUE

P3V3S5_VBSTDIDT=TRUE


DIDT=TRUE MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm

P3V3S5_DRVLGATE_NODE=TRUE

P3V3S5_DRVH

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUE DIDT=TRUE

P5VP3V3_VREF2


P5VP3V3_VREG3MIN_LINE_WIDTH=0.2 mm

=PPVIN_S5_P5VP3V3

P5VS3_VBSTMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm

DIDT=TRUE


=PP5V_S5_LDO

MIN_NECK_WIDTH=0.2 mmVOLTAGE=0V

GND_P5VP3V3_SGNDMIN_LINE_WIDTH=0.6 mm


P3V3S5_CSN2

P3V3S5_CSP2_R


P3V3S5_CSP2


P3V3S5_VFB2

SWITCH_NODE=TRUEP3V3S5_LL

MIN_LINE_WIDTH=0.6 mmDIDT=TRUEMIN_NECK_WIDTH=0.2 mm

5V / 3.3V Power Supply


MF1/20W1%6.65K

X5R-CERM

20%

2.2UF

SKIP_5V3V3:INAUDIBLE

05%1/20WMF

SKIP_5V3V3:AUDIBLE

MF1/20W5%0

POWERPAK-6X3.7SIZ710DT

CRITICAL

CASE-B

11VPOLY

CRITICAL

20%62UF

11V

CASE-B

62UF20%

CRITICAL

POLY

CRITICAL

62UF

POLYCASE-B

20%11V

CASE-B

CRITICAL

POLY11V

62UF20%

603

20%

10UF

PCMC063T-SM

1.5UH-20%-18A-15MOHM

CRITICAL

10UF20%

603

10UF20%

603

SIZ710DTPOWERPAK-6X3.7

CRITICAL

CASE-B2-SM

6.3V20%

POLY-TANT

CRITICAL

150UF

62UF20%6.3V

CASE-B2SELEC

CRITICAL

05%

MF-LF1/16W

4700PF

62

62

5%


0

MF1/20W

05%1/20WMF


05%

1/16WMF-LF

QFN

CRITICAL

TPS51980

0

1/20W

MF

5%

5%

0

MF

1/20W

62 62

4700PF

1/20W

7.5K1%

MF

220PF

X7R-CERM25V

NO STUFF

1%

MF

1/20W

20K

150UF-0.018OHM-1.8A

TANT

20%

CRITICAL

6.3V

CASE-B2-SM

PLACE_NEAR=L7220.1:3mm

SM

SM

PLACE_NEAR=L7260.2:3mm20K

MF

1%

NO STUFF

1/20W

1%

1/20W

7.5K

SM


SM


1%4.22K

1/20WMF

1/20WMF

1.33K

1%

SM


1/20W1%

1.54K

MF


SM

10K

MF1/20W1%

1%41.2K

MF1/20W

1%10K

1/20WMF

1%1/20WMF

23.2K

0.22UF

CERM

SM


62

249K

1/20W

1%

MF

1UF

20%

POLY-TANT

150UF

6.3V

CRITICAL

CASE-B2-SM

25V 25V

1UF

PCMC063T-SM

2.5UH-14A

CRITICAL

1UF

X5R

X5R

X5R

X5R

X5R X5R

X5R

X5R

0.1UF 0.1UF

X7R-CERM0402

0.1UF

X7R-CERM0402

0.1UFPLACE_NEAR=L7260.2:1.5mm



PLACE_NEAR=L7220.1.2:1.5mm

X7R-CERM0201

1000PF

X7R-CERM0201

1000PF

X7R-CERM0201

1000PF

X7R-CERM0201

1000PF

C7200 1

2

L7260

1 2

C72411

2

C7264 1

2

C72241

2

C7252 1

2

C72811

2

R72061

2

XW7261

1

2

C7201 1

2

R72601

2

R72611

2

R72201

2

R72211

2

XW7200

1 2

R72461 2

XW7260

1

2

C7218

1 2

R72471 2

R72561

2

XW7220

1

2

XW7221

1

2

R72361

2

R72371

2

XW7262

1

2

XW7222

1

2

C72921

2

R72391

2

C7239 1

2

R72381

2

C7238 1

2

R72481 2

R72491

2

C72721

2

C72831

2

C72701

2

C72711

2

U7201

10 15

8 17

7 18

1 24

30 27

12

4 21

28

11

14

5 20

3

6

19

32 25

33

2

31 26

9 16

23

13

22

29

R72451

2

R72511

2

R72521

2

C7236 1

2

C7288

1 2

R72642

1

C72541

2

C72531

2

Q7260

1

6

4 5

2 3 7

8

C72901

2

C7250 1

2

L72201 2

C72051

2

C7242 1

2

C7240 1

2

C7284 1

2

C7282 1

2

Q7220

1

6

45

237

8

R72001

2

R72011

2

C7203 1

2

R72161

2C7237 1

2

55 OF 73

72 OF 109

2.8.0

051-9277

55

7

55 55

55 7

55 7

55

55

7

7

D

G S

IN

IN

V5IN

REFIN

S5

VREF

S3

MODETRIP

SW

DRVLPGOOD

VDDQSNSVTT

VTTSNS

VTTREF

DRVHVBST

VLDOIN

THRMVTTGNDPGND PADGND

OUT

IN

OUT

OUT

G

D

S

G

D

S


Apple Inc.


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REVISION

BRANCH

6 3



C7360, C7361 close to memory

If LVDDR3_HW:NO is turned ON, switch R2821 & R7971 back to the original value for 1.5V DDR unless 1V5R1V35_SW is turned ON

(DDRREG_DRVL)

(DDRREG_VDDQSNS)

10mA max load

(DDRREG_DRVH)

(DDRREG_LL)

VTT Enable

VDDQ/VTTREF Enable

Vout = 1.5V

f = 400 kHz

14.1A max output

(Q7335 limit)

10%

10%

10%

10%

10%

10%

10%

201201

201

201

201

10V

10V

10V

16V

16V

0.1UF

0402X7R-CERM


0.1UF

402

402

402

402

X5R

X5R

X5R

X5R

X5R

X5R

X5R

X5R

SSM3K15AMFVAPECRITICAL

VESM

1V5R1V35_SW

17


10UF

603

20%

CRITICAL

6.3V

MF1/20W1%84.5K


PLACE_NEAR=U7300.12:1mm603

20%10UF

25V

603-1

1UF

25V

6.3V

603

10UF20%

SM

62

CRITICAL

QFN

TPS51916

8

SM


SM


CERM

0.22UF


603

CRITICAL

6.3V20%

10UF

8 26


10UF

603

6.3V20%

CRITICAL

200K


1/20W

20K


1%

MF

LVDDR3_HW:NO

1%

100K

MF

1/20W


0.01UF

CERM



20%

603

10UF

1/16W05%

MF-LF

0.88UH-20%-19A-2.3MOHM

CRITICAL

1%MF1206

CRITICAL

46 72

72

CRITICAL

PQFN3.3X3.3

PQFN3.3X3.3

CRITICAL

POLY11V20%62UF

CASE-B

62UF

11VPOLY

CRITICAL

20%

CASE-B

CRITICAL

POLY11V20%62UF

CASE-B

1V5R1V35_SWPLACE_NEAR=U7300.8:5mm

150K1%

MF

1/20W

RES,MF,60.4KOHM,1,1/20W,0201 LVDDR3_HW:YESR7316118S0460 1

1.5V DDR3 Supply



DDRREG_FB


=PPVIN_S3_DDRREG

DDRREG_P1V35_L

MEM_VDD_SEL_1V5_L

=DDRVTT_EN

=PPVIN_S0_DDRREG_LDO



SWITCH_NODE=TRUE DIDT=TRUE

DDRREG_LL

DDRREG_DRVH

GATE_NODE=TRUE DIDT=TRUE





DIDT=TRUEGATE_NODE=TRUE

DDRREG_DRVL

=PPVTT_S0_DDR_LDO



=PPVTT_S3_DDR_BUF

DDRREG_PGOOD

DDRREG_MODE



DDRREG_VBST_RC

DIDT=TRUE

VOLTAGE=1.5V



ISNS_1V5_S3_N



DDRREG_VTTSNS

=PP5V_S3_DDRREG

DDRREG_VDDQSNS



ISNS_1V5_S3_P

=PPDDR_S3_REG

DIDT=TRUE

DDRREG_VBST



=DDRREG_EN

DDRREG_TRIP



DDRREG_1V8_VREF

VOLTAGE=0V



GND_DDRREG_SGND

1/20W

1%

MF

CRITICAL46

IRFHM830DPBF

0.5W0.001

IRFHM831PBF


MPCG1040LR88-SM

PPDDR_S3_REG_R

CRITICAL

POLY-TANT2.0V20%330UF

CASE-B2-SM1

CRITICAL

POLY-TANT2.0V20%

330UF

CASE-B2-SM1

50VX7R-CERM0402

0.001UF

50VX7R-CERM

0402

0.001UF

C7300 1

2

C73321

2

C7325

1 2

C73331

2

C73451

2

C7346 1

2

XW7301

1

2

U730014

11

7

19

10

20

8

17

16

13

21

18

12 15

9

2

6

3

4

5

1

XW7360

1 2

XW7300

1

2 C7350 1

2

C7360 1

2

C7315 1

2

C73611

2

R73171

2

R73151

2

R73161

2

C73161

2

C7301 1

2

R7325

1 2

L7330

1 2

R7350

1 23 4

Q7330

5

4

1 2 3

Q7335

5

4

1 2 3

C73301

2

C73311

2

C73341

2

R73141

2

Q73193

1 2

C73621

2R73181

2

C73401

2

C7341 1

2

051-9277

2.8.0

73 OF 109

56 OF 73

31

7

7

7

7 31

7

7

IN

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

OUT

NC

OUT

NCNCNCNC

PAD

IMAXA

SR

IMAXB

ALERT*

THERMATHERMB

VDIO

POKB

CLK

EN

POKA

CSPA3

DRVPWMA

GNDSB

GNDSA

THRM

CSPB1

DHBLXB

BSTB

DLA2

DLB

CSNBFBB

LXA1DHA1BSTA1

TON

DLA1CSPA1

CSPAAVE

FBACSNA

BSTA2CSPA2

DHA2LXA2

VCC

VDDA

VDDB

VR_HOT*

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10%

10%

10%

10%

10%

10%

10%

10%

10%

201

201

201 201

201201201

201

201

201201

201

201

201

201

201

201

201

10V

10V

10V

10V

10V

10V10V

0.01UF

0.01UF

402

402

402

402402402

402

50V

50V

1000PF

0201X7R-CERM

16V

1000PF

0201X7R-CERM16V

1000PF

0201X7R-CERM16V

1000PF

0201X7R-CERM16V

0201

0201

NO STUFF

X5R-CERM

NO STUFF

X5R-CERM

CPUIMVP_AXG_PGOOD

NO STUFF

47PF5%25VNP0-C0G-CERM0201

100PF

8.25K

6.34K

100PF

5%25V

NP0-CERM0201

NO STUFF

0201NP0-CERM

25V5%

NO STUFF

CPU IMVP7 & AXG VCore Regulator

NP0-CERM25V5%100PF

02010201

5%

NP0-CERM

NO STUFFNO STUFF

NP0-CERM25V5%100PF

02010201

100PF5%25VNP0-CERM

NO STUFF

CPU_AXG_SENSE_R

MIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm CPUIMVP_FBA

CPUIMVP_PHASE1


=PPVIN_S0_CPUIMVP

CPUIMVP_ISUM

=PP5V_S0_CPUIMVP

CPUIMVP_ISUM_R


CPUIMVP_ISUM_N

CPUIMVP_ISUMG_P


CPU_VCCSENSE_RMIN_LINE_WIDTH=0.2 mm

=PPVCCIO_S0_CPUIMVP

CPUIMVP_SLEW

CPUIMVP_ISNS1_P

CPU_VCCSENSE_P

CPU_VIDSCLK

CPUIMVP_UGATE1GCPUIMVP_PHASE1G

CPUIMVP_BOOT1G

CPUIMVP_LGATE1G

CPUIMVP_FBB

CPUIMVP_UGATE1_RCPUIMVP_BOOT1

CPUIMVP_TON

CPUIMVP_LGATE1

CPUIMVP_FBA

CPU_AXG_SENSE_N

CPU_VCCSENSE_N

CPUIMVP_PGOOD

CPUIMVP_VR_ON

CPU_AXG_SENSE_PCPUIMVP_FBB_RMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mmCPUIMVP_FBA_RMIN_NECK_WIDTH=0.2 mm


CPUIMVP_ISUM_P

CPUIMVP_ISUMG_N

CPUIMVP_IMAXA

GND_CPUIMVP_SGND

VOLTAGE=0V

CPUIMVP_NTC


CPU_VIDSOUT


CPUIMVP_FBBMIN_LINE_WIDTH=0.2 mm

CPUIMVP_IMAXB


CPUIMVP_NTCG

CPU_VIDALERT_L

CPU_PROCHOT_L

VOLTAGE=5V


P5V_S0_CPUIMVP_VDD



TQFN

CRITICAL

MAX15120

MF1/20W1%

2.2MF-LF5% 1/16W

1%1/20WMF

1/20W

10K1%

MF1/20W

137K

MF

1%

1/20W1%

MF

215K


CRITICAL

0603

100KOHM-1%-100MW


CRITICAL

0603

100KOHM-1%-100MW

2200PF

X7R-CERM0201

0.0022UF

CERM

5.76K1%

MF1/20W

5.76K1%1/20WMF

1%

MF-LF

90.9K

1/16W

137K1%

MF1/20W

MF1/20W

215K1%

58


1/20WMF

1%130


MF

1%54.9

1/20W

72 58

72 58 45

1/20WMF

10

5%

66 12

66 12

5%

MF

10

1/20W

66 12

66 12

10

1/20W5%

MF

1/20WMF

5%

10

1%200K

1/20W

NO STUFF

MF

X5R-CERM

2.2UF20%


SM

72 58

58

58

58

58

72 58

58

58

58

58

66 42 41 10

62

62

25

NO STUFF

0402X5R-CERM

0.039UF

5%

1

MF1/20W


MF

5%1/20W

300

66 12

66 12

66 12

X5R-CERM

2.2UF20%


2.2UF

X5R-CERM

20%

1/16WMF-LF

5%

10

CPUIMVP_UGATE1

100PF

25V

72

470PF

NP0-C0G-CERM

5%

0402

NO STUFF

R74011 2

C7401 1

2

C74021

2

R74061 2

R74101 2

C7408

1 2

XW7400

12

C74031

2

R74641

2

R74401 2

R74411 2

C74401

2

C74411

2

C74121

2

R74131 2

C7422 1

2

R74231 2

R74791

2

R74801

2

R74601

2

R74611

2

R74021 2

R74681

2

R74661

2

C74071

2

C74041

2

R7469

1

2

R7467

1

2

R74621

2

R74631

2

R74651

2

R74121 2

R74031 2

R74221 2

U7400

17

20

28

11

18

37

9

36

38

39

35

8

22

26

13

23

25

14

31

1

4

6

3 7

2930

21

27

12

1910

32

3334

41

2

40

24

15

16

5

C74181

2

C74191

2

C74141

2

C74151

2

C7462

1 2

C7452

1 2

C74441

2

C74091 2

C74421

2

C74431

2

051-9277

2.8.0

74 OF 109

57 OF 73

58 7

7

7

57

57

57

57

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

S

G

D

D

GS

VSW

PGND

TGR

TG

BG

VIN

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CPU=IV Bridge ULV, AXG=GT2

376S1005

376S0984

376S0985

AXG PHASE

THESE TWO CAPS ARE FOR EMC

PHASE 1

152S1323

152S1323

THESE TWO CAPS ARE FOR EMC

10%

10% 10%

10%10%

10%

10%

10%

10%

10%

10%

201

201 201

201

10V

10V

10V

402

402

402

402

402

402402

402

50V 50V

50V50V

50V

16V

16V

16V

1000PF

0201X7R-CERM

NO STUFF

0.001UF

0402X7R-CERM

0.001UF

0402X7R-CERM

0.001UF

0402X7R-CERM

0.001UF

0402X7R-CERM

0.001UF

CASE-B

62UF

CRITICAL

POLY

20%11V

POLYCASE-B

CRITICAL

PIMB104T-SM



CPUIMVP_VSWG

SWITCH_NODE=TRUE

CPUIMVP_PHASE1GDIDT=TRUE


GATE_NODE=TRUEDIDT=TRUE

CPUIMVP_UGATE1G_R



MIN_LINE_WIDTH=0.5 MMGATE_NODE=TRUEDIDT=TRUE

CPUIMVP_LGATE1G


CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N

CPUIMVP_ISUMG_P

=PPVCORE_S0_CPU_REG

CPUIMVP_UGATE1G




DIDT=TRUE

CPUIMVP_BOOT1G_RCMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MM

DIDT=TRUEMIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1GMIN_LINE_WIDTH=0.5 MM

DIDT=TRUEMIN_NECK_WIDTH=0.2 MM

CPUIMVP_BOOT1MIN_LINE_WIDTH=0.5 MM

CPUIMVP_ISNS1_N

CPUIMVP_ISUM_P

CPUIMVP_ISUMG_N

CPUIMVP_ISNS1_P



CPUIMVP_UGATE1MIN_LINE_WIDTH=0.5 MM


DIDT=TRUE

SWITCH_NODE=TRUE

CPUIMVP_PHASE1MIN_LINE_WIDTH=0.5 MM


CPUIMVP_LGATE1


VOLTAGE=1.25V


PPVCORE_S0_CPU_PH1


=PPVIN_S0_CPUIMVP

CPUIMVP_BOOT1_RC

DIDT=TRUE


CPUIMVP_ISUM_N

=PPVCORE_S0_AXG_REG

DIDT=TRUE

VOLTAGE=1.25V


CPUIMVP_AXG_SNUB

PPVCORE_S0_AXG_R


VOLTAGE=1.05V

=PPVIN_S0_CPUAXG

CPU IMVP7 & AXG VCore Output


20%11V

CRITICAL

POLYCASE-B

62UF

CSD58872Q5DSON5X6

CRITICAL

105%

1/16W

MF-LF

CRITICAL

DIRECTFET-MXIRF6894MTRPBF

10UF20%

X5R-CERM0603

CRITICAL

25V20%

CRITICAL

10UF

25VX5R-CERM0603

0603

CRITICAL

25V20%10UF

X5R-CERM

CRITICAL

11V20%62UF

POLYCASE-B

20%62UF

CRITICAL

POLY11V

CASE-B

CRITICAL

IRF6811STRPBFSQ

CRITICAL

PIMB104T-SM

0.36UH-20%-30A-1.2MOHM

20%

CRITICAL

62UF

11VPOLYCASE-B

20%11VPOLY

CRITICAL

62UF

CASE-BPOLY11V20%62UF

CASE-B

CRITICAL

CRITICAL

POLY11V20%62UF

CASE-B

CRITICAL

POLY

20%62UF

11V

CASE-B

62UF20%11V

CRITICAL

2200PF

0201X7R-CERM

NO STUFF

1/20W1%

MF

46.4

46.41%

MF1/20W

1%1WMF0612

0.00075

CRITICAL

1%

0612MF1W

0.00075

CRITICAL

5%

1/16WMF-LF

4.7

72 57 45

72 57

72 57

72 57

72 57

MF

101%1/20W

MF

101%1/20W

57

57

57

57

0.22UF

CERM

CERM

NOSTUFF

2.2

NOSTUFF

1/10W5%

603MF-LF

X5R

1UF

0.22UF

CERMMF-LF

5%0

1/16W

57

57

57

57

1UF

X5R

10UF20%25V

0603X5R-CERM

CRITICAL

0.36UH-20%-30A-1.2MOHML7510

1 2

C75151

2

C75171

2

C75181

2

C75191

2

R75111

2

C75111

2

C75591

2

C75581

2

C75571

2

R75521

2

C75521

2

C7551 1

2

R75141

2

R75541

2

R7555

1 2

R7510

1 2

3 4

R7550

1 2

3 4

R75531

2

R75131

2

C75711

2

C75741

2

C75131

2

C75141

2

C75401

2

C75411

2

C75601

2

C75531

2

C75541

2

L7550

1 2

Q7510

1

2

5

64

3

C75101

2

C75201

2

C75161

2

C75551

2

C75561

2

Q7520

1 2 6 7

5

3 4

R75511

2

Q7550

5

9

3

4

1

678

C75611

2

051-9277

2.8.0

75 OF 109

58 OF 73

72 45 72 45

7

72 45

57 7

7

7

OUT

IN BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC PVCC

GND PGND

EN

FB VSW

PGND

TGR

TG

BG

VIN

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(CPUVCCIOS0_VO)

(CPUVCCIOS0_OCSET)

OCP = 25.6A

<Ra>

CPU VCCIO (1.05V S0) Regulator

21A Max Output

Vout = 1.05V

f = 300 kHz

OCP = R7641 x 8.5uA / R7640

Vout = 0.5V * (1 + Ra / Rb)

<Rb>

10%

10%

10%

201

201 201

201

201

201

201

201

10V

0.047UF

0402X7R-CERM16V

402

402

402

402

402

16V

16V

NP0-C0G-CERM02010201

47PF5%

25V

47PF5%25VNP0-C0G-CERM

10UF

VOLTAGE=0V

=PPVIN_S0_CPUVCCIOS0


CPUVCCIOS0_VO

CPUVCCIOS0_CS_N

CPUVCCIOS0_AGNDMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.15 mm

CPUVCCIOS0_OCSET


PPCPUVCCIO_S0_REG_R

VOLTAGE=1.05V


=PP5V_S0_CPUVCCIOS0

CPUVCCIOS0_PGOOD

CPU_VCCIOSENSE_P

CPUVCCIOS0_FSEL

=CPUVCCIOS0_EN


VOLTAGE=5V

PP5V_S0_CPUVCCIOS0_VCC

=PPCPUVCCIO_S0_REG

CPUVCCIOS0_DRVH



CPUVCCIOS0_RTNMIN_LINE_WIDTH=0.2 mmMIN_NECK_WIDTH=0.2 mm

CPU_VCCIOSENSE_N

CPUVCCIOS0_FB


CPUVCCIOS0_SREF

CPUVCCIOS0_CS_P


CPUVCCIOS0_VBST

DIDT=TRUE

CPUVCCIOS0_BOOT_RC

DIDT=TRUEMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.5 mm

DIDT=TRUE

CPUVCCIOS0_DRVL

GATE_NODE=TRUE


CPUVCCIOS0_R


CPUVCCIOS0_LLMIN_LINE_WIDTH=0.6 mm




PPCPUVCCIO_S0_REG

VOLTAGE=1.05V

CPU VCCIO (1.05V) Power Supply


1/20WMF

3.01K1%

1%2.74K

MF1/20W

1%1/20WMF

2.74K

CRITICAL

CSD58872Q5DSON5X6

CRITICAL

CASE-BPOLY11V20%

62UF

CASE-B

CRITICAL

POLY11V20%

62UF

CASE-B

62UF20%11VPOLY

CRITICAL

CRITICAL

0.0011%1WMF0612

PIMB104T-SM

0.68UH-22A-2.7MOHM

CRITICAL

MF1/20W

5%2.2

270UF

2VTANT

CASE-B2-SM

CRITICAL

20%

CASE-B2-SM

CRITICAL

TANT2V20%270UF

0

1/16WMF-LF

5%

MF-LF

1/10W

603

5%0

25V


NP0-C0G

5%

25VNP0-C0G

5%

PLACE_NEAR=L7630.2:1.5mm

25VNP0-C0G

5%

1/20WMF

1%3.01K

MF1/20W1%3.01K

1UF

20%

603

CRITICAL

CRITICAL

ISL95870UTQFN

SM


0

MF1/20W5%2.2UF

603

62

62

3.01K1%

MF1/20W

X5R

X5R

X5R

1000PF

1000PF

1000PF

C76031

2

R76451

2

R76051

2

R76041

2

R76441

2

C7602 1

2

R76031

2

XW7600

1 2

U7600

123

6

5

1

15

7

16

9

10

14

2

4

11

13

8

C76011

2 C76301

2

R76421

2

R76411

2C7640

12

C7623 1

2

C7622 1

2R76301

2

R76311 2

C76481

2

C7649 1

2

R76011

2

L76301 2

R7640

1234

C76191

2

C7620 1

2

C7621 1

2

Q7630

5

9

3

4

1

678

C76051

2

C7604 1

2

051-9277

2.8.0

76 OF 109

59 OF 73

7

72 45

7

66 12

7

66 12

72 45

IN

BIAS

NC

OUT

THRM

EN

PADGND

NC

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

NCNCNC

LXVDD

VIN

THRM_PAD

PGND

SGND

EN

PG

SYNCH

LX

VFB

NC

IN

OUT

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

IN

IN

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Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.

1.05V SUS LDOPull-ups (3) must be 51 ohms to support XDP (not required in production).70mA is required to support pull-ups. Alternative is strong voltage

Max Current = 0.020A

Vout = 1.05V

Freq = 1 MHz

Max Current = 0.02A Max Current = 0.35A

Vout = 1.05V

<Ra>

152S1302

1.8V S0 Regulator

dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

1.05V S0 LDO

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

Vout = 1.794V

Max Current = 1.8A

Vout = 1.5V

1.5V S0 LDO

10% 10% 10%10% 10% 10%

10%10%10%

402 402 402402 402 402

40240216V

201

201

5%25V

=PP3V3_S0_P1V8S0

P1V8S0_PGOOD

=PP3V3_SUS_P1V05SUSLDO

=PP1V8_S0_REG=P1V8S0_EN P1V8S0_SW


=1V05_S0_LDO_EN

=PP3V3_S0_P1V05S0LDO

=PP1V8_S0_P1V05S0LDO

=PP1V05_S0_LDO=PP3V3_S0_P1V5S0

=PP1V8_S0_P1V5S0

=P1V5S0_EN

=PP1V5_S0_REG

P1V8S0_FB

=PP1V05_SUS_LDO


Misc Power Supplies

62

7

6.3VCERM

1UF


1UF

CERM6.3V


SONTPS72015

CRITICAL

2.2UF6.3V

1/20WMF

90.9K1%

62

62 QFN

ISL8014A

CRITICAL

22UF6.3V

CRITICAL

20%

X5R-CERM-1603

CRITICAL

1.0UH-20%-4.5A-24MOHMPIMB042T-SM

1/20WMF

113K1%

22UF6.3V20%

CRITICAL

X5R-CERM-1603

22UF

CRITICAL

20%6.3VX5R-CERM-1603


6.3VCERM

1UF


1UF

CERM6.3V

SONTPS720105

CRITICAL

2.2UF6.3V

XDP_PCH

2.2UF6.3V

SON

CRITICAL

TPS720105

XDP_PCH

1UF

CERM6.3V

XDP_PCH

0201NP0-C0G-CERM

47PF

X5RX5R

X5RX7R-CERM

0201

1000PF

C7740 1

2

U7740

4

3

5

6 1

7C77411

2

C77811

2

U7780

4

3

5

6 1

7C7780 1

2

C7782 1

2

C77211

2

C7722 1

2

R77201

2

L7720

1 2

C7720 1

2

U7720

5 14

15

6

16

13

7

11

129

10

4

17

3

8

1 2C7724 1

2

R77211

2

C77721

2

U7770

4

3

5

6 1

7C7771 1

2

C7770 1

2

C77231

2

051-9277

2.8.0

77 OF 109

60 OF 73

2

22

7

7

7

62

7

7

7

7 7

7

IN

IN

IN

D

SG

D

SG

IN

THRMGND

G

PG

SHDN*

D

VCC

S

ON

PAD

OUT

IN

IN

D

SG

D

SG

D

SG

DSG

DSG

DSG

DSG

G

S

D

DSG

IN

G

S D

D

G S

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6 3



3.3V S3 FET

1.5V S3/S0 FET

PQFN2X2

3.3V S4 FET376S0945

LOADING

RDS(ON)

0.7? A (EDP)

26 mOhm @1.8V

SiA427

3.3V_SUS FET

3.2 A (EDP)

SiA427

N-TYPE

1.5V S3/S0 FET

APN 376S0928

1.608 A (EDP)

31 mOhm @1.8V

SiA427

P-TYPE 8V/5V

MOSFET

CHANNEL

5 A (EDP)

9.4 mOhm @4.5VRDS(ON)

LOADING

CHANNEL

29 mOhm @4.5V

P-TYPE 12V/8V

100? mA (EDP)

26 mOhm @1.8V

SiA427

SiA427

LOADING

CHANNEL

RDS(ON)

MOSFET

RDS(ON)

3.3V S0 FET

RDS(ON)

P-TYPE 8V/5VCHANNEL

1.678 A (EDP)LOADING

CHANNEL

LOADING

MOSFET TPCP8102

P-TYPE

100? mA (EDP)

P-TYPE 8V/5V

LOADING

3.3V S3 FET

5.0V S0 FET

MOSFET

5V_SUS FET

18 MOHM @4.5V

LOADING

RDS(ON)

CHANNEL

MOSFET

5V SUS FET

26 mOhm @1.8V

3.3V SUS FET

MOSFET

3.3V S0 FET

5.0V S0 FET

RDS(ON)

P-TYPE 8V/5V

MOSFET

CHANNEL

3.3V S4 FET

26

0.01UF

X5R

0.033UF16VX5R402

5%1/20W

47K

MF

X5R

0.01UF

0.033UF

402

16VX5R

62

38 62

SSM6N37FEAPESOT563

SSM6N37FEAPESOT563

62

5%

1/20W

MF

10K

0.033UF

402

16V

X5R

402

0.01UF

CERM

16V

TDFNCRITICAL

SLG5AP020

20%0.1UF

CERM402

1/16W

402

0

5%

MF-LF

603

4.7UF

X5R-CERM6.3V

NO STUFF

8

61 62

61 62

SOT563SSM6N37FEAPE

402

16VX5R

0.033UF

16V

402X5R

0.033UF

0.01UF

CERM16V

402

X5R

0.01UF

SOT563SSM6N37FEAPE

SOT563

SSM6N37FEAPE

MF5%1/20W100K

1/20W5%MF

12K

3.3K

MF1/20W5%

1/20WMF5%220K

SIA427DJSC70-6L

CRITICAL

SIA427DJ

CRITICAL

SC70-6L

SC70-6L

SIA427DJ

CRITICAL

5%

91K

1/20WMF

10K

MF1/20W5%

220K

MF

5%1/20W

100K5%1/20WMF

SC70-6LSIA413DJ

CRITICAL

CRITICAL

MF-LF1206

1/4W5%

0

CRITICAL

FDMC2514SDCPOWER33

CRITICAL

1/10W5%

603

0

MF-LF

402

5%

MF-LF1/16W

0

CRITICAL

CRITICAL

402

0

5%1/16WMF-LF

1W1%

0.001

0612MF-1

CRITICAL

NOSTUFF

5%

1/16W

0

MF-LF

402CRITICAL

SIA427DJ

SC70-6L

16V

CERM

0.01UF

402

0.033UF

402

16V

X5R

402

MF-LF

5%

1/16W

47K

MF-LF

402

1/16W

5%

220K

62

CRITICAL

DMP2018LFKDFN2563-6

402

5%

1/16W

0

MF-LF

SSM3K15AMFVAPEVESM

SYNC_MASTER=K21_MLB

Power FETsSYNC_DATE=07/28/2011

=P3V3S4_EN

P3V3S4_EN_L P3V3S3_S4

=PP3V3_S3_P3V3S3FET

P3V3S3_EN_L P3V3S3_SS

=PP1V5_S3_P1V5S3RS0_FET

P1V5S0FET_GATE_R

ISNS_3V3S0_P

ISNS_3V3S0_N

=PP3V3_S0_FET

=PP1V5_S3RS0_FET

P3V3S0_SSP3V3S0_EN_L

=P3V3S3_EN

=P5V_3V3_SUS_EN

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MMVOLTAGE=3.3VPP3V3_S3_FET_R =PP3V3_S3_FET

P1V5S3RS0_RAMP_DONE

=PP5V_S5_P1V5DDRFET

=P5VS0_EN

=P3V3S0_EN

=P5V_3V3_SUS_EN

P5VSUS_EN_L

P5V0S0_EN_L

P1V5CPU_EN

P1V5S0FET_GATE

=PP3V3_SUS_FET

P3V3SUS_SS

PP3V3_SUS_FET_R

VOLTAGE=3.3VMIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.50MM

=PP3V3_S5_P3V3SUSFET

P3V3SUS_EN_L

P5VSUS_SS

=PP5V_S5_P5VSUSFET

=PP5V_S0_FET

=PP5V_SUS_FET

PP1V5_S3RS0_FET_RVOLTAGE=1.5VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.6 MM

PP3V3_S0_FET_R

MIN_LINE_WIDTH=0.50MMMIN_NECK_WIDTH=0.20MMVOLTAGE=3.3V

=PP3V3_S0_P3V3S0FET

P5V0S0_SS

=PP5V_S3_P5VS0FET

VOLTAGE=5VMIN_NECK_WIDTH=0.20MM

PP5V_S0_FET_RMIN_LINE_WIDTH=0.40MM

=PP3V3_S4_P3V3S4FET

=PP3V3_S4_FETPP3V3_S4_FET_R

10V

10V

10V

10V

201201

201

201

201

201

201

201

201

201

201

201

201

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

C7810

1 2

C7811 1

2

R78101 2

C7830

1 2

C7831 1

2

Q7812 6

2 1

Q7812 3

5 4

R78601 2

C7861 1

2

C78601 2

U78015

7

4

2

8

6

3

9

1

C7801 1

2

R78011 2

C7802 1

2

Q7822 6

2 1

C7841 1

2

C7821 1

2

C78401 2

C78201 2

Q7822 3

5 4

Q7802 3

5 4

R78121

2

R78201 2

R78401 2

R78621

2

Q7830

1

3

47

Q7820

1

3

47

Q7810

1

3

47

R78301 2

R78321

2

R78421

2

R78221

2

Q7840

1

3

47

R78501 2

Q7801

5

4

1 2 3

R78111 2

R78211 2

R78411 2

R7831

1234

R7803

1 2

Q7800

1

3

47

C7800

1 2

C7809 1

2

R7800

1 2

R78021

2

Q7860

4

3

12

R7804

1 2Q7809

3

1 2

051-9277

2.8.0

78 OF 109

61 OF 73

7

7

45 72

45 72

7

7

7

7

7

7

7

7

7

7

7

7

7

G

D

SIN

IN

G

D

S

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

D

G S

IN

OUT

IN

IN

IN

INNC

NC

NC

Q3

Q2

Q4

Q1

SENSE

CT

VDD

GND

RESET*

MR*

IN

G

D

S

OUT

OUT

VDD

MR*

RST*V4MONV3MON

V2MON

GND THRM_PAD

OUT

OUT

OUT

IN

VDD

OUT_A*

OUT_A

THRMGND

IN_A

DLY_1C

IN_B

OUT_BDLY (OD,IPU)

(OD,IPU)

(OD,IPU)(IPD)

1.3V

PAD

2:1-+

OUT

OUT

VCC

A

Y

GND

B

CIN

IN

OUT

IN

IN

G

D

SNC

NC

NC

NC

OUT

NC

NC

IN

IN

OUT

OUT

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PM_SLP_S5_L:100K pull down on PCH page DP S4 Power Enable

VFRQ Low: Fix Frequency

(PM_SLP_S3_R_L)

Q3: 0.640V

S0 Rail PGOOD (BJT Version)

S5 Rail Enables & PGOOD

Threshold: ??DLY > 10 ms

343S0497

3.3V,5V S3 ENABLE

(90K IPU)

(AC_EN_L)

(IPU)

P1V5S0_PGOOD from U7710

Q4: 0.660V

353S2809

Thresholds:VDD: 2.734V-3.010V

(PM_SLP_S3_L)

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))WLAN Enable Generation

Unused fet

S5_PWRGD (old name RSMRST_PWRGD)-->SMC SMC-->PM_DSW_PWRGD

Worst-Case Thresholds:

S0 Rail PGOOD Circuitry

V3MON: 0.572V-0.630VV2MON: 2.815V-3.099V

V4MON: 0.572V-0.630V

(ISL Version in development)

PM_SLP_S3_L

1

0

01

1

1

PM_SLP_S4_L

1

1

PM_SLP_S5_L

1

1

1

PM_SUS_EN

0

1

X

SMC_PM_G2_ENABLE

1

1

1

1

SMC_S4_WAKESRC_EN

1

1

1 1 01 00 0

0

0

0

0

0

0

0

0

0

0

0

0 0

0

0

0

0 0

0

1

0

0

1 0

1

0

0

0

1

1

0

0

1

Battery Off (G3HotAC)

Battery Off (G3Hot)

Run (S0)

Sleep (S3AC)

Sleep (S3)

State

Deep Sleep (S4AC)

Deep Sleep (S5)

Deep Sleep (S4)

Deep Sleep (S5AC)

Internal pull-ups 100K +/- 20% SMC_ADAPTER_EN

toggle 3Hz

353S2310

0

CPUVCORE ENABLE

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

SMC_BATLOW_L:100K pull up on SMC page

3.3V w/Divider: 2.345V

Q2: 0.XXXV

PP1V5_S3RS0

3.3V/5.0V Sus ENABLE

No stuff C7931, 12msMin delay time

3.3V SUS Detect

PM_RSMRST_L goes to U1800.C21

PCH power down timing t235Could stuff R7930 to satisfy

threhold is 3.07V

S0 ENABLE

CHGR VFRQ Generation

VFRQ High: Variable Frequency

1

Mobile System Power State Table

U7930 Sense input

2N7002DW-X-GSOT-363

17 41 42

17 26 41 62

SOT-3632N7002DW-X-G

37

55

56

61


CERM-X5R402

0.47UF6.3V

57

PLACE_NEAR=U7400.1:5mm1/20WMF5%

0

61

38 61

45

59

60

54

MF1/20W5%5.1K



0.47UF

402CERM-X5R6.3V

17 26 37 41

49


0.47UF

CERM-X5R402

6.3V

1/20W


MF

5.1K5%


402CERM-X5R

0.47UF6.3V


CERM-X5R

0.47UF6.3V

402

33K

MF1/20W5%


1/20WMF

10K5%

53

SOD-VESM-HFSSM3K15FV

17 26 41 62

NO STUFF

5%0

MF1/20W

5%10K

MF1/20W

23 25 41 52 62

5%1001/20W

MF

5%

MF1/20W

100

5%1/20W

100

MF

100

MF1/20W5%

60

55

5%

100

MF1/20W

5%

MF1/20W

330

S0PGOOD_ISL

59

54

MF

1%150K1/20W

S0PGOOD_ISL

6.3VX5R

0.1UF

1/20WMF

15K1%

7.15K1/20WMF

1%DFN2015H4-8

CRITICAL

ASMCC0179

5%

1K

1/20WMF

1/20W

1K

MF

5%

CRITICAL

TPS3808G33DBVRG4SOT23-6

1/20WMF

100K5%6.3V

X5R

0.1UF


5%

MF1/20W

NO STUFF

10057

SOT-3632N7002DW-X-G

5%

100

MF1/20W

60

CERM-X5R


0.47UF6.3V

402

17

ISL88042IRTEZ

CRITICALTDFN

S0PGOOD_ISL

1/20WMF

1%

S0PGOOD_ISL

15K

S0PGOOD_ISL

12.4K

MF1/20W

1%

15K

S0PGOOD_ISL

1%

MF1/20W

1%

MF

10K1/20W

S0PGOOD_ISL

1/20W1%

MF

S0PGOOD_ISL

6.04KMF

1%

S0PGOOD_ISL

6.04K1/20W

55

X5R402NO STUFF

0.033UF1/20W

100

MF5%

41

6.3VX5R

0.1UF

41

TDFNSLG4AP012

CRITICAL

220PFX7R-CERM25V

6 39 40

5%1/20WMF

0

NO STUFF

402

0.068UF

CERM

60

20K


1/20WMF

5%

1/20WMF

NO STUFF

5%

0

SOT89174AUP1G3208


X5R

0.1UF6.3V

17

41 42

61


1/20WMF

39K5%


MF1/20W5%9.1K

MF

5%

100

1/20W

55

18 23 37

SOT-3632N7002DW-X-G

5%

1K

1/20WMF

64

MF-LF

0

NOSTUFF

5%

1/16W

402

SOT89174LVC1G32

17 41 20%


0.1uF

402

CERM

41 42

64

MF1/20W5%0

NO STUFF

61


Power Control 1/ENABLE

MAKE_BASE=TRUE

P5V3V3_S4_EN

=P3V3S4_EN

=TBTAPWRSW_EN

MAKE_BASE=TRUE

SMC_S4_WAKESRC_EN

=PP3V3_S5_PWRCTL

=PP3V3_S0_PWRCTL

PM_SLP_S5_L

PM_SLP_S3_L

PVCCSA_ENMAKE_BASE=TRUE

=PVCCSA_EN

=1V05_S0_LDO_EN=CPUVCCIOS0_EN

P1V5S0_ENMAKE_BASE=TRUE

=P1V5S0_EN

MAKE_BASE=TRUEP1V8S0_EN =P1V8S0_EN

=TBT_S0_EN

=P3V3S0_EN

=PBUSVSENS_EN

=P5VS0_EN

CPUVCCIOS0_ENMAKE_BASE=TRUE

CHGR_VFRQ

=PP3V42_G3H_PWRCTL

P1V8S0_PGOOD

DDRREG_ENMAKE_BASE=TRUE

=PP3V3_SUS_PWRCTL

MAKE_BASE=TRUEPM_SLP_S4_L

ALL_SYS_PWRGD

=P3V3S5_EN


P5VS3_ENMAKE_BASE=TRUE

=P5VS3_EN

AP_PWR_EN

CPUVCCIOS0_PGOOD

=PP5V_S0_VMON

=PP1V05_S0_VMON

VMON_3V3_DIV VMON_Q2_BASE

=PP3V3_S5_VMON

S0PGD_C

VMON_Q4_BASE

S0PGD_BJT_GND_R

S4_PGOOD_CT

=PP3V3_SUS_PWRCTL

=P3V3S3_EN

=USB_PWR_EN

=DDRREG_EN

=PP1V5_S3RS0_VMON

SMC_ADAPTER_EN

=PP3V3_S0_VMON

=PP1V5_S3RS0_VMON

=PP1V05_S0_VMON

P3V3S5_PGOOD

PVCCSA_PGOOD

AC_EN_L

PM_WLAN_EN_L

S5PGOOD_DLY

MAKE_BASE=TRUEP5V3V3_REG_EN

PM_SLP_S3_L

CPUIMVP_AXG_PGOOD

SMC_PM_G2_ENMAKE_BASE=TRUE

=PP3V42_G3H_PWRCTL

=PP3V3_S5_PWRCTL

ALL_SYS_PWRGD_RP1V05_DIV_VMON

P1V5_DIV_VMON

P5V_DIV_VMON

=PP3V3_S0_VMON

ALL_SYS_PWRGD

P5VS3_PGOOD


=P5V3V3_REG_EN

MAKE_BASE=TRUES5_PWRGD

=PP3V3_S5_PWRCTL

=P5V_3V3_SUS_ENPM_SUS_ENMAKE_BASE=TRUE

=PP3V3_S5_PWRCTL

SMC_BATLOW_L

ALL_SYS_PWRGD

PM_SLP_SUS_L

VMON_Q3_BASE

CPUIMVP_VR_ON

PM_SLP_S3_R_LMAKE_BASE=TRUE

PM_RSMRST_L

SUS_PGOOD_MR_L

16V

NO STUFF

16VX7R-CERM0201

1000PF

10V

10V

201

201

201201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201

201201

201

201

201

201

201

201

201

201

201

201

10%10%

10%10%10%

10%

10%

10%

10%

10%

10%

10%

10%

10%

Q79206

2

1

Q79256

2

1

C79121

2

R79741 2

R7911

1

2

C79101

2

C79861

2

R7986

1

2

C79811

2

C79871

2

R7987

1

2

R7931

12

Q79313

1 2

R79291

2

R79671

2

R79571

2

R79661 2

R79641 2

R79011 2

R79631 2

R79621 2

R79561

2

C7960 1

2

R79511

2

R79521

2

Q79505

7

1

6 4

8

2

3

R79541 2

R79551 2

U79304

2

3

15

6C79311

2

R79331

2

C7930 1

2

R79681 2

Q79203

5

4

R79781 2

C79881

2

U7960

4

1

8

9

356

2 7

R79731

2

R79711

2

R79611

2

R79701

2

R79721

2

R79601

2

C79421

2

R79411 2

C7940 1

2 U7941

7

5

2

6 3

4

8

9

1

C79411

2

R79131 2

C79131

2

R7981

1

2

R79171 2

U7940

1

3

6

2

5

4

C7943 1

2

R7988

1

2

R7912

1

2

R79651 2

Q79253

5

4

R79531 2

R7915

1 2

U7970

2

1

3

6

4

C7970 1

2

R79301

2

051-9277

2.8.0

79 OF 109

62 OF 73

5

7 62

7

7 62

7 62

23 25 41 52 62

7

7 62

7

7 62

7 62

7 62

7 62

7 62

7 62

7 62

7 62

7 62

45

7 62

23 25 41 52 62

GND THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

NC

NC

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

BI

BI

BI

IN

NC

NCNC

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BRANCH

6 3




Pull-ups on panel side,4.7 kOhm to 3.3V

LED Backlight I/F

(DP_INT_AUX_CH_C_N)

Internal DP Connector: 518S0787

LCD Connector

DisplayPort I/F

CHECK IF LVDS_IG_PANEL_PWR GLITCHES ON POWER UP

(DP_INT_AUX_CH_C_P)

10%

10%

10%

10%

10%10% 10%

50V

16V

16V

16V

16V

16V

201201

201

201

201

201

201

201

201201 201

1000PF

0201X7R-CERM

1000PF


PP3V3_SW_LCD

VOLTAGE=3.3V


DP_INT_AUX_CH_C_P

DP_INT_HPD

DP_INT_ML_F_P<0>

LED_RETURN_3

DP_INT_AUX_CH_C_N

DP_INT_HPD_CONN

=I2C_TCON_SCL I2C_TCON_SCL_R

LED_RETURN_2

LED_RETURN_5LED_RETURN_6

DP_INT_AUX_CH_P

=I2C_TCON_SDA

LED_RETURN_1

PPVOUT_SW_LCDBKLT

DP_INT_ML_N<0>

DP_INT_ML_P<0>

DP_INT_AUX_CH_N

LCD_IG_PWR_EN

I2C_TCON_SDA_R

LED_RETURN_4

DP_INT_ML_F_N<0>

MIN_NECK_WIDTH=0.20 MMVOLTAGE=3.3V

MIN_LINE_WIDTH=0.30 MMPP3V3_SW_LCD_UF

=PP3V3_S3_LCD

1518S0829 CONNTWIN-AX,P=0.4,30P,W-BOSS,HF J9000


Internal DisplayPort Connector

0402-LF

FERR-120-OHM-1.5A

MF1/20W5%1M


1/20W5%1M


MF

5%

0

MF1/20W

5%

0

1/20WMF

44

44

66 9

66 9

8

66 9

66 9

65 6

65 6

65 6

65 6

65 6

65 6

9

1/20W5%100K

MF

MF1/20W5%100K

5%

0

MF1/20W

100K

1/20WMF

5%


F-RT-SMCABLINE-CA

CRITICALOMIT_TABLE

0.1UF

0201X5R-CERM

0201

0.1UF

X5R-CERM

0.1UF

X5R-CERM0201

0201X5R-CERM

0.1UF

C0G-CERM

5%

603


MFET-2X2-8INFPF1009

CRITICAL

0.1UF

X5R6.3V1/20W

1K5%

MF6.3VX5R

0.1UF 10UF

603X5R6.3V20%

L9004

1 2

C90121

2

C9011 1

2

R90141

2

C90091

2

U9000

6

1

7

2

3

4

5

C9017 1

2

C9015 1

2

C9024

1 2

C9025

1 2

C9020

1 2

C9021

1 2

J9000

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

5

6

7

8

9

R90501

2

R90601 2

R90801

2

R90701

2

R90611 2

R90621 2

R90171

2

R90181

2

051-9277

2.8.0

90 OF 109

63 OF 73

6

66 6

66 6

66 6

6

6

65 6

6

66 6

7

IN

IN

OUT

IN

IN

IN

IN

IN

DPMLO+DPMLO-

VDD

DP-DP+

DDC_CLK

AUX+AUX-

AUXIO_EN

AUXIO-AUXIO+

THMPADGND

BIASIN BIASOUT

DDC_DAT

CA_DETOUT CA_DET

DP_PD

LSTXLSRX

HPDOUT HPDOUT

BI

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN

BI

BI

IN

IN

DP_PWR

AUX_CHP

ML_LANE3P

ML_LANE3N

CONFIG1

AUX_CHN

RETURN

GND GNDML_LANE0NML_LANE0P

CONFIG2

HOT_PLUG_DETECT

GND

GND

GND

ML_LANE1PML_LANE1N

ML_LANE2PML_LANE2N

SHIELD PINS

Y A

B

C

VCC

GND

OUT

ISET_S3

V3P3OUT

ISET_S0

EN

S0

HV_EN

RSVD

GND THRM

OUTVHV

ISET_V3P3

RSVD

V3P3

PAD


Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3



Y = B

TBT: LSX_A_R2P/P2R (P/N)

TBT: RX_1 Bias Sink

470k R’s for ESD protection

TBT: TX_0

TBT Dir

(Both D’s)

514-0818

TBT: LSX_R2P/P2R (P/N)TBT: Unused

greater than or equal

(Both C’s)

TBT: TX_1

down HPD input with

Sink HPD range:

below

For J9400 TBT SMT pads

Nominal Min Max

requires two R’s per HV

Single R on ISET_V3P3 OK.

TBT DirDP Dir

ISET_Sx with CD3210.

ILIM = 40000 / RISET

(Both C’s)

(Both C’s)

For 12V systems:

12V: See

18.9V Max

Nominal Min Max

Low: 0 - 0.8VHigh: 2.0 - 5.0V

(0-18.9V)DP Dir

(0-18.9V)

(Both C’s)

to 100K (DPv1.1a).

3.3V/HV Power MUX

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

V3P3 must be S4 to support

(3, 5, 17 & 19):

on AC-coupled signals.

DP Source must pull

wake from Thunderbolt devices.

Thunderbolt Connector A

Single-fault protection

IV3P3 1100mA 1030mA 1200mAIHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

10%

10%

10% 10%

10%

10%

10%10%

10% 10%

10%

10%

10%

10%

10%

10%

201

201

201

201201 201

201 201

201 201

201201

201

201

201201

201

201

201

201 201

201

201

201

201 201

201

10V

0.01UF

0402X7R-CERM

50V

0.01UF

0402X7R-CERM

0.01UF

0.01UF

0.01UF

402402

402

50V 50V

0402

TBT_A_D2R_C_N<1>TBT_A_D2R_C_P<1>

16V 16V

16V

16V

16V 16V

16V

16V

16V

330PF

0201X7R-CERM

330PF

0201X7R-CERM

34 70

34 70

1/20W

125%

MF

SIGNAL_MODEL=EMPTY

1K

MF1/20W

5%1K

SIGNAL_MODEL=EMPTY

MF1/20W5%

100K

MF1/20W5%

CRITICAL

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY

650NH-5%-0.430MA-0.52OHM

0603

GND_VOID=TRUE

CRITICAL

0603

0402

20%10UF

X5R-CERM0201

0.1UF

0201

22UF

603

CRITICAL

20%6.3V

X5R-CERM-1

CRITICAL

CASE-B2-SM

100UF20%6.3V

POLY-TANT

1/20W

1M

MF

5%1M

MF

5%1/20W

GND_VOID=TRUE

2.2K

MF1/20W

5%2.2K

GND_VOID=TRUE

MF1/20W5%

FERR-120-OHM-3A

0603

34

0.1UF

X5R

TSLP-2-7

CRITICAL

BAR90-02LRH

SIGNAL_MODEL=TBTPINGND_VOID=TRUE

CRITICAL

TSLP-2-7

GND_VOID=TRUESIGNAL_MODEL=TBTPIN

BAR90-02LRH

470K

MF1/20W

GND_VOID=TRUE

5%

MF

470K

1/20W

GND_VOID=TRUE

5%

34 70

34 70

GND_VOID=TRUE

470K

1/20WMF

5%470K

1/20WMF

GND_VOID=TRUE

5%

34 36

62

62

MF

36.5K1%1/20W

25V

0.1UF

X5R

HVQFNCBTL05023

CRITICAL

SIGNAL_MODEL=TBT_MUX

5%1/20W

MF

100K

100K

1/20WMF

5%

X5R-CERM

0.1UF

0201

0.1UF

0201X5R-CERM

34

8

8

25

34

34

34

5%1/20W

MF

1M

10K

MF1/20W5%

0201X5R-CERM

0.1UF

34

34 70

34 70

34 70

34 70

34 70

34 70

0.1UF X5R-CERM 0201

X5R-CERM0.1UF 0201

34 70

34 70

34 70

34 70

470K5% 1/20WMF

5% 1/20WMF

470K

GND_VOID=TRUEGND_VOID=TRUEGND_VOID=TRUE

1%

MF

22.6K1/20W

TBTHV:P15V

MF1/20W1%22.6K

TBTHV:P15V

CERM-X5R-1

GND_VOID=TRUE

4V20%0.47UF

GND_VOID=TRUE

CERM-X5R-14V20%0.47UF

0.47UF 20% 4VCERM-X5R-1

GND_VOID=TRUE

0.47UF

GND_VOID=TRUE

20% 4V

TBTHV:P15V

1/20W

22.6K

MF

1%

TBTHV:P15V

1/20W

22.6K

MF

1%

0.22UF 20%X5R

6.3V0201

X5R6.3V20%0.22UF 0201

GND_VOID=TRUE

0.22UF02016.3V20%

X5R

GND_VOID=TRUE

02010.22UF 6.3V20%

X5R

GND_VOID=TRUE

02016.3V

X5R20%0.22UF

GND_VOID=TRUE

02010.22UF 6.3V20%

X5R

02010.22UF 6.3V20%

X5R

0201X5R20% 6.3V0.22UF

X5R-CERM0201

25V

25VX5R-CERM0201

0201X5R-CERM

25V

CRITICAL

74AUP1T97SOT891

CERM

20%0.1UF

34

QFN

CRITICAL

TBTHV:P12VRES,MF,1/20W,17.8K,1,0201118S0145 R9410,R94132

RES,MF,1/20W,17.8K,1,0201118S0145 R9411,R94142 TBTHV:P12V


Thunderbolt Connector A

TBT_A_LSRX

PP3V3_SW_TBTAPWRTBT_A_LSRX_UNBUFTBT_A_LSTX

DP_TBTPA_HPD

TBT_A_DP_PWRDN

TBT_A_HPD

TBT_A_CONFIG1_RCTBT_A_CONFIG1_BUF

DP_TBTSNK0_DDC_DATA

TBT_A_CIO_SEL

DP_AUXIO_EN

DP_TBTSNK0_DDC_CLK

DP_A_LSX_ML_N<1>DP_A_LSX_ML_P<1>

PP3V3_SW_TBTAPWR

DP_A_AUXCH_DDC_NDP_A_AUXCH_DDC_P

VOLTAGE=3.3VTBT_A_BIAS

DP_TBTPA_ML_C_N<1> DP_TBTPA_ML_N<1>

DP_TBTPA_AUXCH_C_N

DP_TBTPA_ML_C_P<1>

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_P<1>

DP_TBTPA_AUXCH_PDP_TBTPA_AUXCH_N

DP_A_LSX_ML_N<1>

TBT_A_D2R1_AUXDDC_PTBT_A_D2R_N<1>

TBT_A_HPD

DP_TBTPA_ML_P<3>

TBTACONN_7_C

VOLTAGE=18.9V

DP_A_LSX_ML_P<1>

TBT_A_D2R_P<1>

TBT_A_CONFIG1_RC

DP_A_AUXCH_DDC_P

TBT_A_R2D_C_N<1>TBT_A_R2D_N<1>

TBT_A_BIAS

DP_TBTPA_ML_C_N<3> DP_TBTPA_ML_N<3>DP_TBTPA_ML_C_P<3>

TBT_A_R2D_C_P<1>

TBT_A_R2D_C_N<0>

TBT_A_D2R_C_P<0>

PP3V3RHV_SW_TBTAPWR

TBT_A_D2R_N<0>TBT_A_D2R_P<0>

TBT_A_R2D_C_P<0>TBT_A_R2D_P<0>

TBTACONN_1_CMIN_LINE_WIDTH=0.38 MM


TBT_A_R2D_P<1>

TBT_A_R2D_N<0>

TBTAPWRSW_ISET_V3P3

=PPHV_SW_TBTAPWRSW

MIN_NECK_WIDTH=0.20 MMVOLTAGE=15V

MIN_LINE_WIDTH=0.38 MMPPHV_SW_TBTAPWR

TBT_A_HV_EN

=TBT_S0_EN

=TBTAPWRSW_EN

TBTAPWRSW_ISET_S0

MIN_NECK_WIDTH=0.20 MMVOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MMPP3V3_SW_TBTAPWR

TBTAPWRSW_ISET_S3

TBT_A_CONFIG2_RC


TBT_A_D2R_C_N<0>

VOLTAGE=18.9V


SIGNAL_MODEL=EMPTY

CERM-X5R-1

DP_A_AUXCH_DDC_N

C0G-NP0

5%30PF

C0G-NP0

5%30PF

0402

VOLTAGE=15VMIN_NECK_WIDTH=0.20 MM

50V

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.38 MMTBTACONN_20_RC

MDP-J11F-RT-TH


CRITICALGND_VOID=TRUE

TBTAPWRSW_ISET_S0_R

TBTAPWRSW_ISET_S3_R

TBT_A_D2R1_AUXDDC_N

650NH-5%-0.430MA-0.52OHM


=PP3V3_S4_TBTAPWRSW

X5R-CERM

0.1UF

CERM-X5R6.3V

CD3210A0RGP25V25VX5R-CERM

0603

4.7UF10%

L9400

1 2

C9400 1

2

R94011

2

C9401 1

2

R94941

2

R94951

2

R94411

2

L9498

12

L9499

12

C94861

2

C9485 1

2

C94811

2

C9480 1

2

C9487 1

2

R94521

2

R94511

2

C9494 1

2

C94951

2

R94981

2

R94991

2

C9410 1

2

D9499 A K

D9498 A K

R94701

2

R94711

2

R94731

2

R94721

2

R94121

2

C94111

2

U9420

7

8

2

23

22

1 24

1816

5

4

10

11

6

20

19

9

21

1712

13

14

25

3 15

R94291

2

R94281

2

C9420 1

2

C9421 1

2

R94261

2

R94271

2

C94251

2

C9430 1 2

C9431 1 2

R9479 1 2

R9478 1 2

J9400

1816

46

20

1

713

814

2

2122232425262728

53

119

1715

1210

19

R94101

2

R94111

2

C9415 1

2

C9474 1 2

C9475 1 2

C9476 1 2

C9477 1 2

R94131

2

R94141

2

C9433 1 2

C9432 1 2

C9470 1 2

C9471 1 2

C9472 1 2

C9473 1 2

C9479 1 2

C9478 1 2

C94051 2

C940612

C9402 1

2

U9460

2

3

1

6

5

4

C94601

2

U9410

5

1 2 3 413

11 10

9

8

1214

1516

17

21

1920

18

67

C9498 1

2

C94991

2

051-9277

2.8.0

94 OF 109

64 OF 73

7 64

64

64

64 70

64 70

7 64

64 70

64 70

64

70

70

70

70

64 70

70

64

70 64 70

70

64

64 70

70

64

70

70

70

70

70

64 70

70

70

70

7

7

7 64

VDDIO VINVLDO

SW_0SW_1

FB

OUT3OUT2

OUT1

OUT4OUT5

OUT6

GND_SW

GND_S

GND_L

GND_SW

VSYNC

ISET

FILTER

FSET

SCLK

PWM

SDA

FAULT

EN

IN

IN

D

SG

D

SG

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

BI

Apple Inc.


124578

B

D

8 7 6 5 4 3

C

B

A


PAGE

12

D

A

C

PAGE TITLE

SHEET


R

DSIZEDRAWING NUMBER

REVISION

BRANCH

6 3




see spec for othersFpwm=9.62kHz

PPBUS S0 LCDBkLT FET

Addr: 0x58(Wr)/0x59(Rd)

(EEPROM should set EN_I_RES=1)I_LED=369/Riset

measurement on LED strings.

10.2 ohm resistors for current

AND PPBUS_SW_BKL

THERE IS A SENSE RESISTOR BETWEEN

LOADING 0.65 A (EDP)

P-TYPE

MOSFET

CHANNEL

FDC638APZ

43 mOhm @4.5VRDS(ON)

*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS

*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

I_LED=20.3mA

ON THE SENSOR PAGE *LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

PPBUS_SW_LCDBKLT_PWR


X7R-CERM50V

220PF


PLACE_NEAR=D9701.2:3mm

PLACE_NEAR=D9701.2:5mm

1210-1

PPBUS_SW_LCDBKLT_PWR_SW

5%

16V

0.1UF

0402

X7R-CERM

0.1UF

0.1UF

402

402

402

402

402

402

402

X5R

X5RX5R

X5R

X5R

X5R X5R

VOLTAGE=50V

VOLTAGE=50V

VOLTAGE=50V

50V 50V

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

5%

25V

25V

25V25V

0201NPO-C0G

33PF

1/20W

PLACE_NEAR=U9701.C4:4mm

BKL_VSYNC_R

=PP5V_S0_BKL

=PPBUS_SW_BKLLCDBKLT_EN_DIV

=PPBUS_S0_LCDBKLT

BKL_PWM

=PP3V3_S0_BKL_VDDIO

BKL_FSET

LCD_BKLT_PWM

=I2C_BKL_1_SDA BKL_SDA

=I2C_BKL_1_SCL

BKL_ENPPBUS_SW_LCDBKLT_PWR

BKL_ISET

LCDBKLT_EN_L

BKLT_PLT_RST_L

LCD_BKLT_ENLCDBKLT_DISABLE

MIN_LINE_WIDTH=0.5 mmLED_RETURN_5


LED_RETURN_4MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20 mm

LED_RETURN_1


LED_RETURN_2


LED_RETURN_3MIN_LINE_WIDTH=0.5 mmMIN_NECK_WIDTH=0.20 mm


LED_RETURN_6

VOLTAGE=12.6V

PPBUS_SW_LCDBKLT_PWRMIN_LINE_WIDTH=0.4 mmMIN_NECK_WIDTH=0.25 mm


PPVOUT_SW_LCDBKLTMIN_LINE_WIDTH=0.5 MM

PLACE_SIDE=BOTTOMTP_BKL_FAULT


PPVOUT_SW_LCDBKLT_FB


GND_BKL_SGND

VOLTAGE=0VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM


PPBUS_S0_LCDBKLT_FUSED




BKL_ISEN6


BKL_ISEN5


BKL_FLTR

BKL_ISEN1


BKL_ISEN2


BKL_ISEN3


BKL_ISEN4


BKL_SCL

BKLT:ENG3 R9717,R9718,R9719103S0198 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM

BKLT:ENGRES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM3 R9720,R9721,R9722103S0198


LCD Backlight Driver

44

44

8

SM

PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)

603-1

PLACE_NEAR=U9701.D1:5mm

1UF

0

1/16WMF-LF

BKLT:PROD

PLACE_NEAR=U9701.E5:10mm

BOTTOM

BKLT:PROD

1/16WMF-LF

0PLACE_NEAR=U9701.C5:10mm

BOTTOM

0

MF-LF1/16W

BKLT:PROD


BOTTOM

63 6

63 6

63 6

63 6

63 6

63 6

MF-LF1/16W

BKLT:PROD

0

BOTTOM


0

1/16WMF-LF

BKLT:PROD


BOTTOM

0

1/16WMF-LF

BKLT:PROD


BOTTOM

RB160M-60G


SOD-123

CRITICAL


CRITICAL

10UF

805



0.01UF

6.3V

MF1/20W

10K

1/20W

90.9K

MF

1%

MF

33

0

MF1/20W

1/20WMF

0MF

10K

1/20W

1%1/20W

100K

MF

200K1/20W1%

MF

MF1/20W1%18.2K

SM

CRITICAL

FDC638APZ_SBMS001

SSOT6-HF

1%

301K

MF

1/20W

603-HF

3AMP-32V-467

BOTTOM

SOT563

SSM6N15FEAPE

1%

147K

MF

1/20W

SOT563

SSM6N15FEAPE

8

25

CRITICAL

25-BUMP-MICRO

LP8550

CRITICAL

15UH-2.8A

PIMB053T-SM

1210-1

10UF

CRITICAL CRITICAL

10UF

0402

10V

201

201

201 201

201

201

201

201

201

201

201

201

201

10%

10%

10%

10%10%

10%

10%

10% 10%

C9712 1

2

C97131

2

D9701A K

R97221 2

R97211 2

R97201 2

R97181 2

R97191 2

R97171 2

C9710 1

2

XW9710

1 2

C97991

2

C97971

2

L9701

1 2

U9701

A3

C3

A5

C2

B4

E4

B5

A1

A2

B3

E5

D5

C5

E3

E2

E1

A4

D3

D4

B1

B2

C4

C1

D1

D2

Q9707 3

54

R97891

2

Q9707 6

21

F9700

1 2

R97881

2

C9782 1

2

Q9706

12

56

3

4

XW9720

1 2

R97141

2

R9731

1 2

R97151

2

R97411 2R9753

1 2

R97571 2

R97041 2

R97161

2

R97551

2

C9711 1

2

C97141

2

C97041

2

C97961

2

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LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM


AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD





MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

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PCI-Express Interface Constraints

Note: DisplayPort tables are on Page 103

CPU PCIE Spacing

Note: CPU_8MIL and CPU_ITP can be convertedback to TABLE_SPACING_RULE once rdar://10308147 is resolved

ELECTRICAL_CONSTRAINT_SET

CPU Signal Constraints

PCIE Clock Spacing

PCH PCIE Spacing

SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

DMI/FDI

PCIe SSD

DP

(FSB_CPURST_L)(XDP_BPM_L_R_CFG)(XDP_BPM_L_R_CFG)

SPACINGPHYSICALNET_TYPE

CPU Net Properties

PCIE_PCH_TXPCIE_PCH_TX * PCIE_TX2TX

PCIE_RX2RX*PCIE_PCH_RX PCIE_PCH_RX

*PCIE_PCH_TX *_PCH_TX PCIE_TX2OTHERTX

PCIE_PCH_RX * PCIE_RX2OTHERRX*_PCH_RX

PCIE_2OTHERHS*_RX *PCIE_PCH_TX

PCIE_PCH_RX * PCIE_2OTHERHS*_TX

PCIE_PCH_TX PCIE_2OTHERHS**_TX

*_PCH_RX * PCIE_TX2RXPCIE_PCH_TX

*_PCH_TX * PCIE_RX2TXPCIE_PCH_RX

*_RX * PCIE_2OTHERHSPCIE_PCH_RX

PCIE_PCH_TX * PCIE_2OTHER*

PCIE_PCH_RX * * PCIE_2OTHER

PCIE_CPU_RX * PCIE_2OTHER*

PCIE_CPU_TX ** PCIE_2OTHER

PCIE_CPU_RX * PCIE_2OTHERHS*_RX

*PCIE_CPU_TX *_RX PCIE_2OTHERHS

PCIE_2OTHERHSPCIE_CPU_RX *_TX *

*_CPU_TXPCIE_CPU_TX * PCIE_TX2OTHERTX

*_CPU_RX PCIE_RX2OTHERRX*PCIE_CPU_RX

PCIE_CPU_RX * PCIE_RX2RXPCIE_CPU_RX

PCIE_CPU_TX * PCIE_TX2TXPCIE_CPU_TX

?=2x_DIELECTRICCPU_AGTL TOP,BOTTOM

* *CPU_COMP CPU_COMP_2OTHER

CPU_COMP_2SELF*CPU_COMPCPU_COMP

?TOP,BOTTOM =5x_DIELECTRICPCIE_TX2OTHERTX

?TOP,BOTTOMPCIE_RX2OTHERRX =5x_DIELECTRIC

?=7x_DIELECTRICTOP,BOTTOMPCIE_TX2RX

TOP,BOTTOM ?=6x_DIELECTRICPCIE_2OTHERHS

PCIE_2OTHER =5x_DIELECTRIC ?TOP,BOTTOM

PCIE_TX2OTHERTX =4x_DIELECTRIC* ?

?PCIE_TX2TX =2.5x_DIELECTRIC*

=2.5x_DIELECTRICPCIE_RX2RX ?*

* ?PCIE_RX2OTHERRX =4x_DIELECTRIC

?*PCIE_TX2RX =6x_DIELECTRIC

* =3x_DIELECTRIC ?PCIE_2OTHER

*PCIE_RX2TX ?=6x_DIELECTRIC

*CLK_PCIE * CLK_PCIE_2OTHER

*CLK_PCIE CLK_PCIE CLK_PCIE_2SELF

CPU_VCCSENSE_2OTHER ?TOP,BOTTOM =10x_DIELECTRIC

=45_OHM_SE* =STANDARDCPU_45S =45_OHM_SE=45_OHM_SE =45_OHM_SE =STANDARD

CPU_8MIL_2ANY * ?8 MIL

=27P4_OHM_SE 0.100 MM*CPU_27P4S =27P4_OHM_SE =27P4_OHM_SE 0.100 MM=27P4_OHM_SE

CPU_VCCSENSE CPU_VCCSENSE_2SELF*CPU_VCCSENSE

TOP,BOTTOM ?PCIE_RX2TX =7x_DIELECTRIC

PCIE_CPU_TX *_TX * PCIE_2OTHERHS

* PCIE_RX2TXPCIE_CPU_RX *_CPU_TX

PCIE_TX2RX**_CPU_RXPCIE_CPU_TX

CLK_PCIE_2SELF * ?=4x_DIELECTRIC

CPU_VCCSENSE_2OTHER* *CPU_VCCSENSE

CLK_PCIE_2OTHER =10x_DIELECTRICTOP,BOTTOM ?

=5x_DIELECTRIC ?TOP,BOTTOMPCIE_RX2RX

?* =4x_DIELECTRICPCIE_2OTHERHS

?TOP,BOTTOM =5x_DIELECTRICPCIE_TX2TX

=6x_DIELECTRIC* ?CLK_PCIE_2OTHER

?TOP,BOTTOM =6x_DIELECTRICCPU_VCCSENSE_2SELF

=6x_DIELECTRIC* ?CPU_COMP_2OTHER

=4x_DIELECTRIC* ?CPU_COMP_2SELF

* * CPU_ITP_2ANYCPU_ITP

CPU_8MIL CPU_8MIL_2ANY**

?*CPU_AGTL =STANDARD

SYNC_MASTER=J13_CONSTRAINTS

CPU Constraints


=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFFCLK_PCIE_80D * =80_OHM_DIFF

CLK_PCIE_2SELF =6x_DIELECTRIC ?TOP,BOTTOM

=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF*PCIE_80D =80_OHM_DIFF=80_OHM_DIFF

CPU_VCCSENSE_2OTHER =6x_DIELECTRIC* ?

CPU_VCCSENSE_2SELF =4x_DIELECTRIC* ?

=4x_DIELECTRIC* ?CPU_ITP_2ANY

CPU_COMP_2SELF ?TOP,BOTTOM =6x_DIELECTRIC

TOP,BOTTOMCPU_COMP_2OTHER ?=10x_DIELECTRIC

CPU_45S XDP_DBRESET_LCPU_ITP

CPU_45S PM_SYNCPM_SYNC CPU_AGTL

CPU_PECICPU_PECI CPU_COMPCPU_45S

CPU_45S FDI_INTCPU_AGTL

PCIE_80DFDI_DATA FDI_DATA_N<7:0>PCIE_PCH_RX

DMI_N2S DMI_N2S_P<3:0>PCIE_80D PCIE_PCH_RXDMI_S2N PCIE_80D DMI_S2N_N<3:0>PCIE_PCH_TXDMI_S2N DMI_S2N_P<3:0>PCIE_80D PCIE_PCH_TX

CPU_ITP XDP_CPU_PREQ_LCPU_45S

CPU_SM_RCOMP CPU_27P4S CPU_SM_RCOMP<1>CPU_COMP

CPU_SM_RCOMP<0>CPU_27P4SCPU_SM_RCOMP CPU_COMP

CPU_27P4SCPU_SM_RCOMP CPU_SM_RCOMP<2>CPU_COMPCPU_45S CPU_CFG<11..0>CPU_ITPCPU_45SCPU_CATERR_L CPU_CATERR_LCPU_AGTL

CPU_45S CPU_PROCHOT_LCPU_PROCHOT_L CPU_AGTLCPU_45S CPU_VCCIO_SELCPU_AGTL

CPU_45S CPU_PWRGDCPU_PWRGD CPU_AGTL

DMI_CLK100M DMI_CLK100M_CPU_PCLK_PCIE_80D CLK_PCIECPU_45S PM_THRMTRIP_LPM_THRMTRIP_L CPU_8MIL

DMI_CLK100M DMI_CLK100M_CPU_NCLK_PCIE_80D CLK_PCIEDPLL_REF_CLK120M DPLL_REF_CLKPCLK_PCIECLK_PCIE_80D

DPLL_REF_CLKNDPLL_REF_CLK120M CLK_PCIECLK_PCIE_80DCLK_PCIE_80DITPCPU_CLK100M ITPCPU_CLK100M_PCLK_PCIE

ITPCPU_CLK100M CLK_PCIE_80D ITPCPU_CLK100M_NCLK_PCIEITPCPU_CLK100M ITPXDP_CLK100M_PCLK_PCIE_80D CLK_PCIEITPCPU_CLK100M CLK_PCIE_80D ITPXDP_CLK100M_NCLK_PCIE

ITPCPU_CLK100M XDP_CPU_CLK100M_NCLK_PCIECLK_PCIE_80D

CPU_COMP CPU_PEG_COMPCPU_27P4SCPU_COMP EDP_COMPCPU_27P4S

XDP_CPU_TDOXDP_TDO CPU_ITPCPU_45S

CPU_ITP XDP_BPM_L<7..4>XDP_BPM_L_R_CFG CPU_45S

CPU_CFG<15..12>CPU_ITPCPU_45S

CPU_VCCSENSE_PCPU_VCCSENSESENSE_1TO1_P2MMCPU_VCCSENSECPU_VCCSENSE_NCPU_VCCSENSESENSE_1TO1_P2MMCPU_VCCSENSE

CPU_VCCIOSENSE CPU_VCCIOSENSE_PSENSE_1TO1_P2MM CPU_VCCSENSECPU_VCCIOSENSE CPU_VCCIOSENSE_NSENSE_1TO1_P2MM CPU_VCCSENSE

CPU_VALSENSE CPU_VDDQ_SENSE_PCPU_27P4S CPU_VCCSENSE

CPU_AXG_SENSE_NSENSE_1TO1_P2MM CPU_VCCSENSECPU_AXG_SENSE

CPU_27P4SCPU_VALSENSE CPU_VDDQ_SENSE_NCPU_VCCSENSECPU_VALSENSE CPU_27P4S CPU_AXG_VALSENSE_PCPU_VCCSENSECPU_VALSENSE CPU_27P4S CPU_VCCSENSE CPU_AXG_VALSENSE_N

CPU_27P4SCPU_VALSENSE CPU_VCCSENSE CPU_VCC_VALSENSE_PCPU_VALSENSE CPU_27P4S CPU_VCCSENSE CPU_VCC_VALSENSE_N

CPU_VIDALERT_LCPU_SVIDALERT_L CPU_45S CPU_COMPCPU_45SCPU_SVIDSCLK CPU_VIDSCLKCPU_COMP

CPU_VIDSOUTCPU_45SCPU_SVIDSOUT CPU_COMP

PCIE_80D PCIE_CPU_RXPCIE_CPU_MUX_D2R PCIE_SSD_D2R_N<0>PCIE_SSD_D2R_MUX_OUT_PPCIE_80D PCIE_CPU_RX

PCIE_SSD_R2D_C_N<1>PCIE_80D PCIE_CPU_RXPCIE_CPU_SSD_R2D

PCIE_SSD_R2D_N<1>PCIE_80D PCIE_CPU_TX

PCIE_SSD_D2R_N<1>PCIE_80D PCIE_CPU_RXPCIE_CPU_SSD_D2R

PCIE_SSD_D2R_C_N<1>PCIE_80D PCIE_CPU_RX

PCIE_SSD_D2R_P<1>PCIE_80D PCIE_CPU_RXPCIE_CPU_SSD_D2R

PCIE_SSD_R2D_C_P<1>PCIE_80D PCIE_CPU_RXPCIE_CPU_SSD_R2D

PCIE_SSD_D2R_MUX_OUT_NPCIE_80D PCIE_CPU_RX

PCIE_SSD_D2R_C_P<1>PCIE_80D PCIE_CPU_RX

PCIE_CLK100M_SSD PCIE_CLK100M_SSD_PCLK_PCIECLK_PCIE_80D

DP_80D DP_TX DP_INT_ML_F_P<3..0>DP_INT_ML DP_80D DP_INT_ML_N<3..0>DP_TX

DP_80D DP_INT_ML_F_N<3..0>DP_TX

DP_INT_AUXCH DP_80D DP_INT_AUX_CH_C_PDP_AUX

DP_80D DP_AUX DP_INT_AUX_CH_PDP_80DDP_INT_AUXCH DP_INT_AUX_CH_C_NDP_AUX

DP_80D DP_INT_AUX_CH_NDP_AUX

CLK_PCIE_80DITPCPU_CLK100M XDP_CPU_CLK100M_PCLK_PCIE

XDP_TDI XDP_CPU_TDICPU_ITPCPU_45S

XDP_CPU_TCKCPU_ITPCPU_45SXDP_TCK

CPU_AXG_SENSE_PCPU_AXG_SENSE SENSE_1TO1_P2MM CPU_VCCSENSE

PCIE_80D PCIE_SSD_R2D_P<1>PCIE_CPU_TX

PCIE_CLK100M_SSD CLK_PCIECLK_PCIE_80D PCIE_CLK100M_SSD_N

DP_INT_ML DP_80D DP_TX DP_INT_ML_P<3..0>

CPU_ITP XDP_OBSDATA_B<3..0>CPU_45S

XDP_CPURST_LCPU_45S CPU_ITP

CPU_ITP XDP_BPM_L<3..0>XDP_BPM_L CPU_45S

XDP_CPU_TRST_LCPU_ITPCPU_45SXDP_TRST_L

XDP_CPU_TMSXDP_TMS CPU_ITPCPU_45S

CPU_45S FDI_FSYNC<1..0>CPU_AGTLFDI_LSYNC<1..0>CPU_AGTLCPU_45S

PCIE_80DDMI_N2S DMI_N2S_N<3:0>PCIE_PCH_RXPCIE_80D FDI_DATA_P<7:0>FDI_DATA PCIE_PCH_RX

CPU_45SPM_MEM_PWRGD PM_MEM_PWRGDCPU_AGTL

XDP_CPU_PRDY_LCPU_ITPCPU_45S

PCIE_SSD_R2D_C_P<0>PCIE_80DPCIE_CPU_MUX_R2D PCIE_CPU_TX

PCIE_80D PCIE_SSD_D2R_P<0>PCIE_CPU_RXPCIE_CPU_MUX_D2RPCIE_80D PCIE_CPU_TX PCIE_SSD_R2D_MUX_IN_N

PCIE_SSD_R2D_MUX_IN_PPCIE_80D PCIE_CPU_TXPCIE_80D PCIE_SSD_R2D_C_N<0>PCIE_CPU_MUX_R2D PCIE_CPU_TX

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10

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10 41 42 57

12

10 19 23

10 16

10 19 42

10 16

8 10

8 10

10 16

10 16

16 23

16 23

23

9

9

10 23

10 23

9 23

12 57

12 57

12 59

12 59

12

12 57

12

9

9

9

9

12 57

12 57

12 57

8 38

38

8 38

6 38

6 8 38

6 8 38

8 38

38

6 16 38

6 63

9 63

6 63

6 63

9 63

6 63

9 63

23

10 23

10 23

12 57

6 38

6 16 38

9 63

23

23

10 23

10 23

10 23

9 17

9 17

9 17

9 17

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10 23

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SPACINGNET_TYPE

ELECTRICAL_CONSTRAINT_SET PHYSICAL

Memory Net Properties

Memory to Power Spacing

Memory to GND Spacing

Memory Bus Spacing Group Assignments

Spacing Rule Sets

Memory Bus Constraints

=8.6x_DIELECTRIC

=5.7x_DIELECTRIC

=2x_DIELECTRIC

=GND_P2MM

=PWR_P2MM

=4x_DIELECTRIC

=4x_DIELECTRIC

=4x_DIELECTRIC

PalPilot Spacing

=4x_DIELECTRIC

=3x_DIELECTRIC

=3x_DIELECTRIC

=3x_DIELECTRIC

=3x_DIELECTRIC

"Real" Spacing=2x_DIELECTRIC

=GND_P2MM

=PWR_P2MM

=6x_DIELECTRIC

=6x_DIELECTRIC

=5.7x_DIELECTRIC

=8.6x_DIELECTRIC

MEM_*GND * MEM_2GND

=45_OHM_SE =45_OHM_SE*MEM_45S =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE

=72_OHM_DIFFMEM_72D * =72_OHM_DIFF =72_OHM_DIFF=72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF

=80_OHM_DIFF* =80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFFMEM_80D

=6x_DIELECTRICMEM_2OTHER ?*

DEFAULT**MEM_PWR

MEM_B_DATA_2 MEM_2OTHER* *

MEM_2OTHERMEM_B_DATA_3 * *



MEM_B_DQS_1 MEM_2OTHER* *

MEM_2OTHER*MEM_B_DQS_2 *





MEM_2OTHER*MEM_A_DQS_1 *


MEM_2OTHER*MEM_A_DATA_0 *








MEM_2OTHER*MEM_B_DATA_0 *



MEM_CLK MEM_CLK * MEM_CLK2CLK

MEM_CMD MEM_CMD * MEM_CMD2CMD

MEM_CMD MEM_CTRL * MEM_CMD2CTRL

MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL

*MEM_A_DQS_0 MEM_A_DATA_0 MEM_DQS2OWNDATA

* MEM_DQS2OWNDATAMEM_A_DQS_1 MEM_A_DATA_1







* MEM_DQS2OWNDATAMEM_B_DATA_0MEM_B_DQS_0

* MEM_DQS2OWNDATAMEM_B_DQS_4 MEM_B_DATA_4






MEM_2OTHERMEM*MEM_*MEM_*

* MEM_DATA2SELFMEM_*_DATA_* =SAME

MEM_2PWR*MEM_PWR MEM_*








MEM_DQS2OWNDATA*MEM_B_DQS_1 MEM_B_DATA_1


Memory Constraints


* MEM_2OTHERMEM_B_DATA_7 *


MEM_CTRL ** MEM_2OTHER

MEM_CMD ** MEM_2OTHER

MEM_CLK ** MEM_2OTHER

=GND_P2MM ?*MEM_2GND

=PWR_P2MM ?*MEM_2PWR

=4x_DIELECTRIC ?*MEM_2OTHERMEM

=6x_DIELECTRIC ?*MEM_CLK2CLK

=3x_DIELECTRIC ?*MEM_CTRL2CTRL

=2x_DIELECTRIC ?MEM_DATA2SELF *

=3x_DIELECTRIC ?MEM_DQS2OWNDATA *

=3x_DIELECTRICMEM_CMD2CMD * ?

=3x_DIELECTRIC ?*MEM_CMD2CTRL

MEM_A_DQS_P<3>MEM_80DMEM_A_DQS3 MEM_A_DQS_3

MEM_80DMEM_A_DQS6 MEM_A_DQS_N<6>MEM_A_DQS_6


MEM_72D MEM_CLKMEM_B_CLK MEM_B_CLK_N<5..0>

MEM_PWR PP1V5_S3RS0

MEM_45SMEM_A_DQ_BYTE4 MEM_A_DQ<39..32>MEM_A_DATA_4MEM_A_DQ<47..40>MEM_45SMEM_A_DQ_BYTE5 MEM_A_DATA_5

MEM_B_DQS_4MEM_80DMEM_B_DQS4 MEM_B_DQS_P<4>

MEM_80DMEM_B_DQS3 MEM_B_DQS_3 MEM_B_DQS_P<3>MEM_80D MEM_B_DQS_N<2>MEM_B_DQS2 MEM_B_DQS_2

MEM_B_DQS3 MEM_80D MEM_B_DQS_3 MEM_B_DQS_N<3>

MEM_80DMEM_B_DQS2 MEM_B_DQS_2 MEM_B_DQS_P<2>MEM_80DMEM_B_DQS1 MEM_B_DQS_1 MEM_B_DQS_N<1>

MEM_B_DQS_P<1>MEM_80DMEM_B_DQS1 MEM_B_DQS_1

MEM_B_DQS_N<0>MEM_80DMEM_B_DQS0 MEM_B_DQS_0

MEM_45SMEM_B_DQ_BYTE7 MEM_B_DATA_7 MEM_B_DQ<63..56>

MEM_45SMEM_B_DQ_BYTE5 MEM_B_DATA_5 MEM_B_DQ<47..40>MEM_45SMEM_B_DQ_BYTE4 MEM_B_DATA_4 MEM_B_DQ<39..32>

MEM_B_DQS5 MEM_B_DQS_N<5>MEM_B_DQS_5MEM_80D

MEM_A_DQS_P<0>MEM_80DMEM_A_DQS0 MEM_A_DQS_0MEM_45SMEM_A_DQ_BYTE7 MEM_A_DQ<63..56>MEM_A_DATA_7

MEM_A_DQS_P<1>MEM_80DMEM_A_DQS1 MEM_A_DQS_1

MEM_A_DQS_N<2>MEM_80DMEM_A_DQS2 MEM_A_DQS_2


MEM_80DMEM_A_DQS7 MEM_A_DQS_P<7>MEM_A_DQS_7

MEM_80DMEM_B_DQS5 MEM_B_DQS_5 MEM_B_DQS_P<5>

MEM_80D MEM_B_DQS_N<6>MEM_B_DQS6 MEM_B_DQS_6

MEM_45SMEM_B_DQ_BYTE6 MEM_B_DATA_6 MEM_B_DQ<55..48>

MEM_80DMEM_B_DQS0 MEM_B_DQS_0 MEM_B_DQS_P<0>

MEM_B_DQS7 MEM_80D MEM_B_DQS_P<7>MEM_B_DQS_7

MEM_80DMEM_A_DQS1 MEM_A_DQS_N<1>MEM_A_DQS_1MEM_A_DQS_P<2>MEM_80DMEM_A_DQS2 MEM_A_DQS_2

MEM_45SMEM_A_DQ_BYTE6 MEM_A_DQ<55..48>MEM_A_DATA_6

MEM_72D MEM_CLKMEM_A_CLK MEM_A_CLK_P<5..0>

MEM_45S MEM_CTRLMEM_A_CTRL MEM_A_CKE<3..0>

MEM_45S MEM_CMDMEM_A_CMD MEM_A_A<15..0>

MEM_45SMEM_A_DQ_BYTE2 MEM_A_DQ<23..16>MEM_A_DATA_2

MEM_A_DQS4 MEM_A_DQS_P<4>MEM_80D MEM_A_DQS_4MEM_A_DQS_4MEM_A_DQS4 MEM_A_DQS_N<4>MEM_80D

MEM_80DMEM_A_DQS5 MEM_A_DQS_P<5>MEM_A_DQS_5

MEM_B_DQS4 MEM_80D MEM_B_DQS_N<4>MEM_B_DQS_4

MEM_45S MEM_CTRLMEM_A_CTRL MEM_A_ODT<3..0>MEM_45S MEM_CTRLMEM_A_CTRL MEM_A_CS_L<3..0>

MEM_72D MEM_CLKMEM_A_CLK MEM_A_CLK_N<5..0>

MEM_45S MEM_CMDMEM_A_CMD MEM_A_BA<2..0>

MEM_B_CLK_P<5..0>MEM_72D MEM_CLKMEM_B_CLK

MEM_45S MEM_CMDMEM_B_CMD MEM_B_BA<2..0>

MEM_45S MEM_CMDMEM_B_CMD MEM_B_CAS_L

MEM_45SMEM_B_DQ_BYTE0 MEM_B_DQ<7..0>MEM_B_DATA_0


MEM_80D MEM_B_DQS_P<6>MEM_B_DQS_6MEM_B_DQS6

MEM_A_DQS_N<5>MEM_A_DQS5 MEM_80D MEM_A_DQS_5MEM_A_DQS_P<6>MEM_80DMEM_A_DQS6 MEM_A_DQS_6

MEM_B_CKE<3..0>MEM_45SMEM_B_CTRL MEM_CTRLMEM_45S MEM_CTRLMEM_B_CTRL MEM_B_CS_L<3..0>

MEM_45S MEM_CMDMEM_B_CMD MEM_B_A<15..0>


MEM_PWR PP0V75_S3_MEM_VREFCA_A


MEM_A_DQ<15..8>MEM_45SMEM_A_DQ_BYTE1 MEM_A_DATA_1MEM_45SMEM_A_DQ_BYTE0 MEM_A_DQ<7..0>MEM_A_DATA_0

MEM_45S MEM_A_DQ<31..24>MEM_A_DATA_3MEM_A_DQ_BYTE3

MEM_45S MEM_CMDMEM_A_CMD MEM_A_RAS_L

MEM_CMDMEM_45SMEM_A_CMD MEM_A_WE_L


MEM_45S MEM_CMDMEM_A_CMD MEM_A_CAS_L

MEM_45S MEM_CMDMEM_B_CMD MEM_B_WE_L

MEM_B_RAS_LMEM_45S MEM_CMDMEM_B_CMD

MEM_45S MEM_CTRLMEM_B_CTRL MEM_B_ODT<3..0>

MEM_PWR PP0V75_S3_MEM_VREFDQ_A

MEM_PWR PP1V5_S3

MEM_80D MEM_B_DQS_N<7>MEM_B_DQS_7MEM_B_DQS7

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SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

USB 2.0 Interface Constraints

UART Interface ConstraintsSOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.

SATA SSD

SATA Interface ConstraintsELECTRICAL_CONSTRAINT_SET SPACING

NET_TYPEPHYSICAL

PCH Net Properties

USB 3.0 Interface ConstraintsSOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8

USB Hub nets

USB EXTA nets (Right USB port)

USB Camera nets

USB EXTB nets (Left USB port)

(USB_TPAD_HUB)(USB_TPAD_HUB)

Unused USB nets

PCH Constraints 1

SYNC_MASTER=J13_CONSTRAINTS SYNC_DATE=01/11/2012

PCH_USB_RBIAS 8 MIL =STANDARD8 MIL=STANDARD* =STANDARD =STANDARD

=2x_DIELECTRIC*USB ?

*USB3_PCH_RX USB3_PCH_RX USB3_RX2RX

*_TXSATA3_PCH_RX SATA3_2OTHERHS*

**_RXSATA3_PCH_TX SATA3_2OTHERHS

=4x_DIELECTRIC* ?SATA3_TX2OTHERTX

=80_OHM_DIFF=80_OHM_DIFF* =80_OHM_DIFF=80_OHM_DIFF=80_OHM_DIFFSATA_80D =80_OHM_DIFF

?*SATA_ICOMP =4x_DIELECTRIC

SATA3_PCH_RX * SATA3_RX2TX*_PCH_TX

SATA3_PCH_TX SATA3_TX2OTHERTX**_PCH_TX

SATA3_PCH_TX SATA3_PCH_TX SATA3_TX2TX*

SATA3_PCH_RX SATA3_RX2OTHERRX*_PCH_RX *

SATA3_PCH_TX SATA3_TX2RX*_PCH_RX *

SATA3_PCH_RX SATA3_PCH_RX SATA3_RX2RX*

SATA3_2OTHERHS*_TXSATA3_PCH_TX *

SATA3_PCH_RX * SATA3_2OTHERHS*_RX

SATA3_2OTHERSATA3_PCH_TX * *

SATA3_PCH_RX * * SATA3_2OTHER

=5x_DIELECTRIC ?SATA3_TX2TX TOP,BOTTOM

TOP,BOTTOM =5x_DIELECTRIC ?SATA3_RX2RX

=5x_DIELECTRIC ?TOP,BOTTOMSATA3_TX2OTHERTX

=5x_DIELECTRIC ?TOP,BOTTOMSATA3_2OTHER

=5x_DIELECTRICTOP,BOTTOMSATA3_RX2OTHERRX ?

=7x_DIELECTRIC ?TOP,BOTTOMSATA3_TX2RX

=7x_DIELECTRICSATA3_RX2TX TOP,BOTTOM ?

=6x_DIELECTRICSATA3_2OTHERHS TOP,BOTTOM ?

SATA3_RX2TX =6x_DIELECTRIC ?*

SATA3_TX2TX =2.5x_DIELECTRIC* ?

SATA3_RX2RX =2.5x_DIELECTRIC* ?

=4x_DIELECTRICSATA3_RX2OTHERRX ?*

SATA3_TX2RX =6x_DIELECTRIC* ?

?*SATA3_2OTHERHS =4x_DIELECTRIC

SATA3_2OTHER =3x_DIELECTRIC* ?

* ?UART =2x_DIELECTRIC

UART_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE=45_OHM_SE =45_OHM_SE

TOP,BOTTOM =4x_DIELECTRICUSB ?

TOP,BOTTOM =5x_DIELECTRIC ?USB3_TX2TX

TOP,BOTTOM ?USB3_RX2RX =5x_DIELECTRIC

=5x_DIELECTRIC ?USB3_TX2OTHERTX TOP,BOTTOM

TOP,BOTTOM =5x_DIELECTRIC ?USB3_RX2OTHERRX

=7x_DIELECTRIC ?TOP,BOTTOMUSB3_TX2RX

TOP,BOTTOM ?USB3_RX2TX =7x_DIELECTRIC

TOP,BOTTOM ?=6x_DIELECTRICUSB3_2OTHERHS

=5x_DIELECTRIC ?USB3_2OTHER TOP,BOTTOM

USB3_RX2RX ?=2.5x_DIELECTRIC*

USB3_TX2RX ?=6x_DIELECTRIC*

USB3_TX2OTHERTX ?=4x_DIELECTRIC*

USB3_RX2OTHERRX ?=4x_DIELECTRIC*

USB3_RX2TX ?=6x_DIELECTRIC*

?USB3_2OTHER =3x_DIELECTRIC*

=4x_DIELECTRICUSB3_2OTHERHS ?*

*USB3_PCH_TX USB3_PCH_TX USB3_TX2TX

*_PCH_TX *USB3_PCH_RX USB3_RX2TX

*_PCH_TX * USB3_TX2OTHERTXUSB3_PCH_TX

*_PCH_RX *USB3_PCH_RX USB3_RX2OTHERRX

*_PCH_RX *USB3_PCH_TX USB3_TX2RX

USB3_2OTHERHS*_TX *USB3_PCH_RX

USB3_2OTHERHS*_TX *USB3_PCH_TX

USB3_2OTHERHS*_RX *USB3_PCH_TX

* *USB3_PCH_RX USB3_2OTHER

USB3_2OTHERHS*_RX *USB3_PCH_RX

* *USB3_PCH_TX USB3_2OTHER=2.5x_DIELECTRICUSB3_TX2TX ?*

USB_80D =80_OHM_DIFF* =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF=80_OHM_DIFF

UART_45S UART SMC_DEBUGPRT_TX_LUSB_EXTA USB_80D USB USB_EXTA_N

USB3_EXTB_RX_RC_PUSB3_PCH_RXUSB_80DUSB3_EXTB_RX_RC_NUSB3_PCH_RXUSB_80D

USB3_EXTB_RX_NUSB3_EXTB_RX USB3_PCH_RXUSB_80D

USB_EXTB_PUSBUSB_EXTB USB_80D

USB_EXTB_EHCI_NUSB_80D USB

USB_EXTB_NUSB_80D USBUSB_EXTBUSB_EXTB_EHCI_PUSB_80D USB

USB_EXTB_XHCI_NUSB_80D USBUSB3_EXTB_RX_PUSB_80D USB3_PCH_RXUSB3_EXTB_RX

USB_EXTB_XHCI_PUSBUSB_80D

USB3_EXTB_TX_C_PUSB_80D USB3_PCH_TXUSB3_EXTB_TX_C_NUSB_80D USB3_PCH_TX

USB3_EXTB_TX_PUSB3_EXTB_TX USB_80D USB3_PCH_TX

USB3_EXTB_RX_CONN_NUSB_80D USB3_PCH_RX

USB3_EXTB_TX_NUSB3_EXTB_TX USB_80D USB3_PCH_TX

USB3_EXTB_RX_CONN_PUSB3_PCH_RXUSB_80D

CLK_PCIE_80D CLK_PCIEPCH_DIFFCLK_UNUSED_ PCH_CLK100M_SATA_NCLK_PCIE PCH_CLK14P3M_REFCLKCPU_45S

PCH_DIFFCLK_UNUSED_ CLK_PCIECLK_PCIE_80D PCH_CLK96M_DOT_NPCH_DIFFCLK_UNUSED_ CLK_PCIE PCH_CLK100M_SATA_PCLK_PCIE_80D

PCH_DIFFCLK_UNUSED_ CLK_PCIE PCH_CLK96M_DOT_PCLK_PCIE_80DCLK_PCIEPCH_DIFFCLK_UNUSED_ CLK_PCIE_80D PCIE_CLK100M_PCH_N

PCH_DIFFCLK_UNUSED_ CLK_PCIECLK_PCIE_80D PCIE_CLK100M_PCH_PPCH_USB_RBIAS PCH_USB_RBIAS PCH_USB_RBIAS

USB_EXTD_XHCI_NUSB_80D USBUSB_80D USB USB_EXTD_XHCI_P

USB3_EXTA_RX_F_PUSB_80D USB3_PCH_RX

USB3_PCH_TXUSB_80D USB3_EXTA_TX_C_P

USB_80D USB3_PCH_TXUSB3_EXTA_TX USB3_EXTA_TX_NUSB3_PCH_TXUSB_80D USB3_EXTA_TX_PUSB3_EXTA_TX

USB_80DUSB3_EXTA_RX USB3_EXTA_RX_NUSB3_PCH_RXUSB_80D USB3_EXTA_RX_PUSB3_EXTA_RX USB3_PCH_RX

USBUSB_80D USB2_EXTA_MUXED_F_NUSB USB2_EXTA_MUXED_F_PUSB_80DUSBUSB_80D USB2_EXTA_MUXED_NUSB USB2_EXTA_MUXED_PUSB_80D

USB3_PCH_TXUSB_80D USB3_EXTA_TX_C_N

USB3_PCH_TXUSB_80D USB3_EXTA_TX_F_PUSB3_PCH_TXUSB_80D USB3_EXTA_TX_F_N

USB_80D USB3_PCH_RX USB3_EXTA_RX_F_N

UARTUART_45S SMC_DEBUGPRT_RX_L

USB_EXTA USB_80D USB USB_EXTA_P

USB_CAMERA USBUSB_80D USB_CAMERA_PUSB_CAMERA USBUSB_80D USB_CAMERA_N

USB_SMC USBUSB_80D USB_SMC_NUSB_SMC USBUSB_80D USB_SMC_P

USB_SDCARD USB_80D USB USB_SDCARD_PUSB_TPAD_M USBUSB_80D USB_TPAD_M_N

USB_SDCARD USB_80D USB USB_SDCARD_N

USB_TPAD_R_NUSB_80D USBUSB_TPAD_M USBUSB_80D USB_TPAD_M_P

USB_TPAD_R_PUSB_80D USBUSB_TPAD_HUB USBUSB_80D USB_TPAD_HUB_NUSB_TPAD_HUB USB USB_TPAD_HUB_PUSB_80D

USBUSB_80D USB_TPAD_CONN_NUSBUSB_80D USB_TPAD_CONN_P

USB_TPAD USB_80D USB USB_TPAD_N

USB_80D USB USB_BT_WAKE_NUSB_TPAD USB_80D USB USB_TPAD_P

USB_80D USB USB_BT_CONN_NUSB_80D USB USB_BT_CONN_P

USB_80D USB USB_BT_WAKE_P

USB_BT USBUSB_80D USB_BT_PUSB_BT USBUSB_80D USB_BT_N

USB_HUB_UP_PUSB_80DUSB_HUB1_UP USBUSB_80D USB_HUB_UP_NUSB_HUB1_UP USB

PCH_SATAICOMPPCH_SATA_ICOMP SATA_ICOMPSATA3_PCH_RX SATA_SSD_D2R_NSATA_80DSATA_MUX_SSD_D2RSATA3_PCH_RXSATA_80D SATA_SSD_D2R_PSATA_MUX_SSD_D2R

SATA_80D SATA_SSD_D2R_MUX_OUT_NSATA3_PCH_RX

SATA_PCH_MUX_D2R SATA3_PCH_RX SATA_HDD_D2R_NSATA_80DSATA_PCH_MUX_D2R SATA_HDD_D2R_PSATA3_PCH_RXSATA_80D

SATA_80D SATA_SSD_D2R_MUX_OUT_PSATA3_PCH_RX

SATA_80D SATA_HDD_R2D_C_PSATA3_PCH_TXSATA_PCH_MUX_R2D

SATA3_PCH_TX SATA_SSD_R2D_NSATA_80DSATA_MUX_SSD_R2DSATA3_PCH_TXSATA_80D SATA_SSD_R2D_PSATA_MUX_SSD_R2D

SATA_80D SATA3_PCH_TX SATA_SSD_R2D_MUX_IN_PSATA_80D SATA3_PCH_TX SATA_HDD_R2D_C_NSATA_PCH_MUX_R2D

SATA_80D SATA3_PCH_TX SATA_SSD_R2D_MUX_IN_N

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DisplayPort

SPACINGNET_TYPE

PHYSICAL

Clock Net PropertiesELECTRICAL_CONSTRAINT_SET

Chipset Net PropertiesELECTRICAL_CONSTRAINT_SET

System Clock Signal Constraints

SPACINGNET_TYPE

PHYSICALELECTRICAL_CONSTRAINT_SETNET_TYPE

PCH Net PropertiesPHYSICAL

HD Audio Interface Constraints

NOTE: 25MHz system clocks very sensitive to noise.

SPACING

LPC Bus Constraints

XDP Constraints

SPI Interface Constraints

SMBus Interface ConstraintsSOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

SIO Signal ConstraintsSOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15

SMB_45S_R_50S =45_OHM_SE =45_OHM_SE =45_OHM_SE* =STANDARD=STANDARD=45_OHM_SE

=45_OHM_SE =45_OHM_SE =STANDARD* =45_OHM_SEPCH_45S =45_OHM_SE =STANDARD

=45_OHM_SESPI_45S * =STANDARD=STANDARD=45_OHM_SE =45_OHM_SE=45_OHM_SE

*SPI ?=4x_DIELECTRIC

*PCH_ITP ?=2:1_SPACING

* ?=4x_DIELECTRICCLK_SLOW

* ?CLK_SLOW =2x_DIELECTRIC

* =2x_DIELECTRIC ?HDA

SMB * =2x_DIELECTRIC ?

SMB_45S_R_50S TOP,BOTTOM =50_OHM_SE =50_OHM_SE =50_OHM_SE=50_OHM_SE

LPC_45S =45_OHM_SE=45_OHM_SE =45_OHM_SE =45_OHM_SE* =STANDARD =STANDARD

* =5x_DIELECTRIC ?CLK_25M

=STANDARD=45_OHM_SE=45_OHM_SE=45_OHM_SEHDA_45S * =STANDARD=45_OHM_SE

?CLK_LPC * =4x_DIELECTRIC

* ?=3x_DIELECTRICLPC

=45_OHM_SE =45_OHM_SE* =STANDARD =STANDARD=45_OHM_SE=45_OHM_SECLK_LPC_45S

=45_OHM_SE=45_OHM_SE=45_OHM_SE*CLK_SLOW_45S =STANDARD=45_OHM_SE =STANDARD

TOP,BOTTOM =4x_DIELECTRIC ?DP_2DP

=6x_DIELECTRICDP_2OTHERHS ?TOP,BOTTOM

DP_AUX TOP,BOTTOM =4x_DIELECTRIC ?

DP_2OTHER ?=4x_DIELECTRICTOP,BOTTOM

=80_OHM_DIFF=80_OHM_DIFFDP_80D =80_OHM_DIFF=80_OHM_DIFF* =80_OHM_DIFF=80_OHM_DIFF

DP_2DP =3x_DIELECTRIC* ?

=4x_DIELECTRICDP_2OTHERHS ?*

=3x_DIELECTRIC ?*DP_AUX

DP_2OTHER ?* =3x_DIELECTRIC

DP_2OTHERHS*_TXDP_TX *

*DP_TX DP_TX DP_2DP

DP_2OTHERHSDP_TX **_RX

*DP_TX * DP_2OTHER


PCH Constraints 2


=45_OHM_SE=45_OHM_SE=45_OHM_SE=45_OHM_SE* =STANDARD =STANDARDCLK_25M_45S

=45_OHM_SE=45_OHM_SE=45_OHM_SE* =STANDARD =STANDARDCLK_SLOW_45S =45_OHM_SE

PCH_45S XDP_PCH_TDIPCH_ITPXDP_TDI

PCIE_TBT_D2R_P<3..0>PCIE_80D PCIE_PCH_RXPCIE_TBT_D2R

PCIE_PCH_TXPCIE_80D PCIE_TBT_R2D_N<3..0>PCIE_TBT_R2D

PCIE_TBT_D2R_C_P<3..0>PCIE_80D PCIE_PCH_RXPCIE_TBT_D2R_C_N<3..0>PCIE_80D PCIE_PCH_RXPCIE_CLK100M_TBT_PCLK_PCIE_80DPCIE_CLK100M_TBT CLK_PCIEPCIE_CLK100M_TBT_NPCIE_CLK100M_TBT CLK_PCIE_80D CLK_PCIE

PCIE_80DPCIE_TBT_D2R PCIE_PCH_RX PCIE_TBT_D2R_N<3..0>

PCIE_AP_D2R_NPCIE_80DPCIE_AP_D2R PCIE_PCH_RX

SPI_45S SPI SPI_MLB_CLK

SPI_CS0 SPI SPI_CS0_R_LSPI_45SSPI_MISO SPI_45S SPI SPI_MISO

XDP_TCK XDP_PCH_TCKPCH_45S PCH_ITP

XDP_TDO XDP_PCH_TDOPCH_45S PCH_ITP

CLK_PCIECLK_PCIE_80D PEG_CLK100M_P

PCIE_CLK100M_AP_NPCIE_CLK100M_AP CLK_PCIECLK_PCIE_80D

PCIE_80D PCIE_PCH_TX PCIE_AP_R2D_C_N

SPI_45S SPI SPI_SMC_MISOSPI_45S SPI SPI_SMC_MOSI

XDP_PCH_TMSXDP_TMS PCH_ITPPCH_45S

PCIE_PCH_TXPCIE_80D PCIE_TBT_R2D_C_N<3..0>

HDAHDA_45S HDA_BIT_CLK_R

HDA HDA_SYNC_RHDA_45SHDA_45S HDA_RST_R_LHDA_RST_L HDA

SPI_45S SPISPI_CLK SPI_CLK_R

SPI_45S SPI_CS0_LSPI

PCIE_PCH_TXPCIE_80DPCIE_AP_R2D PCIE_AP_R2D_PPCIE_PCH_TXPCIE_80DPCIE_AP_R2D PCIE_AP_R2D_N

PCIE_80D PCIE_PCH_TX PCIE_AP_R2D_C_P

SMB_45S_R_50S SMBSMBUS_PCH_CLK SMBUS_PCH_CLK

HDA_45SHDA_BIT_CLK HDA HDA_BIT_CLK

SPISPI_45S SPI_MLB_MISOSPI_MLB_MOSISPISPI_45S

SPI_SMC_CLKSPI_45S SPI

SPISPI_45S SPI_CLK

HDA_RST_LHDAHDA_45S

HDA_SYNC HDAHDA_45S HDA_SYNC

CLK_LPC_45S CLK_LPC PCH_CLK33M_PCIOUT

CLK_LPC_45S LPC_CLK33M_LPCPLUS_RCLK_LPC

SPISPI_45SSPI_MOSI SPI_MOSI_RSPI_45S SPI SPI_MOSI

PM_CLK32K_SUSCLK_RPM_SUS_CLK CLK_SLOW_45S CLK_SLOW

HDA_45S HDA HDA_SDIN0HDA_SDIN0HDAHDA_45S HDA_SDOUTHDA_SDOUT

HDA_45S HDA HDA_SDOUT_R

SMC_CLK32KCLK_SLOWCLK_SLOW_45S

LPC_CLK33M CLK_LPC_45S LPC_CLK33M_SMCCLK_LPCCLK_LPC_45S CLK_LPC LPC_CLK33M_SMC_R

CLK_LPC LPC_CLK33M_LPCPLUSCLK_LPC_45SLPC_CLK33M

SMBUS_SMC_1_S0_SDA SMBSMB_45S_R_50S SML_PCH_1_DATASMBUS_SMC_1_S0_SCL SMBSMB_45S_R_50S SML_PCH_1_CLK

SMBUS_PCH_0_CLK SMB SML_PCH_0_CLKSMB_45S_R_50SSMB_45S_R_50S SMBSMBUS_PCH_DATA SMBUS_PCH_DATA

CLK_LPC_45S CLK_LPC PCH_CLK33M_PCIINLPC_CLK33M

LPC_45S LPC LPCPLUS_RESET_LLPC_FRAME_L LPC_45S LPC_FRAME_LLPC

SPI_45S SPI SPI_SMC_CS_L

PCIE_AP_D2R PCIE_80D PCIE_PCH_RX PCIE_AP_D2R_P

PCIE_CLK100M_AP_PCLK_PCIECLK_PCIE_80DPCIE_CLK100M_AP

CLK_PCIECLK_PCIE_80D PEG_CLK100M_N

PCIE_80D PCIE_PCH_TX PCIE_TBT_R2D_C_P<3..0>

PCIE_TBT_R2D PCIE_PCH_TXPCIE_80D PCIE_TBT_R2D_P<3..0>

SPISPI_45S SPI_MLB_CS_L

SMB_45S_R_50SSMBUS_PCH_0_DATA SMB SML_PCH_0_DATA

LPC_AD LPC_45S LPC LPC_AD<3..0> DP_80D DP_TXDP_TBT_ML DP_TBTSNK0_ML_P<3..0>DP_80D DP_TXDP_TBT_ML DP_TBTSNK0_ML_N<3..0>DP_80D DP_TX DP_TBTSNK0_ML_C_P<3..0>DP_80D DP_TX DP_TBTSNK0_ML_C_N<3..0>DP_80D DP_AUX DP_TBTSNK0_AUXCH_PDP_TBT_AUXCHDP_80D DP_TBTSNK0_AUXCH_NDP_TBT_AUXCH DP_AUXDP_80D DP_AUX DP_TBTSNK0_AUXCH_C_PDP_80D DP_TBTSNK0_AUXCH_C_NDP_AUX

DP_TBTSNK1_ML_P<3..0>DP_80D DP_TXDP_TBT_MLDP_TBTSNK1_ML_N<3..0>DP_TXDP_80DDP_TBT_MLDP_TBTSNK1_ML_C_P<3..0>DP_TXDP_80DDP_TBTSNK1_ML_C_N<3..0>DP_TXDP_80D

DP_AUXDP_80D DP_TBTSNK1_AUXCH_PDP_TBT_AUXCHDP_AUXDP_80D DP_TBTSNK1_AUXCH_NDP_TBT_AUXCHDP_AUXDP_80D DP_TBTSNK1_AUXCH_C_PDP_AUXDP_80D DP_TBTSNK1_AUXCH_C_N

CLK_25MCLK_25M_45S SYSCLK_CLK25M_X2_RCLK_25M_45S CLK_25M SYSCLK_CLK25M_X2CLK_25M_45S CLK_25MSYSCLK_CLK25M_XTAL SYSCLK_CLK25M_X1

CLK_25M_45S CLK_25M SYSCLK_CLK25M_TBT_RSYSCLK_CLK25M_TBTCLK_25MCLK_25M_45SSYSCLK_CLK25M_TBT

CLK_25M SYSCLK_CLK25M_SB_RCLK_25M_45SSYSCLK_CLK25M_SB CLK_25MCLK_25M_45S SYSCLK_CLK25M_SB

SYSCLK_CLK32K_RTC CLK_SLOW_45S SYSCLK_CLK32K_RTCCLK_SLOW

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Only used on dual-port hosts.

ELECTRICAL_CONSTRAINT_SET PHYSICALNET_TYPE

Thunderbolt IC Net PropertiesSPACING

Only used on hosts supporting Thunderbolt video-in

Thunderbolt/DP Net PropertiesDisplayPort Signal Constraints

Thunderbolt SPI Signal ConstraintsNOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

ELECTRICAL_CONSTRAINT_SETNET_TYPE

PHYSICAL SPACING

Thunderbolt/DP Connector Signal Constraints

TBTDP_TX2TXTBTDP_TX TBTDP_TX *

Thunderbolt Constraints

SYNC_DATE=01/11/2012SYNC_MASTER=J13_CONSTRAINTS

=10x_DIELECTRICTBTDP_TX2RX ?TOP,BOTTOM

TBTDP_2OTHERHS =10x_DIELECTRICTOP,BOTTOM ?

=6x_DIELECTRICTBTDP_RX2RX ?TOP,BOTTOM

TBTDP_TX *_TX TBTDP_2OTHERHS*

TBTDP_2OTHERTBTDP_RX **

TBTDP_2OTHER*TBTDP_TX *

*_RX TBTDP_2OTHERHS*TBTDP_RX

TBTDP_2OTHER =6x_DIELECTRIC ?TOP,BOTTOM

TBTDP_TX2RXTBTDP_TX TBTDP_RX *

?TBTDP_TX2TX * =4x_DIELECTRIC

TBTDP_TX2RX ?* =6x_DIELECTRIC

TBTDP_RX2RX ?* =4x_DIELECTRIC

=4x_DIELECTRICTBTDP_2OTHER ?*

=6x_DIELECTRICTBTDP_2OTHERHS * ?

*_TX TBTDP_2OTHERHS*TBTDP_RX

TBTDP_2OTHERHS*_RX *TBTDP_TX

TBT_SPI * =2x_DIELECTRIC ?

=80_OHM_DIFFTBTDP_80D * =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

TBTDP_RX TBTDP_RX * TBTDP_RX2RX

TBTDP_TX TBTDP_TX2RXTBTDP_RX *

=6x_DIELECTRICTBTDP_TX2TX ?TOP,BOTTOM

TBT_SPI_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD

TBTDP_RXTBTDP_80D TBT_A_D2R_C_P<1..0>

TBTDP_RXTBTDP_80DTBT_A_D2R1 TBT_A_D2R_P<1>TBTDP_RXTBT_A_D2R1 TBT_A_D2R_N<1>TBTDP_80DTBTDP_RXTBT_A_D2R0 TBT_A_D2R_P<0>TBTDP_80DTBTDP_RXTBT_A_D2R0 TBT_A_D2R_N<0>TBTDP_80D

DP_AUXTBT_A_AUXCH DP_80D DP_TBTPA_AUXCH_C_PDP_AUXDP_80DTBT_A_AUXCH DP_TBTPA_AUXCH_C_NDP_AUX DP_TBTPA_AUXCH_PDP_80DDP_AUX DP_TBTPA_AUXCH_NDP_80DDP_AUXDP_80D DP_A_AUXCH_DDC_P

TBTDP_RXTBTDP_80D TBT_A_D2R_C_N<1..0>

TBTDP_RXTBTDP_80D TBT_A_D2R1_AUXDDC_PTBTDP_RXTBTDP_80D TBT_A_D2R1_AUXDDC_N

TBTDP_TX TBT_B_R2D_C_N<1..0>TBT_B_R2D TBTDP_80D

TBTDP_TX TBT_B_R2D_N<1..0>TBTDP_80D

TBTDP_TX TBT_A_R2D_C_P<1..0>TBT_A_R2D TBTDP_80DTBTDP_TX TBT_A_R2D_C_N<1..0>TBT_A_R2D TBTDP_80D

TBTDP_TX TBT_A_R2D_N<1..0>TBTDP_80DTBTDP_TX TBT_A_R2D_P<1..0>TBTDP_80D

DP_TBTSRC_ML_C_P<3..0>DP_80D DP_TXDP_TBTSRC_ML_C_N<3..0>DP_80D DP_TXDP_TBTSRC_AUXCH_C_PDP_80D DP_AUXDP_TBTSRC_AUXCH_C_NDP_80D DP_AUX

TBT_SPI_CLKTBT_SPI_CLK TBT_SPI_45S TBT_SPITBT_SPI_MOSITBT_SPI_MOSI TBT_SPI_45S TBT_SPITBT_SPI_MISOTBT_SPI_MISO TBT_SPI_45S TBT_SPITBT_SPI_CS_LTBT_SPI_45S TBT_SPITBT_SPI_CS_L

TBTDP_TXTBT_B_R2D TBT_B_R2D_C_P<1..0>TBTDP_80D

TBTDP_TX TBT_B_R2D_P<1..0>TBTDP_80D

DP_TBTPB_ML DP_TBTPB_ML_C_P<3..1:2>DP_80D DP_TX

DP_TBTPB_ML_P<3..1:2>DP_80D DP_TX

DP_TBTPB_ML_C_N<3..1:2>DP_TBTPB_ML DP_80D DP_TX

DP_TBTPB_ML_N<3..1:2>DP_80D DP_TX

DP_80D DP_TX DP_B_LSX_ML_N<1>DP_80D DP_TX DP_B_LSX_ML_P<1>

TBTDP_RXTBTDP_80D TBT_B_D2R_C_P<1..0>TBTDP_RX TBT_B_D2R_C_N<1..0>TBTDP_80DTBTDP_RX TBT_B_D2R_P<1..0>TBTDP_80DTBT_B_D2RTBTDP_RX TBT_B_D2R_N<1..0>TBT_B_D2R TBTDP_80D

DP_AUX DP_TBTPB_AUXCH_C_PTBT_B_AUXCH DP_80DDP_AUX DP_TBTPB_AUXCH_C_NTBT_B_AUXCH DP_80D

DP_AUX DP_B_AUXCH_DDC_PDP_80D

DP_AUX DP_TBTPB_AUXCH_PDP_80DDP_AUX DP_TBTPB_AUXCH_NDP_80D

DP_AUX DP_B_AUXCH_DDC_NDP_80DTBTDP_RX TBT_B_D2R1_AUXDDC_PTBTDP_80DTBTDP_RX TBT_B_D2R1_AUXDDC_NTBTDP_80D

DP_AUXDP_80D DP_A_AUXCH_DDC_N

DP_TXDP_80D DP_A_LSX_ML_P<1>

DP_TXDP_80DDP_TBTPA_ML1 DP_TBTPA_ML_C_N<1>DP_TXDP_80DDP_TBTPA_ML1 DP_TBTPA_ML_C_P<1>

DP_80D DP_TXDP_TBTPA_ML3 DP_TBTPA_ML_C_P<3>

DP_80D DP_A_LSX_ML_N<1>DP_TX

DP_TXDP_TBTPA_ML3 DP_TBTPA_ML_C_N<3>DP_80D

DP_TX DP_TBTPA_ML_N<3..1:2>DP_80DDP_TX DP_TBTPA_ML_P<3..1:2>DP_80D

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SMC SMBus Net Properties

PHYSICAL

NET_TYPEPHYSICAL SPACING

SPACING

ELECTRICAL_CONSTRAINT_SET

NET_TYPEELECTRICAL_CONSTRAINT_SET

SMBus Charger Net Properties

SMC Constraints


1:1_DIFFPAIR 0.1 MM=STANDARD* =STANDARD =STANDARD=STANDARD 0.1 MM

SMBUS_SMC_1_S0_SCL SMB SMBUS_SMC_1_S0_SCLSMB_45S_R_50SSMBUS_SMC_1_S0_SDA SMB SMBUS_SMC_1_S0_SDASMB_45S_R_50S

CHGR_CSO_R_N1:1_DIFFPAIR

CHGR_CSO_R_P1:1_DIFFPAIR

SENSE_DIFFPAIR CHGR_CSI_N1:1_DIFFPAIRCHGR_CSI_R_P1:1_DIFFPAIRCHGR_CSI_R_N1:1_DIFFPAIR

SENSE_DIFFPAIR 1:1_DIFFPAIR CHGR_CSO_NSENSE_DIFFPAIR 1:1_DIFFPAIR CHGR_CSO_P

SENSE_DIFFPAIR CHGR_CSI_P1:1_DIFFPAIR

SMB_45S_R_50S SMBUS_SMC_0_S0_SCLSMBUS_SMC_0_S0_SCL SMBSMB_45S_R_50S SMBUS_SMC_0_S0_SDASMBUS_SMC_0_S0_SDA SMB

SMBUS_SMC_2_S3_SCL SMBUS_SMC_2_S3_SCLSMBSMB_45S_R_50SSMBUS_SMC_2_S3_SDA SMBUS_SMC_2_S3_SDASMBSMB_45S_R_50S

SMB_45S_R_50S SMBUS_SMC_5_G3_SCLSMBSMBUS_SMC_5_G3_SCLSMB_45S_R_50S SMBUS_SMC_5_G3_SDASMBSMBUS_SMC_5_G3_SDA

SMBUS_SMC_3_SCL SMBUS_SMC_3_SCLSMBSMB_45S_R_50SSMBUS_SMC_3_SDA SMB SMBUS_SMC_3_SDASMB_45S_R_50S

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ELECTRICAL_CONSTRAINT_SETNET_TYPE

SPACINGPHYSICAL

J11/J13 Specific Net Properties

SB_POWER CLK_PCIE * PWR_P2MM

GND * GND_P2MMUSB*

SATA*GND * GND_P2MM

GND PCIE* GND_P2MM*

GND_P2MMGND *CLK_PCIE

*GND GND_P2MMCPU_VCCSENSE

GND_P2MMCPU_COMP *GND

=45_OHM_SE=1:1_DIFFPAIR =1:1_DIFFPAIR* =45_OHM_SE =45_OHM_SE =1:1_DIFFPAIRSENSE_1TO1_45S

0.200 MM =1:1_DIFFPAIR0.100 MMSENSE_1TO1_P2MM =1:1_DIFFPAIR* =1:1_DIFFPAIR=1:1_DIFFPAIR

=45_OHM_SE=45_OHM_SE =45_OHM_SE =1:1_DIFFPAIR=1:1_DIFFPAIRTHERM_1TO1_45S =1:1_DIFFPAIR*

0.300 MM =1:1_DIFFPAIR0.100 MM =1:1_DIFFPAIR=1:1_DIFFPAIR*SPKR_DIFFPAIR =1:1_DIFFPAIR

?=2:1_SPACINGSENSE *

?=2:1_SPACINGAUDIO *

?=STANDARD*GND

* ?=2:1_SPACINGTHERM

SB_POWER *SATA* PWR_P2MM

* 0.20 MM 1000PWR_P2MMSB_POWER SATA* * PWR_P2MM

1000GND_P2MM * 0.20 MMGND LVDS* * GND_P2MM

Project Specific Constraints


ISNS_3V3S0_R_PSENSE_1TO1_45S SENSE

SENSE_DIFFPAIR THERM_1TO1_45S THERM INLET_THMSNS_D1_PTHERM_1TO1_45S THERM INLET_THMSNS_D1_NSENSE_DIFFPAIR

THERM_1TO1_45S TBTTHMSNS_D2_R_PTHERM

SENSESENSE_1TO1_P2MMSENSE_DIFFPAIR CPUVCCIOS0_CS_P

CPUTHMSNS_D2_NSENSE_DIFFPAIR SENSE_1TO1_45S SENSE

CPUTHMSNS_D2_PSENSE_DIFFPAIR SENSE_1TO1_45S SENSE

THERM_1TO1_45S TBTTHMSNS_D2_R_NTHERM

SENSE_1TO1_45S SENSE CPU_THERMD_PSENSE_DIFFPAIR

SENSESENSE_1TO1_45SSENSE_DIFFPAIR ISNS_1V5_S3_N

SENSE_1TO1_P2MM SENSE CPUIMVP_ISNS1G_PSENSE_DIFFPAIRSENSE_1TO1_P2MM SENSE CPUIMVP_ISNS1G_NSENSE_DIFFPAIR

SENSE_1TO1_P2MM SENSESENSE_DIFFPAIR CPUIMVP_ISNS1_NSENSE_1TO1_45S SENSE CPUIMVP_ISUM_R_P

VCCSAISNS_R_NSENSESENSE_1TO1_45S

ISNS_3V3S0_NSENSE_1TO1_45S SENSESENSE_DIFFPAIR

CPUIMVP_ISUMG_PSENSESENSE_1TO1_P2MMSENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_45S SENSE CPU_THERMD_N

CPUVCCIOS0_CS_NSENSE_1TO1_P2MM SENSESENSE_DIFFPAIR

SENSE_DIFFPAIR SENSESENSE_1TO1_P2MM CPUIMVP_ISNS1_P

SENSE_1TO1_45S SENSE CPUIMVP_ISUM_R_N

SENSE CPUIMVP_ISUMG_R_PSENSE_1TO1_45S

SENSE ISNS_HS_OTHER_PSENSE_1TO1_45SSENSE_DIFFPAIR

SENSE CPUIMVP_ISUMG_R_NSENSE_1TO1_45S

VCCSAS0_CS_PSENSESENSE_DIFFPAIR SENSE_1TO1_P2MM

TBT_MLBBOT_THMSNS_PTHERM_1TO1_45S THERM

TBT_THERMD_NTHERM_1TO1_45S THERMSENSE_DIFFPAIRSENSE_DIFFPAIR THERM_1TO1_45S THERM TBT_THERMD_P

THERM TBT_MLBBOT_THMSNS_NTHERM_1TO1_45S

CPUIMVP_ISUMG_NSENSE_1TO1_P2MM SENSESENSE_DIFFPAIR

ISNS_3V3S0_R_NSENSE_1TO1_45S SENSE

SENSE_1TO1_45S ISNS_3V3S0_PSENSESENSE_DIFFPAIR

VCCSAISNS_R_PSENSESENSE_1TO1_45S

VCCSAS0_CS_NSENSESENSE_DIFFPAIR SENSE_1TO1_P2MM

SENSE_1TO1_P2MM CPUIMVP_ISUM_PSENSESENSE_DIFFPAIR

SENSESENSE_1TO1_45S ISNS_HS_OTHER_NSENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE ISNS_1V5_S3_PSENSE_1TO1_45S

ISNS_AIRPORT_NSENSE_1TO1_45S SENSESENSE_DIFFPAIR

CPUIMVP_ISUM_NSENSESENSE_DIFFPAIR SENSE_1TO1_P2MM

SENSE ISNS_HS_COMPUTING_NSENSE_DIFFPAIR SENSE_1TO1_45S

SENSE_1TO1_45SSENSE_DIFFPAIR ISNS_AIRPORT_PSENSE

SENSE_DIFFPAIR SENSE_1TO1_45S SENSE ISNS_SSD_N

ISNS_HS_COMPUTING_PSENSE_1TO1_45S SENSESENSE_DIFFPAIR

SENSESENSE_1TO1_45S ISNS_SSD_PSENSE_DIFFPAIR

ISNS_LCDBKLT_NSENSE_DIFFPAIR SENSESENSE_1TO1_45SSENSE_DIFFPAIR SENSE ISNS_LCDBKLT_PSENSE_1TO1_45S

SPKRAMP_ROUT_NSPKR_DIFFPAIR AUDIOSPKR_OUT

SB_POWER PP3V3_S5SB_POWER PP3V3_S0

SPKRAMP_INR_PAUDIO1:1_DIFFPAIRAUD_DIFFSPKRAMP_INR_NAUDIO1:1_DIFFPAIRAUD_DIFF

AUDIO1:1_DIFFPAIR MAX98300_R_PAUDIO1:1_DIFFPAIR MAX98300_R_N

SPKR_DIFFPAIR AUDIOSPKR_OUT SPKRAMP_ROUT_P

GNDGND

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TABLE_BOARD_INFO

VERSIONALLEGRO

(MIL or MM)BOARD UNITSBOARD LAYERS BOARD AREAS

























































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Single-ended Physical Constraints

Differential Pair Physical Constraints

Spacing Constraints

J11/J13 Board-Specific Spacing & Physical Constraints

100 MM55_OHM_SE 100 MMN* =STANDARD =STANDARD =STANDARD

80_OHM_DIFF Y 0.132 MM 0.132 MM 0.130 MM 0.130 MMTOP,BOTTOM

80_OHM_DIFF ISL3,ISL10 Y 0.081 MM 0.081 MM 0.115 MM 0.115 MM

0.090 MMY 0.090 MMTOP,BOTTOM55_OHM_SE

0.096 MMISL3,ISL1040_OHM_SE 0.096 MMY

16.2MMNO_TYPE,BGATOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

?0.100 MM*1:1_SPACING

* * BGA BGA_P1MM

MEM_CLK * BGA BGA_P2MM

CLK_SLOW * BGA BGA_P2MM

CLK_PCIE * BGA BGA_P2MM

DEFAULT 0 MM0 MM10 MM* N 100 MM100 MM

?0.071 MMTOP,BOTTOM1x_DIELECTRIC

?0.053 MMISL3,ISL101x_DIELECTRIC

* 0.1 MM ?DEFAULT

=45_OHM_SE=45_OHM_SEYDEFAULT ISL4,ISL9

=45_OHM_SE=45_OHM_SEYDEFAULT ISL2,ISL11

=45_OHM_SE=45_OHM_SEYISL3,ISL10DEFAULT

100 MM =STANDARD=STANDARD=STANDARD35_OHM_SE * N 100 MM

0.170 MM0.170 MM40_OHM_SE YTOP,BOTTOM

0.096 MM0.096 MM40_OHM_SE YISL2,ISL11

=STANDARD40_OHM_SE =STANDARD=STANDARD* N 100 MM 100 MM

ISL4,ISL9 Y40_OHM_SE 0.099 MM 0.099 MM

0.135 MM0.135 MM45_OHM_SE YTOP,BOTTOM

0.075 MM0.075 MM45_OHM_SE YISL2,ISL11

=STANDARD45_OHM_SE =STANDARD* N 100 MM 100 MM =STANDARD

0.080 MM0.080 MM45_OHM_SE ISL4,ISL9 Y


=STANDARD50_OHM_SE =STANDARD=STANDARD* N 100 MM 100 MM

0.165 MM 0.130 MM0.130 MM0.165 MM72_OHM_DIFF TOP,BOTTOM Y

72_OHM_DIFF YISL3,ISL10 0.109 MM 0.109 MM 0.150 MM 0.150 MM



ISL2,ISL1180_OHM_DIFF 0.081 MM 0.081 MM 0.115 MM 0.115 MMY

100 MM 100 MM72_OHM_DIFF N* =STANDARD =STANDARD =STANDARD

100 MM80_OHM_DIFF =STANDARD=STANDARD=STANDARD* N 100 MM

80_OHM_DIFF ISL4,ISL9 Y 0.088 MM 0.088 MM 0.110 MM 0.110 MM

TOP,BOTTOM Y50_OHM_SE 0.110 MM 0.110 MM


ISL2,ISL11 0.125 MMY35_OHM_SE 0.125 MM

35_OHM_SE 0.125 MM0.125 MMISL3,ISL10 Y

35_OHM_SE 0.195 MM 0.195 MMYTOP,BOTTOM

* =DEFAULT ?BGA_P1MM

=DEFAULT ?BGA_P2MM *

* ?=DEFAULTSTANDARD

1x_DIELECTRIC ?0.090 MM*

?0.050 MMISL4,ISL91x_DIELECTRIC

Y =50_OHM_SE =50_OHM_SETOP,BOTTOMDEFAULT


PCB Rule Definitions

=DEFAULT =DEFAULT=DEFAULT=DEFAULT*STANDARD =DEFAULT=DEFAULT

TOP,BOTTOM 0.310 MM 0.310 MM27P4_OHM_SE Y

ISL2,ISL11 0.182 MM0.182 MM27P4_OHM_SE Y

27P4_OHM_SE 0.182 MMISL3,ISL10 Y 0.182 MM

0.182 MM 0.182 MM27P4_OHM_SE YISL4,ISL9

=STANDARD =STANDARD =STANDARD100 MM100 MM* N27P4_OHM_SE

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