SEMICONDUCTOR DEVICES & IC

TECHNOLOGY

Scaling of MOSFET

LEARNING OUTCOME

After completing the unit, students should be

able to:

Explain the evolution of integrated circuit

Describe scaling of MOSFETS Describe briefly some of the methods to

implement scaling.

EVOLUTION OF INTEGRATED CIRCUIT

Invented by Robert Noyce in 1960 Developed the chip using a 10 mm

silicon wafer

MINIMUM FEATURE SIZE The demand in IC industry :

Increase its speedReduced power dissipation per function Increased number of transistors and

functionReduced the cost of a chip pushes the

scaling down of a transistor feature size. Minimum feature size is the smallest size

that can be achieved for a transistor by reducing its gate length or interconnect linewidth.

MOORE’S LAW In 1965, Gordon Moore, pointed out that the

number of transistors on a chip doubled every 18 to 24 months.

He made a prediction that integrated circuit technology will doubled its effectiveness every 18 months.

INVENTION OF INTEGRATED CIRCUIT

The demand of having smaller and smaller feature size is very obvious when the IC technology moves from SSI to GSI.

Year 1947 1950 1961 1966 1971 1980 1990 2000

Techno-logy

Inventi-on of transis-tor

Discrete compon-ent

Small Scale Integra-tion (SSI)

Medium Scale Integra-tion

Large Scale Integra-tion (LSI)

Very Large Scale Integra-tion (VLSI)

Ultra Large Scale Integrat-ion (ULSI)

Giga /Giant Scale Integrat-ion (GSI)

Number of transis-tor per chip

1 1 Less than 30

30 - 100 100,000 1 million 40 million More than 40 million

Typical products

- Diode, Transis-tor

Logic gates, Flip-flop

Counter, Multiplex-er, Adder

Micropro-cessor 8 bit, ROM, RAM

Micropro-cessor 16 bit, and 32 bit, DRAM

Pentium 2 with 300 MHz

Micropro-cessor with speed 10 GHz

SCALING OF MOSFETS Minimum feature size of transistor is the smallest size of IC

chip that is its gate length or interconnect line width of an IC. Minimum feature size is measured in micrometers or microns

for example 0.18 mm in year 2000

In year 2008 the measurement is in nanometer that is the introduction of 45 nm technology due to considerable shrinking and increased in number of transistors.

More innovations on IC technology with reduced dimension, improved leakage current to reduce power dissipation and more transistors can be integrated on a chip with less cost are in the roadmap with 32 nm, 22 nm, 16 nm and 11 nm dimensions.

More advanced manufacturing or fabrication process is needed when the dimension of transistor had reached the atomic size.

SCALING PARAMETER The scaling parameter,ε is the factor by

which transistor dimensions are reduced, that is ε < 1.

The gate length, LG is εLG and the gate width, Z is εZ for the scaling down the dimensions of a transistor.

SCALING PARAMETER Shorter gate length and smaller gate

thickness give higher transconductance, gm. Smaller gate width reduces input

capacitance. Line width (gate length) shrunk on a two to

three year cycle; in 2002 the line width was 0.13 mm to 0.18 mm and the die size was 2 cm2.

TYPE OF SCALING Constant voltage scaling & constant field scaling

Constant voltage scaling lateral dimensions are scaled without reducing the power supply

voltage. The disadvantage - the electric field increases as the minimum

feature length is reduced. This results to mobility degradation, velocity saturation, lower breakdown voltages and increased leakage currents.

Constant field scaling, The lateral dimensions, length and width of the channel (LG, Z),

the perpendicular dimension, oxide thickness (dox) and the operating voltages (VDS, VGS, Vth) of the MOSFETs are scaled and thus are reduced by a factor ε.

constant field scaling results in reduction of power delay product but it requires a reduction in the power supply voltage.

Therefore voltage scaling method is the preferred approach.

EFFECTS OF SCALING ON MOSFET DEVICE PARAMETER WITH SCALING

FACTOR

EFFECTS OF SCALING ON MOSFET DEVICE PARAMETER WITH SCALING

FACTOR

Majority of these parameters reduced by a factor or .

Substrate doping increased by a factor to reduce depletion widths to prevent punch-through breakdown.

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