Computer Organization and Architecture

By

Renjith V RaviAssistant Professor,

Dept of ECE

INSTRUCTION SETS

INSTRUCTIN FORMATSThe purpose of an instruction is to specify both - an operation to be carried out by a CPU or

other processor and - the set of operands or data to be used in the

operation. The operands include the input data or

arguments of the operation and the results that are produced.

Most instructions specify a register-transfer operation of the form

X1 :=op{X1,X2,...,Xn)

INSTRUCTIN FORMATSIn assembly language it is

Op X1,X2,…..XnEg : Mov A,B Where op is called the opcode or operation code. X1,X2,…Xn are addresses

Source operand address

Destination operand address

An address Xi represents a

-register in a register addressing mode. MOVE D2,D1

-memory location in a direct addressing mode

-value in immediate addressing mode. MOVE #99,D1

One address InstructionThe one address instruction can be

represented symbolically as ADD B

In the above instruction the second operand is implicitly in a unique location.

The general format is

Operation Source address

Two address InstructionThe two address instruction can be

represented symbolically as ADD A,B

In the above instruction A is the source operand and. B is the destination operand

The general format is

Opcode Source , Destination

Three address InstructionThe three address instruction can

be represented symbolically as ADD A,B,C

In the above instruction A and B are the source operands . C is the destination operand

The general format is

Operation Source 1,source 2, Destination

RISC and CISC

Based on the number of instructions, a computer is classified into

RISC - Reduced instruction set computer.

CISC - Complexed instruction set computer

RISC Vs CISC

ADDRESSING MODESThe way in which an operand is specified in an instruction

Or the way in which the processor can access the data

Let X be an operand and V(x) is its value

Let X is reg. B and V(B) =2 then

This value can be specified in different ways such as

Immediate mode

Direct mode

Indirect mode

Register mode

Register Mode – The operand is the contents of the processor register. The name of the register is specified in the instruction.

Immediate mode

Absolute mode or direct mode

Indirect mode

Register Indirect modeThe effective address of the operand is

the contents of a register or the main memory location whose address is given explicitly in the instruction

EA = R

Eg : MOVE A,(R0)

The above instruction copies the contents of memory addressed by the contents of register R0 into register A

Index Addressing Mode The effective address of the operand is

generated by adding a constant value(specified in the instruction) called offset to the contents of register.

EA = offset + R

Eg : MOVE 20[R1],R2

The above instruction loads the contents of register R2 into the memory location whose address is calculated by addition of the contents of register R1 and constant value(offset or displacement) 20

Relative addressing mode

The effective address is determined by the index mode using program counter in place of the general purpose processor register.

EA = PC + Address part of instruction.

This addressing mode is commonly used to specify the target address in branch instructions.

Eg: JNZ BACK

Auto Increment mode The effective address of the operand is the contents

of a register specified in the instruction.

After accessing the operand the contents of this register are incremented to address the next location.

Eg : MOVE (R2),+ R0

The above instruction copies the contents of register R0 into the memory location whose address is specified by the contents of register R2.

After copy operation , the contents of register R2 is automatically incremented by 1.

Auto decrement mode The contents of a register specified in the

instruction are decremented and then they are used as an effective address to access a memory location

Eg : MOVE R1,-(R0)

This instruction, initially decrements the contents of register R0 and then the decremented contents of register R0 are used to address the memory location.

Finally, the contents from the addressed memory location are copied into the register R1

PROGRAMMING CONSIDERATIONS

Most of the computer programming is now done using C or assembly language and translated(compiled) into machine language.

Assembly language programs are in the general form of

Opcode operand1, operand 2,…….,operand n

machine-language version of the instruction for the Motorola 680X0 microprocessor series

"Load the (immediate) decimal operand 2001 into address register A0,has the 32-bit binary format MOVE.L #2001,A0

00100000 01111000 00000111 11010001

It may also be written more compactly in hexadecimal code thus:

2078 07D1

PROGRAMMING CONSIDERATIONS

The assembly language version of the above instruction is

MOVE.L #2001,A0

MOVE.L #$07D1,A0

# indicates immediate value

$ indicates Hexadecimal numb

Here

Assembler – converts the high level language program into machine language program

Assembler DirectivesAssembly language uses some symbolic names,

which does not translate into executable instruction in machine language.

eg: A EQU 2001

tells A = 2001

Or it tells the assembler how to treat the symbol A

These type of non executable assembly language instructions are called assembler directives or pseudo instructions

Macro instruction or macro –

assigning a symbolic name to a sequence of instructions, permits these instructions to be treated as a single instruction

Datapath Design ALU

ALUsThe various circuits used to execute data-

processing instructions are usually combined in a single circuit called an arithmetic-logic unit or ALU.

The complexity of an ALU is determined by the way in which its arithmetic instructions are realize Simple ALUs that perform fixed-point addition and subtraction,

Word based logical operations, can be realized by combinational circuits.

ALUs that also perform multiplication and division can be constructed around the circuits developed for these operations in the preceding section.

Combinational ALUs

The simplest ALUs combine the functions of a twos-complement adder-subtracter with those of a circuit that generates word-based logic functions of the form f(X,Y), for example, AND, XOR, and NOT.

They can thus implement most of a CPU's fixed-point data-processing instructions.

Combinational ALUsThe specific operation to be performed by the desired subunit is determined by a select control line S.

The ALUs logical operations were performed bitwise.

Can perform maximum 16 logical operations

Can perform maximum 16 arithmetic operations

Sequential ALUs

Sequential ALUsIt is intended to implement multiplication and division using one of the sequential digit-by-digit shift-and-add/subtract algorithms.

Three one-word registers are used for operand storage: the accumulator AC, the multiplier-quotient register MQ. and the data register DR.

AC and MQ are organized as a single register AC.MQ capable of left- and right-shifting.

Sequential ALUsAdditional data processing is provided by a combinational ALU capable of addition, subtraction, and logical operations;

we will refer to this unit as the add-subtract unit.

This unit derives its inputs from AC and DR and places its results in AC.

The MQ register is so-called because it stores the multiplier during multiplication and the quotient during division.

Sequential ALUsDR stores the multiplicand or divisor,

The result (product or quotient and remainder) is stored in the register-pair AC.MQ.

CONTROL UNIT DESIGN

CONTROL UNIT DESIGN

Two general approaches

1. Hardwired control

2. Micro programmed control

Hardwired control Views the controller as a

sequential logic circuit or finite state machine that generates specific sequences of control signals in response to externally supplied instructions.

It is designed with the usual goals of minimizing the number of components used

And maximizing the speed of operation.

Once the unit is constructed, the only way to implement the changes in control unit behavior is by redesigning the entire unit.

Hardwired control

Hardwired controlThe instruction decoder decodes the instruction loaded in the IR. If IR is an 8-bit register then instruction decoder generates 2^8 , i.e. 256 lines; one for each instruction.

According to code in the IR, only one line amongst all output lines of decoder goes high i.e., set to 1 and all other lines are set to 0.

The step decoder provides a separate signal line for each step, or time slot, in a control sequence.

Hardwired controlThe encoder gets in the input from instruction decoder, step decoder, external inputs and condition codes.

It uses all these inputs to generate the individual control signals.

After execution of each instruction end signal is generated which resets control step counter and make it ready for generation of control step for next instruction.

The encoder circuit implements the following logic function to generate Yin.

Yin = T1 + T5 • ADD + T4 • BRANCH + ...

As another example, the logic function to generate Zout signal can given by,

Zout = T2 + T7 . ADD + T6 BRANCH + .....

Microprogramming

Microprogramming [Lynch 1993] is a method of control-unit design

The control signal selection and sequencing information is stored in a ROM or RAM called a control memory CM.

The control signals to be activated at any time are specified by a microinstruction, which is fetched from CM in much the same way an instruction is fetched from main memory.

Each microinstruction also explicitly or implicitly specifies the next microinstruction to be used, thereby providing the necessary information for micro operation sequencing.

A set of related microinstructions forms a microprogram.

Micro programs can be changed relatively easily by changing the contents of CM;

hence microprogramming yields control units that are more flexible than their hardwired counterparts.

Micro programmed control unit

It is built around a storage unit called a control memory, where all the control signals are stored.

Micro programmed control unit

The control memory stores a set of micro programs designed to implement or emulate the behavior of the given instruction set.

Each instruction causes the corresponding micro program to be fetched and

Its control information extracted in a manner that resembles the fetching and execution of a program from the computer's main memory.

Microinstruction format and control unit organization.

Microinstruction format A condition-select field

specifies the external condition to be tested in the case of conditional branch microinstructions.

An address field contains the next-address field to be used when a branch condi tion is satisfied.

A micro program counter (µPC provides the next microinstruction address when no branching is needed.

The rest of the microinstruction specifies in encoded or unencoded format the control signals that are activated to perform the desired micro operations.

Micro programmed control unit organization.

The counter µPC is the address register for the control memory CM.

The contents of the addressed word in CM are transferred to the microinstruction register µIR

The control fields are decoded if necessary and produce control signals for the data processing unit; µPC is then incremented.

If a branch is specified by the microinstruction in µIR, the contents of the microinstruction's address field are loaded into µPC