SAS3 Transmitter/Receiver testing

Application engineer of Tektronix China.

Bright Zeng

What Happens in an Internet Minute?

Source: Intel Newsroom

Need for Speed

Increased bandwidth not enough, need lower latency

Traditional SATA/SAS storage replaced by PCIe storage

– AHCI -> NVME

Emerging form factors -> SFF-8639, M.2, NVDIMM

Source: IDC WW SSD 2014-2018 Forecast

SATA 3.2 Specification

SATA Express:

– Includes both SATA and PCIe signaling

– Hosts supports both SATA or PCIe storage device.

– With PCIe transfer rates of up to 2 GB/s (2 lanes of PCIe 3.0), compared with

today’s SATA technology at 0.6 GB/s.

M.2:– SATA revision 3.2 also incorporates the M.2 form factor, enabling small form-

factor M.2 SATA SSDs suitable for thin devices such as tablets and notebooks.

Additional features of the SATA-IO Revision 3.2 Specification include:

– microSSD–standard for embedded solid state drives (SSDs) that enables

developers to produce single-chip SATA implementations for embedded storage

applications.

– Universal Storage Module (USM)– enables removable and expandable storage for

consumer electronic devices. SATA revision 3.2 introduces USM Slim, which

reduces module thickness, allowing smaller removable storage solutions.

– DevSleep– the lowest level of power management yet, where the drive is almost

completely shut down, meeting the requirements of new always on, always

connected mobile devices such as Ultrabooks™.

NVM Express

Host controller interface utilizing PCI Express

– Introduced March 2011

– Latest 1.2 spec released November 2014

Key features:

– Optimized for low latency – over 50% less overhead than SATA/SAS

– High performance, scalable with multi-lane data transfer

– Security, encryption and error handling capabilities

– Low power with power management states

Non-Volatile DIMM

Complementary memory tier to flash/SSD

Higher scalability

Speed/latency/endurance of DRAM with the persistence of flash

NVDIMM Target applications:

– Write caching

– Metadata storage

– Online transaction processing

– Other low latency applications

Standardization in progress

– JEDEC/DDR4 (Hybrid Memory Task Group)

– NVDIMM Special Interest Group

Server Memory – DDR4 (new solutions – in progress)

DRAM DRAM DRAM DRAMRCDFlash

DRAM DRAM DRAM DRAMRCDFlash

RCDFlash Flash Flash Flash Flash Flash Flash FlashNVDIMM-F

NVDIMM-P

NVDIMM-N

RCD – Register Clock Driver

N – Equal Flash/DRAM

P- Flash > DRAM

F – Flash

Flash Flash

Flash Flash Flash

FlashFlashFlash

Storage Timeline

Today

2012 2013

6G Deployment Phase

Commercial Gen3

product deployment

24 Gb/sSilicon Phase

2014 2015 2016

8G (Spec 3.2) SATA-Express Deployment Phase

IOL SAS (12)

Interop

12 Gb/sDeployment Phase

SATA 3.2(8/2013)

SAS-3 Rev 06 (11/2013)

NVME 1.2 (11/2014)

2017

SAS-3 Spec

NVME 1.1

NVME Plugfest#1

NVME Plugfest#2

NVME 1.2

NVME Plugfest#2

24 Gb/sDeployment Phase

12 Gb/sSilicon Phase

IOL SAS (12)

InteropIOL SAS (12)

Interop

SAS 12G+ Design Problem:1000mV, FFE, Crosstalk, DFE, 50mV

Crosstalk and signal loss problems are the largest design challenge today.

Significant advances in high tap count Decision Feedback Equalization are key to operating at 12G+.

12 Gb/s SAS Transmitter Measurements

Group 1 – OOB Signaling5.1.1 Maximum Noise During OOB Idle

5.1.2 OOB Burst Amplitude

5.1.3 OOB Offset Delta

5.1.4 OOB Common Mode Delta

Group 2 – Spread Spectrum Clocking (SSC) Requirements5.2.1 SSC Modulation Type

5.2.2 SSC Modulation Frequency

5.2.3 SSC Modulation Deviation

5.2.4 SSC Balance

5.2.5 SSC DFDT

Group 3 – NRZ Data Signaling Requirements5.3.1 Physical Link Rate Long Term Stability

5.3.2 Common Mode RMS Voltage Limit

5.3.3 Common Mode Spectrum

5.3.4 Peak to Peak Voltage

5.3.5 Voltage Modulation Amplitude (VMA)

5.3.6 Equalization

5.3.7 Rise Time

5.3.8 Fall Time

5.3.9 Random Jitter (RJ)

5.3.10 Total Jitter (TJ)

5.3.11 Waveform Distortion Penalty (WDP)

5.3.12 SAS3_EYEOPENING

5.3.13 Pre Cursor Equalization Ratio

5.3.14 Post Cursor Equalization Ratio

5.3.15 Transition Bit Voltage PK-PK (VHL)

5.3.16 Unit Interval

OOB Amplitude/Timing

Common Mode Spectrum

Transmitter Equalization

VMA(Voltage modulation amplitude)

Pre/Post cursor equalization ratio

Pre-cursor =( V1/V2) Post-Cursor= (V3/V2) VMA=V2-V5

Eye Opening

SAS3_EYEOPENING* Measurement for analysis of ISI and crosstalk effects

Provides measure of relative vertical eye opening after reference equalization

Recommended patterns: IDLE, higher order PRBS, CJTPAT*

*Note, this measurement is similar to the SAS-2 Waveform Distortion Penalty (WDP) measurement but also includes Tx

EQ in addition to DFE. The code was provided and distributed through the T10 Technical Committee and permission has

been granted for Tektronix to reuse.

Source: 12-244r3

Tx Waveform Distortion Penalty (WDP)

1.Computing WDP with all influenced source including DCD,BUJ,ISI

2.Capture SCRAMBLED_0 pattern

A Note about SAS Test Points

IT

ER

ET

IR

Tekexpress SAS TX automation software/Fixture

Bandwidth recommendation for TX measurement

System testing:≥20GHz at least; 23/25GHz is better

Silicon validation ≥33GHz

Power spectrum:6GHz -24dBm;18GHz:-43dBm;30GHz:-60dBm

SAS 12Gbps CJPAT pattern:

Difference between Transmitter and Receiver testing

Transmitter testing:

1. Signal quality such as eye,jitter,amplitude of TX

2. Pre-shoot/De-emphasis(Tx equalization)

3. PCB/connector loss

Receiver testing:

1. CDR of receiver side in the chip.

2. Decision circuit

3. Equalization capability

4. Buffer and processing speed for encode/decode

5. Channel Loss

What is Receiver testing? Need a Bert!

Device Under Test

(DUT)

From Stressed

Pattern Generator

To Error Detector

loopback

Pattern Generator (with optional Stress)

sends bits, e.g. a PRBS pattern

Bits come back from DUT to Error Detector

and compared to expected pattern for Bit

Error Ratio (BER) measurement.

1

2

BER measurements

also used for scope-like

analysis

3

A Typical Receiver Test Setup

A Combination BERT and Scope for Computer Bus and Communications

Serial Data Applications

Theory of Receiver testing

Equalization

Error Detector

Receiver jitter tolerance test

Testing FIFO(Bert need to filter Align or Skip symbol)

SAS 12 Gb/s Rx Test Setup

Similar to SAS 6 Gb/s Rx configuration

Rx calibration -> CJTPAT -> BER test

Tektronix Method of Implementation (MOI) provides complete Rx Test

procedure

SAS 12 Gb/s Rx MOI

Source: sas3r06

Calibration process-AC/DC

1.AC/DC Amplitude: ensure the initial high-frequency and low-frequency

amplitudes are equalized.

Using 64 1’s_64 0’s_64 10’s pattern

Calibration process-Lunch amplitude

2.Lunch Amplitude : target minimum peak-to-peak amplitude of 850mVpp.

Calibration process-De-emphasis/pre-shoot

Adjust the preset: De-emphasis target is -10.9dB +/- 2dB. Pre-shoot

meets target of 8dB +/- 2dB.

De-emphasis

Pre-shoot

Calibration process-Rj

Adjust the Rj using 0101 pattern:Tartet: 16.5%UI

Calibration process-Sj

Adjust the Sj using 0101 pattern:

SJ@ 111KHz: 34UI

SJ@ 2.06MHz:0.10UI

SJ@ 15MHz: 0.10UI

Calibration process-eye opening

Calibrate SAS3_Eye Opening using CJT pattern or PRBS pattern:

Target Eye Opening: 63 – 73%.

Calibration process-cross talk

Max 15-20mVpp

amplitude.

GRL Company Confidential 31

GRL Framework: SAS12G: Calibration selection

SAS 12G Rx Equipment

DUT

Crosstalk

2XTest Fixture

ISI

RX TX

Enable DUT to Loop back mode

SAS chip vendor can provide the

utility/tools to enable the chip into

loopback mode

SAS12G: Test setup for Jitter Tolerance for SJ sweep

GRL Company Confidential 33

User can select

“Compliance+ fixed

margin”

User can configure

Search/Margin mode for

Receiver margin testing

Analog Design and Characteristics of Error detector

23+ GHz analog bandwidth

Indium Phosphate Technology

2 1 bit ADCs working in parallel

Sampling clock at full data rate!

Trouble shooting and debug capability of Bertscope

Jitter and eye diagram analysis using Bertscope：The Bandwidth of the error detector input >23GHz

1.Bertscope can really measure the Tj@10^-12.

2.Bertscope can separate the Sj/Rj/DDj.

3.Bertscope with CDR can get the jitter spectrum.

Trouble shooting and debug capability of BERT

4.Bertscope can use two ADC sample the data accurately, scan eye

diagram with very fast speed. Also support mask testing with build in

mask.

5.Bertscope can draw BER contour in 3D and 360 degree.

Bit error analysis capability

1.Pattern sensitivity can locate the error bit in PRBS pattern.

2.Strip chart can track when and where the error happen during

long time.

Pattern sensitivity Strip chart

Bit error analysis capability

3. Bertscope can find the rule when and where the error bit happen

and help to identify the root cause of the error.

4.FEC emulation can emulate the BER after FEC comparing to

before FEC.

Error free interval FEC emulation

Summary

1.TX solution

• Real time scope BW≥20GHz

• Tekexpress SAS12G TX software

2.RX solution

• Bertscope ≥12.5Gbps

• DPP/LE for emphasis

• ISI board/BSAITS125

• CDR

• Other cable and accessories

• RX automation software from GRL

• Contact Tektronix office for detail

Q&A

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