SAMTEC TERASPEED SYSTEM DESIGN CAPABILITIES FINAL · 2018. 11. 19. · Ansys HFSS (Full Wave 3D...

SAMTEC TERASPEED SYSTEM DESIGN CAPABILITIESFINAL

June 14, 2016Scott McMorrow

Samtec Proprietary Information

ADVANCED SIGNAL INTEGRITY SERVICES (SIG) PLUS TERASPEED® CONSULTING (TC)

SIG Product Focus:• Design, development, and

characterization of connectors, and cable systems.

• Application Specific Product Design

• Signal integrity

• Electromagnetic modeling/EMI/EMC

• Application Notes / White Papers

• Corporate Component R&D

TC System Focus:

• Design, development, and characterization of Systems, cable systems, and custom products.

• System product design

• Signal and power integrity

• Electromagnetic modeling

• SI/PI training / System White Papers

• Corporate System R & D

• Advanced semiconductor packaging design and analysis

SIG TC

SIG and TC work together with complimentary skill sets to provide Samtec solutions from Silicon-to-Silicon

+


COMPUTATIONAL ELECTROMAGNETICS BACKED BY MEASUREMENT VERIFICATION

• Ansys HFSS (Full Wave 3D Finite Element Method)• Ansys Siwave (Full wave hybrid planar substrate solver)• CST Microwave Studio (Full Wave 3D Finite Integration Technique)• Matlab simulation and post processing environment• Massive S-parameter compute capability• Multi-processor High Performance Computing Environment (HPC)• Measurement confirmation of modeled properties using time and

frequency domain measurement techniques to 67 GHZ bandwidth.


PACKAGE SUBSTRATE CASE STUDY


NOVEL DIFFERENTIAL SERDES PACKAGE DESIGN CELL

• Package trace to ball transitions no longer performance limit

• Transition BW > 70 GHz

• Enables 56 G / 112 G NRZ

• 56G / 112 G PAM4

• GZ-41 material

• Conventional 6-2-6 organic 1 mm BGA


INSERTION LOSS AND RETURN LOSS WELL-BEHAVED TO 60 GHZ BANDWIDTH

Return loss well-behaved to 60 GHz

-3 dB @ 69 GHz


PRBS 21 EYE OF 10 MM PACKAGE TRACE WITH VIA/BALL TRANSITION TO PCB100 FF DIE CAP ON EACH OUTPUT @ 64 GBPS NRZ


DESIGN APPLIED TO A REAL14-LAYER 40 GBPS ORGANIC GZ-41 PACKAGE

-3 dB Insertion Loss @ 50GHz


OUTPUT EYE WITH EQUALIZATION56 GBPS NRZ


Ansys Nexxim simulation

OUTPUT EYE WITH 3 TAP FFE EQUALIZATION112 GBPS NRZ


Ansys Nexxim simulation100 Ohm Driver model

100 Ohm Receiver

0

0

25fF

C1122

25fF

C112350

R1124

50

R1125

E1126

100

R1127

FC=$besselFC

FC=$besselFC

ID=1130

ID=1131ID=1133

100

R1134Port1Port2

Port3Port4

TRANSITION CELL

• Samtec/Teraspeed Technology• Has been incorporated into 2 package designs thus far• Validates a path to 56G and 112G NRZ signaling• Validates a path to 112G PAM4 signaling.


COBO SYSTEM ANALYSIS CASE STUDY


COBO DIRECT CABLE ARCHITECTUREORIGINAL CONCEPT DRAWING

UEC5-X4-G2 ExaMax C2C

UEC5-X4-G2 ExaMax C2C

28 Gauge 92 Ohm

30 Gauge 100 Ohm

30 Gauge 100 Ohm


FIREFLY UEC5-G2 FLYOVER SYSTEM


UEC5-X4-G2 STEPPED CABLE TRANSITION

TS-70GHz-50ohms-UEC5G2-X4-30100FQSFP-Stripline-EdgeCard.s32p


EXAMAX C2C DIRECT MATE MODEL


8 mm

21. 4mm

14.3 mm

20.7 mm

SYSTEM MODELING TOPOLOGY

IC

DualUEC5

300mm 30 Gauge 100 ohm

ExaMax C2C

Trace1.5” Meg692 Ohm

IC

300mm 30 Gauge 100 ohm

ExaMax C2C

Trace1.5” Meg692 Ohm

0.5 to 3 meter28 Gauge 92 ohm

DualUEC5


DIFFERENTIAL PORT MAPPING ( 1 VICTIM, 16 AGGR)ICR = 16.2 DB @ 25 GHZ

Tx5 Tx6 Tx7 Tx8Tx1 Tx2 Tx3 Tx4

Rx5 Rx6 Rx7 Rx8Rx1 Rx2 Rx3 Rx3

Rx5 R

x6 Rx7 R

x8

Rx1 R

x2 Rx3 R

x4

Tx5 T

x6 Tx7 T

x8

Tx1 T

x2 Tx3 T

x4

UEC5 UEC5

ExaMax C2C

FEXT only XTK

Only 1 NEXT Aggressor

Best design practice for 56G NRZ / 112G PAM4 is to place Tx and Rx pairs in separate UEC5 connectors,

allocating channels with 8 Tx and 8 Rx wafers in

Examax assembly.


DIFFERENTIAL INSERTION LOSS2 METER BACKPLANE (TOTAL PATH LENGTH = 2.675 METERS


DIFFERENTIAL RETURN LOSS2 METER BACKPLANE


DIFFERENTIAL PSXT2 METER BACKPLANE


CASE 4 - 2 METER BACKPLANEECU5G2_EXAMAXC2C_ECU5G2__STDORDER_50MHZ_4.S64P

-25.7 dB IL20.1 dB ICR


56G PAM2 TRANSCEIVER SUMMARYUSING IEEE COM STATISTICAL SYSTEM SIMULATION


56G PAM2 VOLTAGE BATHTUB CURVE2 METER BACKPLANE


56G NRZ PROBABILITY DENSITY EYE - BEFORE DFE2 METER BACKPLANE


56G PAM2 PROBABILITY DENSITY EYE - AFTER DFE2 METER BACKPLANE


56G PAM4 TRANSCEIVER SUMMARY


56G PAM4 VOLTAGE BATHTUB CURVE (PRE-FEC)2 METER BACKPLANE WITH 1 VICTIM / 15 AGGRESSORS


56G PAM4 PROBABILITY DENSITY EYE - BEFORE DFE2 METER BACKPLANE WITH 1 VICTIM / 15 AGGRESSORS


56G PAM4 PROBABILITY DENSITY EYE - AFTER DFE2 METER BACKPLANE WITH 1 VICTIM / 15 AGGRESSORS


56G PAM4 TRANSCEIVER SUMMARY


56G PAM4 VOLTAGE BATHTUB CURVE (PRE-FEC)2 METER BACKPLANE WITH 1 VICTIM / 15 AGGRESSORS


10-4 BER is the IEEE Limit for

application of FEC

112G PAM4 PROBABILITY DENSITY EYE - AFTER DFE2 METER BACKPLANE WITH 1 VICTIM / 15 AGGRESSORS


ADDITIONAL CONFIRMATION

• 112 Gbps PAM4 silicon partner simulations have been performed on projected SERDES device model

• Resulting performance of 6.6 e-7 BER without FEC and without full signal processing optimization. (1 e-4 BER is the target for FEC)

• Silicon vendor’s results have validated our direction in cable-to-cable twin-ax interconnect architecture development

• These new system Engineering R&D efforts, when combined with Samtec Optical Group’s capabilities, demonstrate design and performance leadership for the future.


SAMTEC TERASPEED SYSTEM DESIGN CAPABILITIES FINAL · 2018. 11. 19. · Ansys HFSS (Full Wave 3D...

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