Samsung Poland R&D Center 2009.09.18

18
Samsung Poland R&D Center 2009.09.18

description

Samsung SoCs Multimedia Capabilities. Samsung Poland R&D Center 2009.09.18. Version History. Contents. 1. Samsung System on Chip products. 2. Samsung S5PC110 SoC multimedia capabilities. 3. Samsung S5PC110 - Display pipelines. 4. Samsung S5PC110 – Multimedia Use Cases. 5. - PowerPoint PPT Presentation

Transcript of Samsung Poland R&D Center 2009.09.18

Page 1: Samsung Poland R&D Center 2009.09.18

Samsung Poland R&D Center2009.09.18

Page 2: Samsung Poland R&D Center 2009.09.18

2© Samsung Electronics Co., LTD S/W Platform Team |

Ver. Date Description Author Reviewer

0.1 2009/09/18

Initial Version Marek Szyprowski

Page 3: Samsung Poland R&D Center 2009.09.18

3© Samsung Electronics Co., LTD S/W Platform Team |

Samsung System on Chip products1

2

3

4

5

6

7

8

Samsung S5PC110 SoC multimedia capabilities

Samsung S5PC110 - Display pipelines

Samsung S5PC110 – Multimedia Use Cases

Samsung S3C6410 SoC multimedia capabilities

Samsung S5PC110 - Display pipelines

Samsung S3C6410 – Multimedia Use Cases

Summary

Page 4: Samsung Poland R&D Center 2009.09.18

4© Samsung Electronics Co., LTD S/W Platform Team |

S5PC100 and S5PC110

- latest Samsung System on Chip products

S3C6410

- mature Samsung SoC

- already well supported in Linux Kernel v2.6.29+

Common features:

- ARM CPU

- A bunch of integrated multimedia peripherals

- All multimedia IPs can access system memory directly.

- All multimedia IPs require buffers to be contiguous in physical

memory.

Page 5: Samsung Poland R&D Center 2009.09.18

5© Samsung Electronics Co., LTD S/W Platform Team |

CPU – ARM CortexA8 1GHz

Display Controller (5 independent windows with OSD/Blending)

TV Encoder with Mixer and HDMI output

FIMC x3 (unified camera interface, image scaler, rotator and color

space converter)

Multi Format Codec (MPEG1,2,4, H.263, H.264 encoder/decoder)

JPEG coder/encoder

3D accelerator

Page 6: Samsung Poland R&D Center 2009.09.18

6© Samsung Electronics Co., LTD S/W Platform Team |

Display Controller

Window 0

Window 1

Window 2

Window 3

Window 4

Camera A Camera B System Memory

FIMC 0

FIMC 2

FIMC 1

DM

A in

DM

A out

DM

A in

Simplified architecture of the main display pipeline

Page 7: Samsung Poland R&D Center 2009.09.18

7© Samsung Electronics Co., LTD S/W Platform Team |

TV Mixer

Background

Graphics 1

Graphics 2

Video

System Memory

Video Processor

DM

A in

DM

A in

Simplified architecture of the TV display pipeline

Page 8: Samsung Poland R&D Center 2009.09.18

8© Samsung Electronics Co., LTD S/W Platform Team |

Multiple input support:

- Camera A or Camera B interfaces (ITU-R BT 601/656/709 mode)

- DMA in from system memory

Multiple output support:

- DMA out to system memory

- Direct FIFO to Display Controller’s Window

Image scaler, mirror and rotation support

Color space conversion support

Direct FIFO to Display Controller heavily reduces system

memory throughput (800x480x32bits/pixel @ 70 fps

consumes about 100MB/s)

Page 9: Samsung Poland R&D Center 2009.09.18

9© Samsung Electronics Co., LTD S/W Platform Team |

FIMC 0

Scaling to OSD window size

Camera A

YUV frame(s)

FIMC 1

Scaling to target size, color space conversion

Display Controller

Window 0OSD

System Memory

Recording a movie from camera with live preview in OSD

Window

Page 10: Samsung Poland R&D Center 2009.09.18

10© Samsung Electronics Co., LTD S/W Platform Team |

FIMC 0

Scaling to OSD window size

Display Controller

Window 0OSD input

System Memory

YUV frame(s)

Decoding and displaying a movie (i.e. H264)

Multi Format Codec

H264 decoder mode

System Memory

H246 frame(s)

Page 11: Samsung Poland R&D Center 2009.09.18

11© Samsung Electronics Co., LTD S/W Platform Team |

FIMC 0

Scaling to target picture

size

System Memory

YUV frame

One Shot operations (hardware accelerated image

manipulation in system memory)

JPEG accelerator

encoder mode

System Memory

RGB frame

System Memory

JPEG image

Page 12: Samsung Poland R&D Center 2009.09.18

12© Samsung Electronics Co., LTD S/W Platform Team |

CPU - ARM1176JZF-S 533MHz

Display Controller (5 independent windows with OSD/Blending)

Camera Interface (2 separate paths, image scaler and color space

converter)

Post Processor and TV Scaler (image scaler and color space

converter)

Image Rotator

Multi Format Codec (MPEG2, MEPEG-4, DivX, H.263, H.264

encoder/decoder)

JPEG coder/encoder

3D accelerator

2D accelerator

Page 13: Samsung Poland R&D Center 2009.09.18

13© Samsung Electronics Co., LTD S/W Platform Team |

Display Controller

Window 0

Window 1

Window 2

Window 3

Window 4

Camera A System Memory

Post Processor

CameraIF (codec)

CameraIF (preview)

DM

A in

DM

A out

DM

A in

Simplified architecture of the main display pipeline

TV Scaler

Page 14: Samsung Poland R&D Center 2009.09.18

14© Samsung Electronics Co., LTD S/W Platform Team |

Camera IF(preview)

Scaling to OSD window size

Camera A

YUV frame(s)

Camera IF(codec)

Scaling to target size, color space conversion

Display Controller

Window 0OSD

System Memory

Recording a movie from camera with live preview in OSD

Window

Page 15: Samsung Poland R&D Center 2009.09.18

15© Samsung Electronics Co., LTD S/W Platform Team |

Post Processor

Scaling to OSD window size

Display Controller

Window 0OSD input

System Memory

YUV frame(s)

Decoding and displaying a movie with rotation (i.e. H264)

Multi Format Codec

H264 decoder mode

System Memory

H246 frame(s)

System Memory

rotatedYUV

frame(s)

Image Rotator

Page 16: Samsung Poland R&D Center 2009.09.18

16© Samsung Electronics Co., LTD S/W Platform Team |

Post Processor

Scaling to target picture

size

System Memory

YUV frame

One Shot operations (hardware accelerated image

manipulation in system memory)

JPEG accelerator

encoder mode

System Memory

RGB frame

System Memory

JPEG image

Page 17: Samsung Poland R&D Center 2009.09.18

17© Samsung Electronics Co., LTD S/W Platform Team |

Samsung SoCs also have multimedia accelerators that work

in transactional mode:

- DMA input, processing, DMA output

- Some of them (like 2D accelerator/blitter or 3D engine) does not fit well

into Video4Linux framework

All multimedia devices require buffers that are contiguous in

physical memory

- Buffer Manager is required

- Buffer Manager should not be tied only to Video4Linux devices

- Memory fragmentation issues

No dedicated video memory bus in Samsung SoCs, all video

data is pipelined through system memory

Page 18: Samsung Poland R&D Center 2009.09.18