University of Saskatchewan 2-1 EE 392 Electrical Engineering Laboratory III

Sampling and Quantization

Objectives: To investigate PAM sampling and to observe the effects of sampling and quantization and to measure output quality in terms of signal to noise ratio (SNR) for PCM systems.

Equipment: You will require a PAM module for the first part and a PCM module for the second part. You will also require a filter module The modules are available from the technicians in 2C94.

Reference: Virtual experiment found at http://www.engr.usask.ca/classes/EE/352/

Procedure: Sampling—Pulse Amplitude Modulation

1. Obtain a PAM sampling module (Figure 1) from the technicians and set up the sampling

Safety

The voltages used in this experiment are less than 15 V and normally do not present a risk of shock. However, you should always follow safe procedures when working on any electronic circuit. Assemble or modify a circuit with the power off or disconnected. Don’t touch different nodes of a live circuit simultaneously, and don’t touch the circuit if any part of you is grounded. Don’t touch a circuit if you have a cut or sore that might come in contact with a live wire. Check the orientation of polarized capacitors before powering a circuit, and remember that capacitors can store charge after the power is turned off. Never remove a wire from an inductor while current is flowing through it. Components can become hot if a fault develops or even during normal operation so use appropriate caution when touching components.

Fig. 1 Sampling Module

University of Saskatchewan 2-2 EE 392 Electrical Engineering Laboratory III

circuit of Figure 2. Use a pulse generator to generate a gating signal for the sampling module. Set the pulse voltage to TTL levels (0 V low to 4 V high). Attach a 3 kHz filter module to the output of the sampling module. You will use a signal generator for the input signal for most of the steps below. Limit the input signal to ±4 V; larger signals may damage the sampling gate chip.

The sampling module (Fig. 3) uses a 4066 CMOS switch, controlled by the gating pulse, to apply the input signal to either a 10K resistor or a 10 nF capacitor to ground, selected by switch S1. With the 10K resistor selected, the output voltage will follow the input voltage so long as the 4066 switch is closed but will be pulled to ground through the 10K resistor when the 4066 switch is open. The result is natural sampling. With the 10 nF capacitor

50ohm

3 kHz LPFW (t)

+4 v 0 v

SamplingModule

+15 gnd -15

TTL clock

In Out

Fig. 2 Sampling Circuit

Fig. 3 PAM Sampling Module

University of Saskatchewan 2-3 EE 392 Electrical Engineering Laboratory III

selected, the input voltage charges the capacitor while the 4066 switch is closed and the voltage is maintained by the capacitor when the 4066 switch is open. The result is flat-top sampling provided the gate signal has a small duty cycle. A second 4066 switch allows the capacitor to be discharged before the next sample resulting in less than 100% width flat-top sampling. The timing is controlled by a PIC microcontroller; the % width of flat-top sampling is set by the dip switch. The TL082 voltage follower prevents loading of the sampling circuit by the device connected to the output.

2. Set the sampling pulse to 100 µs period (10 kHz) and 25% duty cycle. Apply 2 V DC to the input and confirm that the sampling gate is operating correctly. Use the 10K load resistor to produce natural sampling, and check the result with both an oscilloscope and a spectrum analyzer. Measure the spectrum and confirm that it agrees with theory.

3. Apply a 4

!

Vpp sinusoid at 2 kHz to the sampling circuit input. Display the input signal,

the sampled signal and the filter output signal on the oscilloscope and spectrum analyzer. Measure the spectrum and confirm that it agrees with theory.

4. Investigate how the sampled signal’s spectrum and the filtered output wave form changes as

a) the input signal frequency

!

fm is increased b) the pulse duty cycle is increased c) the sampling frequency

!

fs is altered d)

!

fm is increased up to twice

!

fs

5. Generate an approximation to flat-top sampling by using the 10 nF capacitor in place of the 10K load resistor and by reducing the duty cycle of the gating pulses as much as possible; be sure the sampling frequency is 10 kHz. Start with 100% width flat-top sampling. Observe the sampled waveform on the oscilloscope and use the spectrum analyzer to observe baseband alias frequency components as the input signal frequency is increased up to and beyond

!

fs . Confirm that the relative gain follows the theoretical

!

sin x / x function part of which is shown in Figure 4. Switch to 50% and then 25% width flat-top sampling and measure the relative gain as a function of signal frequency.

52.50

0.7

0.8

0.9

1.0

Frequency in kHz

Rela

tive G

ain

Sampling Frequency

Fs = 10 kHz

100%

50%

25%

12%

Fig. 4 Signal Gain in Flat Top Sampling

University of Saskatchewan 2-4 EE 392 Electrical Engineering Laboratory III

Procedure: Quantization—Pulse Code Modulation

1. Obtain the PCM test module shown in Figure 5. The circuit uses a AD7575 8-bit A/D converter to digitize the input signal. Provide a 100 kHz TTL sampling clock to operate the converter. Apply a 1 kHz sine wave and adjust the amplitude to match the maximum input range of the A/D converter (about 6

!

Vpp ). The capacitive coupling and the resistor network

is used to shift the input voltage so that the voltage applied to the A/D converter is positive. If the input range of the A/D converter is exceeded your signal will be clipped, but if your signal is much less than the input range then the effective number of bits will be reduced. The module also includes two 8-bit DACs and switches that allow the bits to go to either the first or the second DAC. If n higher order bits are sent to the first DAC then its output will be the n-bit PCM signal. The second DAC receives the 8–n lower order bits, and its output approximates the error signal.

2. Using the setup of Figure 6 without the speaker or voltmeter, observe and sketch the quantized signal and the error signal. Observe the effect of using different numbers of bits of quantization. Reduce the sampling frequency to 20 kHz and measure the signal-to-noise ratio (SNR) in the sampled signal after the 3 kHz low-pass filter for different n bits of quantization (the expected change is 6 dB per bit).

3. Plot the 6 bit SNR as the signal level is reduced up to -20 dB relative to the maximum

+5V

+5V

+V

(LSB)

(MSB)

Vref (–)

VLC

COMP-V

DAC08

13

Io

4

15

2

1

16

3

–15V

+15V

14Vref (+)

Io

DAC #1TL072

+

-

TL072

+

-

13

2

76

5

5.1K

0.1µF

0.1µF

1K

1K

DAC REF

0.1µF

1K

12

11

10

9

8

7

6

5

47µF0.1µF

18

VDD

(LSB) D0

D1

D2

D3

D4

D5

(MSB) D7

D6

TP

RD

CSBUSY

AGND DGND

AIN

CLK

VREF

14

13

12

11

10

8

7

6

3

2

1

4

915

16

17

5

AD7575

1K

1K1K

INPUT

1µF

0.1µF

CA3140

+

–

63

2

+5V

74

DAC REF

47µFAD589

+

–

+5V

3.3K

4MHZCONVERSIONCLOCK

+5V

14

27pF

11

10

74121

ONE

SHOT

5

SAMPLECLOCK

3

4

7

6

10K

OUTPUT #1

+V

(LSB)

(MSB)

Vref (–)

VLC

COMP-V

DAC08

13

Io

4

15

12

11

10

9

8

7

6

2

1

16

3

–15V

5

+15V

14Vref (+)

Io

DAC #2

TL072

+

-

76

5

5.1K

TL072

+

-

13

2

0.1µF

0.1µF

1K

1K

DAC REF

0.1µF

1K

OUTPUT #2

Fig. 5 PCM A/D and D/A Circuit

University of Saskatchewan 2-5 EE 392 Electrical Engineering Laboratory III

signal. (Note that quantizing noise power should be constant except when overload occurs).

4. Increasing the sampling rate improves the SNR of a band-limited PCM system (i.e. a system with a low-pass filter on the output). Verify this experimentally by changing the sampling rate from 10 kHz to 80 kHz and measuring the SNR.

Fig. 6 PCM Measurement Setup