Sample Code (Simple) Run the following code on a pipelined datapath: add1 2 3 ; reg 3 = reg 1 + reg...
13
Sample Code (Simple) • Run the following code on a pipelined datapath: add 1 2 3 ; reg 3 = reg 1 + reg 2 nand 4 5 6 ; reg 6 = reg 4 & reg 5 lw 2 4 20 ; reg 4 = Mem[reg2+20] add 2 5 5 ; reg 5 = reg 2 + reg 5 sw 3 7 10 ; Mem[reg3+10] =reg 7
-
Upload
erin-hodges -
Category
Documents
-
view
219 -
download
6
Transcript of Sample Code (Simple) Run the following code on a pipelined datapath: add1 2 3 ; reg 3 = reg 1 + reg...
Sample Code (Simple)• Run the following code on a pipelined
datapath: add 1 2 3 ; reg 3 = reg 1 + reg 2
nand 4 5 6 ; reg 6 = reg 4 & reg 5
lw 2 4 20 ; reg 4 = Mem[reg2+20]
add 2 5 5 ; reg 5 = reg 2 + reg 5
sw 3 7 10 ; Mem[reg3+10] =reg 7
PC Instmem
Reg
iste
r fi
le
MUXA
LU
MUX
1
Datamemory
++
MUX
IF/ID
ID/EX
EX/Mem
Mem/WB
MUX
Bits 0-2
Bits 16-18
op
dest
offset
valB
valA
PC+1PC+1target
ALUresult
op
dest
valB
op
dest
ALUresult
mdata
eq?instru
ction
0
R2
R3
R4
R5
R1
R6
R0
R7
regA
regB
Bits 22-24
data
dest
PC Instmem
Reg
iste
r fi
le
MUXA
LU
MUX
1
Datamemory
++
MUX
IF/ID
ID/EX
EX/Mem
Mem/WB
MUX
Bits 0-2
Bits 16-18
noop
0
0
0
0
000
0
noop
0
0
noop
0
0
0
0
noop
912187
36
41
0
22
R2
R3
R4
R5
R1
R6
R0
R7
Bits 22-24
data
dest
InitialState
PC Instmem
Reg
iste
r fi
le
MUXA
LU
MUX
1
Datamemory
++
MUX
IF/ID
ID/EX
EX/Mem
Mem/WB
MUX
Bits 0-2
Bits 16-18
noop
0
0
0
0
010
0
noop
0
0
noop
0
0
0
0add
1 2 3
912187
36
41
0
22
R2
R3
R4
R5
R1
R6
R0
R7
Bits 22-24
data
dest
Fetch: add 1 2 3
add 1 2 3
Time: 1
PC Instmem
Reg
iste
r fi
le
MUXA
LU
MUX
1
Datamemory
++
MUX
IF/ID
ID/EX
EX/Mem
Mem/WB
MUX
Bits 0-2
Bits 16-18
add
3
3
9
36
120
0
noop
0
0
noop
0
0
0
0nan
d 4 5 6
912187
36
41
0
22
R2
R3
R4
R5
R1
R6
R0
R7
1
2
Bits 22-24
data
dest
Fetch: nand 4 5 6
nand 4 5 6 add 1 2 3
Time: 2
PC Instmem
Reg
iste
r fi
le
MUXA
LU
MUX
1
Datamemory
++
MUX
IF/ID
ID/EX
EX/Mem
Mem/WB
MUX
Bits 0-2
Bits 16-18
nand
6
6
7
18
234
45
add
3
9
noop
0
0
0
0lw 2 4 20
912187
36
41
0
22
R2
R3
R4
R5
R1
R6
R0
R7
4
5
Bits 22-24
data
dest
Fetch: lw 2 4 20
lw 2 4 20 nand 4 5 6 add 1 2 3
Time: 3
36
9
1
3
3
PC Instmem
Reg
iste
r fi
le
MUXA
LU
MUX
1
Datamemory
++
MUX
IF/ID
ID/EX
EX/Mem
Mem/WB
MUX
Bits 0-2
Bits 16-18
lw
4
20
18
9
348
-3
nand
6
7
add
3
45
0
0add
2 5 8
912187
36
41
0
22
R2
R3
R4
R5
R1
R6
R0
R7
2
4
Bits 22-24
data
dest
Fetch: add 2 5 5
add 2 5 5 lw 2 4 20 nand 4 5 6 add 1 2 3
Time: 4
18
7
2
6
6
45
3
PC Instmem
Reg
iste
r fi
le
MUXA
LU
MUX
1
Datamemory
++
MUX
IF/ID
ID/EX
EX/Mem
Mem/WB
MUX
Bits 0-2
Bits 16-18
add
5
5
7
9
4523
29
lw
4
18
nand
6
-3
0
0sw 3 7 10
945187
36
41
0
22
R2
R3
R4
R5
R1
R6
R0
R7
2
5
Bits 22-24
data
dest
Fetch: sw 3 7 10
sw 3 7 10 add 2 5 5 lw 2 4 20 nand 4 5 6 add
Time: 5
9
20
3
20
4
-3
6
45
3
PC Instmem
Reg
iste
r fi
le
MUXA
LU
MUX
1
Datamemory
++
MUX
IF/ID
ID/EX
EX/Mem
Mem/WB
MUX
Bits 0-2
Bits 16-18
sw
7
10
22
45
5 9
16
add
5
7
lw
4
29
99
0
945187
36
-3
0
22
R2
R3
R4
R5
R1
R6
R0
R7
3
7
Bits 22-24
data
dest
No moreinstructions
sw 3 7 10 add 2 5 5 lw 2 4 20 nand
Time: 6
9
7
4
5
5
29
4
-3
6
PC Instmem
Reg
iste
r fi
le
MUXA
LU
MUX
1
Datamemory
++
MUX
IF/ID
ID/EX
EX/Mem
Mem/WB
MUX
Bits 0-2
Bits 16-18
15
55
sw
7
22
add
5
16
0
0
945997
36
-3
0
22
R2
R3
R4
R5
R1
R6
R0
R7
Bits 22-24
data
dest
No moreinstructions
sw 3 7 10 add 2 5 5 lw
Time: 7
45
5
10
7
10
16
5
99
4
PC Instmem
Reg
iste
r fi
le
MUXA
LU
MUX
1
Datamemory
++
MUX
IF/ID
ID/EX
EX/Mem
Mem/WB
MUX
Bits 0-2
Bits 16-18
sw
7
55
0
9459916
36
-3
0
22
R2
R3
R4
R5
R1
R6
R0
R7
Bits 22-24
data
dest
No moreinstructions
sw 3 7 10 add
Time: 8
2255
22
16
5
PC Instmem
Reg
iste
r fi
le
MUXA
LU
MUX
1
Datamemory
++
MUX
IF/ID
ID/EX
EX/Mem
Mem/WB
MUX
Bits 0-2
Bits 16-18
9459916
36
-3
0
22
R2
R3
R4
R5
R1
R6
R0
R7
Bits 22-24
data
dest
No moreinstructions
sw
Time: 9
Time graphs
Time: 1 2 3 4 5 6 7 8 9
add
nand
lw
add
sw
fetch decode execute memory writeback
fetch decode execute memory writeback
fetch decode execute memory writeback
fetch decode execute memory writeback
fetch decode execute memory writeback
![IOTC-2010-S14-CoC17-Add1[E] -FLEET DEVELOPMENT PLANS](https://static.fdocuments.net/doc/165x107/6256a751b3b41667710c2012/iotc-2010-s14-coc17-add1e-fleet-development-plans.jpg)
![IOTC-2018-CoC15-10 Add1 Rev2 [E] COLLECTION OF DRIFTING ...](https://static.fdocuments.net/doc/165x107/61d14ed7aaa8bb3c7c29ee3c/iotc-2018-coc15-10-add1-rev2-e-collection-of-drifting-.jpg)
