s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu...
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8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 E E D D C C B B A A DESCRIPTION REV DATE PAGES PAGE DESCRIPTION 2 Title, Notes, Rev. History 1 3 4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 5 6 0.1 All INITIAL REVISION A RELEASE Block Diagram Stratix 10 SoC FPGA Development Kit Board Reset & Reconfiguration_CLK 26 27 28 29 PAGE DESCRIPTION 40 41 42 43 30 31 32 33 35 36 37 38 39 34 44 45 46 47 48 49 50 51 52 53 54 57 56 55 58 61 60 59 62 65 64 63 66 69 68 67 70 73 72 71 74 77 76 75 78 81 80 79 82 85 84 83 86 JTAG BLOCK Diagram Clock Block Diagram I2C BUS Block Diagram On Board USB BLASTER II 1 On Board USB BLASTER II 2 PCIe x16 Connector 10/100/1000 SGMII PHYA 10/100/1000 SGMII PHYB SDI Transmit/Receive S10 XCVR Banks - 4C/D/E/F SFP+ Port A HDMI (VIDEO ONLY) QSFP28 Interface 0&MXP QSFP28 Interface 1 FMC Port A S10 XCVR Banks - 4K/L/M/N S10 Banks - 2 A/B/C FMC Port B S10 Banks - 3 A/B/C S10 XCVR Banks - 1K/L/M/N S10 Banks - 2 F/L/M/N HPS HILO 72-bit 72-Bit Dual Rank SODIMM1 S10 Banks - 3 I/J/L/K S10 Banks - CFG & XCVR IO S10 Banks - HPS IO-48 CON User IO FPGA Mem Ref clock HILO 72-bit XCVR REF Clocks CLOCK CLEANER DB9RS232 I2C_MUX SystemMAX10 1 System MAX10 2 Flash Memory System MAX10 3 System MAX10 4 PDN Diagram Power Sequence MAX10 PWR Manager 1 MAINSwitch_12V_DC_12V 12Vto5V M12Vto3V3 3V3to2V5 240ACore_Phase2 240ACore_Contrller S10switch_12V_3V3 3V3toHILOHPSVDD 240ACore_Phase3 2.4V, 1.8Vand VTT Power VCCPT&VCCT VCCERAM&HPScore 3.3Vto1V2 VCCR S10 PWR S10 GND Decoupling 2 FMCSwitch_3V3 Decoupling 1 2V5_1V8Switch 3V3IOSwitch 3V3_1V8Discharge Load DC3V3currentsensors Videoclockgenerator MAX10 PWR Manager 2 S10 XCVR Banks - 1C/D/E/F 3V3to1V8 A.0 release All Power/SI/Mechanical Test Board Release A.1 release Add FGPA dedicated I2C port to Optical Module Move signal FALAP17 to FPGA clock input pin 25 21,22 Add Header to select USB blaster code 7 SWAP byte assignment of FGPA DDR ports. 25 Move signal FBLAP17 to FPGA clock input pin 28 C185 to 1uf 15 35 R851 value is changed to 17.4K. Wrong connection of C1614 27 Change C249 decoupling to VDD Add more Power test pins Change Memory IO connection for I J K L 28 10,11 Sepearte case gnd and signa gnd 10,11 Change R63, R87 to 4.7K 12 Update U13 Symbol 15 ADD U18 I2C Address 21 Fix Signal PN connections 22 Fix Signal PN connections, add dedicated I2C ports for clock cleaner and QSFP+ ports 25 Add dedicated I2C ports for Video and SFP ports 30 Change JTAG_RESET to DC Power good 31 Add pull down resistor 36 Change AC coupling cap from 4.7uf to 0.1uf 42 Fix Signal PN connections. Change J56 from 2-pin to 3-pin 46 Short A-GND to Signal GND Title Size Document Number Rev Date: Sheet of A1 Stratix 10 SoC FPGA Development Kit Board B 1 71 Tuesday, May 09, 2017 150-0321319 (6XX-44468R ) Intel Corporation,101 innovation Dr, San Jose, CA 95134 Copyright (c) 2014, Intel Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of A1 Stratix 10 SoC FPGA Development Kit Board B 1 71 Tuesday, May 09, 2017 150-0321319 (6XX-44468R ) Intel Corporation,101 innovation Dr, San Jose, CA 95134 Copyright (c) 2014, Intel Corporation. All Rights Reserved. Title Size Document Number Rev Date: Sheet of A1 Stratix 10 SoC FPGA Development Kit Board B 1 71 Tuesday, May 09, 2017 150-0321319 (6XX-44468R ) Intel Corporation,101 innovation Dr, San Jose, CA 95134 Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Transcript of s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu...
![Page 1: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/1.jpg)
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DESCRIPTIONREV DATE PAGES
PAGE DESCRIPTION
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0.1 All INITIAL REVISION A RELEASE
Block Diagram
Stratix 10 SoC FPGA Development Kit Board
Reset & Reconfiguration_CLK
26272829
PAGE DESCRIPTION
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JTAG BLOCK DiagramClock Block DiagramI2C BUS Block DiagramOn Board USB BLASTER II 1On Board USB BLASTER II 2PCIe x16 Connector10/100/1000 SGMII PHYA10/100/1000 SGMII PHYBSDI Transmit/ReceiveS10 XCVR Banks - 4C/D/E/FSFP+ Port AHDMI (VIDEO ONLY)QSFP28 Interface 0&MXPQSFP28 Interface 1
FMC Port AS10 XCVR Banks - 4K/L/M/N
S10 Banks - 2 A/B/C
FMC Port BS10 Banks - 3 A/B/C
S10 XCVR Banks - 1K/L/M/NS10 Banks - 2 F/L/M/NHPS HILO 72-bit72-Bit Dual Rank SODIMM1S10 Banks - 3 I/J/L/KS10 Banks - CFG & XCVR IOS10 Banks - HPS IO-48 CONUser IOFPGA Mem Ref clockHILO 72-bitXCVR REF Clocks
CLOCK CLEANERDB9RS232I2C_MUXSystemMAX10 1
System MAX10 2Flash Memory
System MAX10 3System MAX10 4
PDN DiagramPower SequenceMAX10 PWR Manager 1
MAINSwitch_12V_DC_12V12Vto5VM12Vto3V33V3to2V5
240ACore_Phase2240ACore_Contrller
S10switch_12V_3V3
3V3toHILOHPSVDD
240ACore_Phase32.4V, 1.8Vand VTT Power
VCCPT&VCCTVCCERAM&HPScore
3.3Vto1V2
VCCRS10 PWRS10 GND
Decoupling 2FMCSwitch_3V3
Decoupling 1
2V5_1V8Switch3V3IOSwitch3V3_1V8Discharge Load
DC3V3currentsensors
Videoclockgenerator
MAX10 PWR Manager 2
S10 XCVR Banks - 1C/D/E/F
3V3to1V8
A.0 release All Power/SI/Mechanical Test Board ReleaseA.1 release Add FGPA dedicated I2C port to Optical ModuleMove signal FALAP17 to FPGA clock input pin2521,22 Add Header to select USB blaster code7SWAP byte assignment of FGPA DDR ports.
25 Move signal FBLAP17 to FPGA clock input pin28 C185 to 1uf1535 R851 value is changed to 17.4K. Wrong connection of C161427 Change C249 decoupling to VDDAdd more Power test pins
Change Memory IO connection for I J K L 2810,11 Sepearte case gnd and signa gnd10,11 Change R63, R87 to 4.7K12 Update U13 Symbol15 ADD U18 I2C Address 21 Fix Signal PN connections22 Fix Signal PN connections, add dedicated I2C ports for clock cleaner and QSFP+ ports25 Add dedicated I2C ports for Video and SFP ports30 Change JTAG_RESET to DC Power good31 Add pull down resistor36 Change AC coupling cap from 4.7uf to 0.1uf42 Fix Signal PN connections. Change J56 from 2-pin to 3-pin46 Short A-GND to Signal GND
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
1 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
1 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
1 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
![Page 2: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/2.jpg)
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Stratix 10 Dev Kit Block Diagram
Title
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Stratix 10 SoC FPGA Development Kit BoardB
2 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
2 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
2 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
![Page 3: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/3.jpg)
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S10soc Dev Kit Reset Block
Title
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Stratix 10 SoC FPGA Development Kit BoardB
3 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
3 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
3 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
![Page 4: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/4.jpg)
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JTAG Connection Diagram
Title
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Stratix 10 SoC FPG Development Kit BoardB
4 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPG Development Kit BoardB
4 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPG Development Kit BoardB
4 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
![Page 5: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/5.jpg)
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Stratix 10 Dev Kit Clock Connection
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
5 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
5 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
5 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
![Page 6: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/6.jpg)
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Stratix 10 Dev Kit I2C bus Connection
Title
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Stratix 10 SoC FPGA Development Kit BoardB
6 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
6 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
6 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
![Page 7: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/7.jpg)
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On Board USB BLASTER II
PLACE CLOSE CY7C68013
Route as matched pair on Top layer
CAD Notes:
USB_T_CLK8
FX2_RESETn 8
FBTRST23
FATDO19 FATCK19 FATDI19FATMS19
FATRST19
USB2_1V8 8,32,47,52,683V3 8,29,31,46,47,50,51,52,53,67,692V5 8,46,51,68
3V3
3V3
3V3
3V3
3V3
USB2_1V8
3V3 USB2_1V82V5
3V3
USB2_1V8Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
7 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
7 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
7 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R6 2.00KU3
TPD2EUSB30D- 2D+ 1
GND3
R21 10.0K
MAX10 10M04SCU169
U4D
10M04SCU169
IO_3_L5/DIFFIO_TX_RX_B1NL5IO_3_M4/DIFFIO_RX_B2NM4IO_3_L4/DIFFIO_TX_RX_B1PL4IO_3_M5/DIFFIO_RX_B2PM5IO_3_K5/DIFFIO_TX_RX_B3NK5IO_3_N4/DIFFIO_RX_B4NN4IO_3_J5/DIFFIO_TX_RX_B3PJ5IO_3_N5/DIFFIO_RX_B4PN5IO_3_N6/DIFFIO_TX_RX_B5NN6IO_3_N7/DIFFIO_RX_B6NN7IO_3_M7/DIFFIO_TX_RX_B5PM7IO_3_N8/DIFFIO_RX_B6PN8IO_3_J6/DIFFIO_TX_RX_B7NJ6IO_3_M8/DIFFIO_RX_B8NM8IO_3_K6/DIFFIO_TX_RX_B7PK6IO_3_M9/DIFFIO_RX_B8PM9IO_3_J7/DIFFIO_TX_RX_B9NJ7IO_3_K7/DIFFIO_TX_RX_B9PK7IO_3_N12N12IO_3_M13/DIFFIO_TX_RX_B10NM13IO_3_N10/DIFFIO_RX_B11NN10IO_3_M12/DIFFIO_TX_RX_B10PM12IO_3_N9/DIFFIO_RX_B11PN9IO_3_M11/DIFFIO_TX_RX_B12NM11IO_3_L11/DIFFIO_TX_RX_B12PL11IO_3_J8/DIFFIO_TX_RX_B14NJ8IO_3_K8/DIFFIO_TX_RX_B14PK8IO_3_M10/DIFFIO_TX_RX_B16NM10IO_3_L10/DIFFIO_TX_RX_B16PL10
R3100K
R8 10.0K
R15 0
U1
MAX811
GND1
RESET2VCC 4
MR 3
J58
CON2
12
R1010.0K
U2
CY7C68013A_QFN
RDY0 1RDY1 2
XTALIN5
AVCC03
DMINUS9
AGND06
VCC011
GND012
PD7 52
CLKOUT 54
XTALOUT4
AVCC17
DPLUS8
AGND110
IFCLK13
RESERVED14
PD5 50PD4 49
PD6 51
SCL 15SDA 16
PB0 18
GND126GND228GND341
PB1 19
PB3 21PB2 20
VCC117VCC227
PB6 24PB5 23PB4 22
PD3 48PD2 47
PA740PA437PA134
PB7 25
PD1 46
WAKEUP 44
PA639
GND453
VCC443
PA336
CTL1 30CTL0 29
PD0 45
RESET 42
PA538
GND556
VCC555
PA235PA033
CTL2 31VCC332
EXPOSED_PAD 57
C412pF
C14DNI
R1 10K
R23 10.0K
R20 10.0K
MAX10 10M04SCU169
U4IIO_1B_E5/JTAGEN/DIFFIO_RX_L9PE5IO_1B_G1/TMS/DIFFIO_RX_L11NG1IO_1B_G2/TCK/DIFFIO_RX_L11PG2IO_1B_F5/TDI/DIFFIO_RX_L12NF5IO_1B_F6/TDO/DIFFIO_RX_L12PF6IO_8_B9/DEV_CLRN/DIFFIO_RX_T16NB9IO_8_D8/DEV_OE/DIFFIO_RX_T18PD8IO_8_D7/BOOT_SELD7IO_8_D6/CRC_ERROR/DIFFIO_RX_T22ND6IO_8_C4/NSTATUS/DIFFIO_RX_T24PC4IO_8_C5/CONF_DONE/DIFFIO_RX_T24NC5INPUT_ONLY_8_E7/NCONFIGE7
Y1
24.00MHz1 3
24
C2 0.1uF
MAX10 10M04SCU169
U4B
10M04SCU169
IO_1A_D1/DIFFIO_RX_L1ND1IO_1A_C2/DIFFIO_RX_L1PC2IO_1A_E3/DIFFIO_RX_L3NE3IO_1A_E4/DIFFIO_RX_L3PE4IO_1A_C1/DIFFIO_RX_L5NC1IO_1A_B1/DIFFIO_RX_L5PB1IO_1A_F1/DIFFIO_RX_L7NF1IO_1A_E1/DIFFIO_RX_L7PE1
IO_1B_F4/DIFFIO_RX_L14NF4IO_1B_G4/DIFFIO_RX_L14PG4IO_1B_H2/DIFFIO_RX_L16NH2IO_1B_H3/DIFFIO_RX_L16PH3
R16 10.0KR1310.0K
C100.1uF
R22 10.0K
R956 DNI
C130.1uF
C90.1uF
R220K
C34.7nF
C70.1uF
R1110.0K
C60.1uF
C80.1uF
R1210.0K
R170 R180
VBUSD-D+ID
J57MICRO_USB_CONN12345
6789
R9DNI
C120.1uF
R4 2.00K
C110.1uF
R140
C512pF
R190
J1
2X5_100mil
1 13 35 57 7
22446688
9 91010
R7 0
R51M
C10.1uF
FX2_D_NFX2_D_PVBUS_5V
24M_XTALIN24M_XTALOUT
FX2_RESETn
FX2_FLAGB
FX2_PA2
FX2_SLWRnFX2_SLRDn
FX2_PD2FX2_PD0FX2_PD3
FX2_PD1
FX2_PA0FX2_PA1FX2_PA2FX2_PA3FX2_PA4FX2_PA5FX2_PA6FX2_PA7
FX2_PB0FX2_PB1FX2_PB2FX2_PB3FX2_PB4FX2_PB5FX2_PB6FX2_PB7
FX2_PD0FX2_PD1FX2_PD2FX2_PD3FX2_PD4FX2_PD5FX2_PD6FX2_PD7
FX2_SDAFX2_SCLFX2_RESETn
FX2_PB2FX2_PB3
FX2_PD5FX2_PD7FX2_PD4
FX2_PB0
FX2_PB7
BLASTER_DISn EXT_JTAG_TCK
FX2_PB1
FX2_PB4
FX2_PB6
FX2_PB[0:7]
FX2_PD[0:7]
FX2_PB5
FX2_PA[0:7]
FX2_FLAGB
FX2_PD6
FX2_SCLMAX_SDA
FX2_WAKEUP
FX2_FLAGA
FX2_FLAGA
FX2_FLAGC
FX2_FLAGCFX2_SLRDnFX2_SLWRn
USB_T_CLK
BLASTER_DISnEXT_JTAG_TCK
EXT_JTAG_TDO
EXT_JTAG_TMS
EXT_JTAG_TMS
EXT_JTAG_TDI
EXT_JTAG_TDI
EXT_PROC_RSTnEXT_PROC_RSTnEXT_RESERVED
EXT_RESERVED EXT_RESERVED1
EXT_JTAG_TDO_OUT
VBUS_5V FX2_WAKEUP
FX2_PA3FX2_PA1
FX2_PA6FX2_PA7
FX2_PA4
FX2_PA5
FX2_PA0
USB_MAX_TDOUSB_MAX_TDIUSB_MAX_TCKUSB_MAX_TMS
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3
3
2
2
1
1
D D
C C
B B
A A
On Board USB BLASTER II 2, JTAGSwitch
GUI Test
OFF
MSTR1
OFFON
OFFON
ON-board UBII
OFF
BOOT
ON
MSTR2
FMCA Master
MSTR0
ON
ON
MAX10A Progrm Mode
OFF
Mode
OFF
ON
OFF
ONON
OFF
ON
ON
OFF
ON
OFF
OFF
FMCB Master
OFFRESERVEDReserved
ON
Logic 0 = Device JTAG BypassLogic 1 = Device JTAG Enable
PLACE CLOSE MAX 10 PWR PIN
MAX 10 constant mode has power ramp up requirement
CAD Notes:
Direct USB D022Direct USB D122 Direct USB D222 Direct USB D322 Direct USB D422 Direct USB D522Direct USB D622 Direct USB D722 Direct USB_RDn22 Direct USB_Wrn22 Direct USB_OEn22
Direct USB_RESETn22 Direct USB_EMPTY22 Direct USB_FULL22 Direct_USB_CLK22
M10A_JTAG_TMS47 USB_T_CLK7M10A_JTAG_TDO47 M10A_JTAG_TDI47 M10A_JTAG_TCK47 FX2_RESETn7
MAX10A_CLK47 MAX10B_USB_CLK42
Direct USB_SDA22 Direct USB_SCL22
S10_JTAG_TDI29 S10_JTAG_TCK29 S10_JTAG_TMS29 S10_JTAG_TDO29
M10B_JTAG_TMS39M10B_JTAG_TCK39 M10B_JTAG_TDI39 M10B_JTAG_TDO39
FBTDO23 FBTCK23FBTMS23 FBTDI23
PCIE_TRSTN9 PCIE_TDO9PCIE_TCK9 PCIE_TDI9 PCIE_TMS9
USB2_1V8 7,32,47,52,683V3 7,29,31,46,47,50,51,52,53,67,692V5 46,51,68
DC_POWER_GOOD30MICTOR_JTAG_TCK30 MICTOR_JTAG_TMS30 MICTOR_JTAG_TDI30 MICTOR_JTAG_TDO30
HPS_warm_RESET1n47
PCIE_PRSNT2n9,41,46 USBIO_disable46
USBMAX_MAX10A_IO047 USBMAX_MAX10A_IO147 USBMAX_MAX10A_IO247 USBMAX_MAX10A_IO347
3V3
USB2_1V8 MAX10VCCA
2V53V3
USB2_1V8
3V3 MAX10VCCA3V3
3V3 USB2_1V82V5USB2_1V8
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
8 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
8 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
8 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C240.1uF
R857
4.7K
C1610uF
C220.1uF
C200.1uF
C400.1uF
C1810uF
C380.1uF
R24160
D4 Green
MAX10 10M04SCU169
U4EIO_5_K10/DIFFIO_RX_R1PK10IO_5_K11/DIFFIO_RX_R2PK11IO_5_J10/DIFFIO_RX_R1NJ10IO_5_L12/DIFFIO_RX_R2NL12IO_5_K12/DIFFIO_RX_R7PK12IO_5_L13L13IO_5_J12/DIFFIO_RX_R7NJ12IO_5_J9/DIFFIO_RX_R8PJ9IO_5_J13/DIFFIO_RX_R9PJ13IO_5_H10/DIFFIO_RX_R8NH10IO_5_H13/DIFFIO_RX_R9NH13IO_5_H9/DIFFIO_RX_R10PH9IO_5_G13/DIFFIO_RX_R11PG13IO_5_H8/DIFFIO_RX_R10NH8IO_5_G12/DIFFIO_RX_R11NG12
C150.1uF
C360.1uF
MAX10 10M04SCU169
U4JGND__A1A1GND__A13A13GND__B8B8GND__C3C3GND__D2D2GND__D5D5GND__E11E11GND__E2E2GND__F3F3GND__G7G7GND__H12H12GND__J4J4GND__L9L9GND__M6M6GND__N1N1GND__N13N13
C340.1uF
C320.1uF
SW1
TDA08H0SB1
12345678
161514131211109
C290.1uF
C3010uF
C270.1uF
D3 Green
MAX10 10M04SCU169
U4HIO_2_G5/CLK0N/DIFFIO_RX_L18NG5IO_2_H6/CLK0P/DIFFIO_RX_L18PH6IO_2_H5/CLK1N/DIFFIO_RX_L20NH5IO_2_H4/CLK1P/DIFFIO_RX_L20PH4IO_2_N2/DPCLK0/DIFFIO_RX_L22NN2IO_2_N3/DPCLK1/DIFFIO_RX_L22PN3IO_6_G9/CLK2P/DIFFIO_RX_R14PG9IO_6_G10/CLK2N/DIFFIO_RX_R14NG10IO_6_F13/CLK3P/DIFFIO_RX_R16PF13IO_6_E13/CLK3N/DIFFIO_RX_R16NE13IO_6_F9/DPCLK3/DIFFIO_RX_R26PF9IO_6_F10/DPCLK2/DIFFIO_RX_R26NF10
IO_1B_H1/VREFB1N0H1IO_2_L1/VREFB2N0L1IO_3_N11/VREFB3N0N11IO_5_K13/VREFB5N0K13IO_6_D13/VREFB6N0D13IO_8_B7/VREFB8N0B7
C170.1uF
R25160
C250.1uF
R858
4.7K
C230.1uF
MAX10 10M04SCU169
U4AVCCIO1A__F2F2VCCIO1B__G3G3VCCIO2__K3K3VCCIO2__J3J3VCCIO3__L8L8VCCIO3__L7L7VCCIO3__L6L6VCCIO5__J11J11VCCIO5__H11H11VCCIO6__G11G11VCCIO6__F11F11VCCIO8__C8C8VCCIO8__C7C7VCCIO8__C6C6
VCCA3__D3D3VCCA1__K4K4VCCA2__D10D10VCCA3__D4D4VCCA4__K9K9
VCC_ONE__H7H7VCC_ONE__G8G8VCC_ONE__G6G6VCC_ONE__F7F7
C210.1uF
C410.1uF
MAX10 10M04SCU169
U4GIO_8_C10/DIFFIO_RX_T14PC10IO_8_A8/DIFFIO_RX_T15PA8IO_8_C9/DIFFIO_RX_T14NC9IO_8_A9/DIFFIO_RX_T15NA9IO_8_B10/DIFFIO_RX_T16PB10IO_8_A10/DIFFIO_RX_T17PA10IO_8_A11/DIFFIO_RX_T17NA11IO_8_E8/DIFFIO_RX_T18NE8IO_8_A7/DIFFIO_RX_T19PA7IO_8_A6/DIFFIO_RX_T19NA6IO_8_B6/DIFFIO_RX_T20PB6IO_8_A4/DIFFIO_RX_T21PA4IO_8_B5/DIFFIO_RX_T20NB5IO_8_A3/DIFFIO_RX_T21NA3IO_8_E6/DIFFIO_RX_T22PE6IO_8_B3/DIFFIO_RX_T23PB3IO_8_B4/DIFFIO_RX_T23NB4IO_8_A5/DIFFIO_RX_T25PA5IO_8_A2/DIFFIO_RX_T26PA2IO_8_B2/DIFFIO_RX_T26NB2
C190.1uF
C390.1uF
D1 Green
MAX10 10M04SCU169
U4C
10M04SCU169
IO_2_M3/PLL_L_CLKOUTN/DIFFIO_RX_L27NM3IO_2_L3/PLL_L_CLKOUTP/DIFFIO_RX_L27PL3
IO_2_J1/DIFFIO_RX_L19NJ1IO_2_J2/DIFFIO_RX_L19PJ2IO_2_M1/DIFFIO_RX_L21NM1IO_2_M2/DIFFIO_RX_L21PM2IO_2_L2L2IO_2_K1/DIFFIO_RX_L28NK1IO_2_K2/DIFFIO_RX_L28PK2
C370.1uF
L1
BLM15AG221SN1300mA
R27160
C350.1uF
C330.1uF
MAX10 10M04SCU169
U4FIO_6_F12/DIFFIO_RX_R18PF12IO_6_E12/DIFFIO_RX_R18NE12IO_6_C13C13IO_6_F8/DIFFIO_RX_R27PF8IO_6_B12/DIFFIO_RX_R28PB12IO_6_E9/DIFFIO_RX_R27NE9IO_6_B11/DIFFIO_RX_R28NB11IO_6_C12/DIFFIO_RX_R29PC12IO_6_B13/DIFFIO_RX_R30PB13IO_6_C11/DIFFIO_RX_R29NC11IO_6_A12/DIFFIO_RX_R30NA12IO_6_E10/DIFFIO_RX_R31PE10IO_6_D9/DIFFIO_RX_R31ND9IO_6_D12/DIFFIO_RX_R33PD12IO_6_D11/DIFFIO_RX_R33ND11
C310.1uF
C280.1uF
D2 Green
C260.1uF
R26160
S10_BYPASSM10B_BYPASSFMCA_BYPASSFMCB_BYPASSPCIE_BYPASS
RESn_JTAG_RX
RESn_JTAG_TX
RESn_SC_RX
RESn_SC_TX
MAX10VCCA
MSTR0MSTR1MSTR2
![Page 9: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/9.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
PCI Express GEN3 X 16 Connector
75-ohm to 100-ohm XCVR traces.
PCIE_12V48
PCIE_DC_3V371
PCIE_aux3V369
PCIE_RX_P0 13PCIE_RX_N0 13
PCIE_RX_P1 13PCIE_RX_N1 13
PCIE_RX_P2 13PCIE_RX_N2 13
PCIE_RX_P3 13PCIE_RX_N3 13
PCIE_RX_P4 13PCIE_RX_N4 13
PCIE_RX_P5 13PCIE_RX_N5 13
PCIE_RX_P6 13PCIE_RX_N6 13
PCIE_RX_P7 13PCIE_RX_N7 13
PCIE_TX_P013 PCIE_TX_N013
PCIE_TX_P113 PCIE_TX_N113
PCIE_TX_P213 PCIE_TX_N213
PCIE_TX_P313 PCIE_TX_N313
PCIE_TX_P413 PCIE_TX_N413
PCIE_TX_P513 PCIE_TX_N513
PCIE_TX_P613 PCIE_TX_N613
PCIE_TX_P713 PCIE_TX_N713
PCIE_REFCLK_SYN_P 32PCIE_REFCLK_SYN_N 32
PCIE_PERSTn 41
PCIE_TCK 8PCIE_TDI 8
PCIE_TRSTN8 PCIE_TMS 8PCIE_TDO 8EXTB_SDA19,23,38 EXTB_SCL19,23,38
PCIE_RX_P8 13PCIE_RX_N8 13
PCIE_RX_P9 13PCIE_RX_N9 13
PCIE_RX_P10 13PCIE_RX_N10 13
PCIE_RX_P11 13PCIE_RX_N11 13
PCIE_RX_P12 13PCIE_RX_N12 13
PCIE_RX_P13 13PCIE_RX_N13 13
PCIE_RX_P14 13PCIE_RX_N14 13
PCIE_RX_P15 13PCIE_RX_N15 13
PCIE_TX_P813 PCIE_TX_N813
PCIE_TX_P913 PCIE_TX_N913
PCIE_TX_P1013 PCIE_TX_N1013
PCIE_TX_P1113 PCIE_TX_N1113
PCIE_TX_P1213 PCIE_TX_N1213
PCIE_TX_P1313 PCIE_TX_N1313
PCIE_TX_P1413 PCIE_TX_N1413
PCIE_TX_P1513 PCIE_TX_N1513PCIE_PRSNT2n8,41,46
PCIE_WAKE_N41
PCIE_12V
PCIE_DC_3V3
PCIE_12V
PCIE_DC_3V3
PCIE_aux3V3
PCIE_12V PCIE_DC_3V3 PCIE_aux3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
9 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
9 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
9 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R30 DNI
C790.1uF
C45 0.22uF
C57 0.22uF
C48 0.22uF
C56 0.22uF
C44 0.22uF
C50 0.22uF
KEY
X4
X8
X1
X16
J53
1775793-3
+12VB1+12VB2+12VB3GNDB4SMCLKB5SMDATB6GNDB7+3_3VB8JTAG_TRSTNB9+3_3VAUXB10WAKE_NB11
RSVD1B12GNDB13PET0PB14PET0NB15GNDB16PRSNT2n_X1B17GNDB18
PET1PB19PET1NB20GNDB21GNDB22PET2PB23PET2NB24GNDB25GNDB26PET3PB27PET3NB28GNDB29RSVD3B30PRSNT2n_X4B31GNDB32
PET4PB33PET4NB34GNDB35GNDB36PET5PB37PET5NB38GNDB39GNDB40PET6PB41PET6NB42GNDB43GNDB44PET7PB45PET7NB46GNDB47PRSNT2n_X8B48GNDB49
PRSNT1_N A1+12V A2+12V A3GND A4
JTAG_TCK A5JTAG_TDI A6
JTAG_TDO A7JTAG_TMS A8
+3_3V A9+3_3V A10
PERST_N A11
GND A12REFCLK+ A13REFCLK- A14
GND A15PER0P A16PER0N A17
GND A18
RSVD2 A19GND A20
PER1P A21PER1N A22
GND A23GND A24
PER2P A25PER2N A26
GND A27GND A28
PER3P A29PER3N A30
GND A31RSVD4 A32
RSVD5 A33GND A34
PER4P A35PER4N A36
GND A37GND A38
PER5P A39PER5N A40
GND A41GND A42
PER6P A43PER6N A44
GND A45GND A46
PER7P A47PER7N A48
GND A49
PET8PB50PET8NB51GNDB52GNDB53PET9PB54PET9NB55GNDB56GNDB57PET10PB58PET10NB59GNDB60GNDB61PET11PB62PET11NB63GNDB64GNDB65PET12PB66PET12NB67GNDB68GNDB69PET13PB70PET13NB71GNDB72GNDB73PET14PB74PET14NB75GNDB76GNDB77PET15PB78PET15NB79GNDB80PRSNT2n_X16B81RSVD6B82
RSVD7 A50GND A51
PER8P A52PER8N A53
GND A54GND A55
PER9P A56PER9N A57
GND A58GND A59
PER10P A60PER10N A61
GND A62GND A63
PER11P A64PER11N A65
GND A66GND A67
PER12P A68PER12N A69
GND A70GND A71
PER13P A72PER13N A73
GND A74GND A75
PER14P A76PER14N A77
GND A78GND A79
PER15P A80PER15N A81
GND A82
C54 0.22uF
C840.1uFC770.1uF
C47 0.22uF
C55 0.22uF
C46 0.22uF
C820.1uFC83
100uF6.3VC7422uF
C52 0.22uF
C51 0.22uF
C43 0.22uF
C49 0.22uF
C63 0.22uF
C69 0.22uF
C59 0.22uF
C65 0.22uF
C71 0.22uF
C61 0.22uF
C67 0.22uF
C73 0.22uF
C750.1uF
C53 0.22uF
C780.1uF C800.1uF
C62 0.22uF
C68 0.22uF
C760.1uF
C58 0.22uF
C64 0.22uF
C70 0.22uF
C60 0.22uF
C66 0.22uF
C72 0.22uF
C42 0.22uF
R29 4.7K
C810.1uF
R28 DNI
PCIE_TX_CP6PCIE_TX_CN6
PCIE_TX_CP7PCIE_TX_CN7
PCIE_TX_CN5PCIE_TX_CP5
PCIE_TX_CN4PCIE_TX_CP4
PCIE_TX_CP2PCIE_TX_CN2
PCIE_TX_CP3PCIE_TX_CN3
PCIE_TX_CN1PCIE_TX_CP1
PCIE_TX_CP0PCIE_TX_CN0
PCIE_TX_CP8PCIE_TX_CN8
PCIE_TX_CP9PCIE_TX_CN9
PCIE_TX_CP10PCIE_TX_CN10
PCIE_TX_CP11PCIE_TX_CN11
PCIE_TX_CP12PCIE_TX_CN12
PCIE_TX_CP13PCIE_TX_CN13
PCIE_TX_CP14PCIE_TX_CN14
PCIE_TX_CP15PCIE_TX_CN15
![Page 10: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/10.jpg)
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6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
10/100/1000 Ethernet XCVR
SGMII Mode (default)
Place near 88E1111 PHY
88E1111-B2-CAA1C000 EOL88E1111-B2-NDC2C000 Replacement
DVDD = 1.0VDVDD = 1.2V
ENET_DVDD = 1.0V/0.207A
3KV
IO_3V3 14,15,16,17,22,25,26,29,30,31,32,34,35,36,37,38,43,57,69,70IO_2V5 11,12,22,26,27,32,38,43,68IO_5V 11,15,38,46,49
ENETA_MDC 22ENETA_MDIO 22
ENETA_INTn 22ENETA_RESETn 22
ENETA_TX_P 13ENETA_TX_N 13
ENETA_RX_P 13ENETA_RX_N 13
ENETA_DVDD
ENETA_DVDD
ENETA_DVDD
IO_3V3IO_2V5IO_5V
IO_2V5
IO_2V5
IO_5V
IO_2V5
IO_2V5
IO_2V5
IO_2V5
IO_2V5
IO_2V5
Ethernet1_CASE_GND
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
10 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
10 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
10 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C1040.1uF
C1130.1uF
C1171uF
R51 49.9
C1100.1uF
C1180.1uF
U100
25.00MHz
VCC 4
GND2 OUT 3EN1
C1200.1uF
C1252.2uF
C102 0.01uFR49 49.9R48 49.9
C1070.1uF
R70
10K
D8GREEN_LED
R66 4.7K
C1060.1uF
R60240
C12310uF
J3
7499111001A
TD0_P 1TD0_N 2
TD1_P 3TD1_N 6
TD2_P 4TD2_N 5
TD3_P 7TD3_N 8
VCC 9
GND 10
GND_
TAB
11GN
D_TA
B12
C1490 0.01uF
R584.99K
C12422uF
C1050.1uF
D7GREEN_LED
R68240
C1210.1uF
R54 49.9
C1110.1uF
D11GREEN_LED
U10
LTC3025-1
BIAS1
GND 2ADJ 5OUT 4
SHDN6EP_GND 7
IN3
R50 49.9
R550
R61240
D10GREEN_LED
C1080.1uF
C1140.01uF
R67 4.7K
C1160.1uFR594.7K
R69 15K
R63 4.7KR64 4.7K
R52 49.9
C1150.1uF
R62240
C103 0.01uF
C1190.1uF
R560
GMII/M
II/TBI
INTER
FACE
TESTSGM
II INT
ERFACE
JTAGMDI INTERFACE
MGMT
U8A
88E1111
COMA27RESET_N28
CONFIG658 CONFIG559 CONFIG460 CONFIG361 CONFIG263 CONFIG164 CONFIG065
125CLK22XTAL155XTAL254VSSC53
RSET30SEL_FREQ56
MDI3_P42MDI3_N43MDI2_P39MDI2_N41MDI1_P33MDI1_N34MDI0_P29MDI0_N31
MDIO24MDC25INT_N23
HSDAC_P37HSDAC_N38
GTX_CLK 8TX_CLK 4
TX_EN 9
RXCLK 2RX_DV 94
CRS 84COL 83
S_CLK_P 79S_CLK_N 80
S_IN_P 82S_IN_N 81
S_OUT_P 77S_OUT_N 75
LED_TX 68LED_RX 69
LED_DUPLEX 70LED_LINK1000 73
LED_LINK100 74LED_LINK10 76
RXD0 95RXD1 92RXD2 93RXD3 91RXD4 90RXD5 89RXD6 87RXD7 86
RX_ER 3
TXD0 11TXD1 12TXD2 14TXD3 16TXD4 17TXD5 18TXD6 19TXD7 20
TX_ER 7
TMS46 TDO50 TDI44 TCK49 TRST_N47
R47 49.9
C101 0.01uF
C1220.1uF
R53 49.9
C1090.1uF
C1657 DNI
R65240
C1120.1uF
U8B
88E1111
NC113
VSS97
DVDD 1DVDD 6DVDD 10DVDD 15DVDD 57DVDD 62DVDD 67DVDD 71DVDD 85
AVDD32AVDD36AVDD35AVDD40AVDD45AVDD78
VDDO
X26
VDDO
X48
VDDO
5VD
DO21
VDDO
88VD
DO96
VDDO
H72
VDDO
H66
VDDO
H52
NC251
D9GREEN_LED
R5710K
ENETA_LED_RX
ENETA_LED_TX
ENETA_LED_LINK100
ENETA_LED_LINK1000
ENETA_RSET
ENETA_LED_LINK10
AMDI_P0AMDI_N0AMDI_P1AMDI_N1AMDI_P2AMDI_N2AMDI_P3AMDI_N3
ENETA_TXC_PENETA_TXC_NENETA_RXC_PENETA_RXC_N
![Page 11: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/11.jpg)
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6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
10/100/1000 Ethernet XCVR
SGMII Mode (default)
Place near 88E1111 PHY
88E1111-B2-CAA1C000 EOL88E1111-B2-NDC2C000 Replacement
DVDD = 1.0VDVDD = 1.2V
ENET_DVDD = 1.0V/0.207A
3KV
IO_1V8 12,21,22,25,29,30,32,33,34,36,39,40,43,63,64,65,66,68IO_3V3 14,15,16,17,22,25,26,29,30,31,32,34,35,36,37,38,43,57,69,70IO_2V5 10,12,22,26,27,32,38,43,68IO_5V 10,15,38,46,49
ENETB_MDC 22ENETB_MDIO 22
ENETB_INTn 22ENETB_RESETn 22
ENETB_TX_P 13ENETB_TX_N 13
ENETB_RX_P 13ENETB_RX_N 13
ENETB_DVDD
ENETB_DVDD
ENETB_DVDD
IO_1V8IO_3V3IO_2V5IO_5V
IO_2V5
IO_2V5
IO_5V
IO_2V5
IO_2V5
IO_2V5
IO_2V5
IO_2V5
IO_2V5
Ethernet2_CASE_GND
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
11 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
11 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
11 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R76 49.9
C1300.1uF
R84240
C1330.1uF
R75 49.9
R824.99K
U9B
88E1111
NC113
VSS97
DVDD 1DVDD 6DVDD 10DVDD 15DVDD 57DVDD 62DVDD 67DVDD 71DVDD 85
AVDD32AVDD36AVDD35AVDD40AVDD45AVDD78
VDDO
X26
VDDO
X48
VDDO
5VD
DO21
VDDO
88VD
DO96
VDDO
H72
VDDO
H66
VDDO
H52
NC251
C15022uF
C1470.1uF
C1450.1uF
R77 49.9
C1440.1uF
R78 49.9C128 0.01uF
R71 49.9
C1658 DNI
C1400.01uF
R86240
GMII/M
II/TBI
INTER
FACE
TESTSGM
II INT
ERFACE
JTAGMDI INTERFACE
MGMT
U9A
88E1111
COMA27RESET_N28
CONFIG658 CONFIG559 CONFIG460 CONFIG361 CONFIG263 CONFIG164 CONFIG065
125CLK22XTAL155XTAL254VSSC53
RSET30SEL_FREQ56
MDI3_P42MDI3_N43MDI2_P39MDI2_N41MDI1_P33MDI1_N34MDI0_P29MDI0_N31
MDIO24MDC25INT_N23
HSDAC_P37HSDAC_N38
GTX_CLK 8TX_CLK 4
TX_EN 9
RXCLK 2RX_DV 94
CRS 84COL 83
S_CLK_P 79S_CLK_N 80
S_IN_P 82S_IN_N 81
S_OUT_P 77S_OUT_N 75
LED_TX 68LED_RX 69
LED_DUPLEX 70LED_LINK1000 73
LED_LINK100 74LED_LINK10 76
RXD0 95RXD1 92RXD2 93RXD3 91RXD4 90RXD5 89RXD6 87RXD7 86
RX_ER 3
TXD0 11TXD1 12TXD2 14TXD3 16TXD4 17TXD5 18TXD6 19TXD7 20
TX_ER 7
TMS46 TDO50 TDI44 TCK49 TRST_N47
D13GREEN_LED
D12GREEN_LED
D14GREEN_LED
R8110K
C1481uF
C1350.1uF
J4
7499111001A
TD0_P 1TD0_N 2
TD1_P 3TD1_N 6
TD2_P 4TD2_N 5
TD3_P 7TD3_N 8
VCC 9
GND 10
GND_
TAB
11GN
D_TA
B12
C1340.1uF
R87 4.7K
C1360.1uF
R92240
R790
R89240
C139 0.1uF
C1460.1uF
R800
D15GREEN_LED
C141 0.1uF
R834.7K
C14910uF
D16GREEN_LED
C1310.1uF
C1430.1uF
C142 0.1uF
C138 0.1uF
R72 49.9C126 0.01uF R73 49.9
C1370.1uF
U11
25.00MHz
VCC 4
GND2 OUT 3EN1
C1320.1uF
R88 4.7K
R93 15K
R91 4.7K
R74 49.9
R85240
C1512.2uF
R90 4.7K
C127 0.01uF
C129 0.01uF
U12
LTC3025-1
BIAS1
GND 2ADJ 5OUT 4
SHDN6EP_GND 7
IN3R94
10K
ENETB_LED_RX
ENETB_LED_TX
ENETB_LED_LINK100
ENEB_LED_LINK1000
ENETB_RSET
ENETB_LED_LINK10
BMDI_P0BMDI_N0BMDI_P1BMDI_N1BMDI_P2BMDI_N2BMDI_P3BMDI_N3
ENETB_TXC_PENETB_TXC_NENETB_RXC_PENETB_RXC_N
![Page 12: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/12.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
SDI Cable Driver, Equalizer, and SMB
95 Ohm Differential Impedance
95 Ohm Differential ImpedanceSDI_RX_P 18SDI_RX_N 18
SDI_RX_CS41 SDI_RX_SCLK41 SDI_RX_MISO41 SDI_RX_MOSI41
SDI_27MHz__REFCLK32
SD_RX_GPIO0 41SD_RX_GPIO2 41SD_RX_GPIO3 41
SDI_TX_P18 SDI_TX_N18
SDI_27MHz__REFCLK132 SDI_TX_MOSI41 SDI_TX_MISO41 SDI_TX_SCLK41 SDI_TX_CS41
SD_TX_GPIO0 41SD_TX_GPIO2 41SD_TX_GPIO3 41SD_TX_GPIO1 41
IO_1V8 21,22,25,29,30,32,33,34,36,39,40,43,63,64,65,66,68
IO_2V5 10,11,22,26,27,32,38,43,68
IO_1V8
IO_1V8
IO_1V8
IO_2V5
IO_2V5
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
12 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
12 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
12 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C1600.01uF
J6HDBNC
1
2345
C161 4.7uF
C1660.01uF
GS12281
U13
VEE_
DDI1
1VE
E_DD
I28
RSVD12RSVD23
RSVD39
RSVD430
TERM5DDI6DDI_N7
CS_N10SDIN11SDOUT12SCLK13
VSS1
14VS
S215
VDD
16
GPIO0 17GPIO1 18
VEE_
CORE
119
VEE_
CORE
231
VEE_
CORE
337
VEE_
CORE
438
CCO1
P8_1
20VE
EO1
21VE
EO2
28
SDO1/RCO_N 22
SDO1/RCO 23
VCCO
_124
VCCO
_025
SDO0_N 26SDO0 27
VCCO
1P8_0
29
REF_CLK32
GPIO2 33
VCO_FILT34
VCC_
CORE
35
GPIO3 36
LF+ 39
LF- 40
TAB
41
VCC_
DDI
4
R98 75
C165110uF
C176 4.7uF
C1700.01uF
R95 0
C1640.47uF
C156 4.7uFC157 4.7uFC162 4.7uF
C1530.01uF
R101 0
C1520.01uF
C1650.1uF
C1690.01uF
C1540.01uF
GS12241
U14
VEE_
SDI1
1VE
E_SD
I28
SDI2SDI_TERM3 VC
C_SD
I4
RSVD15RSVD26RSVD37
RSVD49
RSVD530
REF_CLK32
CS_N10SDIN11SDOUT12SCLK13
VSS1
14VS
S215
VDD
16
GPIO0 17GPIO1 18
VEE_
DORE
219
VEE_
CORE
131
VEE_
CORE
337
VEE_
CORE
438
VCC_
CORE
35VC
CO1P
8_029
VCCO
1P8_1
20VE
EO21
VEEO
128
DDO1_N_RCO_N0 22DDO1_RC0_P0 23
VCCO
_124
VCCO
_025
DDO0_N 26DDO0 27
GPIO2 33
VCO_FILT34
GPIO3 36
LF+ 39
LF- 40
TAB
41
R103 0
C1590.01uF
C175 4.7uF
J5HDBNC
1
2 3 4 5
C174 4.7uF
R97 0
C1780.1uF
C1630.01uF
R102 0
C1720.01uF
C1770.47uF
C1680.01uF
R99 0
R104 0
C1580.01uF
R96 0
C1710.01uF
C165210uF
C1670.01uF
C1550.01uF
R100 0
C173 4.7uF
SDO_NSDO_P
SDI_IN_P1
REF_CLK_OUT
SDI_RX_VCC1
SDI_RX_VCC2
SDI_RX_VCC3
SDI_TXCAP_PSDI_TXCAP_N
SDI_TX_REF_CLK_OUTREF_CLK_OUT
SDT_TX_P SDI_TXBNC_P
SDI_TX_VCC2
SDI_TX_VCC3
SDI_TX_VCC1
![Page 13: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/13.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Stratix 10 XCVR Banks - 4K/L/M/NPCIE_REFCLK_QR0_P32PCIE_REFCLK_QR0_N32
PCIE_TX_N59 PCIE_TX_P59 PCIE_TX_N49PCIE_TX_P49 PCIE_TX_N39 PCIE_TX_P39 PCIE_TX_N29 PCIE_TX_P29PCIE_TX_N19 PCIE_TX_P19 PCIE_TX_N09 PCIE_TX_P09PCIE_RX_N59 PCIE_RX_P59 PCIE_RX_N49 PCIE_RX_P49 PCIE_RX_N39PCIE_RX_P39 PCIE_RX_N29 PCIE_RX_P29 PCIE_RX_N19 PCIE_RX_P19PCIE_RX_N09 PCIE_RX_P09
PCIE_TX_N119 PCIE_TX_P119 PCIE_TX_N109 PCIE_TX_P109 PCIE_TX_N99PCIE_TX_P99 PCIE_TX_N89 PCIE_TX_P89 PCIE_TX_N79 PCIE_TX_P79PCIE_TX_N69 PCIE_TX_P69
PCIE_RX_N119 PCIE_RX_P119PCIE_RX_N109 PCIE_RX_P109 PCIE_RX_N99 PCIE_RX_P99 PCIE_RX_N89PCIE_RX_P89 PCIE_RX_N79 PCIE_RX_P79 PCIE_RX_N69 PCIE_RX_P69
CLK_ENET_FPGA_P 34CLK_ENET_FPGA_N 34
ENETB_TX_N 11ENETB_TX_P 11ENETA_TX_N 10ENETA_TX_P 10PCIE_TX_N15 9PCIE_TX_P15 9PCIE_TX_N14 9PCIE_TX_P14 9
PCIE_TX_N13 9PCIE_TX_P13 9PCIE_TX_N12 9PCIE_TX_P12 9ENETB_RX_N 11ENETB_RX_P 11ENETA_RX_N 10ENETA_RX_P 10PCIE_RX_N15 9
PCIE_RX_P15 9PCIE_RX_N14 9PCIE_RX_P14 9PCIE_RX_N13 9PCIE_RX_P13 9PCIE_RX_N12 9PCIE_RX_P12 9
Clearner_XVR_644.53125MHZ_P 36Clearner_XVR_644.53125MHZ_N 36
ZQSFP0_TXN3 16ZQSFP0_TXP3 16ZQSFP0_TXN2 16ZQSFP0_TXP2 16
ZQSFP0_TXN1 16ZQSFP0_TXP1 16ZQSFP0_TXN0 16ZQSFP0_TXP0 16
ZQSFP0_RXN3 16ZQSFP0_RXP3 16ZQSFP0_RXN2 16ZQSFP0_RXP2 16
ZQSFP0_RXN1 16ZQSFP0_RXP1 16ZQSFP0_RXN0 16ZQSFP0_RXP0 16REFCLK0_P 34REFCLK0_N 34
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
13 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
13 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
13 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
BANK 4
K
BANK 4
M
BANK 4
L
BANK 4
N1SX280LU3F50E3VGS1
U15HREFCLK_GXBR4K_CHTPV12REFCLK_GXBR4K_CHTNV13
GXBR4K_TX_CH5NW4GXBR4K_TX_CH5PW3
GXBR4K_RX_CH5N, GXBR4K_REFCLK5NY6GXBR4K_RX_CH5P, GXBR4K_REFCLK5PY5
GXBR4K_TX_CH4NAB2GXBR4K_TX_CH4PAB1
GXBR4K_RX_CH4N, GXBR4K_REFCLK4NW8GXBR4K_RX_CH4P, GXBR4K_REFCLK4PW7
GXBR4K_TX_CH3NAA4GXBR4K_TX_CH3PAA3
GXBR4K_RX_CH3N, GXBR4K_REFCLK3NAB6GXBR4K_RX_CH3P, GXBR4K_REFCLK3PAB5
GXBR4K_TX_CH2NAD2GXBR4K_TX_CH2PAD1
GXBR4K_RX_CH2N, GXBR4K_REFCLK2NAA8GXBR4K_RX_CH2P, GXBR4K_REFCLK2PAA7
GXBR4K_TX_CH1NAC4GXBR4K_TX_CH1PAC3
GXBR4K_RX_CH1N, GXBR4K_REFCLK1NAD6GXBR4K_RX_CH1P, GXBR4K_REFCLK1PAD5
GXBR4K_TX_CH0NAE4GXBR4K_TX_CH0PAE3
GXBR4K_RX_CH0N, GXBR4K_REFCLK0NAC8GXBR4K_RX_CH0P, GXBR4K_REFCLK0PAC7
REFCLK_GXBR4K_CHBPY12REFCLK_GXBR4K_CHBNY13
REFCLK_GXBR4L_CHTPAB9REFCLK_GXBR4L_CHTNAB10
GXBR4L_TX_CH5NR4GXBR4L_TX_CH5PR3
GXBR4L_RX_CH5N, GXBR4L_REFCLK5NM6GXBR4L_RX_CH5P, GXBR4L_REFCLK5PM5
GXBR4L_TX_CH4NP2GXBR4L_TX_CH4PP1
GXBR4L_RX_CH4N, GXBR4L_REFCLK4NR8GXBR4L_RX_CH4P, GXBR4L_REFCLK4PR7
GXBR4L_TX_CH3NT2GXBR4L_TX_CH3PT1
GXBR4L_RX_CH3N, GXBR4L_REFCLK3NP6GXBR4L_RX_CH3P, GXBR4L_REFCLK3PP5
GXBR4L_TX_CH2NU4GXBR4L_TX_CH2PU3
GXBR4L_RX_CH2N, GXBR4L_REFCLK2NT6GXBR4L_RX_CH2P, GXBR4L_REFCLK2PT5
GXBR4L_TX_CH1NV2GXBR4L_TX_CH1PV1
GXBR4L_RX_CH1N, GXBR4L_REFCLK1NU8GXBR4L_RX_CH1P, GXBR4L_REFCLK1PU7
GXBR4L_TX_CH0NY2GXBR4L_TX_CH0PY1
GXBR4L_RX_CH0N, GXBR4L_REFCLK0NV6GXBR4L_RX_CH0P, GXBR4L_REFCLK0PV5
REFCLK_GXBR4L_CHBPAD9REFCLK_GXBR4L_CHBNAD10
REFCLK_GXBR4M_CHTP V9REFCLK_GXBR4M_CHTN V10
GXBR4M_TX_CH5N J4GXBR4M_TX_CH5P J3
GXBR4M_RX_CH5N, GXBR4M_REFCLK5N F6GXBR4M_RX_CH5P, GXBR4M_REFCLK5P F5
GXBR4M_TX_CH4N H2GXBR4M_TX_CH4P H1
GXBR4M_RX_CH4N, GXBR4M_REFCLK4N J8GXBR4M_RX_CH4P, GXBR4M_REFCLK4P J7
GXBR4M_TX_CH3N L4GXBR4M_TX_CH3P L3
GXBR4M_RX_CH3N, GXBR4M_REFCLK3N H6GXBR4M_RX_CH3P, GXBR4M_REFCLK3P H5
GXBR4M_TX_CH2N K2GXBR4M_TX_CH2P K1
GXBR4M_RX_CH2N, GXBR4M_REFCLK2N L8GXBR4M_RX_CH2P, GXBR4M_REFCLK2P L7
GXBR4M_TX_CH1N N4GXBR4M_TX_CH1P N3
GXBR4M_RX_CH1N, GXBR4M_REFCLK1N K6GXBR4M_RX_CH1P, GXBR4M_REFCLK1P K5
GXBR4M_TX_CH0N M2GXBR4M_TX_CH0P M1
GXBR4M_RX_CH0N, GXBR4M_REFCLK0N N8GXBR4M_RX_CH0P, GXBR4M_REFCLK0P N7
REFCLK_GXBR4M_CHBP Y9REFCLK_GXBR4M_CHBN Y10
REFCLK_GXBR4N_CHTP P9REFCLK_GXBR4N_CHTN P10
GXBR4N_TX_CH5N B6GXBR4N_TX_CH5P B5
GXBR4N_RX_CH5N, GXBR4N_REFCLK5N B10GXBR4N_RX_CH5P, GXBR4N_REFCLK5P B9
GXBR4N_TX_CH4N C4GXBR4N_TX_CH4P C3
GXBR4N_RX_CH4N, GXBR4N_REFCLK4N A8GXBR4N_RX_CH4P, GXBR4N_REFCLK4P A7
GXBR4N_TX_CH3N E4GXBR4N_TX_CH3P E3
GXBR4N_RX_CH3N, GXBR4N_REFCLK3N C8GXBR4N_RX_CH3P, GXBR4N_REFCLK3P C7
GXBR4N_TX_CH2N D2GXBR4N_TX_CH2P D1
GXBR4N_RX_CH2N, GXBR4N_REFCLK2N E8GXBR4N_RX_CH2P, GXBR4N_REFCLK2P E7
GXBR4N_TX_CH1N G4GXBR4N_TX_CH1P G3
GXBR4N_RX_CH1N, GXBR4N_REFCLK1N D6GXBR4N_RX_CH1P, GXBR4N_REFCLK1P D5
GXBR4N_TX_CH0N F2GXBR4N_TX_CH0P F1
GXBR4N_RX_CH0N, GXBR4N_REFCLK0N G8GXBR4N_RX_CH0P, GXBR4N_REFCLK0P G7
REFCLK_GXBR4N_CHBP T9REFCLK_GXBR4N_CHBN T10
![Page 14: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/14.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Optical (SFP) Transceiver Cage & Connector 1I2C Address is 1010000 and 1010001.
Optical (SFP+) Transceiver Cage & Connector 0
Small Form Factor Pluggable Plus (SFP+) Port A
IO_3V315,16,17,22,25,26,29,30,31,32,34,35,36,37,38,43,57,69,70
SFPA_TX_P 18
SFPA_RX_P18SFPA_TX_N 18
SFPA_RX_N18SFPA_LOS 41SFPA_TXFAULT 41
SFPA_TXDISABLE41 SFPA_RATESEL041 SFPA_RATESEL141SFPA_MOD0_PRSNTn41
SFPA_I2C_B_SDA25 SFPA_I2C_B_SCL25
SFPA_VCCT
SFPA_VCCR
GND_CAGE GND_CAGE
IO_3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
14 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
14 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
14 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C1800.1uF
L3 1.0uHC18310uF
L2 1.0uHC18110uF
B1
SFP+_CAGE
C1820.1uF
J7
SFP+_AND_CAGE<Agile Part Number>
CAGE_GND21CAGE_GND22CAGE_GND23CAGE_GND24CAGE_GND25CAGE_GND26CAGE_GND27CAGE_GND28CAGE_GND29CAGE_GND30CAGE_GND31
CAGE_GND 32CAGE_GND 33CAGE_GND 34
VEET 1VEET 17VEET 20RS19
VEER 10VEER 11VEER 14
TD_P 18TD_N 19
RX_LOS 8TX_FAULT 2
VCCT16VCCR15
RD_P13RD_N12
TX_DISABLE3RS07
MOD_ABS6SCL5SDA4
CAGE_GND 35CAGE_GND 36CAGE_GND 37CAGE_GND 38CAGE_GND 39CAGE_GND 40
MH1 41MH2 42
C1790.1uF
SFPB_VCCR
SFPB_VCCT
![Page 15: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/15.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDMI (VIDEO ONLY)
27K ohm
I2C address 1110011
HDMI_LANE_P018 HDMI_LANE_N018
HDMI_LANE_P118 HDMI_LANE_N118
HDMI_LANE_P218 HDMI_LANE_N218
HDMI_LANE_CLKP18 HDMI_LANE_CLKN18
IO_5V 10,11,38,46,49IO_3V3 14,16,17,22,25,26,29,30,31,32,34,35,36,37,38,43,57,69,70
HDMI_POWER_ON41HDMI_VFlagn41
HDMI_TX_SDA38 HDMI_TX_SCL38
HDMI_LINE_SDA 38HDMI_LINE_SCL 38
HDMI_HPDn 41
DVI_TX_IN_CECn 41DVI_TX_CEC_OUT_N41HDMI_3V3
IO_5VIO_3V3
IO_3V3
HDMI_3V3 HDMI_3V3
IO_5V
HDMI_5.0V
HDMI_5.0V
HDMI_5.0V
IO_3V3
IO_3V3
HDMI_5.0V
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardA3
15 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardA3
15 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardA3
15 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
L4 120 Ohm FB
R113 DNI
C1990.1uF
Q3FDV305N
D
G
S
C189 0.1uF
R111 4.7K
R123 0R121 10.0K
Q1FDV305N
D
G
S
R128 DNI
C2000.1uF
C192 0.1uF
R107 4.7KR106 4.7K
U17DT1240A-04LP
LINE1
1
LINE2
2
GND1
3
LINE3
4
LINE4
5
NC1
10
NC2
9
GND2
8
NC3
7
NC4
6
C1960.1uF
R130 4.7K
R115 0
R120 0
C190 0.1uF
U18
PI3HDX1204B1
DE11DE02
A0RX+4A0RX-5GND16VCC13
A1RX+7A1RX-8VCC29
GND212
VCC315
A2RX+10A2RX-11
A3RX+13A3RX-14
A116A417
SDA
18SC
L19
PEN
20Pin
_Mode
21
A0 22VOD1 23VCC4 24A3TX- 25A3TX+ 26VCC5 27A2TX- 28A2TX+ 29GND3 30A1TX- 31A1TX+ 32VCC6 33A0TX- 34A0TX+ 35NC1 37NC2 38BS
T039
BST1
40BS
T241
BST3
42HG
ND43
VCC7 36
U19DT1240A-04LP
LINE1
1
LINE2
2
GND1
3
LINE3
4
LINE4
5
NC1
10
NC2
9
GND2
8
NC3
7
NC4
6
R117 2.0K
C1950.1uF
C187 0.1uFC188 0.1uF
R126 DNI
R131
10
R129 4.7K
R110 4.7K
R116 0
R124 0
R13249.9K
R114 DNI
C186 0.1uF
R112 4.7K
R119 2.0K
C1980.1uF
Q4FDV305N
D
G
S
R127 DNI
C2010.1uF
U16
MAX14523B
IN5 OUT 4
ON7 GND 8FLAG2NC26 SETI 3NC11
GND_PAD 9
HDMI 19-Pin ConnectorJ8685119134923
TMDS_DATA_N23 TMDS_DATA_P21TMDS_DATA_N16 TMDS_DATA_P14TMDS_DATA_N09 TMDS_DATA_P075V_VCC18
SCL 15
TMDS_CLK_P10TMDS_DATA_SHLD22
RESERVED_NC 14
MTG2
G2
TMDS_DATA_SHLD15
TMDS_DATA_SHLD08SDA 16
MTG1
G1
TMDS_DATA_SHLD_CLK11 TMDS_CLK_N12
CEC 13
DDC_CEC_GND 17
HOT_PLUG_DETECT 19
MTG3
G3MT
G4G4
R109 4.7K
R122 0
C1970.1uF
C1851uF
C1842.2uF R105
137K
1%
R125 0
C1932.2uF
R118 0
C1940.1uF
R108 4.7K
Q2FDV305N
D
G
S
C1492 0.1uF
R13349.9K
C191 0.1uF
HDMI_HPD
HDMI_TX_CLKpHDMI_TX_CLKn
HDMI_TX_D0pHDMI_TX_D0n
HDMI_TX_D1pHDMI_TX_D1n
HDMI_TX_D2pHDMI_TX_D2n HDMI_TX_Line_D0pHDMI_TX_Line_D0n
HDMI_TX_Line_D1pHDMI_TX_Line_D1n
HDMI_TX_Line_D2pHDMI_TX_Line_D2n
HDMI_TX_Line_CLKpHDMI_TX_Line_CLKn
HDMI_VFlagn
![Page 16: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/16.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
QSFP28 Interface 0 & MXP Cable connection
QSFP28 Interface
Cage GND on top layer
P and N can be swapped for better SI performance
Maximum current is 500ma per pinModsell need be pull high to disabel I2C bus
Internal Pull high of RESETL and LPMode
Dc resistanc should be less than 0.1ohm
Maximum power is 3,5WADDRESS 1010000
ZQSFP0_TXN0 13ZQSFP0_RXN013ZQSFP0_TXP0 13
ZQSFP0_TXP1 13ZQSFP0_TXN1 13ZQSFP0_TXP2 13ZQSFP0_TXN2 13ZQSFP0_TXP3 13ZQSFP0_TXN3 13
ZQSFP0_RXP013
ZQSFP0_RXP113 ZQSFP0_RXN113ZQSFP0_RXP213 ZQSFP0_RXN213ZQSFP0_RXP313 ZQSFP0_RXN313
IO_3V3 14,15,17,22,25,26,29,30,31,32,34,35,36,37,38,43,57,69,70
ZQSFP0_ModprsL41ZQSFP0_intL41
ZQSFP0_ModselL41ZQSFP0_ResetL41
ZQSFP0_LPmode41
MXP_TXN318 MXP_RXP3 18MXP_TXP318 MXP_RXN3 18MXP_TXN218 MXP_RXP2 18MXP_TXP218 MXP_RXN2 18
MXP_TXN118 MXP_RXP1 18MXP_TXP118 MXP_RXN1 18MXP_TXN018
MXP_RXP0 18MXP_TXP018MXP_RXN0 18
ZQSFP_I2C_B_SDA17,22 ZQSFP_I2C_B_SCL17,22
ZQSFP0_VCC1
ZQSFP0_VCCTX
ZQSFP0_VCCRX
GND_QSFP_CAGE
GND_QSFP_CAGE
IO_3V3
IO_3V3
IO_3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
16 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
16 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
16 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C21022uf
C2030.1uF
R13410.0K
L6 1.0uH
L7 1.0uH
L5 1.0uH
C2024.7nF
C20422uf
C20822uf
J9
zQSFP+
GND0 1
TX2n 2TX2p 3
GND1 4
TX4n 5TX4p 6
GND2 7
ModselL8ResetL9
VCCRX 10
SCL11SDA12
GND3 13
RX3p14RX3n15
GND4 16
RX1p17RX1n18
GND5 19GND6 20
RX2n21 RX2p22
GND7 23
RX4n24 RX4p25
GND8 26
ModPrsL27
Intl28VCCTX 29VCC1 30
LPMode31
GND9 32
TX3p 33TX3n 34
GND10 35
TX1p 36TX1n 37
GND11 38
R904
4.7K
C2070.1uF
C2090.1uF
R909
4.7K
2X8 MX
P
J50
2x8 MXP
1 12 23 34 45 56 67 78 899 1010 1111 1212 1313 1414 1515 1616
M1M1
M2M2
C2050.1uF
B2
zQSFP+_CAGE
CAGE_GND01CAGE_GND12CAGE_GND23CAGE_GND34CAGE_GND45CAGE_GND56 CAGE_GND6 7CAGE_GND7 8CAGE_GND8 9CAGE_GND9 10CAGE_GND10 11CAGE_GND11 12
C20622uf
R905
4.7K
![Page 17: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/17.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
QSFP28 Interface 1
QSFP28 Interface
Modsell need be pull high to disabel I2C busMaximum current is 500ma per pinInternal Pull high of RESETL and LPMode
Dc resistanc should be less than 0.1ohm
Maximum power is 3,5W
ADDRESS 1010000
ZQSFP1_TXN0 18ZQSFP1_RXN018 ZQSFP1_TXP0 18
ZQSFP1_TXP1 18ZQSFP1_TXN1 18ZQSFP1_TXP2 18ZQSFP1_TXN2 18ZQSFP1_TXP3 18ZQSFP1_TXN3 18
ZQSFP1_RXP018
ZQSFP1_RXP118 ZQSFP1_RXN118ZQSFP1_RXP218 ZQSFP1_RXN218ZQSFP1_RXP318ZQSFP1_RXN318
IO_3V3 14,15,16,22,25,26,29,30,31,32,34,35,36,37,38,43,57,69,70
ZQSFP1_ModprsL41ZQSFP1_intL41
ZQSFP1_ModselL41 ZQSFP1_ResetL41ZQSFP1_LPmode41
ZQSFP_I2C_B_SCL16,22 ZQSFP_I2C_B_SDA16,22
ZQSFP1_VCC1
ZQSFP1_VCCTX
ZQSFP1_VCCRX
IO_3V3
IO_3V3
IO_3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
17 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
17 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
17 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C21522uf
C2160.1uF
R908
4.7K
L9 1.0uH
C2180.1uF
R907
4.7K
C2140.1uF
C21722uf
C2120.1uF
C21922uf
C21322uf
J10
zQSFP+
GND0 1
TX2n 2TX2p 3
GND1 4
TX4n 5TX4p 6
GND2 7
ModselL8ResetL9
VCCRX 10
SCL11SDA12
GND3 13
RX3p14RX3n15
GND4 16
RX1p17RX1n18
GND5 19GND6 20
RX2n21 RX2p22
GND7 23
RX4n24 RX4p25
GND8 26
ModPrsL27
Intl28VCCTX 29VCC1 30
LPMode31
GND9 32
TX3p 33TX3n 34
GND10 35
TX1p 36TX1n 37
GND11 38
R906
4.7K
L10 1.0uH
L8 1.0uH
![Page 18: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/18.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 XCVR Banks - 4C/D/E/FHDMIREFCLK_P32 HDMIREFCLK_N32
HDMI_LANE_CLKN15 HDMI_LANE_CLKP15HDMI_LANE_N215 HDMI_LANE_P215 HDMI_LANE_N115 HDMI_LANE_P115 HDMI_LANE_N015HDMI_LANE_P015
SFPA_TX_N14 SFPA_TX_P14
SFPA_RX_N14 SFPA_RX_P14REFCLK_SFPA_P34REFCLK_SFPA_N34
REFCLK_SMA_P33 REFCLK_SMA_N33
MXP_TXN316 MXP_TXP316MXP_TXN216 MXP_TXP216
MXP_TXN116MXP_TXP116 MXP_TXN016 MXP_TXP016
MXP_RXN316 MXP_RXP316 MXP_RXN216 MXP_RXP216
MXP_RXN116 MXP_RXP116 MXP_RXN016MXP_RXP016
Clearner_SDI_245MHZ_P 36Clearner_SDI_245MHZ_N 36
SDI_TX_N 12SDI_TX_P 12
SDI_RX_N 12SDI_RX_P 12
Clearner_SDI_297MHZ_P 36Clearner_SDI_297MHZ_N 36
ZQSFP1_TXN3 17ZQSFP1_TXP3 17ZQSFP1_TXN2 17ZQSFP1_TXP2 17
ZQSFP1_TXN1 17ZQSFP1_TXP1 17ZQSFP1_TXN0 17ZQSFP1_TXP0 17
ZQSFP1_RXN3 17ZQSFP1_RXP3 17ZQSFP1_RXN2 17ZQSFP1_RXP2 17
ZQSFP1_RXN1 17ZQSFP1_RXP1 17ZQSFP1_RXN0 17ZQSFP1_RXP0 17REFCLK_QSFP1_P 34REFCLK_QSFP1_N 34
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
18 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
18 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
18 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
BANK 4
CBAN
K 4D
BANK 4
EBAN
K 4F
1SX280LU3F50E3VGS1
U15GREFCLK_GXBR4C_CHTPAP9REFCLK_GXBR4C_CHTNAP10
GXBR4C_TX_CH5NBC4GXBR4C_TX_CH5PBC3
GXBR4C_RX_CH5N, GXBR4C_REFCLK5NBD6GXBR4C_RX_CH5P, GXBR4C_REFCLK5PBD5
GXBR4C_TX_CH4NBF2GXBR4C_TX_CH4PBF1
GXBR4C_RX_CH4N, GXBR4C_REFCLK4NBC8GXBR4C_RX_CH4P, GXBR4C_REFCLK4PBC7
GXBR4C_TX_CH3NBE4GXBR4C_TX_CH3PBE3
GXBR4C_RX_CH3N, GXBR4C_REFCLK3NBE8GXBR4C_RX_CH3P, GXBR4C_REFCLK3PBE7
GXBR4C_TX_CH2NBG4GXBR4C_TX_CH2PBG3
GXBR4C_RX_CH2N, GXBR4C_REFCLK2NBG8GXBR4C_RX_CH2P, GXBR4C_REFCLK2PBG7
GXBR4C_TX_CH1NBF6GXBR4C_TX_CH1PBF5
GXBR4C_RX_CH1N, GXBR4C_REFCLK1NBJ8GXBR4C_RX_CH1P, GXBR4C_REFCLK1PBJ7
GXBR4C_TX_CH0NBJ5GXBR4C_TX_CH0PBJ4
GXBR4C_RX_CH0N, GXBR4C_REFCLK0NBH10GXBR4C_RX_CH0P, GXBR4C_REFCLK0PBH9
REFCLK_GXBR4C_CHBPAT9REFCLK_GXBR4C_CHBNAT10
REFCLK_GXBR4D_CHTPAK9REFCLK_GXBR4D_CHTNAK10
GXBR4D_TX_CH5NAU4GXBR4D_TX_CH5PAU3
GXBR4D_RX_CH5N, GXBR4D_REFCLK5NAV6GXBR4D_RX_CH5P, GXBR4D_REFCLK5PAV5
GXBR4D_TX_CH4NAY2GXBR4D_TX_CH4PAY1
GXBR4D_RX_CH4N, GXBR4D_REFCLK4NAU8GXBR4D_RX_CH4P, GXBR4D_REFCLK4PAU7
GXBR4D_TX_CH3NAW4GXBR4D_TX_CH3PAW3
GXBR4D_RX_CH3N, GXBR4D_REFCLK3NAY6GXBR4D_RX_CH3P, GXBR4D_REFCLK3PAY5
GXBR4D_TX_CH2NBB2GXBR4D_TX_CH2PBB1
GXBR4D_RX_CH2N, GXBR4D_REFCLK2NAW8GXBR4D_RX_CH2P, GXBR4D_REFCLK2PAW7
GXBR4D_TX_CH1NBA4GXBR4D_TX_CH1PBA3
GXBR4D_RX_CH1N, GXBR4D_REFCLK1NBB6GXBR4D_RX_CH1P, GXBR4D_REFCLK1PBB5
GXBR4D_TX_CH0NBD2GXBR4D_TX_CH0PBD1
GXBR4D_RX_CH0N, GXBR4D_REFCLK0NBA8GXBR4D_RX_CH0P, GXBR4D_REFCLK0PBA7
REFCLK_GXBR4D_CHBPAM9REFCLK_GXBR4D_CHBNAM10
REFCLK_GXBR4E_CHTP AF9REFCLK_GXBR4E_CHTN AF10
GXBR4E_TX_CH5N AM2GXBR4E_TX_CH5P AM1
GXBR4E_RX_CH5N, GXBR4E_REFCLK5N AK6GXBR4E_RX_CH5P, GXBR4E_REFCLK5P AK5
GXBR4E_TX_CH4N AN4GXBR4E_TX_CH4P AN3
GXBR4E_RX_CH4N, GXBR4E_REFCLK4N AM6GXBR4E_RX_CH4P, GXBR4E_REFCLK4P AM5
GXBR4E_TX_CH3N AP2GXBR4E_TX_CH3P AP1
GXBR4E_RX_CH3N, GXBR4E_REFCLK3N AN8GXBR4E_RX_CH3P, GXBR4E_REFCLK3P AN7
GXBR4E_TX_CH2N AT2GXBR4E_TX_CH2P AT1
GXBR4E_RX_CH2N, GXBR4E_REFCLK2N AP6GXBR4E_RX_CH2P, GXBR4E_REFCLK2P AP5
GXBR4E_TX_CH1N AR4GXBR4E_TX_CH1P AR3
GXBR4E_RX_CH1N, GXBR4E_REFCLK1N AT6GXBR4E_RX_CH1P, GXBR4E_REFCLK1P AT5
GXBR4E_TX_CH0N AV2GXBR4E_TX_CH0P AV1
GXBR4E_RX_CH0N, GXBR4E_REFCLK0N AR8GXBR4E_RX_CH0P, GXBR4E_REFCLK0P AR7
REFCLK_GXBR4E_CHBP AH9REFCLK_GXBR4E_CHBN AH10
REFCLK_GXBR4F_CHTP AK12REFCLK_GXBR4F_CHTN AK13
GXBR4F_TX_CH5N AG4GXBR4F_TX_CH5P AG3
GXBR4F_RX_CH5N, GXBR4F_REFCLK5N AE8GXBR4F_RX_CH5P, GXBR4F_REFCLK5P AE7
GXBR4F_TX_CH4N AF2GXBR4F_TX_CH4P AF1
GXBR4F_RX_CH4N, GXBR4F_REFCLK4N AG8GXBR4F_RX_CH4P, GXBR4F_REFCLK4P AG7
GXBR4F_TX_CH3N AJ4GXBR4F_TX_CH3P AJ3
GXBR4F_RX_CH3N, GXBR4F_REFCLK3N AF6GXBR4F_RX_CH3P, GXBR4F_REFCLK3P AF5
GXBR4F_TX_CH2N AH2GXBR4F_TX_CH2P AH1
GXBR4F_RX_CH2N, GXBR4F_REFCLK2N AJ8GXBR4F_RX_CH2P, GXBR4F_REFCLK2P AJ7
GXBR4F_TX_CH1N AL4GXBR4F_TX_CH1P AL3
GXBR4F_RX_CH1N, GXBR4F_REFCLK1N AH6GXBR4F_RX_CH1P, GXBR4F_REFCLK1P AH5
GXBR4F_TX_CH0N AK2GXBR4F_TX_CH0P AK1
GXBR4F_RX_CH0N, GXBR4F_REFCLK0N AL8GXBR4F_RX_CH0P, GXBR4F_REFCLK0P AL7
REFCLK_GXBR4F_CHBP AM12REFCLK_GXBR4F_CHBN AM13
![Page 19: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/19.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FMC Port A
I2C Address: b' 101 0010
PCIE_PRSNTshort
FALAP021 FALAP16 22FAHBP021 FAHBP11 21FALAN021 FALAN16 22FAHBN021 FAHBN11 21FALAP119 FALAP17 22FAHBP122 FAHBP12 21FALAN119 FALAN17 22FAHBN122 FAHBN12 21FALAP222 FALAP18 22FAHBP221 FAHBP13 21FALAN222 FALAN18 22FAHBN221 FAHBN13 21FALAP321 FALAP19 22FAHBP321 FAHBP14 21FALAN321 FALAN19 22FAHBN321 FAHBN14 21FALAP421 FALAP20 22FAHBP421 FAHBP15 21FALAN421 FALAN20 22FAHBN421 FAHBN15 21FALAP521 FALAP21 22FAHBP521 FAHBP16 22FALAN521 FALAN21 22FAHBN521 FAHBN16 22FALAP621 FALAP22 21FAHBP625 FAHBP17 21FALAN621 FALAN22 21FAHBN625 FAHBN17 21FALAP721 FALAP23 21FAHBP721 FAHBP18 21FALAN721 FALAN23 21FAHBN721 FAHBN18 21FALAP821 FALAP24 22FAHBP821 FAHBP19 25FALAN821 FALAN24 22FAHBN821 FAHBN19 25FALAP921 FALAP25 22FAHBP921 FAHBP20 21FALAN921 FALAN25 22FAHBN921 FAHBN20 21FALAP1021 FALAP26 22FAHBP1021 FAHBP21 21FALAN1021 FALAN26 22FAHBN1021 FAHBN21 21FALAP1122 FALAP27 22FALAN1122 FALAN27 22
FALAP1221 FALAP28 22FALAN1221 FALAN28 22
FAHAP022 FAHAP12 21FALAP1322 FALAP29 21
FAHAN022 FAHAN12 21FALAN1322 FALAN29 21
FAHAP122 FAHAP13 21FALAP1421 FALAP30 21
FAHAN122 FAHAN13 21FALAN1421 FALAN30 21
FAHAP222 FAHAP14 22FALAP1522 FALAP31 21
FAHAN222 FAHAN14 22FALAN1522 FALAN31 21
FAHAP321 FAHAP15 22FALAP32 19
FAHAN321 FAHAN15 22FALAN32 19FALAP33 19
FAHAP421 FAHAP16 22FALAN33 19
FAHAN421 FAHAN16 22FAHAP521 FAHAP17 22FAHAN521 FAHAN17 22FAHAP622 FAHAP18 22FAHAN622 FAHAN18 22FAHAP721 FAHAP19 22FAHAN721 FAHAN19 22FAHAP821 FAHAP20 22FAHAN821 FAHAN20 22FAHAP921 FAHAP21 22FAHAN921 FAHAN21 22FAHAP1022 FAHAP22 22FAHAN1022 FAHAN22 22FAHAP1122 FAHAP23 22FAHAN1122 FAHAN23 22
FAD0C2MP20 FAD0C2MN20 FAD1C2MP20 FAD1C2MN20 FAD2C2MP20 FAD2C2MN20 FAD3C2MP20 FAD3C2MN20 FAD4C2MP20 FAD4C2MN20 FAD5C2MP20 FAD5C2MN20 FAD6C2MP20 FAD6C2MN20 FAD7C2MP20 FAD7C2MN20 FAD8C2MP20 FAD8C2MN20 FAD9C2MP20 FAD9C2MN20 FAD10C2MP20 FAD10C2MN20 FAD11C2MP20 FAD11C2MN20 FAD12C2MP20 FAD12C2MN20 FAD13C2MP20 FAD13C2MN20 FAD14C2MP20 FAD14C2MN20 FAD15C2MP20 FAD15C2MN20 FAD16C2MP20 FAD16C2MN20 FAD17C2MP20 FAD17C2MN20 FAD18C2MP20 FAD18C2MN20 FAD19C2MP20 FAD19C2MN20 FAD20C2MP20 FAD20C2MN20 FAD21C2MP20 FAD21C2MN20 FAD22C2MP20 FAD22C2MN20 FAD23C2MP20 FAD23C2MN20
FAD0M2CP 20FAD0M2CN 20FAD1M2CP 20FAD1M2CN 20FAD2M2CP 20FAD2M2CN 20FAD3M2CP 20FAD3M2CN 20FAD4M2CP 20FAD4M2CN 20FAD5M2CP 20FAD5M2CN 20FAD6M2CP 20FAD6M2CN 20FAD7M2CP 20FAD7M2CN 20FAD8M2CP 20FAD8M2CN 20FAD9M2CP 20FAD9M2CN 20
FAGBTCLK0M2CP 20FAGBTCLK0M2CN 20FAGBTCLK1M2CP 20FAGBTCLK1M2CN 20
FAD10M2CP 20FAD10M2CN 20FAD11M2CP 20FAD11M2CN 20FAD12M2CP 20FAD12M2CN 20FAD13M2CP 20FAD13M2CN 20FAD14M2CP 20FAD14M2CN 20FAD15M2CP 20FAD15M2CN 20FAD16M2CP 20FAD16M2CN 20FAD17M2CP 20FAD17M2CN 20FAD18M2CP 20FAD18M2CN 20FAD19M2CP 20FAD19M2CN 20FAD20M2CP 20FAD20M2CN 20FAD21M2CP 20FAD21M2CN 20FAD22M2CP 20FAD22M2CN 20FAD23M2CP 20FAD23M2CN 20
FAGBTCLK2M2CP 20FAGBTCLK2M2CN 20
FAGBTCLK3M2CP20 FAGBTCLK3M2CN20 FAGBTCLK4M2CP20 FAGBTCLK4M2CN20 FAGBTCLK5M2CP20 FAGBTCLK5M2CN20
FMCAVADJ 71
FAM2CVIO
FAREFBFAREFA
FAM2CPgood 46
FATRST 7FATMS 7FATDO 7FATDI 7FATCK 7FACLK0M2CP 22FACLK0M2CN 22FACLK1M2CP 22FACLK1M2CN 22
FMCA_aux3V367
FMCA_DC_3V371
FMCA_12V48
FAPRSNT_N31,47EXTB_SDA9,23,38 EXTB_SCL9,23,38
FACLK2BIDIRP22 FACLK2BIDIRN22 FACLK3BIDIRP22 FACLK3BIDIRN22 FACLKDIR22
FACLKC2MP42 FACLKC2MN42 FACLK2M2CP41 FACLK2M2CN41
FASYNC2MP 42FASYNC2MN 42FASYNM2CP 22FASYNM2CN 22
FAC2MPgood46
FALAP119 Clearner_FMC0_122.88MHZ_P 36FALAN119 Clearner_FMC0_122.88MHZ_N 36
FA_LA_DEVCLK_P 21FA_LA_DEVCLK_N 21
FALAP3219 FALAN3219
FALAP3319 FALAN3319 PCIEA_EP_PERSTn 41PCIEA_WAKEn 41
FALAP33_FPGA 21FALAN33_FPGA 21
FALAP32_FPGA 21FALAN32_FPGA 21
FMCA_DC_3V3
FMCA_DC_3V3
FMCA_DC_3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
19 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
19 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
19 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C223 10uF
R1361.00K
R866DNI
R862DNI
R137DNI
R8640
C220 10uF
J11C
ASP-184329-01
HB_N0_CCK26
HB_N1J25
HB_N10K32
HB_N11 J31
HB_N12 F32
HB_N13 E31
HB_N14 K35
HB_N15 J34
HB_N16 F35
HB_N17_CC K38
HB_N18 J37
HB_N19 E34
HB_N2F23
HB_N20 F38
HB_N21 E37
HB_N3E22
HB_N4F26
HB_N5E25
HB_N6_CCK29
HB_N7J28
HB_N8F29
HB_N9E28
HB_P0_CCK25
HB_P1J24
HB_P10K31
HB_P11 J30
HB_P12 F31
HB_P13 E30
HB_P14 K34
HB_P15 J33
HB_P16 F34
HB_P17_CC K37
HB_P18 J36
HB_P19 E33
HB_P2F22
HB_P20 F37
HB_P21 E36
HB_P3E21
HB_P4F25
HB_P5E24
HB_P6_CCK28
HB_P7J27
HB_P8F28
HB_P9E27
R8600
R2280
R1401.00K
J11A
ASP-184329-01
LA_N0_CCG7
LA_N1_CCD9
LA_N10C15
LA_N11H17
LA_N12G16
LA_N13D18
LA_N14C19
LA_N15H20
LA_N16 G19
LA_N17_CC D21
LA_N18_CC C23
LA_N19 H23LA_N2H8
LA_N20 G22
LA_N21 H26
LA_N22 G25
LA_N23 D24
LA_N24 H29
LA_N25 G28
LA_N26 D27
LA_N27 C27
LA_N28 H32
LA_N29 G31
LA_N3G10
LA_N30 H35
LA_N31 G34
LA_N32 H38
LA_N33 G37
LA_N4H11
LA_N5D12
LA_N6C11
LA_N7H14
LA_N8G13
LA_N9D15
LA_P0_CCG6
LA_P1_CCD8
LA_P10C14
LA_P11H16
LA_P12G15
LA_P13D17
LA_P14C18
LA_P15H19
LA_P16 G18
LA_P17_CC D20
LA_P18_CC C22
LA_P19 H22LA_P2H7
LA_P20 G21
LA_P21 H25
LA_P22 G24
LA_P23 D23
LA_P24 H28
LA_P25 G27
LA_P26 D26
LA_P27 C26
LA_P28 H31
LA_P29 G30
LA_P3G9
LA_P30 H34
LA_P31 G33
LA_P32 H37
LA_P33 G36
LA_P4H10
LA_P5D11
LA_P6C10
LA_P7H13
LA_P8G12
LA_P9D14
C225 10uF
C221 10uF
J11D
ASP-184329-01
DP0_C2M_NC3 DP0_C2M_PC2DP0_M2C_N C7DP0_M2C_P C6
DP1_C2M_NA23 DP1_C2M_PA22DP1_M2C_N A3DP1_M2C_P A2
DP2_C2M_NA27 DP2_C2M_PA26DP2_M2C_N A7DP2_M2C_P A6
DP3_C2M_NA31 DP3_C2M_PA30DP3_M2C_N A11DP3_M2C_P A10
DP4_C2M_NA35 DP4_C2M_PA34DP4_M2C_N A15DP4_M2C_P A14
DP5_C2M_NA39 DP5_C2M_PA38DP5_M2C_N A19DP5_M2C_P A18
DP6_C2M_NB37 DP6_C2M_PB36DP6_M2C_N B17DP6_M2C_P B16
DP7_C2M_NB33 DP7_C2M_PB32DP7_M2C_N B13DP7_M2C_P B12
DP8_C2M_NB29 DP8_C2M_PB28DP8_M2C_N B9DP8_M2C_P B8
DP9_C2M_NB25 DP9_C2M_PB24DP9_M2C_N B5DP9_M2C_P B4
GBTCLK0_M2C_N D5GBTCLK0_M2C_P D4
GBTCLK1_M2C_N B21GBTCLK1_M2C_P B20
DP10_C2M_PZ24DP10_C2M_NZ25DP11_C2M_PY26DP11_C2M_NY27DP12_C2M_PZ28DP12_C2M_NZ29DP13_C2M_PY30DP13_C2M_NY31DP14_C2M_PM18DP14_C2M_NM19DP15_C2M_PM22DP15_C2M_NM23DP16_C2M_PM26DP16_C2M_NM27DP17_C2M_PM30DP17_C2M_NM31DP18_C2M_PM34DP18_C2M_NM35DP19_C2M_PM38DP19_C2M_NM39DP20_C2M_PZ8DP20_C2M_NZ9DP21_C2M_PY6DP21_C2M_NY7DP22_C2M_PZ4DP22_C2M_NZ5DP23_C2M_PY2DP23_C2M_NY3
DP10_M2C_P Y10DP10_M2C_N Y11DP11_M2C_P Z12DP11_M2C_N Z13DP12_M2C_P Y14DP12_M2C_N Y15DP13_M2C_P Z16DP13_M2C_N Z17DP14_M2C_P Y18DP14_M2C_N Y19DP15_M2C_P Y22DP15_M2C_N Y23DP16_M2C_P Z32DP16_M2C_N Z33DP17_M2C_P Y34DP17_M2C_N Y35DP18_M2C_P Z36DP18_M2C_N Z37DP19_M2C_P Y38DP19_M2C_N Y39DP20_M2C_P M14DP20_M2C_N M15DP21_M2C_P M10DP21_M2C_N M11DP22_M2C_P M6DP22_M2C_N M7DP23_M2C_P M2DP23_M2C_N M3
GBTCLK2_M2C_P L12GBTCLK2_M2C_N L13
GBTCLK3_M2C_PL8GBTCLK3_M2C_NL9GBTCLK4_M2C_PL4GBTCLK4_M2C_NL5GBTCLK5_M2C_PZ20GBTCLK5_M2C_NZ21
R139DNI
R2290
C224 10uF
R865DNI
C226 1uF
C228 1uF
R233DNI
J11E
ASP-184329-01
CLK_DIRB1 CLK0_M2C_N H5CLK0_M2C_P H4
CLK1_M2C_N G3CLK1_M2C_P G2CLK2_BIDIR_NK5 CLK2_BIDIR_PK4
CLK3_BIDIR_NJ3 CLK3_BIDIR_PJ2
GA0C34GA1D35
PG_C2MD1 PG_M2C F1
PRSNT_M2C_LH2
RES0 B40
SCLC30 SDAC31
TCK D29TDI D30TDO D31TMS D33TRST_L D34
3P3VAUXD32
3P3V0D403P3V1C393P3V2D363P3V3D38
12P0V0C3512P0V1C37
VADJ0 E39VADJ1 F40VADJ2 G39VADJ3 H40
VIO_B_M2C_0 K40VIO_B_M2C_1 J39
VREF_B_M2C K1VREF_A_M2C H1
3P3V4Z40
12P0V4L4012P0V2L3612P0V3L37
RES1 L1
REFCLK_M2C_PL24REFCLK_M2C_NL25
SYNC_C2M_P L16SYNC_C2M_N L17
HSPC_PRSNT_M2C_LZ1RES2 L32RES3 L33
REFCLK_C2M_PL20REFCLK_C2M_NL21
SYNC_M2C_N L29SYNC_M2C_P L28
R861DNI
R141
100K
R8630
R142DNI
R8590
J11G
ASP-184329-01
GND119M1GND160M4GND161M5GND162M8GND163M9GND164M12GND165M13GND166M16GND167M17GND168M20GND169M21GND170M24GND171M25GND172M28GND173M29GND174M32GND175M33GND176M36GND177M37GND178M40GND179L2GND180L3GND181L6GND182L7GND183L10GND184L11GND185L14GND186L15GND187L18GND188L19GND189L22GND190L23GND191L26GND192L27GND193L30GND194L31GND195L34GND196L35GND197L38GND198L39
GND219 Z2GND220 Z3GND221 Z6GND222 Z7GND223 Z10GND224 Z11GND225 Z14GND226 Z15GND227 Z18GND228 Z19GND229 Z22GND230 Z23GND231 Z26GND232 Z27GND233 Z30GND234 Z31GND235 Z34GND236 Z35GND237 Z38GND238 Z39
GND200 Y4GND201 Y5GND202 Y8GND203 Y9GND204 Y12GND205 Y13GND206 Y16GND207 Y17GND208 Y20GND209 Y21GND210 Y24GND211 Y25GND212 Y28GND213 Y29GND214 Y32GND215 Y33GND216 Y36GND217 Y37GND218 Y40
GND199 Y1
R232DNI
C227 1uF
J11F
ASP-184329-01
GND8K2GND9K3GND10K6GND11K9GND12K12GND13K15GND14K18GND15K21GND16K24GND17K27GND18K30GND19K33GND20K36GND21K39GND22J1GND23J4GND24J5GND25J8GND26J11GND27J14GND28J17GND29J20GND30J23GND31J26GND32J29GND33J32GND34J35GND35J38GND36J40GND37H3GND38H6GND39H9GND40H12GND41H15GND42H18GND43H21GND44H24GND45H27GND46H30GND47H33GND48H36GND49H39GND50D2GND51D3GND52D6GND53D7GND54D10GND55D13GND56D16GND57D19GND58D22GND59D25GND60D28GND61D37GND62D39GND63C1GND64C4GND65C5GND66C8GND67C9GND68C12GND69C13GND70C16GND71C17GND72C20GND73C21GND74C24GND75C25GND76C28GND77C29GND78C32GND79C33 GND118 C36GND117 C38GND116 C40GND115 B2GND114 B3GND113 B6GND112 B7GND111 B10GND110 B11GND159 B14GND158 B15GND157 B18GND156 B19GND155 B22GND154 B23GND153 B26GND152 B27GND151 B30GND150 B31GND149 B34GND148 B35GND147 B38GND146 B39GND145 A1GND144 A4GND143 A5GND142 A8GND141 A9GND140 A12GND139 A13GND138 A16GND137 A17GND136 A20GND135 A21GND134 A24GND133 A25GND132 A28GND131 A29GND130 A32GND129 A33GND128 A36GND127 A37GND126 A40GND125 G1GND124 G4GND123 G5GND122 G8GND121 G11GND120 G14GND109 G17GND108 G20GND107 G23GND106 G26GND105 G29GND104 G32GND103 G35GND102 G38GND101 G40GND100 F2GND99 F3GND98 F6GND97 F9GND96 F12GND95 F15GND94 F18GND93 F21GND92 F24GND91 F27GND90 F30GND89 F33GND88 F36GND87 F39GND86 E1GND85 E4GND84 E5GND83 E8GND82 E11GND81 E14GND80 E17GND0E20GND1E23GND2E26GND3E29
GND5E32GND6E35GND4E38
GND7E40
R138 DNI
C222 10uF
J11B
ASP-184329-01
HA_N0_CCF5
HA_N1_CCE3
HA_N10K14
HA_N11J13
HA_N12 F14
HA_N13 E13
HA_N14 J16
HA_N15 F17
HA_N16 E16
HA_N17_CC K17
HA_N18 J19
HA_N19 F20
HA_N2K8
HA_N20 E19
HA_N21 K20
HA_N22 J22
HA_N23 K23
HA_N3J7
HA_N4F8
HA_N5E7
HA_N6K11
HA_N7J10
HA_N8F11
HA_N9E10
HA_P0_CCF4
HA_P1_CCE2
HA_P10K13
HA_P11J12
HA_P12 F13
HA_P13 E12
HA_P14 J15
HA_P15 F16
HA_P16 E15
HA_P17_CC K16
HA_P18 J18
HA_P19 F19
HA_P2K7
HA_P20 E18
HA_P21 K19
HA_P22 J21
HA_P23 K22
HA_P3J6
HA_P4F7
HA_P5E6
HA_P6K10
HA_P7J9
HA_P8F10
HA_P9E9
FAGA1 FAGA0
FAGA0FAGA1
FAPG_C2M
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Stratix 10 XCVR Banks - 1C/D/E/F
FAD0M2CP19 FAD0M2CN19 FAD1M2CP19 FAD1M2CN19FAD2M2CP19 FAD2M2CN19 FAD3M2CP19 FAD3M2CN19 FAD4M2CP19FAD4M2CN19 FAD5M2CP19 FAD5M2CN19
FAD6M2CP19 FAD6M2CN19FAD7M2CP19 FAD7M2CN19 FAD8M2CP19 FAD8M2CN19 FAD9M2CP19FAD9M2CN19 FAD10M2CP19 FAD10M2CN19 FAD11M2CP19 FAD11M2CN19
FAD12M2CP 19FAD12M2CN 19FAD13M2CP 19FAD13M2CN 19FAD14M2CP 19FAD14M2CN 19FAD15M2CP 19FAD15M2CN 19FAD16M2CP 19FAD16M2CN 19FAD17M2CP 19FAD17M2CN 19
FAD18M2CP 19FAD18M2CN 19FAD19M2CP 19FAD19M2CN 19FAD20M2CP 19FAD20M2CN 19FAD21M2CP 19FAD21M2CN 19FAD22M2CP 19FAD22M2CN 19FAD23M2CP 19FAD23M2CN 19
FAD0C2MP19FAD0C2MN19 FAD1C2MP19 FAD1C2MN19 FAD2C2MP19 FAD2C2MN19FAD3C2MP19 FAD3C2MN19 FAD4C2MP19 FAD4C2MN19 FAD5C2MP19FAD5C2MN19
FAD6C2MP19 FAD6C2MN19 FAD7C2MP19 FAD7C2MN19FAD8C2MP19 FAD8C2MN19 FAD9C2MP19 FAD9C2MN19 FAD10C2MP19
FAD10C2MN19 FAD11C2MP19 FAD11C2MN19
FAD12C2MP 19FAD12C2MN 19FAD13C2MP 19FAD13C2MN 19FAD14C2MP 19FAD14C2MN 19FAD15C2MP 19FAD15C2MN 19FAD16C2MP 19FAD16C2MN 19FAD17C2MP 19FAD17C2MN 19
FAD18C2MP 19FAD18C2MN 19FAD19C2MP 19FAD19C2MN 19FAD20C2MP 19FAD20C2MN 19FAD21C2MP 19FAD21C2MN 19FAD22C2MP 19FAD22C2MN 19FAD23C2MP 19FAD23C2MN 19
FAGBTCLK5M2CN 19FAGBTCLK5M2CP 19
FAGBTCLK4M2CN 19FAGBTCLK4M2CP 19
FAGBTCLK3M2CN19 FAGBTCLK3M2CP19
FAGBTCLK2M2CN 19FAGBTCLK2M2CP 19
FAGBTCLK1M2CN19FAGBTCLK1M2CP19
FAGBTCLK0M2CN19 FAGBTCLK0M2CP19
Clearner_XVRR_122.88MHZ_P36 Clearner_XVRR_122.88MHZ_N36
REFCLK0_FMC_P 34REFCLK0_FMC_N 34
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
20 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
20 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
20 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
BANK 1
DBAN
K 1C
BANK 1
EBAN
K 1F
1SX280LU3F50E3VGS1
U15AREFCLK_GXBL1C_CHTPAP41REFCLK_GXBL1C_CHTNAP40
GXBL1C_TX_CH5NBC46GXBL1C_TX_CH5PBC47
GXBL1C_RX_CH5N, GXBL1C_REFCLK5NBD44GXBL1C_RX_CH5P, GXBL1C_REFCLK5PBD45
GXBL1C_TX_CH4NBF48GXBL1C_TX_CH4PBF49
GXBL1C_RX_CH4N, GXBL1C_REFCLK4NBC42GXBL1C_RX_CH4P, GXBL1C_REFCLK4PBC43
GXBL1C_TX_CH3NBE46GXBL1C_TX_CH3PBE47
GXBL1C_RX_CH3N, GXBL1C_REFCLK3NBE42GXBL1C_RX_CH3P, GXBL1C_REFCLK3PBE43
GXBL1C_TX_CH2NBG46GXBL1C_TX_CH2PBG47
GXBL1C_RX_CH2N, GXBL1C_REFCLK2NBG42GXBL1C_RX_CH2P, GXBL1C_REFCLK2PBG43
GXBL1C_TX_CH1NBF44GXBL1C_TX_CH1PBF45
GXBL1C_RX_CH1N, GXBL1C_REFCLK1NBJ42GXBL1C_RX_CH1P, GXBL1C_REFCLK1PBJ43
GXBL1C_TX_CH0NBJ45GXBL1C_TX_CH0PBJ46
GXBL1C_RX_CH0N, GXBL1C_REFCLK0NBH40GXBL1C_RX_CH0P, GXBL1C_REFCLK0PBH41
REFCLK_GXBL1C_CHBPAT41REFCLK_GXBL1C_CHBNAT40
REFCLK_GXBL1D_CHTPAK41REFCLK_GXBL1D_CHTNAK40
GXBL1D_TX_CH5NAU46GXBL1D_TX_CH5PAU47
GXBL1D_RX_CH5N, GXBL1D_REFCLK5NAV44GXBL1D_RX_CH5P, GXBL1D_REFCLK5PAV45
GXBL1D_TX_CH4NAY48GXBL1D_TX_CH4PAY49
GXBL1D_RX_CH4N, GXBL1D_REFCLK4NAU42GXBL1D_RX_CH4P, GXBL1D_REFCLK4PAU43
GXBL1D_TX_CH3NAW46GXBL1D_TX_CH3PAW47
GXBL1D_RX_CH3N, GXBL1D_REFCLK3NAY44GXBL1D_RX_CH3P, GXBL1D_REFCLK3PAY45
GXBL1D_TX_CH2NBB48GXBL1D_TX_CH2PBB49
GXBL1D_RX_CH2N, GXBL1D_REFCLK2NAW42GXBL1D_RX_CH2P, GXBL1D_REFCLK2PAW43
GXBL1D_TX_CH1NBA46GXBL1D_TX_CH1PBA47
GXBL1D_RX_CH1N, GXBL1D_REFCLK1NBB44GXBL1D_RX_CH1P, GXBL1D_REFCLK1PBB45
GXBL1D_TX_CH0NBD48GXBL1D_TX_CH0PBD49
GXBL1D_RX_CH0N, GXBL1D_REFCLK0NBA42GXBL1D_RX_CH0P, GXBL1D_REFCLK0PBA43
REFCLK_GXBL1D_CHBPAM41REFCLK_GXBL1D_CHBNAM40
REFCLK_GXBL1E_CHTP AF41REFCLK_GXBL1E_CHTN AF40
GXBL1E_TX_CH5N AM48GXBL1E_TX_CH5P AM49
GXBL1E_RX_CH5N, GXBL1E_REFCLK5N AK44GXBL1E_RX_CH5P, GXBL1E_REFCLK5P AK45
GXBL1E_TX_CH4N AN46GXBL1E_TX_CH4P AN47
GXBL1E_RX_CH4N, GXBL1E_REFCLK4N AM44GXBL1E_RX_CH4P, GXBL1E_REFCLK4P AM45
GXBL1E_TX_CH3N AP48GXBL1E_TX_CH3P AP49
GXBL1E_RX_CH3N, GXBL1E_REFCLK3N AN42GXBL1E_RX_CH3P, GXBL1E_REFCLK3P AN43
GXBL1E_TX_CH2N AT48GXBL1E_TX_CH2P AT49
GXBL1E_RX_CH2N, GXBL1E_REFCLK2N AP44GXBL1E_RX_CH2P, GXBL1E_REFCLK2P AP45
GXBL1E_TX_CH1N AR46GXBL1E_TX_CH1P AR47
GXBL1E_RX_CH1N, GXBL1E_REFCLK1N AT44GXBL1E_RX_CH1P, GXBL1E_REFCLK1P AT45
GXBL1E_TX_CH0N AV48GXBL1E_TX_CH0P AV49
GXBL1E_RX_CH0N, GXBL1E_REFCLK0N AR42GXBL1E_RX_CH0P, GXBL1E_REFCLK0P AR43
REFCLK_GXBL1E_CHBP AH41REFCLK_GXBL1E_CHBN AH40
REFCLK_GXBL1F_CHTP AK38REFCLK_GXBL1F_CHTN AK37
GXBL1F_TX_CH5N AG46GXBL1F_TX_CH5P AG47
GXBL1F_RX_CH5N, GXBL1F_REFCLK5N AE42GXBL1F_RX_CH5P, GXBL1F_REFCLK5P AE43
GXBL1F_TX_CH4N AF48GXBL1F_TX_CH4P AF49
GXBL1F_RX_CH4N, GXBL1F_REFCLK4N AG42GXBL1F_RX_CH4P, GXBL1F_REFCLK4P AG43
GXBL1F_TX_CH3N AJ46GXBL1F_TX_CH3P AJ47
GXBL1F_RX_CH3N, GXBL1F_REFCLK3N AF44GXBL1F_RX_CH3P, GXBL1F_REFCLK3P AF45
GXBL1F_TX_CH2N AH48GXBL1F_TX_CH2P AH49
GXBL1F_RX_CH2N, GXBL1F_REFCLK2N AJ42GXBL1F_RX_CH2P, GXBL1F_REFCLK2P AJ43
GXBL1F_TX_CH1N AL46GXBL1F_TX_CH1P AL47
GXBL1F_RX_CH1N, GXBL1F_REFCLK1N AH44GXBL1F_RX_CH1P, GXBL1F_REFCLK1P AH45
GXBL1F_TX_CH0N AK48GXBL1F_TX_CH0P AK49
GXBL1F_RX_CH0N, GXBL1F_REFCLK0N AL42GXBL1F_RX_CH0P, GXBL1F_REFCLK0P AL43
REFCLK_GXBL1F_CHBP AM38REFCLK_GXBL1F_CHBN AM37
![Page 21: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/21.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Stratix 10 Banks 2 A/B/C
FALAP019 FALAN019FA_LA_DEVCLK_N19 FA_LA_DEVCLK_P19
FALAP2319 FALAN2319
FALAP1019 FALAN1019
FALAP2919 FALAN2919
FALAP1419
FALAP3019
FALAN1419
FALAN3019
FALAP32_FPGA19 FALAN32_FPGA19
FALAP33_FPGA19 FALAN33_FPGA19
FBLAN0 23FBLAP0 23FB_LA_DEVCLK_P 23FB_LA_DEVCLK_N 23
FAHBP819 FAHBN819
FPGA_156.25MHZ_REF_P36 FPGA_156.25MHZ_REF_N36
FPGA_122.88MHZ_REF_P36 FPGA_122.88MHZ_REF_N36
Clearner_FPGA_122.88MHZ_N36 Clearner_FPGA_122.88MHZ_P36
CLK_3An32 CLK_3Ap32
referenceclk_136 referenceclk_236
FBLAN2 23FBLAP2 23
FBLAN3 23FBLAP3 23
FBLAN4 23FBLAP4 23
FBLAN7 23FBLAP7 23
FBLAN8 23FBLAP8 23
FBLAN9 23FBLAP9 23
FBLAN10 23FBLAP10 23
FBLAN11 23FBLAP11 23
FBLAN20 23FBLAP20 23
FBLAN12 23FBLAP12 23
FBLAN13 23FBLAP13 23
FBLAN15 23FBLAP15 23
FBLAN16 23FBLAP16 23
FBLAN18 23FBLAP18 23
FBLAN19 23FBLAP19 23
FBLAN22 23FBLAP22 23
FBLAN23 23FBLAP23 23
FBLAN26 23FBLAP26 23
FBLAN27 23FBLAP27 23
FBLAN6 23FBLAP6 23FBLAN5 23FBLAP5 23
FAHBN319 FAHBP319
FAHBN219 FAHBP219
FAHBP919 FAHBN919
FALAN2219 FALAP2219
FAHBP1219 FAHBN1219
FALAN3119 FALAP3119
FAHBN2119 FAHBP2119
FAHBN2019 FAHBP2019
FAHBN719 FAHBP719
FAHBN019 FAHBP019
FAHBP1119 FAHBN1119
FAHBP1019 FAHBN1019
FAHBP1519 FAHBN1519
FAHBN1819 FAHBP1819FAHBP1419 FAHBN1419
FAHAN319 FAHAP319
FAHAN719 FAHAP719
FALAN419 FALAP419
FALAN319 FALAP319
FAHAN819 FAHAP819
FALAN919 FALAP919
FALAN619 FALAP619
FALAN519 FALAP519
FAHAN1319 FAHAP1319
FALAN819 FALAP819
FALAN719 FALAP719
FAHAN1219 FAHAP1219
FAHAN919 FAHAP919
FAHBN419 FAHBP419
FALAN1219 FALAP1219
FAHAN519 FAHAP519
FAHBN1719 FAHBP1719
FAHBP519 FAHBN519
FAHAN419 FAHAP419
FAHBP13 19FAHBN13 19
IO_1V8
Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardC
21 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardC
21 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardC
21 71Friday, May 05, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C156310uF
R853DNI
C15640.1uF
R83710K
R8310
R83849.9
R8320
R8010
R9200
R8020
R9210
BANK 2
A
BANK 2
C
BANK 2
B
1SX280LU3F50E3VGS1
U15CIO, LVDS2A_1N, DQ44AU28IO, LVDS2A_1P, DQ44AU29IO, LVDS2A_2N, DQ44AW29IO, LVDS2A_2P, DQ44AY29IO, LVDS2A_3N, DQ44BB28IO, LVDS2A_3P, DQ44BA29IO, LVDS2A_4N, DQSN44AV28IO, LVDS2A_4P, DQS44AW28IO, LVDS2A_5N, DQ44AV30IO, LVDS2A_5P, DQ44AU30IO, LVDS2A_6N, DQ44AT30IO, LVDS2A_6P, DQ44AT29IO, LVDS2A_7N, DQ45BA30IO, LVDS2A_7P, DQ45BA31IO, LVDS2A_8N, DQ45BB29IO, LVDS2A_8P, DQ45BB30IO, LVDS2A_9N, DQ45BC32IO, LVDS2A_9P, DQ45BC31IO, PLL_2A_CLKOUT1N, LVDS2A_10N, DQSN45BB32IO, PLL_2A_CLKOUT1P, PLL_2A_CLKOUT1, PLL_2A_FBN, LVDS2A_10P, DQS45BA32IO, LVDS2A_11N, DQ45AY32IO, RZQ_2A, LVDS2A_11P, DQ45AY31IO, CLK_2A_1N, LVDS2A_12N, DQ45AW31IO, CLK_2A_1P, LVDS2A_12P, DQ45AW30IO, CLK_2A_0N, LVDS2A_13N, DQ46BD31IO, CLK_2A_0P, LVDS2A_13P, DQ46BE31IO, LVDS2A_14N, DQ46BE29IO, LVDS2A_14P, DQ46BD29IO, PLL_2A_CLKOUT0N, LVDS2A_15N, DQ46BF30IO, PLL_2A_CLKOUT0P, PLL_2A_CLKOUT0, PLL_2A_FBP, PLL_2A_FB0, LVDS2A_15P, DQ46BF31IO, LVDS2A_16N, DQSN46BD30IO, LVDS2A_16P, DQS46BC30IO, LVDS2A_17N, DQ46BG28IO, LVDS2A_17P, DQ46BG29IO, LVDS2A_18N, DQ46BH30IO, LVDS2A_18P, DQ46BG30IO, LVDS2A_19N, DQ47BE28IO, LVDS2A_19P, DQ47BF29IO, LVDS2A_20N, DQ47BJ29IO, LVDS2A_20P, DQ47BJ30IO, LVDS2A_21N, DQ47BH28IO, LVDS2A_21P, DQ47BJ28IO, LVDS2A_22N, DQSN47BJ31IO, LVDS2A_22P, DQS47BH31IO, LVDS2A_23N, DQ47BF32IO, LVDS2A_23P, DQ47BE32IO, LVDS2A_24N, DQ47BG32IO, LVDS2A_24P, DQ47BH32
IO, LVDS2B_1N, DQ40BD36IO, LVDS2B_1P, DQ40BE36IO, LVDS2B_2N, DQ40BC35IO, LVDS2B_2P, DQ40BC36IO, LVDS2B_3N, DQ40BB34IO, LVDS2B_3P, DQ40BB33IO, LVDS2B_4N, DQSN40BD35IO, LVDS2B_4P, DQS40BD34IO, LVDS2B_5N, DQ40BC33IO, LVDS2B_5P, DQ40BD33IO, LVDS2B_6N, DQ40BF35IO, LVDS2B_6P, DQ40BF36IO, LVDS2B_7N, DQ41BF34IO, LVDS2B_7P, DQ41BG34IO, LVDS2B_8N, DQ41BJ34IO, LVDS2B_8P, DQ41BJ33IO, LVDS2B_9N, DQ41BG35IO, LVDS2B_9P, DQ41BH35IO, PLL_2B_CLKOUT1N, LVDS2B_10N, DQSN41BE34IO, PLL_2B_CLKOUT1P, PLL_2B_CLKOUT1, PLL_2B_FBN, LVDS2B_10P, DQS41BE33IO, LVDS2B_11N, DQ41BJ36IO, RZQ_2B, LVDS2B_11P, DQ41BJ35IO, CLK_2B_1N, LVDS2B_12N, DQ41BG33IO, CLK_2B_1P, LVDS2B_12P, DQ41BH33IO, CLK_2B_0N, LVDS2B_13N, DQ42AV36IO, CLK_2B_0P, LVDS2B_13P, DQ42AW36IO, LVDS2B_14N, DQ42AY33IO, LVDS2B_14P, DQ42AW33IO, PLL_2B_CLKOUT0N, LVDS2B_15N, DQ42BA35IO, PLL_2B_CLKOUT0P, PLL_2B_CLKOUT0, PLL_2B_FBP, PLL_2B_FB0, LVDS2B_15P, DQ42BB35IO, LVDS2B_16N, DQSN42AW35IO, LVDS2B_16P, DQS42AW34IO, LVDS2B_17N, DQ42AY36IO, LVDS2B_17P, DQ42BA36IO, LVDS2B_18N, DQ42BA34IO, LVDS2B_18P, DQ42AY34IO, LVDS2B_19N, DQ43AT32IO, LVDS2B_19P, DQ43AU32IO, LVDS2B_20N, DQ43AV32IO, LVDS2B_20P, DQ43AV33IO, LVDS2B_21N, DQ43AT34IO, LVDS2B_21P, DQ43AT35IO, LVDS2B_22N, DQSN43AR31IO, LVDS2B_22P, DQS43AR32IO, LVDS2B_23N, DQ43AU35IO, LVDS2B_23P, DQ43AV35IO, LVDS2B_24N, DQ43AU33IO, LVDS2B_24P, DQ43AU34
IO, LVDS2C_1N, DQ36 AY40IO, LVDS2C_1P, DQ36 BA40IO, LVDS2C_2N, DQ36 BA39IO, LVDS2C_2P, DQ36 BB39IO, LVDS2C_3N, DQ36 BB40IO, LVDS2C_3P, DQ36 BC40
IO, LVDS2C_4N, DQSN36 BD38IO, LVDS2C_4P, DQS36 BD39
IO, LVDS2C_5N, DQ36 BC38IO, LVDS2C_5P, DQ36 BB38IO, LVDS2C_6N, DQ36 BC37IO, LVDS2C_6P, DQ36 BB37IO, LVDS2C_7N, DQ37 BD40IO, LVDS2C_7P, DQ37 BE40IO, LVDS2C_8N, DQ37 BG38IO, LVDS2C_8P, DQ37 BG37IO, LVDS2C_9N, DQ37 BE38IO, LVDS2C_9P, DQ37 BE39
IO, PLL_2C_CLKOUT1N, LVDS2C_10N, DQSN37 BE37IO, PLL_2C_CLKOUT1P, PLL_2C_CLKOUT1, PLL_2C_FBN, LVDS2C_10P, DQS37 BF37
IO, LVDS2C_11N, DQ37 BF39IO, RZQ_2C, LVDS2C_11P, DQ37 BF40
IO, CLK_2C_1N, LVDS2C_12N, DQ37 BH37IO, CLK_2C_1P, LVDS2C_12P, DQ37 BH36IO, CLK_2C_0N, LVDS2C_13N, DQ38 AW39IO, CLK_2C_0P, LVDS2C_13P, DQ38 AW38
IO, LVDS2C_14N, DQ38 BA37IO, LVDS2C_14P, DQ38 AY37
IO, PLL_2C_CLKOUT0N, LVDS2C_15N, DQ38 AV40IO, PLL_2C_CLKOUT0P, PLL_2C_CLKOUT0, PLL_2C_FBP, PLL_2C_FB0, LVDS2C_15P, DQ38 AW40
IO, LVDS2C_16N, DQSN38 AY39IO, LVDS2C_16P, DQS38 AY38
IO, LVDS2C_17N, DQ38 AU37IO, LVDS2C_17P, DQ38 AU38IO, LVDS2C_18N, DQ38 AV38IO, LVDS2C_18P, DQ38 AV37IO, LVDS2C_19N, DQ39 AR34IO, LVDS2C_19P, DQ39 AP35IO, LVDS2C_20N, DQ39 AR36IO, LVDS2C_20P, DQ39 AP36IO, LVDS2C_21N, DQ39 AP33IO, LVDS2C_21P, DQ39 AN33
IO, LVDS2C_22N, DQSN39 AT36IO, LVDS2C_22P, DQS39 AT37
IO, LVDS2C_23N, DQ39 AR37IO, LVDS2C_23P, DQ39 AT38IO, LVDS2C_24N, DQ39 AR33IO, LVDS2C_24P, DQ39 AP34
R83510K
R7970
R83649.9
R852DNI
R7980
clock1_outnclock1_outp
clock2_outnclock2_outp
inputref_clk0ninputref_clk0pinputref_clk1ninputref_clk1p
![Page 22: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/22.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Stratix 10 Banks - 3 A/B/C
100MHz Clock
AVST_D041 AVST_D141 AVST_D241 AVST_D341 AVST_D441 AVST_D541 AVST_D641 AVST_D741 AVST_D841 AVST_D941 AVST_D1041 AVST_D1141 AVST_D1241 AVST_D1341 AVST_D1441 AVST_D1541
AVST_VALID41
AVST_CLK41
ENETA_MDIO10 ENETA_MDC10 ENETB_MDIO11 ENETB_MDC11ENET_DISABLE_N47
IO_1V8 12,21,25,29,30,32,33,34,36,39,40,43,63,64,65,66,68
ENETA_INTn10ENETB_INTn11 ENETA_RESETn10
ENETB_RESETn11
Direct USB D08 Direct USB D18 Direct USB D28 Direct USB D38 Direct USB D48 Direct USB D58 Direct USB D68 Direct USB D78 Direct USB_RDn8 Direct USB_Wrn8 Direct USB_OEn8 Direct USB_RESETn8 Direct USB_EMPTY8 Direct USB_FULL8 Direct USB_SDA8 Direct USB_SCL8
FAHAP2 19FAHAN2 19
FPGA_MAX10_IO041FPGA_MAX10_IO141FPGA_MAX10_IO241FPGA_MAX10_IO341
ClK_50M_FPGA41FPGA_MAX10_IO541FPGA_MAX10_IO641FPGA_MAX10_IO741FPGA_MAX10_IO841FPGA_MAX10_IO941FPGA_MAX10_IO1041FPGA_MAX10_IO1141FPGA_MAX10_IO1241FPGA_MAX10_IO1341FPGA_MAX10_IO1441 Global_resetn41
Direct_USB_CLK8
FPGA_PR_DONE41FPGA_PR_ERROR41
FPGA_PR_REQUEST41
IO_2V5 10,11,12,26,27,32,38,43,68
FACLK2BIDIRP19 FACLK2BIDIRN19
FACLK3BIDIRP19 FACLK3BIDIRN19
FACLKDIR19
FACLK1M2CN 19FACLK1M2CP 19FACLK0M2CP 19FACLK0M2CN 19
FASYNM2CN19 FASYNM2CP19
CLKUSR32
FAHAP2119 FAHAN2119
FALAN1119 FALAP1119
FALAN1519 FALAP1519
FAHAN15 19FAHAP15 19
FAHAN16 19FAHAP16 19
FAHAN19 19FAHAP19 19
FALAN13 19FALAP13 19
FALAN20 19FALAP20 19
FAHAN23 19FAHAP23 19FALAN19 19FALAP19 19
FAHBN1 19FAHBP1 19
FALAN21 19FALAP21 19
FALAN25 19FALAP25 19
FALAN24 19FALAP24 19
FALAN28 19FALAP28 19
FAHAN1819 FAHAP1819
FALAN18 19FALAP18 19
FALAN26 19FALAP26 19
FALAN27 19FALAP27 19
FAHAN6 19FAHAP6 19
FAHAP1419 FAHAN1419
FAHAN10 19FAHAP10 19FAHAP11 19FAHAN11 19
FALAN16 19FALAP16 19
FALAN2 19FALAP2 19
FAHAN1719 FAHAP1719
FAHBP1619 FAHBN1619
FAHAN22 19FAHAP22 19
FAHAN2019 FAHAP2019
FAHAN019 FAHAP019 FAHAN119 FAHAP119
FALAN1719 FALAP1719
ZQSFP_I2C_B_SDA 16,17ZQSFP_I2C_B_SCL 16,17
IO_3V3 14,15,16,17,25,26,29,30,31,32,34,35,36,37,38,43,57,69,70
Cleaner_SDA 36,38Cleaner_SCL 36,38
IO_2V5
IO_1V8
IO_1V8
IO_2V5 IO_1V8
IO_2V5
IO_1V8 IO_3V3
IO_1V8 IO_3V3
IO_1V8 IO_3V3
IO_1V8 IO_3V3
IO_3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
22 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
22 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
22 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R152 4.7K
R1008 10.0KR1011 10.0KR1010 10.0K
U107
FXMA2102UMX
A0 2A1 3B07
B16
VCCA 1GND 4
OE 5
VCCB8
C16590.1uF
C16620.1uF
R1012 10.0K
R148 4.7K
C2330.1uF
C2290.1uF
C2310.1uF
R151 4.7K
R10141.00kU20
MAX3378
VL 1IO VL1 2IO VL2 3IO VL3 4IO VL4 5
NC1 6GND 7
VCC14IO VCC113IO VCC212IO VCC311IO VCC410NC29/TS8
R1013 10.0KR1016 10.0KR1015 10.0K
U108
FXMA2102UMX
A0 2A1 3B07
B16
VCCA 1GND 4
OE 5
VCCB8
C16390.1uF
C16610.1uF
C2300.1uF
U21
MAX3378
VL 1IO VL1 2IO VL2 3IO VL3 4IO VL4 5
NC1 6GND 7
VCC14IO VCC113IO VCC212IO VCC311IO VCC410NC29/TS8
C2320.1uF
R150 4.7K
C2340.1uF
R153 4.7K
R1007 10.0K
R147 4.7KR149 4.7K
R154 4.7K
R10091.00k
BANK 3
A
BANK 3
C
BANK 3
B
1SX280LU3F50E3VGS1
U15EIO, LVDS3A_1N, DQ92, AVST_DATA0BD13IO, LVDS3A_1P, DQ92, AVST_DATA1BE13IO, LVDS3A_2N, DQ92, AVST_DATA2BF15IO, LVDS3A_2P, DQ92, AVST_DATA3BG15IO, LVDS3A_3N, DQ92, AVST_DATA4BE14IO, LVDS3A_3P, DQ92, AVST_DATA5BF14IO, LVDS3A_4N, DQSN92, AVST_DATA6BE16IO, LVDS3A_4P, DQS92, AVST_DATA7BF16IO, LVDS3A_5N, DQ92, AVST_DATA8BD16IO, LVDS3A_5P, DQ92, AVST_DATA9BC16IO, LVDS3A_6N, DQ92, AVST_DATA10BD14IO, LVDS3A_6P, DQ92, AVST_DATA11BD15IO, LVDS3A_7N, DQ93, AVST_DATA12BF12IO, LVDS3A_7P, DQ93, AVST_DATA13BG12IO, LVDS3A_8N, DQ93, AVST_DATA14BJ13IO, LVDS3A_8P, DQ93, AVST_DATA15BJ14IO, LVDS3A_9N, DQ93, AVST_DATA16BG13IO, LVDS3A_9P, DQ93, AVST_DATA17BG14IO, PLL_3A_CLKOUT1N, LVDS3A_10N, DQSN93, AVST_DATA18BH15IO, PLL_3A_CLKOUT1P, PLL_3A_CLKOUT1, PLL_3A_FBN, LVDS3A_10P, DQS93, AVST_DATA19BJ15IO, LVDS3A_11N, DQ93BH12IO, RZQ_3A, LVDS3A_11P, DQ93, AVST_VALIDBH13IO, CLK_3A_1N, LVDS3A_12N, DQ93, AVST_DATA20BH16IO, CLK_3A_1P, LVDS3A_12P, DQ93, AVST_DATA21BJ16IO, CLK_3A_0N, LVDS3A_13N, DQ94, AVST_DATA22AV15IO, CLK_3A_0P, LVDS3A_13P, DQ94, AVST_DATA23AW15IO, LVDS3A_14N, DQ94, AVST_DATA24BA15IO, LVDS3A_14P, DQ94, AVST_DATA25BA16IO, PLL_3A_CLKOUT0N, LVDS3A_15N, DQ94, AVST_DATA26AW14IO, PLL_3A_CLKOUT0P, PLL_3A_CLKOUT0, PLL_3A_FBP, PLL_3A_FB0, LVDS3A_15P, DQ94, AVST_DATA27AY14IO, LVDS3A_16N, DQSN94, AVST_DATA28BB14IO, LVDS3A_16P, DQS94, AVST_DATA29BA14IO, LVDS3A_17N, DQ94, AVST_DATA30BB15IO, LVDS3A_17P, DQ94, AVST_DATA31BC15IO, LVDS3A_18N, DQ94BB13IO, LVDS3A_18P, DQ94BC13IO, LVDS3A_19N, DQ95AV17IO, LVDS3A_19P, DQ95AV16IO, LVDS3A_20N, DQ95BA17IO, LVDS3A_20P, DQ95AY17IO, LVDS3A_21N, DQ95AY16IO, LVDS3A_21P, DQ95AW16IO, LVDS3A_22N, DQSN95AV18IO, LVDS3A_22P, DQS95AW18IO, LVDS3A_23N, DQ95BC17IO, LVDS3A_23P, DQ95BB17IO, LVDS3A_24N, DQ95AY18IO, LVDS3A_24P, DQ95, AVST_CLKAY19
IO, LVDS3B_1N, DQ88AP16IO, LVDS3B_1P, DQ88AP15IO, LVDS3B_2N, DQ88AU13IO, LVDS3B_2P, DQ88AV13IO, LVDS3B_3N, DQ88AU12IO, LVDS3B_3P, DQ88AT12IO, LVDS3B_4N, DQSN88AR13IO, LVDS3B_4P, DQS88AP12IO, LVDS3B_5N, DQ88AP14IO, LVDS3B_5P, DQ88AP13IO, LVDS3B_6N, DQ88AT14IO, LVDS3B_6P, DQ88AR14IO, LVDS3B_7N, DQ89AR18IO, LVDS3B_7P, DQ89AP18IO, LVDS3B_8N, DQ89AU14IO, LVDS3B_8P, DQ89AU15IO, LVDS3B_9N, DQ89AT16IO, LVDS3B_9P, DQ89AT15IO, PLL_3B_CLKOUT1N, LVDS3B_10N, DQSN89AR16IO, PLL_3B_CLKOUT1P, PLL_3B_CLKOUT1, PLL_3B_FBN, LVDS3B_10P, DQS89AR17IO, LVDS3B_11N, DQ89AN18IO, RZQ_3B, LVDS3B_11P, DQ89AN17IO, CLK_3B_1N, LVDS3B_12N, DQ89AU17IO, CLK_3B_1P, LVDS3B_12P, DQ89AT17IO, CLK_3B_0N, LVDS3B_13N, DQ90AV10IO, CLK_3B_0P, LVDS3B_13P, DQ90AW10IO, LVDS3B_14N, DQ90AY13IO, LVDS3B_14P, DQ90AW13IO, PLL_3B_CLKOUT0N, LVDS3B_15N, DQ90AV12IO, PLL_3B_CLKOUT0P, PLL_3B_CLKOUT0, PLL_3B_FBP, PLL_3B_FB0, LVDS3B_15P, DQ90AV11IO, LVDS3B_16N, DQSN90AY12IO, LVDS3B_16P, DQS90BA12IO, LVDS3B_17N, DQ90BA11IO, LVDS3B_17P, DQ90BA10IO, LVDS3B_18N, DQ90AW11IO, LVDS3B_18P, DQ90AY11IO, LVDS3B_19N, DQ91BC11IO, LVDS3B_19P, DQ91BD11IO, LVDS3B_20N, DQ91BB12IO, LVDS3B_20P, DQ91BC12IO, LVDS3B_21N, DQ91BB10IO, LVDS3B_21P, DQ91BC10IO, LVDS3B_22N, DQSN91BE11IO, LVDS3B_22P, DQS91BE12IO, LVDS3B_23N, DQ91BD10IO, LVDS3B_23P, DQ91BE10IO, LVDS3B_24N, DQ91BF10IO, LVDS3B_24P, DQ91BF11
IO, LVDS3C_1N, DQ84 BA21IO, LVDS3C_1P, DQ84 BA20IO, LVDS3C_2N, DQ84 BB20IO, LVDS3C_2P, DQ84 BC20IO, LVDS3C_3N, DQ84 BD21IO, LVDS3C_3P, DQ84 BC21
IO, LVDS3C_4N, DQSN84 AY21IO, LVDS3C_4P, DQS84 AW21
IO, LVDS3C_5N, DQ84 AW20IO, LVDS3C_5P, DQ84 AW19IO, LVDS3C_6N, DQ84 BA19IO, LVDS3C_6P, DQ84 BB19IO, LVDS3C_7N, DQ85 AR21IO, LVDS3C_7P, DQ85 AT21IO, LVDS3C_8N, DQ85 AU20IO, LVDS3C_8P, DQ85 AT20IO, LVDS3C_9N, DQ85 AP20IO, LVDS3C_9P, DQ85 AN20
IO, PLL_3C_CLKOUT1N, LVDS3C_10N, DQSN85 AP21IO, PLL_3C_CLKOUT1P, PLL_3C_CLKOUT1, PLL_3C_FBN, LVDS3C_10P, DQS85 AN21
IO, LVDS3C_11N, DQ85 AV20IO, RZQ_3C, LVDS3C_11P, DQ85 AV21
IO, CLK_3C_1N, LVDS3C_12N, DQ85 AT19IO, CLK_3C_1P, LVDS3C_12P, DQ85 AR19IO, CLK_3C_0N, LVDS3C_13N, DQ86 BE21IO, CLK_3C_0P, LVDS3C_13P, DQ86 BF21
IO, LVDS3C_14N, DQ86 BG20IO, LVDS3C_14P, DQ86 BF20
IO, PLL_3C_CLKOUT0N, LVDS3C_15N, DQ86 BD20IO, PLL_3C_CLKOUT0P, PLL_3C_CLKOUT0, PLL_3C_FBP, PLL_3C_FB0, LVDS3C_15P, DQ86 BD19
IO, LVDS3C_16N, DQSN86 BF19IO, LVDS3C_16P, DQS86 BE19
IO, LVDS3C_17N, DQ86 BB18IO, LVDS3C_17P, DQ86 BC18IO, LVDS3C_18N, DQ86 BD18IO, LVDS3C_18P, DQ86 BE18IO, LVDS3C_19N, DQ87 BG19IO, LVDS3C_19P, DQ87 BG18IO, LVDS3C_20N, DQ87 BH21IO, LVDS3C_20P, DQ87 BH20IO, LVDS3C_21N, DQ87 BH17IO, LVDS3C_21P, DQ87 BG17
IO, LVDS3C_22N, DQSN87 BJ20IO, LVDS3C_22P, DQS87 BJ19
IO, LVDS3C_23N, DQ87 BF17IO, LVDS3C_23P, DQ87 BE17IO, LVDS3C_24N, DQ87 BJ18IO, LVDS3C_24P, DQ87 BH18
ENETA_MDIO_BENETA_MDC_BENETB_MDIO_BENETB_MDC_B
ENETA_MDIO_BENETA_MDC_BENETB_MDIO_B
ENETA_INTn_BENETA_RESETn_BENETB_INTn_BENETB_RESETn_B
ENETA_INTn_B
ENETA_RESETn_BENETB_INTn_BENETB_RESETn_B
ENETB_MDC_B
Cleaner_I2C_SDACleaner_I2C_SCL
ZQSFP_I2C_SDAZQSFP_I2C_SCL
Cleaner_I2C_SCLCleaner_I2C_SDA
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FMC Port B
I2C Address: b' 101 0011
PCIE_PRSNTshort
FBLAP021 FBLAP16 21FBLAN021 FBLAN16 21FBLAP123 FBLAP17 25FBLAN123 FBLAN17 25FBLAP221 FBLAP18 21FBLAN221 FBLAN18 21FBLAP321 FBLAP19 21FBLAN321 FBLAN19 21FBLAP421 FBLAP20 21FBLAN421 FBLAN20 21FBLAP521 FBLAP21 25FBLAN521 FBLAN21 25FBLAP621 FBLAP22 21FBLAN621 FBLAN22 21FBLAP721 FBLAP23 21FBLAN721 FBLAN23 21FBLAP821 FBLAP24 25FBLAN821 FBLAN24 25FBLAP921 FBLAP25 25FBLAN921 FBLAN25 25FBLAP1021 FBLAP26 21FBLAN1021 FBLAN26 21FBLAP1121 FBLAP27 21FBLAN1121 FBLAN27 21FBLAP1221 FBLAP28 25FBLAN1221 FBLAN28 25FBLAP1321 FBLAP29 25FBLAN1321 FBLAN29 25FBLAP1425 FBLAP30 25FBLAN1425 FBLAN30 25FBLAP1521 FBLAP31 25FBLAN1521 FBLAN31 25FBLAP32 23FBLAN32 23FBLAP33 23FBLAN33 23
FBHBP042 FBHBP11 41FBHBN042 FBHBN11 41FBHBP142 FBHBP12 41FBHBN142 FBHBN12 41FBHBP242 FBHBP13 41FBHBN242 FBHBN13 41FBHBP342 FBHBP14 41FBHBN342 FBHBN14 41FBHBP442 FBHBP15 41FBHBN442 FBHBN15 41FBHBP542 FBHBP16 41FBHBN542 FBHBN16 41FBHBP642 FBHBP17 42FBHBN642 FBHBN17 42FBHBP741 FBHBP18 42FBHBN741 FBHBN18 42FBHBP842 FBHBP19 42FBHBN842 FBHBN19 42FBHBP941 FBHBP20 42FBHBN941 FBHBN20 42FBHBP1041 FBHBP21 42FBHBN1041 FBHBN21 42
FBHAP042 FBHAP12 42FBHAN042 FBHAN12 42FBHAP141 FBHAP13 42FBHAN141 FBHAN13 42FBHAP242 FBHAP14 42FBHAN242 FBHAN14 42FBHAP342 FBHAP15 42FBHAN342 FBHAN15 42FBHAP442 FBHAP16 42FBHAN442 FBHAN16 42FBHAP542 FBHAP17 42FBHAN542 FBHAN17 42FBHAP642 FBHAP18 42FBHAN642 FBHAN18 42FBHAP742 FBHAP19 42FBHAN742 FBHAN19 42FBHAP842 FBHAP20 42FBHAN842 FBHAN20 42FBHAP942 FBHAP21 42FBHAN942 FBHAN21 42FBHAP1042 FBHAP22 42FBHAN1042 FBHAN22 42FBHAP1142 FBHAP23 42FBHAN1142 FBHAN23 42
FBD0C2MP24 FBD0M2CP 24FBD0C2MN24 FBD0M2CN 24FBD1C2MP24 FBD1M2CP 24FBD1C2MN24 FBD1M2CN 24FBD2C2MP24 FBD2M2CP 24FBD2C2MN24 FBD2M2CN 24FBD3C2MP24 FBD3M2CP 24FBD3C2MN24 FBD3M2CN 24FBD4C2MP24 FBD4M2CP 24FBD4C2MN24 FBD4M2CN 24FBD5C2MP24 FBD5M2CP 24FBD5C2MN24 FBD5M2CN 24FBD6C2MP24 FBD6M2CP 24FBD6C2MN24 FBD6M2CN 24FBD7C2MP24 FBD7M2CP 24FBD7C2MN24 FBD7M2CN 24FBD8C2MP24 FBD8M2CP 24FBD8C2MN24 FBD8M2CN 24FBD9C2MP24 FBD9M2CP 24FBD9C2MN24 FBD9M2CN 24FBD10C2MP24 FBD10M2CP 24FBD10C2MN24 FBD10M2CN 24FBD11C2MP24 FBD11M2CP 24FBD11C2MN24 FBD11M2CN 24FBD12C2MP24 FBD12M2CP 24FBD12C2MN24 FBD12M2CN 24FBD13C2MP24 FBD13M2CP 24FBD13C2MN24 FBD13M2CN 24FBD14C2MP24 FBD14M2CP 24FBD14C2MN24 FBD14M2CN 24FBD15C2MP24 FBD15M2CP 24FBD15C2MN24 FBD15M2CN 24FBD16C2MP24 FBD16M2CP 24FBD16C2MN24 FBD16M2CN 24FBD17C2MP24 FBD17M2CP 24FBD17C2MN24 FBD17M2CN 24FBD18C2MP24 FBD18M2CP 24FBD18C2MN24 FBD18M2CN 24FBD19C2MP24 FBD19M2CP 24FBD19C2MN24 FBD19M2CN 24FBD20C2MP24 FBD20M2CP 24FBD20C2MN24 FBD20M2CN 24FBD21C2MP24 FBD21M2CP 24FBD21C2MN24 FBD21M2CN 24FBD22C2MP24 FBD22M2CP 24FBD22C2MN24 FBD22M2CN 24FBD23C2MP24 FBD23M2CP 24FBD23C2MN24 FBD23M2CN 24FBGBTCLK3M2CP24 FBGBTCLK0M2CP 24FBGBTCLK3M2CN24 FBGBTCLK0M2CN 24FBGBTCLK4M2CP24 FBGBTCLK1M2CP 24FBGBTCLK4M2CN24 FBGBTCLK1M2CN 24FBGBTCLK5M2CP24 FBGBTCLK2M2CP 24FBGBTCLK5M2CN24 FBGBTCLK2M2CN 24
FMCB_aux3V367
FMCB_DC_3V371
FMCB_12V48
FBPRSNT_N31,47EXTB_SDA9,19,38 EXTB_SCL9,19,38
FBCLK2BIDIRP41 FBCLK2BIDIRN41 FBCLK3BIDIRP41 FBCLK3BIDIRN41 FBCLKDIR42
FBCLKC2MP42 FBCLKC2MN42 FBCLK2M2CP41 FBCLK2M2CN41
FMCBVADJ 71
FBM2CVIO
FBREFB
FBREFAFBM2CPgood 46
FBTRST 7FBTMS 8FBTDO 8FBTDI 8FBTCK 8FBCLK0M2CP 42FBCLK0M2CN 42FBCLK1M2CP 42FBCLK1M2CN 42
FBSYNC2MP 42FBSYNC2MN 42FBSYNM2CP 41FBSYNM2CN 41
FBC2MPgood46
FBLAP123 Clearner_FMC1_122.88MHZ_P 36FBLAN123 Clearner_FMC1_122.88MHZ_N 36
FB_LA_DEVCLK_N 21FB_LA_DEVCLK_P 21
FBLAP3323 PCIEB_EP_PERSTn 41FBLAN3323 PCIEB_WAKEn 41
FBLAP33_FPGA 25FBLAN33_FPGA 25
FBLAP3223 FBLAN3223
FBLAP32_FPGA 25FBLAN32_FPGA 25
FMCB_DC_3V3
FMCB_DC_3V3
FMCB_DC_3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
23 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
23 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
23 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C241 1uF
J12F
ASP-184329-01
GND8K2GND9K3GND10K6GND11K9GND12K12GND13K15GND14K18GND15K21GND16K24GND17K27GND18K30GND19K33GND20K36GND21K39GND22J1GND23J4GND24J5GND25J8GND26J11GND27J14GND28J17GND29J20GND30J23GND31J26GND32J29GND33J32GND34J35GND35J38GND36J40GND37H3GND38H6GND39H9GND40H12GND41H15GND42H18GND43H21GND44H24GND45H27GND46H30GND47H33GND48H36GND49H39GND50D2GND51D3GND52D6GND53D7GND54D10GND55D13GND56D16GND57D19GND58D22GND59D25GND60D28GND61D37GND62D39GND63C1GND64C4GND65C5GND66C8GND67C9GND68C12GND69C13GND70C16GND71C17GND72C20GND73C21GND74C24GND75C25GND76C28GND77C29GND78C32GND79C33 GND118 C36GND117 C38GND116 C40GND115 B2GND114 B3GND113 B6GND112 B7GND111 B10GND110 B11GND159 B14GND158 B15GND157 B18GND156 B19GND155 B22GND154 B23GND153 B26GND152 B27GND151 B30GND150 B31GND149 B34GND148 B35GND147 B38GND146 B39GND145 A1GND144 A4GND143 A5GND142 A8GND141 A9GND140 A12GND139 A13GND138 A16GND137 A17GND136 A20GND135 A21GND134 A24GND133 A25GND132 A28GND131 A29GND130 A32GND129 A33GND128 A36GND127 A37GND126 A40GND125 G1GND124 G4GND123 G5GND122 G8GND121 G11GND120 G14GND109 G17GND108 G20GND107 G23GND106 G26GND105 G29GND104 G32GND103 G35GND102 G38GND101 G40GND100 F2GND99 F3GND98 F6GND97 F9GND96 F12GND95 F15GND94 F18GND93 F21GND92 F24GND91 F27GND90 F30GND89 F33GND88 F36GND87 F39GND86 E1GND85 E4GND84 E5GND83 E8GND82 E11GND81 E14GND80 E17GND0E20GND1E23GND2E26GND3E29
GND5E32GND6E35GND4E38
GND7E40
J12G
ASP-184329-01
GND119M1GND160M4GND161M5GND162M8GND163M9GND164M12GND165M13GND166M16GND167M17GND168M20GND169M21GND170M24GND171M25GND172M28GND173M29GND174M32GND175M33GND176M36GND177M37GND178M40GND179L2GND180L3GND181L6GND182L7GND183L10GND184L11GND185L14GND186L15GND187L18GND188L19GND189L22GND190L23GND191L26GND192L27GND193L30GND194L31GND195L34GND196L35GND197L38GND198L39
GND219 Z2GND220 Z3GND221 Z6GND222 Z7GND223 Z10GND224 Z11GND225 Z14GND226 Z15GND227 Z18GND228 Z19GND229 Z22GND230 Z23GND231 Z26GND232 Z27GND233 Z30GND234 Z31GND235 Z34GND236 Z35GND237 Z38GND238 Z39
GND200 Y4GND201 Y5GND202 Y8GND203 Y9GND204 Y12GND205 Y13GND206 Y16GND207 Y17GND208 Y20GND209 Y21GND210 Y24GND211 Y25GND212 Y28GND213 Y29GND214 Y32GND215 Y33GND216 Y36GND217 Y37GND218 Y40
GND199 Y1
R874DNI
J12A
ASP-184329-01
LA_N0_CCG7
LA_N1_CCD9
LA_N10C15
LA_N11H17
LA_N12G16
LA_N13D18
LA_N14C19
LA_N15H20
LA_N16 G19
LA_N17_CC D21
LA_N18_CC C23
LA_N19 H23LA_N2H8
LA_N20 G22
LA_N21 H26
LA_N22 G25
LA_N23 D24
LA_N24 H29
LA_N25 G28
LA_N26 D27
LA_N27 C27
LA_N28 H32
LA_N29 G31
LA_N3G10
LA_N30 H35
LA_N31 G34
LA_N32 H38
LA_N33 G37
LA_N4H11
LA_N5D12
LA_N6C11
LA_N7H14
LA_N8G13
LA_N9D15
LA_P0_CCG6
LA_P1_CCD8
LA_P10C14
LA_P11H16
LA_P12G15
LA_P13D17
LA_P14C18
LA_P15H19
LA_P16 G18
LA_P17_CC D20
LA_P18_CC C22
LA_P19 H22LA_P2H7
LA_P20 G21
LA_P21 H25
LA_P22 G24
LA_P23 D23
LA_P24 H28
LA_P25 G27
LA_P26 D26
LA_P27 C26
LA_P28 H31
LA_P29 G30
LA_P3G9
LA_P30 H34
LA_P31 G33
LA_P32 H37
LA_P33 G36
LA_P4H10
LA_P5D11
LA_P6C10
LA_P7H13
LA_P8G12
LA_P9D14
R869DNI
R159
100K
R2410
R8710
R873DNI
R160DNI
R244DNI
R8720
J12E
ASP-184329-01
CLK_DIRB1 CLK0_M2C_N H5CLK0_M2C_P H4
CLK1_M2C_N G3CLK1_M2C_P G2CLK2_BIDIR_NK5 CLK2_BIDIR_PK4
CLK3_BIDIR_NJ3 CLK3_BIDIR_PJ2
GA0C34GA1D35
PG_C2MD1 PG_M2C F1
PRSNT_M2C_LH2
RES0 B40
SCLC30 SDAC31
TCK D29TDI D30TDO D31TMS D33TRST_L D34
3P3VAUXD32
3P3V0D403P3V1C393P3V2D363P3V3D38
12P0V0C3512P0V1C37
VADJ0 E39VADJ1 F40VADJ2 G39VADJ3 H40
VIO_B_M2C_0 K40VIO_B_M2C_1 J39
VREF_B_M2C K1VREF_A_M2C H1
3P3V4Z40
12P0V4L4012P0V2L3612P0V3L37
RES1 L1
REFCLK_M2C_PL24REFCLK_M2C_NL25
SYNC_C2M_P L16SYNC_C2M_N L17
HSPC_PRSNT_M2C_LZ1RES2 L32RES3 L33
REFCLK_C2M_PL20REFCLK_C2M_NL21
SYNC_M2C_N L29SYNC_M2C_P L28
C240 1uF
J12D
ASP-184329-01
DP0_C2M_NC3 DP0_C2M_PC2DP0_M2C_N C7DP0_M2C_P C6
DP1_C2M_NA23 DP1_C2M_PA22DP1_M2C_N A3DP1_M2C_P A2
DP2_C2M_NA27 DP2_C2M_PA26DP2_M2C_N A7DP2_M2C_P A6
DP3_C2M_NA31 DP3_C2M_PA30DP3_M2C_N A11DP3_M2C_P A10
DP4_C2M_NA35 DP4_C2M_PA34DP4_M2C_N A15DP4_M2C_P A14
DP5_C2M_NA39 DP5_C2M_PA38DP5_M2C_N A19DP5_M2C_P A18
DP6_C2M_NB37 DP6_C2M_PB36DP6_M2C_N B17DP6_M2C_P B16
DP7_C2M_NB33 DP7_C2M_PB32DP7_M2C_N B13DP7_M2C_P B12
DP8_C2M_NB29 DP8_C2M_PB28DP8_M2C_N B9DP8_M2C_P B8
DP9_C2M_NB25 DP9_C2M_PB24DP9_M2C_N B5DP9_M2C_P B4
GBTCLK0_M2C_N D5GBTCLK0_M2C_P D4
GBTCLK1_M2C_N B21GBTCLK1_M2C_P B20
DP10_C2M_PZ24DP10_C2M_NZ25DP11_C2M_PY26DP11_C2M_NY27DP12_C2M_PZ28DP12_C2M_NZ29DP13_C2M_PY30DP13_C2M_NY31DP14_C2M_PM18DP14_C2M_NM19DP15_C2M_PM22DP15_C2M_NM23DP16_C2M_PM26DP16_C2M_NM27DP17_C2M_PM30DP17_C2M_NM31DP18_C2M_PM34DP18_C2M_NM35DP19_C2M_PM38DP19_C2M_NM39DP20_C2M_PZ8DP20_C2M_NZ9DP21_C2M_PY6DP21_C2M_NY7DP22_C2M_PZ4DP22_C2M_NZ5DP23_C2M_PY2DP23_C2M_NY3
DP10_M2C_P Y10DP10_M2C_N Y11DP11_M2C_P Z12DP11_M2C_N Z13DP12_M2C_P Y14DP12_M2C_N Y15DP13_M2C_P Z16DP13_M2C_N Z17DP14_M2C_P Y18DP14_M2C_N Y19DP15_M2C_P Y22DP15_M2C_N Y23DP16_M2C_P Z32DP16_M2C_N Z33DP17_M2C_P Y34DP17_M2C_N Y35DP18_M2C_P Z36DP18_M2C_N Z37DP19_M2C_P Y38DP19_M2C_N Y39DP20_M2C_P M14DP20_M2C_N M15DP21_M2C_P M10DP21_M2C_N M11DP22_M2C_P M6DP22_M2C_N M7DP23_M2C_P M2DP23_M2C_N M3
GBTCLK2_M2C_P L12GBTCLK2_M2C_N L13
GBTCLK3_M2C_PL8GBTCLK3_M2C_NL9GBTCLK4_M2C_PL4GBTCLK4_M2C_NL5GBTCLK5_M2C_PZ20GBTCLK5_M2C_NZ21
R1561.00K
R242DNI
R8670
C235 10uF
C238 10uF
J12C
ASP-184329-01
HB_N0_CCK26
HB_N1J25
HB_N10K32
HB_N11 J31
HB_N12 F32
HB_N13 E31
HB_N14 K35
HB_N15 J34
HB_N16 F35
HB_N17_CC K38
HB_N18 J37
HB_N19 E34
HB_N2F23
HB_N20 F38
HB_N21 E37
HB_N3E22
HB_N4F26
HB_N5E25
HB_N6_CCK29
HB_N7J28
HB_N8F29
HB_N9E28
HB_P0_CCK25
HB_P1J24
HB_P10K31
HB_P11 J30
HB_P12 F31
HB_P13 E30
HB_P14 K34
HB_P15 J33
HB_P16 F34
HB_P17_CC K37
HB_P18 J36
HB_P19 E33
HB_P2F22
HB_P20 F37
HB_P21 E36
HB_P3E21
HB_P4F25
HB_P5E24
HB_P6_CCK28
HB_P7J27
HB_P8F28
HB_P9E27
R1551.00K
R157DNI
C239 10uF
J12B
ASP-184329-01
HA_N0_CCF5
HA_N1_CCE3
HA_N10K14
HA_N11J13
HA_N12 F14
HA_N13 E13
HA_N14 J16
HA_N15 F17
HA_N16 E16
HA_N17_CC K17
HA_N18 J19
HA_N19 F20
HA_N2K8
HA_N20 E19
HA_N21 K20
HA_N22 J22
HA_N23 K23
HA_N3J7
HA_N4F8
HA_N5E7
HA_N6K11
HA_N7J10
HA_N8F11
HA_N9E10
HA_P0_CCF4
HA_P1_CCE2
HA_P10K13
HA_P11J12
HA_P12 F13
HA_P13 E12
HA_P14 J15
HA_P15 F16
HA_P16 E15
HA_P17_CC K16
HA_P18 J18
HA_P19 F19
HA_P2K7
HA_P20 E18
HA_P21 K19
HA_P22 J21
HA_P23 K22
HA_P3J6
HA_P4F7
HA_P5E6
HA_P6K10
HA_P7J9
HA_P8F10
HA_P9E9
C237 10uF
C236 10uF
R8680
R158DNI
R2400
R870DNI
FBGA1 FBGA0
FBGA1FBGA0
FBPG_C2M
FBPG_C2M
![Page 24: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/24.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Stratix 10 XCVR Banks - 1K/L/M/N
FBD0M2CP23
FBD0C2MP23
FBD0M2CN23
FBD0C2MN23
FBD1M2CP23
FBD1C2MP23
FBD1M2CN23
FBD1C2MN23
FBD2M2CP23
FBD2C2MP23
FBD2M2CN23
FBD2C2MN23
FBD3M2CP23
FBD3C2MP23
FBD3M2CN23
FBD3C2MN23
FBD4M2CP23
FBD4C2MP23
FBD4M2CN23
FBD4C2MN23
FBD5M2CP23
FBD5C2MP23
FBD5M2CN23
FBD5C2MN23
FBD6M2CP23
FBD6C2MP23
FBD6M2CN23
FBD6C2MN23
FBD7M2CP23
FBD7C2MP23
FBD7M2CN23
FBD7C2MN23
FBD8M2CP23
FBD8C2MP23
FBD8M2CN23
FBD8C2MN23
FBD9M2CP23
FBD9C2MP23
FBD9M2CN23
FBD9C2MN23
FBD10M2CP23
FBD10C2MP23
FBD10M2CN23
FBD10C2MN23
FBD11M2CP23
FBD11C2MP23
FBD11M2CN23
FBD11C2MN23
FBD12M2CP 23
FBD12C2MP 23
FBD12M2CN 23
FBD12C2MN 23
FBD13M2CP 23
FBD13C2MP 23
FBD13M2CN 23
FBD13C2MN 23
FBD14M2CP 23
FBD14C2MP 23
FBD14M2CN 23
FBD14C2MN 23
FBD15M2CP 23
FBD15C2MP 23
FBD15M2CN 23
FBD15C2MN 23
FBD16M2CP 23
FBD16C2MP 23
FBD16M2CN 23
FBD16C2MN 23
FBD17M2CP 23
FBD17C2MP 23
FBD17M2CN 23
FBD17C2MN 23
FBD18M2CP 23
FBD18C2MP 23
FBD18M2CN 23
FBD18C2MN 23
FBD19M2CP 23
FBD19C2MP 23
FBD19M2CN 23
FBD19C2MN 23
FBD20M2CP 23
FBD20C2MP 23
FBD20M2CN 23
FBD20C2MN 23
FBD21M2CP 23
FBD21C2MP 23
FBD21M2CN 23
FBD21C2MN 23
FBD22M2CP 23
FBD22C2MP 23
FBD22M2CN 23
FBD22C2MN 23
FBD23M2CP 23
FBD23C2MP 23
FBD23M2CN 23
FBD23C2MN 23
FBGBTCLK5M2CN23FBGBTCLK5M2CP23
FBGBTCLK4M2CN 23FBGBTCLK4M2CP 23
FBGBTCLK3M2CN 23FBGBTCLK3M2CP 23
FBGBTCLK2M2CN 23FBGBTCLK2M2CP 23
FBGBTCLK1M2CN23 FBGBTCLK1M2CP23
FBGBTCLK0M2CN23 FBGBTCLK0M2CP23
Clearner_XVRL_122.88MHZ_P36 Clearner_XVRL_122.88MHZ_N36
REFCLK1_FMC_P 34REFCLK1_FMC_N 34
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
24 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
24 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
24 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
BANK 1
LBAN
K 1K
BANK 1
MBAN
K 1N
1SX280LU3F50E3VGS1
U15BREFCLK_GXBL1K_CHTPV38REFCLK_GXBL1K_CHTNV37
GXBL1K_TX_CH5NW46GXBL1K_TX_CH5PW47
GXBL1K_RX_CH5N, GXBL1K_REFCLK5NY44GXBL1K_RX_CH5P, GXBL1K_REFCLK5PY45
GXBL1K_TX_CH4NAB48GXBL1K_TX_CH4PAB49
GXBL1K_RX_CH4N, GXBL1K_REFCLK4NW42GXBL1K_RX_CH4P, GXBL1K_REFCLK4PW43
GXBL1K_TX_CH3NAA46GXBL1K_TX_CH3PAA47
GXBL1K_RX_CH3N, GXBL1K_REFCLK3NAB44GXBL1K_RX_CH3P, GXBL1K_REFCLK3PAB45
GXBL1K_TX_CH2NAD48GXBL1K_TX_CH2PAD49
GXBL1K_RX_CH2N, GXBL1K_REFCLK2NAA42GXBL1K_RX_CH2P, GXBL1K_REFCLK2PAA43
GXBL1K_TX_CH1NAC46GXBL1K_TX_CH1PAC47
GXBL1K_RX_CH1N, GXBL1K_REFCLK1NAD44GXBL1K_RX_CH1P, GXBL1K_REFCLK1PAD45
GXBL1K_TX_CH0NAE46GXBL1K_TX_CH0PAE47
GXBL1K_RX_CH0N, GXBL1K_REFCLK0NAC42GXBL1K_RX_CH0P, GXBL1K_REFCLK0PAC43
REFCLK_GXBL1K_CHBPY38REFCLK_GXBL1K_CHBNY37
REFCLK_GXBL1L_CHTPAB41REFCLK_GXBL1L_CHTNAB40
GXBL1L_TX_CH5NR46GXBL1L_TX_CH5PR47
GXBL1L_RX_CH5N, GXBL1L_REFCLK5NM44GXBL1L_RX_CH5P, GXBL1L_REFCLK5PM45
GXBL1L_TX_CH4NP48GXBL1L_TX_CH4PP49
GXBL1L_RX_CH4N, GXBL1L_REFCLK4NR42GXBL1L_RX_CH4P, GXBL1L_REFCLK4PR43
GXBL1L_TX_CH3NT48GXBL1L_TX_CH3PT49
GXBL1L_RX_CH3N, GXBL1L_REFCLK3NP44GXBL1L_RX_CH3P, GXBL1L_REFCLK3PP45
GXBL1L_TX_CH2NU46GXBL1L_TX_CH2PU47
GXBL1L_RX_CH2N, GXBL1L_REFCLK2NT44GXBL1L_RX_CH2P, GXBL1L_REFCLK2PT45
GXBL1L_TX_CH1NV48GXBL1L_TX_CH1PV49
GXBL1L_RX_CH1N, GXBL1L_REFCLK1NU42GXBL1L_RX_CH1P, GXBL1L_REFCLK1PU43
GXBL1L_TX_CH0NY48GXBL1L_TX_CH0PY49
GXBL1L_RX_CH0N, GXBL1L_REFCLK0NV44GXBL1L_RX_CH0P, GXBL1L_REFCLK0PV45
REFCLK_GXBL1L_CHBPAD41REFCLK_GXBL1L_CHBNAD40
REFCLK_GXBL1M_CHTP V41REFCLK_GXBL1M_CHTN V40
GXBL1M_TX_CH5N J46GXBL1M_TX_CH5P J47
GXBL1M_RX_CH5N, GXBL1M_REFCLK5N F44GXBL1M_RX_CH5P, GXBL1M_REFCLK5P F45
GXBL1M_TX_CH4N H48GXBL1M_TX_CH4P H49
GXBL1M_RX_CH4N, GXBL1M_REFCLK4N J42GXBL1M_RX_CH4P, GXBL1M_REFCLK4P J43
GXBL1M_TX_CH3N L46GXBL1M_TX_CH3P L47
GXBL1M_RX_CH3N, GXBL1M_REFCLK3N H44GXBL1M_RX_CH3P, GXBL1M_REFCLK3P H45
GXBL1M_TX_CH2N K48GXBL1M_TX_CH2P K49
GXBL1M_RX_CH2N, GXBL1M_REFCLK2N L42GXBL1M_RX_CH2P, GXBL1M_REFCLK2P L43
GXBL1M_TX_CH1N N46GXBL1M_TX_CH1P N47
GXBL1M_RX_CH1N, GXBL1M_REFCLK1N K44GXBL1M_RX_CH1P, GXBL1M_REFCLK1P K45
GXBL1M_TX_CH0N M48GXBL1M_TX_CH0P M49
GXBL1M_RX_CH0N, GXBL1M_REFCLK0N N42GXBL1M_RX_CH0P, GXBL1M_REFCLK0P N43
REFCLK_GXBL1M_CHBP Y41REFCLK_GXBL1M_CHBN Y40
REFCLK_GXBL1N_CHTP P41REFCLK_GXBL1N_CHTN P40
GXBL1N_TX_CH5N B44GXBL1N_TX_CH5P B45
GXBL1N_RX_CH5N, GXBL1N_REFCLK5N B40GXBL1N_RX_CH5P, GXBL1N_REFCLK5P B41
GXBL1N_TX_CH4N C46GXBL1N_TX_CH4P C47
GXBL1N_RX_CH4N, GXBL1N_REFCLK4N A42GXBL1N_RX_CH4P, GXBL1N_REFCLK4P A43
GXBL1N_TX_CH3N E46GXBL1N_TX_CH3P E47
GXBL1N_RX_CH3N, GXBL1N_REFCLK3N C42GXBL1N_RX_CH3P, GXBL1N_REFCLK3P C43
GXBL1N_TX_CH2N D48GXBL1N_TX_CH2P D49
GXBL1N_RX_CH2N, GXBL1N_REFCLK2N E42GXBL1N_RX_CH2P, GXBL1N_REFCLK2P E43
GXBL1N_TX_CH1N G46GXBL1N_TX_CH1P G47
GXBL1N_RX_CH1N, GXBL1N_REFCLK1N D44GXBL1N_RX_CH1P, GXBL1N_REFCLK1P D45
GXBL1N_TX_CH0N F48GXBL1N_TX_CH0P F49
GXBL1N_RX_CH0N, GXBL1N_REFCLK0N G42GXBL1N_RX_CH0P, GXBL1N_REFCLK0P G43
REFCLK_GXBL1N_CHBP T41REFCLK_GXBL1N_CHBN T40
![Page 25: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/25.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Stratix 10 Banks - 2 F/L/M/N HPS DDR4
HPS DD
R4
HPS DD
R4HPS
DDR4
Do not need length matching
MEM_DQ_ADDR_CMD4 26MEM_DQ_ADDR_CMD3 26MEM_DQ_ADDR_CMD0 26
MEM_DQ_ADDR_CMD2 26MEM_DQ_ADDR_CMD1 26MEM_DQ_ADDR_CMD5 26MEM_DQS_ADDR_CMD_N 26MEM_DQS_ADDR_CMD_P 26MEM_DQ_ADDR_CMD6 26MEM_DQ_ADDR_CMD7 26MEM_DQ_ADDR_CMD8 26
MEM_ADDR_CMD29 26
MEM_ADDR_CMD18 26MEM_ADDR_CMD17 26MEM_ADDR_CMD16 26MEM_ADDR_CMD19 26MEM_ADDR_CMD26 26MEM_ADDR_CMD15 26MEM_ADDR_CMD14 26MEM_ADDR_CMD13 26MEM_ADDR_CMD12 26
MEM_ADDR_CMD11 26MEM_ADDR_CMD10 26MEM_ADDR_CMD9 26MEM_ADDR_CMD8 26MEM_ADDR_CMD7 26MEM_ADDR_CMD6 26MEM_ADDR_CMD5 26MEM_ADDR_CMD4 26MEM_ADDR_CMD3 26MEM_ADDR_CMD2 26MEM_ADDR_CMD1 26MEM_ADDR_CMD0 26MEM_ADDR_CMD31 26MEM_ADDR_CMD30 26MEM_CLK_N 26MEM_CLK_P 26MEM_ADDR_CMD21 26MEM_ADDR_CMD20 26MEM_ADDR_CMD25 26MEM_ADDR_CMD24 26MEM_ADDR_CMD23 26MEM_ADDR_CMD22 26MEM_ADDR_CMD27 26MEM_ADDR_CMD28 26
CLK_EMI_N33
CLK_EMI_P33
FBLAN3123 FBLAP3123
S10_2L_SDA 30,38,41S10_2L_SCL 30,38,41S10I2CEN_FPGA 41
SDI_148.5MHz_REF_P35 SDI_148.5MHz_REF_N35
FPGA_BOOT_DIO029
FPGA_BOOT_DIO529
FPGA_BOOT_DIO1129FPGA_BOOT_DIO1329
FPGA_BOOT_DIO329
FPGA_BOOT_DIO729 FPGA_BOOT_DIO629
FPGA_BOOT_DIO129
FPGA_BOOT_DIO429
FPGA_BOOT_DIO1029FPGA_BOOT_DIO1229
FPGA_BOOT_DIO229
FPGA_BOOT_DIO829 FPGA_BOOT_DIO929
FBLAP33_FPGA23 FBLAN33_FPGA23 FBLAP32_FPGA23 FBLAN32_FPGA23
FAHBN619 FAHBP619
FBLAN2123 FBLAP2123
FBLAN2523 FBLAP2523
FBLAN2423 FBLAP2423
FBLAN1423 FBLAP1423
FBLAN2923 FBLAP2923
FBLAN3023 FBLAP3023
FBLAN2823 FBLAP2823
FAHBN1919 FAHBP1919
MEM_DQB4 26
MEM_DQB2 26
MEM_DQB0 26
MEM_DQB1 26
MEM_DQB5 26
MEM_DMB0 26
MEM_DQSB_N0 26MEM_DQSB_P0 26
MEM_DQB3 26MEM_DQB6 26
MEM_DQB7 26
MEM_DQB10 26
MEM_DQB11 26
MEM_DQB8 26
MEM_DQB9 26
MEM_DQB14 26MEM_DQB12 26
MEM_DQSB_N1 26MEM_DQSB_P1 26MEM_DQB13 26
MEM_DQB15 26
MEM_DMB1 26
MEM_DQB20 26MEM_DQB22 26MEM_DQB17 26
MEM_DQB18 26
MEM_DQB19 26MEM_DQB16 26
MEM_DQSB_N2 26MEM_DQSB_P2 26
MEM_DMB2 26MEM_DQB21 26
MEM_DQB23 26
MEM_DMB3 26
MEM_DQB31 26
MEM_DQB26 26
MEM_DQB30 26MEM_DQB28 26MEM_DQSB_N3 26MEM_DQSB_P3 26
MEM_DQB29 26MEM_DQB27 26
MEM_DQB24 26
MEM_DQB25 26
MEM_DMA026
MEM_DQA126
MEM_DQA626
MEM_DQA526
MEM_DQA026
MEM_DQA226 MEM_DQSA_N026 MEM_DQSA_P026MEM_DQA426
MEM_DQA326
MEM_DQA726
MEM_DQA826 MEM_DQA926MEM_DMA126
MEM_DQA1126
MEM_DQA1426
MEM_DQA1526 MEM_DQSA_N126 MEM_DQSA_P126MEM_DQA1226 MEM_DQA1326
MEM_DQA1026
MEM_DMA226
MEM_DQA3026
MEM_DMA326
MEM_DQA3126
MEM_DQA2926 MEM_DQA2426MEM_DQA2826
MEM_DQSA_N326 MEM_DQSA_P326
MEM_DQA2726
MEM_DQA2526
MEM_DQA2626
MEM_DQA2026
MEM_DQA1826
MEM_DQA1926
MEM_DQA1726 MEM_DQA1626 MEM_DQSA_N226 MEM_DQSA_P226
MEM_DQA2226 MEM_DQA2126
MEM_DQA2326
SFPA_I2C_B_SDA 14SFPA_I2C_B_SCL 14
FBLAN1723 FBLAP1723
VIDEO_I2C_B_SDA 38VIDEO_I2C_B_SCL 38
IO_1V8
IO_1V8 IO_3V3
IO_1V8
IO_1V8 IO_3V3
IO_1V8 IO_3V3
IO_1V8 IO_3V3
IO_1V8 IO_3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
25 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
25 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
25 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
U105
FXMA2102UMX
A0 2A1 3B07
B16
VCCA 1GND 4
OE 5
VCCB8
U109
FXMA2102UMX
A0 2A1 3B07
B16
VCCA 1GND 4
OE 5
VCCB8
R8100
R1004 10.0K
C16030.1uF
R1020 10.0K
R84210K
C16630.1uF
C15590.1uF
R162 0
R161240
R1021 10.0K
C16550.1uF
R1018 10.0K
R8151.00k
R814 10.0K
R10191.00k
R1017 10.0K
R813 10.0K
R8090
R84310K
R1003 10.0K
R10021.00k
C160210uF
R1001 10.0K
R84549.9
C16640.1uF
R84449.9
R1006 DNI
C15600.1uF
BANK 2
FBAN
K 2M
BANK 2
LBAN
K 2N
1SX280LU3F50E3VGS1
U15DIO, LVDS2F_1N, DQ32AT25IO, LVDS2F_1P, DQ32AU25IO, LVDS2F_2N, DQ32AW25IO, LVDS2F_2P, DQ32AV25IO, LVDS2F_3N, DQ32AV26IO, LVDS2F_3P, DQ32AV27IO, LVDS2F_4N, DQSN32AT26IO, LVDS2F_4P, DQS32AR26IO, LVDS2F_5N, DQ32AU27IO, LVDS2F_5P, DQ32AT27IO, LVDS2F_6N, DQ32AY26IO, LVDS2F_6P, DQ32AW26IO, LVDS2F_7N, DQ33AN26IO, LVDS2F_7P, DQ33AP26IO, LVDS2F_8N, DQ33AN25IO, LVDS2F_8P, DQ33AP25IO, LVDS2F_9N, DQ33AP29IO, LVDS2F_9P, DQ33AP28IO, PLL_2F_CLKOUT1N, LVDS2F_10N, DQSN33AR27IO, PLL_2F_CLKOUT1P, PLL_2F_CLKOUT1, PLL_2F_FBN, LVDS2F_10P, DQS33AR28IO, LVDS2F_11N, DQ33AP31IO, RZQ_2F, LVDS2F_11P, DQ33AP30IO, CLK_2F_1N, LVDS2F_12N, DQ33AN28IO, CLK_2F_1P, LVDS2F_12P, DQ33AN27IO, CLK_2F_0N, LVDS2F_13N, DQ34BA26IO, CLK_2F_0P, LVDS2F_13P, DQ34BA27IO, LVDS2F_14N, DQ34BB25IO, LVDS2F_14P, DQ34BA25IO, PLL_2F_CLKOUT0N, LVDS2F_15N, DQ34BB27IO, PLL_2F_CLKOUT0P, PLL_2F_CLKOUT0, PLL_2F_FBP, PLL_2F_FB0, LVDS2F_15P, DQ34BC27IO, LVDS2F_16N, DQSN34BC25IO, LVDS2F_16P, DQS34BC26IO, LVDS2F_17N, DQ34AY27IO, LVDS2F_17P, DQ34AY28IO, LVDS2F_18N, DQ34BD28IO, LVDS2F_18P, DQ34BC28IO, LVDS2F_19N, DQ35BF26IO, LVDS2F_19P, DQ35BE27IO, LVDS2F_20N, DQ35BD26IO, LVDS2F_20P, DQ35BE26IO, LVDS2F_21N, DQ35BF27IO, LVDS2F_21P, DQ35BG27IO, LVDS2F_22N, DQSN35BH25IO, LVDS2F_22P, DQS35BJ25IO, LVDS2F_23N, DQ35BG25IO, LVDS2F_23P, DQ35BH26IO, LVDS2F_24N, DQ35BH27IO, LVDS2F_24P, DQ35BJ26
IO, LVDS2L_1N, DQ8E27IO, LVDS2L_1P, DQ8D26IO, LVDS2L_2N, DQ8G27IO, LVDS2L_2P, DQ8F27IO, LVDS2L_3N, DQ8C27IO, LVDS2L_3P, DQ8B27IO, LVDS2L_4N, DQSN8F26IO, LVDS2L_4P, DQS8E26IO, LVDS2L_5N, DQ8B25IO, LVDS2L_5P, DQ8C26IO, LVDS2L_6N, DQ8D25IO, LVDS2L_6P, DQ8C25IO, LVDS2L_7N, DQ9L26IO, LVDS2L_7P, DQ9K27IO, LVDS2L_8N, DQ9M27IO, LVDS2L_8P, DQ9L27IO, LVDS2L_9N, DQ9H27IO, LVDS2L_9P, DQ9H26IO, PLL_2L_CLKOUT1N, LVDS2L_10N, DQSN9K26IO, PLL_2L_CLKOUT1P, PLL_2L_CLKOUT1, PLL_2L_FBN, LVDS2L_10P, DQS9J26IO, LVDS2L_11N, DQ9G25IO, RZQ_2L, LVDS2L_11P, DQ9F25IO, CLK_2L_1N, LVDS2L_12N, DQ9H25IO, CLK_2L_1P, LVDS2L_12P, DQ9J25IO, CLK_2L_0N, LVDS2L_13N, DQ10V30IO, CLK_2L_0P, LVDS2L_13P, DQ10U30IO, LVDS2L_14N, DQ10T30IO, LVDS2L_14P, DQ10T29IO, PLL_2L_CLKOUT0N, LVDS2L_15N, DQ10U28IO, PLL_2L_CLKOUT0P, PLL_2L_CLKOUT0, PLL_2L_FBP, PLL_2L_FB0, LVDS2L_15P, DQ10U29IO, LVDS2L_16N, DQSN10V27IO, LVDS2L_16P, DQS10V28IO, LVDS2L_17N, DQ10V26IO, LVDS2L_17P, DQ10V25IO, LVDS2L_18N, DQ10U27IO, LVDS2L_18P, DQ10T27IO, LVDS2L_19N, DQ11N25IO, LVDS2L_19P, DQ11P25IO, LVDS2L_20N, DQ11P26IO, LVDS2L_20P, DQ11R26IO, LVDS2L_21N, DQ11T25IO, LVDS2L_21P, DQ11U25IO, LVDS2L_22N, DQSN11R27IO, LVDS2L_22P, DQS11T26IO, LVDS2L_23N, DQ11M25IO, LVDS2L_23P, DQ11L25IO, LVDS2L_24N, DQ11N27IO, LVDS2L_24P, DQ11N26
IO, LVDS2M_1N, DQ4 U34IO, LVDS2M_1P, DQ4 U33IO, LVDS2M_2N, DQ4 T31IO, LVDS2M_2P, DQ4 R31IO, LVDS2M_3N, DQ4 T34IO, LVDS2M_3P, DQ4 R34
IO, LVDS2M_4N, DQSN4 T32IO, LVDS2M_4P, DQS4 R32
IO, LVDS2M_5N, DQ4 U32IO, LVDS2M_5P, DQ4 V32IO, LVDS2M_6N, DQ4 P33IO, LVDS2M_6P, DQ4 R33IO, LVDS2M_7N, DQ5 R36IO, LVDS2M_7P, DQ5 T35IO, LVDS2M_8N, DQ5 L36IO, LVDS2M_8P, DQ5 L35IO, LVDS2M_9N, DQ5 P36IO, LVDS2M_9P, DQ5 N36
IO, PLL_2M_CLKOUT1N, LVDS2M_10N, DQSN5 K37IO, PLL_2M_CLKOUT1P, PLL_2M_CLKOUT1, PLL_2M_FBN, LVDS2M_10P, DQS5 K36
IO, LVDS2M_11N, DQ5 P35IO, RZQ_2M, LVDS2M_11P, DQ5 P34
IO, CLK_2M_1N, LVDS2M_12N, DQ5 N35IO, CLK_2M_1P, LVDS2M_12P, DQ5 M35IO, CLK_2M_0N, LVDS2M_13N, DQ6 P38IO, CLK_2M_0P, LVDS2M_13P, DQ6 N37
IO, LVDS2M_14N, DQ6 R37IO, LVDS2M_14P, DQ6 P37
IO, PLL_2M_CLKOUT0N, LVDS2M_15N, DQ6 L39IO, PLL_2M_CLKOUT0P, PLL_2M_CLKOUT0, PLL_2M_FBP, PLL_2M_FB0, LVDS2M_15P, DQ6 K39
IO, LVDS2M_16N, DQSN6 J38IO, LVDS2M_16P, DQS6 J39
IO, LVDS2M_17N, DQ6 M38IO, LVDS2M_17P, DQ6 M37IO, LVDS2M_18N, DQ6 L37IO, LVDS2M_18P, DQ6 K38IO, LVDS2M_19N, DQ7 H40IO, LVDS2M_19P, DQ7 J40IO, LVDS2M_20N, DQ7 G39IO, LVDS2M_20P, DQ7 F39IO, LVDS2M_21N, DQ7 K40IO, LVDS2M_21P, DQ7 L40
IO, LVDS2M_22N, DQSN7 F40IO, LVDS2M_22P, DQS7 G40
IO, LVDS2M_23N, DQ7 H38IO, LVDS2M_23P, DQ7 G38IO, LVDS2M_24N, DQ7 E40IO, LVDS2M_24P, DQ7 D40
IO, LVDS2N_1N, DQ0 J34IO, LVDS2N_1P, DQ0 K34IO, LVDS2N_2N, DQ0 N32IO, LVDS2N_2P, DQ0 N31IO, LVDS2N_3N, DQ0 K33IO, LVDS2N_3P, DQ0 K32
IO, LVDS2N_4N, DQSN0 L31IO, LVDS2N_4P, DQS0 L32
IO, LVDS2N_5N, DQ0 N33IO, LVDS2N_5P, DQ0 M33IO, LVDS2N_6N, DQ0 M34IO, LVDS2N_6P, DQ0 L34IO, LVDS2N_7N, DQ1 F34IO, LVDS2N_7P, DQ1 E34IO, LVDS2N_8N, DQ1 J35IO, LVDS2N_8P, DQ1 H35IO, LVDS2N_9N, DQ1 F35IO, LVDS2N_9P, DQ1 G35
IO, PLL_2N_CLKOUT1N, LVDS2N_10N, DQSN1 G34IO, PLL_2N_CLKOUT1P, PLL_2N_CLKOUT1, PLL_2N_FBN, LVDS2N_10P, DQS1 G33
IO, LVDS2N_11N, DQ1 H36IO, RZQ_2N, LVDS2N_11P, DQ1 J36
IO, CLK_2N_1N, LVDS2N_12N, DQ1 H33IO, CLK_2N_1P, LVDS2N_12P, DQ1 J33IO, CLK_2N_0N, LVDS2N_13N, DQ2 D39IO, CLK_2N_0P, LVDS2N_13P, DQ2 E39
IO, LVDS2N_14N, DQ2 E38IO, LVDS2N_14P, DQ2 D38
IO, PLL_2N_CLKOUT0N, LVDS2N_15N, DQ2 D35IO, PLL_2N_CLKOUT0P, PLL_2N_CLKOUT0, PLL_2N_FBP, PLL_2N_FB0, LVDS2N_15P, DQ2 D34
IO, LVDS2N_16N, DQSN2 F36IO, LVDS2N_16P, DQS2 E36
IO, LVDS2N_17N, DQ2 F37IO, LVDS2N_17P, DQ2 E37IO, LVDS2N_18N, DQ2 H37IO, LVDS2N_18P, DQ2 G37IO, LVDS2N_19N, DQ3 C36IO, LVDS2N_19P, DQ3 D36IO, LVDS2N_20N, DQ3 C35IO, LVDS2N_20P, DQ3 B35IO, LVDS2N_21N, DQ3 B37IO, LVDS2N_21P, DQ3 C37
IO, LVDS2N_22N, DQSN3 A35IO, LVDS2N_22P, DQS3 A36
IO, LVDS2N_23N, DQ3 B38IO, LVDS2N_23P, DQ3 C38IO, LVDS2N_24N, DQ3 A37IO, LVDS2N_24P, DQ3 A38
U101
FXMA2102UMX
A0 2A1 3B07
B16
VCCA 1GND 4
OE 5
VCCB8
R166100
C16560.1uF
R1000 10.0K
FPGA_I2C_SCL_IO1FPGA_I2C_SDA_IO2
FPGA_I2C_SCL_IO1FPGA_I2C_SDA_IO2
Video_refclknVideo_refclkp
hps_alert_N2
SFPA_I2C_SDASFPA_I2C_SCL
SFPA_I2C_SCLSFPA_I2C_SDA
VIDEO_I2C_SCLVIDEO_I2C_SDA
![Page 26: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/26.jpg)
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E E
D D
C C
B B
A A
External Memory Interface - HiLo connector
Place nearHILO connectorJ14 VDD pins
Place nearHILO connectorJ14 VDDQ pins
VDDQ_1.1V_SET and VDDQ_1.8V_SET NOT USEDOnly support DDR3 and DDR4
MEM_CLK_P 25MEM_CLK_N 25
MEM_DQS_ADDR_CMD_P 25MEM_DQS_ADDR_CMD_N 25
MEM_DQ_ADDR_CMD0 25MEM_DQ_ADDR_CMD1 25MEM_DQ_ADDR_CMD2 25MEM_DQ_ADDR_CMD3 25MEM_DQ_ADDR_CMD4 25MEM_DQ_ADDR_CMD5 25MEM_DQ_ADDR_CMD6 25MEM_DQ_ADDR_CMD7 25MEM_DQ_ADDR_CMD8 25
MEM_DMB0 25MEM_DMB1 25MEM_DMB2 25MEM_DMB3 25MEM_DQB0 25MEM_DQB1 25MEM_DQB2 25MEM_DQB3 25MEM_DQB4 25MEM_DQB5 25MEM_DQB6 25MEM_DQB7 25MEM_DQB8 25MEM_DQB9 25MEM_DQB10 25MEM_DQB11 25MEM_DQB12 25MEM_DQB13 25MEM_DQB14 25MEM_DQB15 25MEM_DQB16 25MEM_DQB17 25MEM_DQB18 25MEM_DQB19 25MEM_DQB20 25MEM_DQB21 25MEM_DQB22 25MEM_DQB23 25MEM_DQB24 25MEM_DQB25 25MEM_DQB26 25MEM_DQB27 25MEM_DQB28 25MEM_DQB29 25MEM_DQB30 25MEM_DQB31 25
MEM_DQSB_P0 25MEM_DQSB_N0 25MEM_DQSB_P1 25MEM_DQSB_N1 25MEM_DQSB_P2 25MEM_DQSB_N2 25MEM_DQSB_P3 25MEM_DQSB_N3 25
MEM_ADDR_CMD025 MEM_ADDR_CMD125 MEM_ADDR_CMD225 MEM_ADDR_CMD325MEM_ADDR_CMD425 MEM_ADDR_CMD525 MEM_ADDR_CMD625 MEM_ADDR_CMD725 MEM_ADDR_CMD825MEM_ADDR_CMD925 MEM_ADDR_CMD1025 MEM_ADDR_CMD1125 MEM_ADDR_CMD1225 MEM_ADDR_CMD1325MEM_ADDR_CMD1425 MEM_ADDR_CMD1525 MEM_ADDR_CMD1625 MEM_ADDR_CMD1725 MEM_ADDR_CMD1825MEM_ADDR_CMD1925 MEM_ADDR_CMD2025 MEM_ADDR_CMD2125 MEM_ADDR_CMD2225 MEM_ADDR_CMD2325MEM_ADDR_CMD2425 MEM_ADDR_CMD2525 MEM_ADDR_CMD2625 MEM_ADDR_CMD2725 MEM_ADDR_CMD2825MEM_ADDR_CMD2925 MEM_ADDR_CMD3025 MEM_ADDR_CMD3125
MEM_DMA025 MEM_DMA125 MEM_DMA225 MEM_DMA325MEM_DQA025 MEM_DQA125 MEM_DQA225 MEM_DQA325 MEM_DQA425MEM_DQA525 MEM_DQA625 MEM_DQA725 MEM_DQA825 MEM_DQA925
MEM_DQA1025 MEM_DQA1125 MEM_DQA1225 MEM_DQA1325 MEM_DQA1425MEM_DQA1525 MEM_DQA1625 MEM_DQA1725 MEM_DQA1825 MEM_DQA1925MEM_DQA2025 MEM_DQA2125 MEM_DQA2225 MEM_DQA2325 MEM_DQA2425MEM_DQA2525 MEM_DQA2625 MEM_DQA2725 MEM_DQA2825 MEM_DQA2925MEM_DQA3025 MEM_DQA3125
MEM_DQSA_P025 MEM_DQSA_N025 MEM_DQSA_P125 MEM_DQSA_N125 MEM_DQSA_P225MEM_DQSA_N225 MEM_DQSA_P325 MEM_DQSA_N325
HILOHPS_1V2_SETn61
HILOHPS_1V35_SETn61 HILOHPS_1V5_SETn61
IO_2V5 10,11,12,22,27,32,38,43,68
IO_3V3 14,15,16,17,22,25,29,30,31,32,34,35,36,37,38,43,57,69,70
HILOHPS_VDD 61,63,66
HILOHPS_VDD
HILOHPS_VDD
HILOHPS_VDD
HILOHPS_VDD
IO_2V5
IO_3V3
HILOHPS_VDD
IO_3V3
IO_2V5
HILOHPS_VDD
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
26 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
26 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
26 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
HiLo EMI - EMI SIGNALSJ13A
HLS-180324-B-12
MEM_CLK_P V1MEM_CLK_N V2
MEM_ADDR_CMD0F1MEM_ADDR_CMD1H1MEM_ADDR_CMD2F2MEM_ADDR_CMD3G2MEM_ADDR_CMD4H2MEM_ADDR_CMD5J2MEM_ADDR_CMD6K2MEM_ADDR_CMD7G3MEM_ADDR_CMD8J3MEM_ADDR_CMD9L3MEM_ADDR_CMD10E4MEM_ADDR_CMD11F4MEM_ADDR_CMD12G4MEM_ADDR_CMD13H4MEM_ADDR_CMD14J4MEM_ADDR_CMD15K4MEM_ADDR_CMD16M1MEM_ADDR_CMD17M2MEM_ADDR_CMD18N2MEM_ADDR_CMD19L4MEM_ADDR_CMD20P5MEM_ADDR_CMD21M5MEM_ADDR_CMD22P1MEM_ADDR_CMD23R4MEM_ADDR_CMD24M4MEM_ADDR_CMD25R3MEM_ADDR_CMD26L2MEM_ADDR_CMD27K1MEM_ADDR_CMD28P2MEM_ADDR_CMD29N4MEM_ADDR_CMD30P4
MEM_DQS_ADDR_CMD_P V4MEM_DQS_ADDR_CMD_N V5
MEM_DQ_ADDR_CMD0 R6MEM_DQ_ADDR_CMD1 T1MEM_DQ_ADDR_CMD2 R2MEM_DQ_ADDR_CMD3 T2MEM_DQ_ADDR_CMD4 U2MEM_DQ_ADDR_CMD5 U3MEM_DQ_ADDR_CMD6 T4MEM_DQ_ADDR_CMD7 U4MEM_DQ_ADDR_CMD8 T5
MEM_DMA0B10MEM_DMA1C4MEM_DMA2B17MEM_DMA3F17
MEM_DQA0A4MEM_DQA1B4MEM_DQA2B5MEM_DQA3B6MEM_DQA4A8MEM_DQA5B8MEM_DQA6B9MEM_DQA7A10MEM_DQA8B1MEM_DQA9B2MEM_DQA10C2MEM_DQA11C3MEM_DQA12E3MEM_DQA13D4MEM_DQA14D1MEM_DQA15D2MEM_DQA16A12MEM_DQA17B12MEM_DQA18B13MEM_DQA19B14MEM_DQA20C15MEM_DQA21A16MEM_DQA22B16MEM_DQA23A18MEM_DQA24C16MEM_DQA25D16MEM_DQA26E16MEM_DQA27F16MEM_DQA28D17MEM_DQA29C18MEM_DQA30D18MEM_DQA31E18MEM_DQA32E2MEM_DQA33G16
MEM_DQSA_P0A6
MEM_DQSA_P1A2
MEM_DQSA_P2A14
MEM_DQSA_P3F18
MEM_DQSA_N0A7
MEM_DQSA_N1A3
MEM_DQSA_N2A15
MEM_DQSA_N3G18
MEM_QKA_N0A11
MEM_DQSB_N0 J18
MEM_DQSB_N1 V18
MEM_DQSB_N2 V17
MEM_DQSB_N3 V9
MEM_DQSB_P0 H18
MEM_DQSB_P1 U18
MEM_DQSB_P2 V16
MEM_DQSB_P3 V8
MEM_QKB_N0 M18
MEM_DMB0 M16MEM_DMB1 U16MEM_DMB2 U11MEM_DMB3 U6
MEM_DQB0 H16MEM_DQB1 J16MEM_DQB2 K16MEM_DQB3 L16MEM_DQB4 H17MEM_DQB5 K17MEM_DQB6 K18MEM_DQB7 L18MEM_DQB8 M17MEM_DQB9 N18
MEM_DQB10 P17MEM_DQB11 P18MEM_DQB12 R18MEM_DQB13 T16MEM_DQB14 T17MEM_DQB15 T18MEM_DQB16 U15MEM_DQB17 T14MEM_DQB18 U14MEM_DQB19 V14MEM_DQB20 T13MEM_DQB21 T12MEM_DQB22 U12MEM_DQB23 V12MEM_DQB24 T10MEM_DQB25 U10MEM_DQB26 V10MEM_DQB27 T9MEM_DQB28 T8MEM_DQB29 U8MEM_DQB30 U7MEM_DQB31 V6MEM_DQB32 R16MEM_DQB33 T6
CONFIG0 L6CONFIG1 M6
RFU2 H5RFU3 K5RFU4 N6RFU5 R7
MEM_ADDR_CMD31N3
MEM_QKA_N1B18 MEM_QKB_N1 V13
RFU6 R8
HiLo EMI - POWER
VDD = 1.1(DEFAULT)
VDDQ = 1.1(DEFAULT))
VEXT = 2.5V
J13B
HLS-180324-B-12
VDDC7VDDC9VDDC11VDDC13VDDD6VDDD8VDDD10VDDD12VDDD14VDDE7VDDE9VDDE11VDDE13VDDF6VDDF8VDDF10
VDDQF12VDDQF14VDDQG7VDDQG9VDDQG11VDDQG13VDDQH6VDDQH8VDDQH10VDDQH12
VEXT L11VEXT L13VEXT M8VEXT M10VEXT M12VEXT M14VEXT N7VEXT N9VEXT N11VEXT N13VEXT P8VEXT P10VEXT P12VEXT P14
2.5V/3.3V (VTT) J72.5V/3.3V (VTT) J92.5V/3.3V (VTT) K62.5V/3.3V (VTT) K8
2.5V/3.3V (VTT) L72.5V/3.3V (VTT) L9
VREF H14
2.5V/3.3V (VTT) J11
VREF J13
2.5V/3.3V (VTT) K102.5V/3.3V (VTT) K12
VREF K14
VDD_1.2V_SETG15VDD_1.25V_SETD5
VDD_1.35V_SETJ15VDD_1.5V_SETL15VDD_1.8V_SETN16
VDDQ_1.8V_SETR11VDDQ_1.35V_SETR14VDDQ_1.25V_SETF5 VDDQ_1.2V_SETP16
VDDQ_1.5V_SETR12
VDDQ_1.1V_SETN15
VDD_1.30V_SETE15
VDDQ_1.30V_SETR15 R167 240
C24610uF
C2420.1uF
R168 240
C2450.1uF
C2480.1uF
HiLo EMI - GNDJ13C
HLS-180324-B-12
GNDA1GNDA5GNDA9GNDA13GNDA17GNDB3GNDB7GNDB11GNDB15GNDC1GNDC5GNDC6GNDC8GNDC10GNDC12GNDC14GNDC17GNDD3GNDD7GNDD9GNDD11GNDD13GNDD15GNDE1GNDE5GNDE6GNDE8GNDE10GNDE12GNDE14GNDE17GNDF3GNDF7GNDF9GNDF11GNDF13GNDF15GNDG1GNDG5GNDG6GNDG8GNDG10GNDG12GNDG14GNDG17GNDH3GNDH7GNDH9GNDH11GNDH13GNDH15GNDJ1GNDJ5GNDJ6GNDJ8
GND J10GND J12GND J14GND J17GND K3GND K7GND K9GND K11GND K13GND K15GND L1GND L5GND L8GND L10GND L12GND L14GND L17GND M3GND M7GND M9GND M11GND M13GND M15GND N1GND N5GND N8GND N10GND N12GND N14GND N17GND P3GND P6GND P7GND P9GND P11GND P13GND P15GND R1GND R5GND R9GND R10GND R13GND R17GND T3GND T7GND T11GND T15GND U1GND U5GND U9GND U13GND U17GND V3GND V7GND V11GND V15
C24310uF
C2471uF
C2441uF
![Page 27: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/27.jpg)
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D D
C C
B B
A A
16GB DDR4 SODIMM
0201
0201
I2C address "1010101" EEPROM
I2C address "0011101" Temperature sensor
SL_DQB028 SL_DQB128 SL_DQB228SL_DQB328 SL_DQB428 SL_DQB528 SL_DQB628 SL_DQB728SL_DM028 SL_DQSP028 SL_DQSN028SL_DQB828SL_DQB928 SL_DQB1028 SL_DQB1128 SL_DQB1228 SL_DQB1328SL_DQB1428 SL_DQB1528 SL_DM128 SL_DQSP128 SL_DQSN128SL_DQB1628 SL_DQB1728 SL_DQB1828 SL_DQB1928SL_DQB2028 SL_DQB2128 SL_DQB2228 SL_DQB2328 SL_DM228SL_DQSP228 SL_DQSN228SL_DQB2428 SL_DQB2528SL_DQB2628 SL_DQB2728 SL_DQB2828 SL_DQB2928 SL_DQB3028SL_DQB3128 SL_DM328 SL_DQSP328 SL_DQSN328SL_DQB3228 SL_DQB3328 SL_DQB3428 SL_DQB3528 SL_DQB3628SL_DQB3728 SL_DQB3828 SL_DQB3928 SL_DM428 SL_DQSP428SL_DQSN428SL_DQB4028 SL_DQB4128 SL_DQB4228SL_DQB4328 SL_DQB4428 SL_DQB4528 SL_DQB4628 SL_DQB4728SL_DM528 SL_DQSP528 SL_DQSN528SL_DQB4828SL_DQB4928 SL_DQB5028 SL_DQB5128 SL_DQB5228 SL_DQB5328SL_DQB5428 SL_DQB5528 SL_DM628 SL_DQSP628 SL_DQSN628
SL_DQB56 28SL_DQB57 28SL_DQB58 28SL_DQB59 28SL_DQB60 28SL_DQB61 28SL_DQB62 28SL_DQB63 28
SL_DM7 28SL_DQSP7 28SL_DQSN7 28
SL_DQB64 28SL_DQB65 28SL_DQB66 28SL_DQB67 28SL_DQB68 28SL_DQB69 28SL_DQB70 28SL_DQB71 28SL_DM8 28SL_DQSP8 28SL_DQSN8 28
SL_A0 28SL_A1 28SL_A2 28SL_A3 28SL_A4 28SL_A5 28SL_A6 28SL_A7 28SL_A8 28SL_A9 28SL_A10 28SL_A11 28SL_A12 28SL_A13 28SL_BA0 28SL_BA1 28SL_BG0 28SL_BG1 28SL_C0n 28SL_C1n 28SL_CK0n 28SL_CK0p 28SL_CK1n 28SL_CK1p 28SL_CKE0 28SL_CKE1 28SL_CS0n 28SL_CS1n 28SL_ODT0n 28SL_ODT1n 28
SL_ACTn 28SL_RASn 28SL_WEn 28SL_CASn 28
SL_RESETn 28
SL_PARITY 28SL_ALERTn 28SL_EVENTn 28
SODIMM_I2C_SDA38SODIMM_I2C_SCL38
IO_2V5 10,11,12,22,26,32,38,43,68
0V6_DDR4_DIMM_VTT 57
S10DDR_1V2 28,31,43,57,60,63,66
0V6_DDR4_DIMM_VTT
0V6_DDR4_DIMM_VTT
S10DDR_1V2
S10DDR_1V2
IO_2V5
IO_2V5
IO_2V5
0V6_DDR4_DIMM_VTT
S10DDR_1V2
IO_2V5
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
27 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
27 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
27 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C25522nF
C2490.1uF
C25322nF
R170 240
R169 240
C259330uF
C25122nF
C260100uF
C26522nF
C26322nF
C25822nF
C26122nF
C25622nF
C25422nF
C267330uF
C25222nF
C25022nF
C268100uF
R910 10K
C26622nF
2309407-5
J28-2SDA254SCL253SA2166SA1260SA0256
VSS65252VSS66248VSS67244VSS68238VSS69234VSS70230VSS71226VSS72222VSS73218VSS74214VSS75210VSS76206VSS77202VSS78196VSS79192VSS80188VSS81184VSS82180VSS83176VSS84172VSS85168VSS86106VSS87102VSS8898VSS8994VSS9090VSS9186VSS9282VSS9378VSS9472
VDD1 111VDD2 117VDD3 123VDD4 129VDD5 135VDD6 141VDD7 147VDD8 153VDD9 159
VDD10 163VDD11 112VDD12 118VDD13 124VDD14 130VDD15 136VDD16 142VDD17 148VDD18 154VDD19 160
VDDSPD 255
VPP1 257VPP2 259
VREFCA 164
VTT 258
VSS1 1VSS2 5VSS3 9VSS4 15VSS5 19VSS6 23VSS7 27VSS8 31VSS9 35
VSS10 39VSS11 43VSS12 47VSS13 51VSS14 57VSS15 61VSS16 65VSS17 69VSS18 73VSS19 77VSS20 81VSS21 85VSS22 89VSS23 93VSS24 99VSS25 103VSS26 107VSS27 167VSS28 171VSS29 175VSS30 181VSS31 185VSS32 189VSS33 193VSS34 197VSS35 201VSS36205 VSS37209 VSS38213 VSS39217 VSS40223 VSS41227 VSS42231 VSS43235 VSS44239 VSS45243 VSS46247 VSS47251 VSS482 VSS496 VSS5010 VSS5114 VSS5218 VSS5322 VSS5426 VSS5530 VSS5636 VSS5740 VSS5844 VSS5948 VSS6052 VSS6156 VSS6260 VSS6364 VSS6468
C26422nF2309407-5
J28-1
CB0/NC 92CB1/NC 91CB2/NC 101CB3/NC 105CB4/NC 88CB5/NC 87CB6/NC 100CB7/NC 104
DM8_N/DBI_N/NC 96
DQS8_C 95DQS8_T 97
DQ08DQ17DQ220DQ321DQ44DQ53DQ616DQ717DM0_N/DBI0_N12DQS0_T13DQS0_C11
DQ828DQ929DQ1041DQ1142DQ1224DQ1325DQ1438DQ1537DM1_N/DBI_N33DQS1_T34DQS1_C32
DQ1650DQ1749DQ1862DQ1963DQ2046DQ2145DQ2258DQ2359DM2_N/DBI4_N54DQS2_T55DQS2_C53
DQ2470DQ2571DQ2683DQ2784DQ2866DQ2967DQ3079DQ3180DM3_N/DBI3_N75DQS3_T76DQS3_C74
DQ32174DQ33173DQ34187DQ35186DQ36170DQ37169DQ38183DQ39182DM4_N/DBI4_N178DQS4_T179DQS4_C177
DQ40195DQ41194DQ42207DQ43208DQ44191DQ45190DQ46203DQ47204DM5_N/DBI5_N199DQS5_T200DQS5_C198
DQ48216DQ49215DQ50228DQ51229DQ52211DQ53212DQ54224DQ55225DM6_N/DBI6_N220DQS6_T221DQS6_C219
DQ56 237DQ57 236DQ58 249DQ59 250DQ60 232DQ61 233DQ62 245DQ63 246
DM7_N/ 241
DQS7_C,DBI7_N 240DQS7_T 242
A0 144A1 133A2 132A3 131A4 128A5 126A6 127A7 122A8 125A9 121
A10/AP 146A11 120A12 119A13 158BA0 150BA1 145BG0 115BG1 113
C0/CS2_N/NC 162C1,CS3_N,NC 165
CK0_C 139CK0_T 137
CK1_C/NF 140CK1_T/NF 138
CKE0 109CKE1/NC 110
CS0_N 149CS1_N/NC 157
ODT0 155ODT1/NC 161
ALERT_N 116EVENT_N,NF 134
PARITY 143
ACT_N 114RAS_N/A16 152WE_N/A14 151
CAS_N/A15 156
RESET_N 108
C26222nF
C25722nF
![Page 28: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/28.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Stratix 10 Banks - 3 I/J/L/K
SL_ALERTn 27
CLK_EMI_1N33
CLK_EMI_1P33
SL_BG1 27SL_RESETn 27SL_ACTn 27SL_CS0n 27
SL_CKE1 27SL_CKE0 27SL_ODT1n 27SL_ODT0n 27
SL_A3 27SL_A2 27
SL_CS1n 27SL_CK0p 27
SL_A0 27
SL_CK0n 27SL_PARITY 27SL_A1 27
SL_A7 27SL_A6 27SL_A5 27SL_A4 27
SL_A11 27SL_A10 27SL_A8 27SL_A9 27
SL_RASn 27SL_CASn 27
SL_C1n 27SL_BG0 27SL_BA1 27SL_BA0 27
SL_A13 27SL_A12 27SL_WEn 27
SL_C0n 27
SL_CK1n 27SL_CK1p 27
SL_EVENTn 27
USER_LED_FPGA231 USER_LED_FPGA131 USER_LED_FPGA331USER_PB_FPGA131 USER_PB_FPGA231 USER_PB_FPGA331
USER_DIPSW_FPGA131 USER_DIPSW_FPGA231 USER_DIPSW_FPGA331
USER_PB_FPGA031
USER_DIPSW_FPGA031
USER_LED_FPGA031
SL_DQB52 27SL_DQB50 27
SL_DQB51 27
SL_DQB49 27SL_DQB53 27SL_DQB48 27SL_DQSN6 27SL_DQSP6 27SL_DQB55 27
SL_DQB54 27
SL_DM6 27
SL_DQB6127
SL_DQB6327SL_DQB5827
SL_DQB5727
SL_DQB5627
SL_DQB6027SL_DQSN727 SL_DQSP727SL_DQB6227SL_DQB5927
SL_DM727
SL_DQB4027SL_DQB4427 SL_DQB4227
SL_DQB4327 SL_DQB4527
SL_DQB4627
SL_DQSN527 SL_DQSP527
SL_DQB4727 SL_DQB4127
SL_DM527
SL_DQB64 27
SL_DQB69 27SL_DQB68 27
SL_DQB65 27
SL_DQB70 27SL_DQB71 27SL_DQSN8 27SL_DQSP8 27SL_DQB67 27SL_DQB66 27SL_DM8 27
SL_DQB527
SL_DQB127
SL_DQB227
SL_DQB627 SL_DQB727SL_DQB327
SL_DQSN027 SL_DQSP027 SL_DQB027
SL_DQB427
SL_DM027
SL_DQB3727
SL_DQB3527 SL_DQB3927SL_DQB3627
SL_DQB3827 SL_DQB3427SL_DQSN427 SL_DQSP427SL_DQB3227
SL_DQB3327
SL_DM427
SL_DQB1527
SL_DQB1227
SL_DQB927 SL_DQB1027
SL_DQB1327
SL_DQB827
SL_DQSN127 SL_DQSP127
SL_DQB1427
SL_DQB1127
SL_DM127
SL_DQB25 27
SL_DQB27 27SL_DQB31 27SL_DQB24 27SL_DQB30 27
SL_DQB26 27
SL_DQSN3 27SL_DQSP3 27SL_DQB29 27
SL_DQB28 27
SL_DM3 27
SL_DQB16 27SL_DQB18 27SL_DQB19 27SL_DQB23 27SL_DQB20 27
SL_DQB22 27SL_DQSN2 27SL_DQSP2 27SL_DQB21 27SL_DQB17 27
SL_DM2 27
S10DDR_1V2
S10DDR_1V2
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
28 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
28 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
28 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R172100
R10051.00k
R9111.00k
R171240
BANK 3
I
BANK 3
K
BANK 3
J
BANK 3
L
1SX280LU3F50E3VGS1
U15FIO, LVDS3I_1N, DQ60V21IO, LVDS3I_1P, DQ60V22IO, LVDS3I_2N, DQ60T21IO, LVDS3I_2P, DQ60R21IO, LVDS3I_3N, DQ60V23IO, LVDS3I_3P, DQ60V24IO, LVDS3I_4N, DQSN60U20IO, LVDS3I_4P, DQS60T20IO, LVDS3I_5N, DQ60R22IO, LVDS3I_5P, DQ60T22IO, LVDS3I_6N, DQ60U23IO, LVDS3I_6P, DQ60U22IO, LVDS3I_7N, DQ61N22IO, LVDS3I_7P, DQ61M22IO, LVDS3I_8N, DQ61L22IO, LVDS3I_8P, DQ61K22IO, LVDS3I_9N, DQ61R23IO, LVDS3I_9P, DQ61P23IO, PLL_3I_CLKOUT1N, LVDS3I_10N, DQSN61R24IO, PLL_3I_CLKOUT1P, PLL_3I_CLKOUT1, PLL_3I_FBN, LVDS3I_10P, DQS61P24IO, LVDS3I_11N, DQ61N23IO, RZQ_3I, LVDS3I_11P, DQ61M23IO, CLK_3I_1N, LVDS3I_12N, DQ61T24IO, CLK_3I_1P, LVDS3I_12P, DQ61U24IO, CLK_3I_0N, LVDS3I_13N, DQ62L24IO, CLK_3I_0P, LVDS3I_13P, DQ62M24IO, LVDS3I_14N, DQ62G24IO, LVDS3I_14P, DQ62F24IO, PLL_3I_CLKOUT0N, LVDS3I_15N, DQ62G23IO, PLL_3I_CLKOUT0P, PLL_3I_CLKOUT0, PLL_3I_FBP, PLL_3I_FB0, LVDS3I_15P, DQ62H23IO, LVDS3I_16N, DQSN62K23IO, LVDS3I_16P, DQS62J23IO, LVDS3I_17N, DQ62J24IO, LVDS3I_17P, DQ62K24IO, LVDS3I_18N, DQ62H22IO, LVDS3I_18P, DQ62G22IO, LVDS3I_19N, DQ63A24IO, LVDS3I_19P, DQ63B24IO, LVDS3I_20N, DQ63F22IO, LVDS3I_20P, DQ63E22IO, LVDS3I_21N, DQ63A26IO, LVDS3I_21P, DQ63A25IO, LVDS3I_22N, DQSN63D23IO, LVDS3I_22P, DQS63D24IO, LVDS3I_23N, DQ63B23IO, LVDS3I_23P, DQ63C23IO, LVDS3I_24N, DQ63E23IO, LVDS3I_24P, DQ63E24
IO, LVDS3J_1N, DQ56E11IO, LVDS3J_1P, DQ56F11IO, LVDS3J_2N, DQ56G10IO, LVDS3J_2P, DQ56H10IO, LVDS3J_3N, DQ56D10IO, LVDS3J_3P, DQ56D11IO, LVDS3J_4N, DQSN56G12IO, LVDS3J_4P, DQS56H12IO, LVDS3J_5N, DQ56F10IO, LVDS3J_5P, DQ56E10IO, LVDS3J_6N, DQ56F12IO, LVDS3J_6P, DQ56E12IO, LVDS3J_7N, DQ57J11IO, LVDS3J_7P, DQ57H11IO, LVDS3J_8N, DQ57K11IO, LVDS3J_8P, DQ57K12IO, LVDS3J_9N, DQ57K10IO, LVDS3J_9P, DQ57J10IO, PLL_3J_CLKOUT1N, LVDS3J_10N, DQSN57M12IO, PLL_3J_CLKOUT1P, PLL_3J_CLKOUT1, PLL_3J_FBN, LVDS3J_10P, DQS57L12IO, LVDS3J_11N, DQ57L10IO, RZQ_3J, LVDS3J_11P, DQ57L11IO, CLK_3J_1N, LVDS3J_12N, DQ57K13IO, CLK_3J_1P, LVDS3J_12P, DQ57J13IO, CLK_3J_0N, LVDS3J_13N, DQ58N13IO, CLK_3J_0P, LVDS3J_13P, DQ58P14IO, LVDS3J_14N, DQ58M13IO, LVDS3J_14P, DQ58M14IO, PLL_3J_CLKOUT0N, LVDS3J_15N, DQ58P15IO, PLL_3J_CLKOUT0P, PLL_3J_CLKOUT0, PLL_3J_FBP, PLL_3J_FB0, LVDS3J_15P, DQ58P16IO, LVDS3J_16N, DQSN58P13IO, LVDS3J_16P, DQS58P12IO, LVDS3J_17N, DQ58R16IO, LVDS3J_17P, DQ58R17IO, LVDS3J_18N, DQ58R14IO, LVDS3J_18P, DQ58R13IO, LVDS3J_19N, DQ59T19IO, LVDS3J_19P, DQ59U19IO, LVDS3J_20N, DQ59R18IO, LVDS3J_20P, DQ59R19IO, LVDS3J_21N, DQ59W18IO, LVDS3J_21P, DQ59V17IO, LVDS3J_22N, DQSN59T17IO, LVDS3J_22P, DQS59U17IO, LVDS3J_23N, DQ59U18IO, LVDS3J_23P, DQ59V18IO, LVDS3J_24N, DQ59T16IO, LVDS3J_24P, DQ59T15
IO, LVDS3K_1N, DQ52 M15IO, LVDS3K_1P, DQ52 N15IO, LVDS3K_2N, DQ52 N18IO, LVDS3K_2P, DQ52 P18IO, LVDS3K_3N, DQ52 K16IO, LVDS3K_3P, DQ52 L16
IO, LVDS3K_4N, DQSN52 K17IO, LVDS3K_4P, DQS52 L17
IO, LVDS3K_5N, DQ52 N17IO, LVDS3K_5P, DQ52 N16IO, LVDS3K_6N, DQ52 M18IO, LVDS3K_6P, DQ52 M17IO, LVDS3K_7N, DQ53 J14IO, LVDS3K_7P, DQ53 K14IO, LVDS3K_8N, DQ53 H17IO, LVDS3K_8P, DQ53 G17IO, LVDS3K_9N, DQ53 F15IO, LVDS3K_9P, DQ53 G15
IO, PLL_3K_CLKOUT1N, LVDS3K_10N, DQSN53 J15IO, PLL_3K_CLKOUT1P, PLL_3K_CLKOUT1, PLL_3K_FBN, LVDS3K_10P, DQS53 H15
IO, LVDS3K_11N, DQ53 L14IO, RZQ_3K, LVDS3K_11P, DQ53 L15
IO, CLK_3K_1N, LVDS3K_12N, DQ53 H16IO, CLK_3K_1P, LVDS3K_12P, DQ53 J16IO, CLK_3K_0N, LVDS3K_13N, DQ54 F16IO, CLK_3K_0P, LVDS3K_13P, DQ54 E16
IO, LVDS3K_14N, DQ54 D15IO, LVDS3K_14P, DQ54 C15
IO, PLL_3K_CLKOUT0N, LVDS3K_15N, DQ54 B15IO, PLL_3K_CLKOUT0P, PLL_3K_CLKOUT0, PLL_3K_FBP, PLL_3K_FB0, LVDS3K_15P, DQ54 A16
IO, LVDS3K_16N, DQSN54 B13IO, LVDS3K_16P, DQS54 B14
IO, LVDS3K_17N, DQ54 A15IO, LVDS3K_17P, DQ54 A14IO, LVDS3K_18N, DQ54 D16IO, LVDS3K_18P, DQ54 C16IO, LVDS3K_19N, DQ55 A12IO, LVDS3K_19P, DQ55 B12IO, LVDS3K_20N, DQ55 D14IO, LVDS3K_20P, DQ55 E14IO, LVDS3K_21N, DQ55 C12IO, LVDS3K_21P, DQ55 C13
IO, LVDS3K_22N, DQSN55 F14IO, LVDS3K_22P, DQS55 G14
IO, LVDS3K_23N, DQ55 D13IO, LVDS3K_23P, DQ55 E13IO, LVDS3K_24N, DQ55 H13IO, LVDS3K_24P, DQ55 G13
IO, LVDS3L_1N, DQ48 B20IO, LVDS3L_1P, DQ48 A19IO, LVDS3L_2N, DQ48 B17IO, LVDS3L_2P, DQ48 A17IO, LVDS3L_3N, DQ48 A21IO, LVDS3L_3P, DQ48 A20
IO, LVDS3L_4N, DQSN48 C18IO, LVDS3L_4P, DQS48 C17
IO, LVDS3L_5N, DQ48 B22IO, LVDS3L_5P, DQ48 A22IO, LVDS3L_6N, DQ48 B19IO, LVDS3L_6P, DQ48 B18IO, LVDS3L_7N, DQ49 E17IO, LVDS3L_7P, DQ49 F17IO, LVDS3L_8N, DQ49 D18IO, LVDS3L_8P, DQ49 E18IO, LVDS3L_9N, DQ49 D19IO, LVDS3L_9P, DQ49 E19
IO, PLL_3L_CLKOUT1N, LVDS3L_10N, DQSN49 C20IO, PLL_3L_CLKOUT1P, PLL_3L_CLKOUT1, PLL_3L_FBN, LVDS3L_10P, DQS49 D20
IO, LVDS3L_11N, DQ49 D21IO, RZQ_3L, LVDS3L_11P, DQ49 E21
IO, CLK_3L_1N, LVDS3L_12N, DQ49 C21IO, CLK_3L_1P, LVDS3L_12P, DQ49 C22IO, CLK_3L_0N, LVDS3L_13N, DQ50 J19IO, CLK_3L_0P, LVDS3L_13P, DQ50 J20
IO, LVDS3L_14N, DQ50 F19IO, LVDS3L_14P, DQ50 G19
IO, PLL_3L_CLKOUT0N, LVDS3L_15N, DQ50 K18IO, PLL_3L_CLKOUT0P, PLL_3L_CLKOUT0, PLL_3L_FBP, PLL_3L_FB0, LVDS3L_15P, DQ50 J18
IO, LVDS3L_16N, DQSN50 F21IO, LVDS3L_16P, DQS50 F20
IO, LVDS3L_17N, DQ50 H18IO, LVDS3L_17P, DQ50 G18IO, LVDS3L_18N, DQ50 H20IO, LVDS3L_18P, DQ50 G20IO, LVDS3L_19N, DQ51 H21IO, LVDS3L_19P, DQ51 J21IO, LVDS3L_20N, DQ51 L19IO, LVDS3L_20P, DQ51 K19IO, LVDS3L_21N, DQ51 L21IO, LVDS3L_21P, DQ51 K21
IO, LVDS3L_22N, DQSN51 L20IO, LVDS3L_22P, DQS51 M20
IO, LVDS3L_23N, DQ51 N21IO, LVDS3L_23P, DQ51 P21IO, LVDS3L_24N, DQ51 N20IO, LVDS3L_24P, DQ51 P20
![Page 29: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/29.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Stratix 10 Banks - Configuration
VFEF_ADC sources from 1.25V zener
HPS_DIO11
HPS_DIO1HPS_DIO4HPS_DIO10HPS_DIO12HPS_DIO2HPS_DIO8HPS_DIO9
HPS_DIO0
Boost Flash Slot
HPS_DIO5HPS_DIO13HPS_DIO3HPS_DIO7HPS_DIO6
Config Mode MSEL2 MSEL1 MSEL0 AVST X 16 on off on QSPI on off on NAND X 8 off on off SDMMC X 4 on off off JTAG ONLY on on on
MSEL0_LINE
MSEL1_LINE
MSEL2_LINE
FPGA_PMVID
Put close to FPGA pin
HPS_DIO11HPS_DIO13HPS_DIO3
HPS_DIO5
HPS_DIO7
HPS_DIO0
HPS_DIO6
FPGA Boost Flash Slot
HPS_DIO8
HPS_DIO10
HPS_DIO9
HPS_DIO12
HPS_DIO1
HPS_DIO2
HPS_DIO4
NPERSTL041
NPERSTL241
NPERSTR0 41
NPERSTR2 41
1V8_IO_MUX039 1V8_IO_MUX139 1V8_IO_MUX239 1V8_IO_MUX339 1V8_IO_MUX439 1V8_IO_MUX539 1V8_IO_MUX639
1V8_IO_MUX739 1V8_IO_MUX839 1V8_IO_MUX939 1V8_IO_MUX1039 1V8_IO_MUX1139 1V8_IO_MUX1239 1V8_IO_MUX27 39
1V8_IO_MUX14 411V8_IO_MUX15 411V8_IO_MUX16 411V8_IO_MUX17 411V8_IO_MUX18 411V8_IO_MUX19 411V8_IO_MUX20 41
1V8_IO_MUX21 411V8_IO_MUX22 411V8_IO_MUX23 391V8_IO_MUX24 391V8_IO_MUX25 391V8_IO_MUX26 391V8_IO_MUX1339
PMbus_SCL_3V3 38,50,54,58,59,62PMbus_SDA_3V3 38,50,54,58,59,62
S10PMBUSEN 41
S10_JTAG_TDO 8
S10_JTAG_TDI 8S10_JTAG_TCK 8S10_JTAG_TMS 8
IO_1V8 12,21,22,25,30,32,33,34,36,39,40,43,63,64,65,66,68
BQSPI_RESETN 47BF_Presentn47
HPS_NRST 47
S10_VCCPT 59,63,66,68,70
MSEL042
MSEL142
MSEL242
IO_3V3 14,15,16,17,22,25,26,30,31,32,34,35,36,37,38,43,57,69,70
FPGA_OSC_CLK134FPGA_nCONFIG41 FPGA_nSTATUS41
CONF_DONE 41
3V3 7,8,31,46,47,50,51,52,53,67,69
FPGAboot_RESETN 47FPGABoot_Presentn46
FPGA_BOOT_DIO0 25FPGA_BOOT_DIO125
FPGA_BOOT_DIO225
FPGA_BOOT_DIO425 FPGA_BOOT_DIO5 25
FPGA_BOOT_DIO6 25FPGA_BOOT_DIO7 25FPGA_BOOT_DIO3 25FPGA_BOOT_DIO825 FPGA_BOOT_DIO925
FPGA_BOOT_DIO1025 FPGA_BOOT_DIO11 25FPGA_BOOT_DIO13 25FPGA_BOOT_DIO1225
AVST_Ready41
SDM_MAXB_IO041 SDM_MAXB_IO142 SDM_MAXB_IO242 SDM_MAXB_IO342 SDM_MAXB_IO442SDM_MAXB_IO5 42SDM_MAXB_IO6 42
IO_1V8 IO_3V3
IO_1V8
IO_1V8
IO_1V8
IO_1V8
IO_3V3IO_3V3
S10_VCCPT
S10_VCCPT
S10_VCCPT
IO_1V8
IO_3V3
3V3
3V3IO_1V8
IO_1V8
IO_3V3IO_3V3
S10_VCCPT
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
29 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
29 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
29 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
J54
QTH-030-02-L-D-A
24681012141618202224262830323436384042444648505254565860
1357911131517192123252729313335373941434547495153555759
61 62 63 64
R198 1.00k
R1840
R195
1.00k
C27210uF
R199DNI
C161910uF
J14
QTH-030-02-L-D-A
24681012141618202224262830323436384042444648505254565860
1357911131517192123252729313335373941434547495153555759
61 62 63 64
R188499
R173 4.70K, 1%
R96210K
R1921.00kR1934.70K, 1%
R196 1.00k
STDOFF2
8mmStandoff
CONFIGURATION
1SX280LU3F50E3VGS1
U15K
TDO BD24TMS BC22TCK AN22TDI AR22
OSC_CLK_1BA22
SDM_IO0,INIT_DONE,PWRMGT_PWM0,PWRMGT_SCLBD23SDM_IO1,AVSTX8_DATA2,AS_DATA1,SDMMC_CFG_DATA1,NAND_RE_NBB22
SDM_IO5,AS_NCSO0,SDMMC_CFG_CCLK, NAND_WE_N,MSEL0,CONF_DONEBC23SDM_IO3,AVSTX8_DATA3,AS_DATA2,SDMMC_CFG_DATA2,NAND_ADQ2BB23
NCONFIGAY22
SDM_IO4,AVSTX8_DATA1,AS_DATA0,SDMMC_CFG_CMD,NAND_ADQ1AN23SDM_IO2,AVSTX8_DATA0,AS_CLK,SDMMC_CFG_DATA0,NAND_ADQ0BE23
SDM_IO7,AS_NCSO2,NAND_ALE,MSEL1BE22
SDM_IO11,AVSTX8_VALID,PWRMGT_SDA,NAND_ADQ6BF22
NSTATUSBJ21
SDM_IO16,CONF_DONE,PWRMGT_SDABG23SDM_IO13,AVSTX8_DATA5,SDMMC_CFG_DATA5,NAND_CE_NAW24
SDM_IO9,AS_NCSO1,NAND_CLE,MSEL2BH22SDM_IO6,AVSTX8_DATA4, AS_DATA3,SDMMC_CFG_DATA3,NAND_ADQ3BA24
SDM_IO10,AVSTX8_DATA7,SDMMC_CFG_DATA7,NAND_ADQ5AY24SDM_IO8,AVST_READY, AS_NCSO3,SDMMC_CFG_DATA4,NAND_RBBE24
SDM_IO12,PWRMGT_PWM0,PWRMGT_SDA,NAND_WP_NBB24
SDM_IO15,AVSTX8_DATA6,SDMMC_CFG_DATA6,NAND_ADQ4BD25 SDM_IO14,AVSTX8_CLK,PWRMGT_SCL,NAND_ADQ7BG22
RREF_SDM BJ23
VREFP_ADC AR23VREFN_ADC AP23VSIGP_0 AU24VSIGN_0 AT24VSIGP_1 AR24VSIGN_1 AP24
RREF_BL AF38RREF_TL AD38RREF_TR AD12RREF_BR AF12 R179 2.0K
Q6MMBT2222A-7-F
CE
B
R180 2.0K
C16220.1uF
C2700.1uF
R202DNI
R197 1.00k
R2004.70K, 1%
R178 2.0K
Q7MMBT2222A-7-F
CE
B
C2710.1uF
R1850
R189
1.00k
C2730.1uF
R1830
C16200.1uF
C2750.1uF
R177 2.0K
R903 33
R181 2.0K
R2034.70K, 1%
R875 0
R176 4.70K, 1%
1SX280LU3F50E3VGS1
U15IIO3V0_10, NPERSTL0AJ34IO3V1_10AG35IO3V2_10AH33IO3V3_10AF34IO3V4_10AE36IO3V5_10AG34IO3V6_10AH32IO3V7_10AJ33
IO3V0_12, NPERSTL2AD34IO3V1_12AD35IO3V2_12AC35IO3V3_12AB34IO3V4_12AC33IO3V5_12AC36IO3V6_12AB35IO3V7_12AB36
IO3V0_20, NPERSTR0 AH16IO3V1_20 AF15IO3V2_20 AB12IO3V3_20 AF17IO3V4_20 AD16IO3V5_20 AF16IO3V6_20 AE16IO3V7_20 AH17
IO3V0_22, NPERSTR2 AE14IO3V1_22 AD15IO3V2_22 AC15IO3V3_22 AC14IO3V4_22 AB13IO3V5_22 AD14IO3V6_22 AB15IO3V7_22 AB14
R182 33
U23
FXMA2102UMX
A0 2A1 3B07
B16
VCCA 1GND 4
OE 5
VCCB8
R791 0
D18
LT1389
Gnd0 4Vout6Gnd1 5
nc1 1nc2 2nc3 3
nc47nc58
R190 0
R902 33
R186 33
R201 1.00k
R790 DNI
R194 0
R191DNI
OPEN
SW2
TDA04H0SB1
12345678
Q5MMBT2222A-7-F
CE
B
C162110uF
C26910uF
STDOFF1
8mmStandoff
R96010K
C2740.1uF
R175 4.70K, 1%
R96110K
R174 4.70K, 1%
R1870
FPGA_nCONFIGFPGA_nSTATUS
BF_DUT_SDM_IO1BF_DUT_SDM_IO2 QSPI_CLKBF_DUT_SDM_IO3BF_DUT_SDM_IO4BF_DUT_SDM_IO5 SDMMC_CLKBF_DUT_SDM_IO6BF_DUT_SDM_IO7BF_DUT_SDM_IO8BF_DUT_SDM_IO9BF_DUT_SDM_IO10BF_DUT_SDM_IO11BF_DUT_SDM_IO12BF_DUT_SDM_IO13BF_DUT_SDM_IO14BF_DUT_SDM_IO15
BF_DUT_SDM_IO4 BF_DUT_SDM_IO2BF_DUT_SDM_IO3BF_DUT_SDM_IO15 BF_DUT_SDM_IO6BF_DUT_SDM_IO11 BF_DUT_SDM_IO10BF_DUT_SDM_IO14BF_DUT_SDM_IO5BF_DUT_SDM_IO8 BF_DUT_SDM_IO1BF_DUT_SDM_IO13 BF_DUT_SDM_IO7BF_DUT_SDM_IO12 BF_DUT_SDM_IO9
BF_DUT_SDM_IO[1:15]
VID_SCL_1V8VID_SDA_1V8
IO8_AVST_ready
![Page 30: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/30.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Stratix 10 Banks - HPS IO-48
HOSTPROCESSOR_I2C
0.5A
0.5AS10_2L_SDA 25,38,41S10_2L_SCL 25,38,41
S10I2CEN_HPS 41
S10_12V 53,54,55,56,58,59,62
IO_1V8 12,21,22,25,29,32,33,34,36,39,40,43,63,64,65,66,68IO_3V3 14,15,16,17,22,25,26,29,31,32,34,35,36,37,38,43,57,69,70
HPS_DC_RESET_n47
HPS_DC_presetn 47
TEMPDIODE_P 38TEMPDIODE_N 38
DC_POWER_GOOD8 MICTOR_JTAG_TCK8MICTOR_JTAG_TMS8MICTOR_JTAG_TDI8 MICTOR_JTAG_TDO8
IO_48_Power_en_3v3 46
S10_12V
IO_1V8
IO_1V8IO_1V8
IO_1V8
IO_1V8
S10_12V
IO_1V8
IO_3V3
IO_3V3
IO_1V8Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
30 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
30 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
30 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R204 10.0K
C2780.1uF
U24
FXMA2102UMX
A0 2A1 3B07
B16
VCCA 1GND 4
OE 5
VCCB8
R2081.00k
J15
QSH-030-01-F-D-A
1 12 23 34 45 56 67 78 89 9
10 1011 1112 1213 1314 1415 1516 1617 1718 1819 1920 2021 2122 2223 2324 2425 2526 2627 2728 2829 2930 3031 3132 3233 3334 3435 3536 3637 3738 3839 3940 4041 4142 4243 4344 4445 4546 4647 4748 4849 4950 5051 5152 5253 5354 5455 5556 5657 5758 5859 5960 60
GND1
61GN
D262
GND3
63GN
D464
C27610uF
STDOFF3
8mmStandoff
R206 10.0K
C2790.1uF
1SX280LU3F50E3VGS1
U15JHPS_IOA_1, GPIO0_IO0, SPIM0_SS1_N, SPIS0_CLK, UART0_CTS_N, NAND_ADQ0, USB0_CLK, SDMMC_CCLKE29HPS_IOA_2, GPIO0_IO1, SPIM1_SS1_N, SPIS0_MOSI, UART0_RTS_N, NAND_ADQ1, USB0_STP, SDMMC_CMDC33HPS_IOA_3, GPIO0_IO2, SPIS0_SS0_N, UART0_TX, I2C1_SDA, NAND_WE_N, USB0_DIR, SDMMC_DATA0D30HPS_IOA_4, GPIO0_IO3, SPIS0_MISO, UART0_RX, I2C1_SCL, NAND_RE_N, USB0_DATA0, SDMMC_DATA1A30HPS_IOA_5, GPIO0_IO4, SPIM0_CLK, UART1_CTS_N, I2C0_SDA, NAND_WP_N, USB0_DATA1, SDMMC_DATA2C32HPS_IOA_6, GPIO0_IO5, SPIM0_MOSI, UART1_RTS_N, I2C0_SCL, NAND_ADQ2, USB0_NXT, SDMMC_DATA3A27HPS_IOA_7, GPIO0_IO6, SPIM0_MISO, MDIO2_MDIO, UART1_TX, I2C_EMAC2_SDA, NAND_ADQ3, USB0_DATA2, SDMMC_DATA4A29HPS_IOA_8, GPIO0_IO7, SPIM0_SS0_N, MDIO2_MDC, UART1_RX, I2C_EMAC2_SCL, NAND_CLE, USB0_DATA3, SDMMC_DATA5E33HPS_IOA_9, GPIO0_IO8, SPIM1_CLK, SPIS1_CLK, MDIO1_MDIO, I2C_EMAC1_SDA, NAND_ADQ4, USB0_DATA4, SDMMC_DATA6F29HPS_IOA_10, GPIO0_IO9, SPIM1_MOSI, SPIS1_MOSI, MDIO1_MDC, I2C_EMAC1_SCL, NAND_ADQ5, USB0_DATA5, SDMMC_DATA7E32HPS_IOA_11, GPIO0_IO10, SPIM1_MISO, SPIS1_SS0_N, MDIO0_MDIO, I2C_EMAC0_SDA, NAND_ADQ6, USB0_DATA6B30HPS_IOA_12, GPIO0_IO11, SPIM1_SS0_N, SPIS1_MISO, MDIO0_MDC, I2C_EMAC0_SCL, NAND_ADQ7, USB0_DATA7D29HPS_IOA_13, GPIO0_IO12, NAND_ALE, USB1_CLK, EMAC0_TX_CLKF31HPS_IOA_14, GPIO0_IO13, NAND_RB, USB1_STP, EMAC0_TX_CTLR29HPS_IOA_15, GPIO0_IO14, NAND_CE_N, USB1_DIR, EMAC0_RX_CLKG28HPS_IOA_16, GPIO0_IO15, USB1_DATA0, EMAC0_RX_CTLF30HPS_IOA_17, GPIO0_IO16, NAND_ADQ8, USB1_DATA1, EMAC0_TXD0J28HPS_IOA_18, GPIO0_IO17, NAND_ADQ9, USB1_NXT, EMAC0_TXD1E28HPS_IOA_19, GPIO0_IO18, NAND_ADQ10, USB1_DATA2, EMAC0_RXD0B34HPS_IOA_20, GPIO0_IO19, SPIM1_SS1_N, NAND_ADQ11, USB1_DATA3, EMAC0_RXD1E31HPS_IOA_21, GPIO0_IO20, SPIM1_CLK, SPIS0_CLK, UART0_CTS_N, I2C1_SDA, NAND_ADQ12, USB1_DATA4, EMAC0_TXD2P29HPS_IOA_22, GPIO0_IO21, SPIM1_MOSI, SPIS0_MOSI, UART0_RTS_N, I2C1_SCL, NAND_ADQ13, USB1_DATA5, EMAC0_TXD3B32HPS_IOA_23, GPIO0_IO22, SPIM1_MISO, SPIS0_SS0_N, UART0_TX, I2C0_SDA, NAND_ADQ14, USB1_DATA6, EMAC0_RXD2G29HPS_IOA_24, GPIO0_IO23, SPIM1_SS0_N, SPIS0_MISO, UART0_RX, I2C0_SCL, NAND_ADQ15, USB1_DATA7, EMAC0_RXD3H28HPS_IOB_1, GPIO1_IO0, SPIM1_CLK, UART0_CTS_N, NAND_ADQ0, EMAC1_TX_CLKG30HPS_IOB_2, GPIO1_IO1, SPIM1_MOSI, UART0_RTS_N, NAND_ADQ1, EMAC1_TX_CTLC28HPS_IOB_3, GPIO1_IO2, SPIM1_MISO, UART0_TX, I2C0_SDA, NAND_WE_N, EMAC1_RX_CLKF32HPS_IOB_4, GPIO1_IO3, SPIM1_SS0_N, UART0_RX, I2C0_SCL, NAND_RE_N, EMAC1_RX_CTLK29HPS_IOB_5, GPIO1_IO4, SPIM1_SS1_N, SPIS1_CLK, UART1_CTS_N, NAND_WP_N, EMAC1_TXD0A34HPS_IOB_6, GPIO1_IO5, SPIS1_MOSI, UART1_RTS_N, NAND_ADQ2, EMAC1_TXD1N30HPS_IOB_7, GPIO1_IO6, SPIS1_SS0_N, UART1_TX, I2C1_SDA, NAND_ADQ3, EMAC1_RXD0B33HPS_IOB_8, GPIO1_IO7, SPIS1_MISO, UART1_RX, I2C1_SCL, NAND_CLE, EMAC1_RXD1H31HPS_IOB_9, GPIO1_IO8, JTAG_TCK, SPIS0_CLK, MDIO2_MDIO, I2C_EMAC2_SDA, NAND_ADQ4, EMAC1_TXD2K28HPS_IOB_10, GPIO1_IO9, JTAG_TMS, SPIS0_MOSI, MDIO2_MDC, I2C_EMAC2_SCL, NAND_ADQ5, EMAC1_TXD3J29HPS_IOB_11, GPIO1_IO10, JTAG_TDO, SPIS0_SS0_N, MDIO0_MDIO, I2C_EMAC0_SDA, NAND_ADQ6, EMAC1_RXD2G32HPS_IOB_12, GPIO1_IO11, JTAG_TDI, SPIS0_MISO, MDIO0_MDC, I2C_EMAC0_SCL, NAND_ADQ7, EMAC1_RXD3A32HPS_IOB_13, GPIO1_IO12, I2C1_SDA, NAND_ALE, SDMMC_DATA0, EMAC2_TX_CLKP30HPS_IOB_14, GPIO1_IO13, I2C1_SCL, NAND_RB, SDMMC_CMD, EMAC2_TX_CTLJ30HPS_IOB_15, GPIO1_IO14, UART1_TX, NAND_CE_N, SDMMC_CCLK, EMAC2_RX_CLKA31HPS_IOB_16, GPIO1_IO15, UART1_RX, SDMMC_DATA1, EMAC2_RX_CTLH30HPS_IOB_17, GPIO1_IO16, UART1_CTS_N, NAND_ADQ8, SDMMC_DATA2, EMAC2_TXD0D31HPS_IOB_18, GPIO1_IO17, SPIM0_SS1_N, UART1_RTS_N, NAND_ADQ9, SDMMC_DATA3, EMAC2_TXD1H32HPS_IOB_19, GPIO1_IO18, SPIM0_MISO, MDIO1_MDIO, I2C_EMAC1_SDA, NAND_ADQ10, SDMMC_DATA4, EMAC2_RXD0B29HPS_IOB_20, GPIO1_IO19, SPIM0_SS0_N, MDIO1_MDC, I2C_EMAC1_SCL, NAND_ADQ11, SDMMC_DATA5, EMAC2_RXD1J31HPS_IOB_21, GPIO1_IO20, SPIM0_CLK, SPIS1_CLK, I2C_EMAC2_SDA, NAND_ADQ12, SDMMC_DATA6, EMAC2_TXD2D33HPS_IOB_22, GPIO1_IO21, SPIM0_MOSI, SPIS1_MOSI, I2C_EMAC2_SCL, NAND_ADQ13, SDMMC_DATA7, EMAC2_TXD3D28HPS_IOB_23, GPIO1_IO22, SPIM0_MISO, SPIS1_SS0_N, MDIO0_MDIO, I2C_EMAC0_SDA, NAND_ADQ14, EMAC2_RXD2K31HPS_IOB_24, GPIO1_IO23, SPIM0_SS0_N, SPIS1_MISO, MDIO0_MDC, I2C_EMAC0_SCL, NAND_ADQ15, EMAC2_RXD3B28
DNU1 C31DNU2 C30DNU3 BJ38DNU4 BH38DNU5 AD36DNU6 AE37DNU7 BJ48DNU8 A48DNU9 BJ2
DNU10 B1
DNU20 AF13DNU19 AF37DNU18 AG13DNU17 AG37DNU16 BF25DNU15 AW23DNU14 BH23DNU13 BF24DNU12 BG24DNU11 BJ24
C27712pF
R205 10.0K
R9151.00k
C16410.1uF
R207DNI
HPS_GPIO0 HPS_GPIO0HPS_GPIO1 HPS_GPIO1HPS_GPIO2 HPS_GPIO2HPS_GPIO3 HPS_GPIO3HPS_GPIO4 HPS_GPIO4HPS_GPIO5 HPS_GPIO5HPS_GPIO6 HPS_GPIO6HPS_GPIO7 HPS_GPIO7HPS_GPIO8 HPS_GPIO8HPS_GPIO9 HPS_GPIO9HPS_GPIO10 HPS_GPIO10HPS_GPIO11 HPS_GPIO11HPS_GPIO12 HPS_GPIO12HPS_GPIO13 HPS_GPIO13HPS_GPIO14 HPS_GPIO14HPS_GPIO15 HPS_GPIO15HPS_GPIO16 HPS_GPIO16HPS_GPIO17 HPS_GPIO17HPS_GPIO18 HPS_GPIO18HPS_GPIO19 HPS_GPIO19HPS_GPIO20 HPS_GPIO20HPS_GPIO21 HPS_GPIO21HPS_GPIO22 HPS_GPIO22HPS_GPIO23 HPS_GPIO23HPS_GPIO24 HPS_GPIO24HPS_GPIO25 HPS_GPIO25HPS_CON_GPIO26HPS_CON_GPIO27HPS_GPIO28 HPS_GPIO28HPS_GPIO29 HPS_GPIO29HPS_GPIO30 HPS_GPIO30HPS_GPIO31 HPS_GPIO31HPS_GPIO32 HPS_GPIO32HPS_GPIO33 HPS_GPIO33HPS_GPIO34 HPS_GPIO34HPS_GPIO35 HPS_GPIO35HPS_GPIO36 HPS_GPIO36HPS_GPIO37 HPS_GPIO37HPS_GPIO38 HPS_GPIO38HPS_GPIO39 HPS_GPIO39HPS_GPIO40 HPS_GPIO40HPS_GPIO41 HPS_GPIO41HPS_GPIO42 HPS_GPIO42HPS_GPIO43 HPS_GPIO43HPS_GPIO44 HPS_GPIO44HPS_GPIO45 HPS_GPIO45HPS_GPIO46 HPS_GPIO46HPS_GPIO47 HPS_GPIO47
![Page 31: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/31.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
User I/O
3V3 Power on LED
MAX_ERROR46
MAX_LOAD41
MAX_CONF_DONE41
PGM_LED042
PGM_LED142
PGM_LED242USER_LED_FPGA0 28USER_LED_FPGA1 28USER_LED_FPGA2 28USER_LED_FPGA3 28
USER_DIPSW_FPGA0 28USER_DIPSW_FPGA1 28USER_DIPSW_FPGA2 28USER_DIPSW_FPGA3 28
PGM_CONFIG42 PGM_SEL41 Logic_RESETn41
USER_PB_FPGA028 USER_PB_FPGA128 USER_PB_FPGA228 USER_PB_FPGA328
2V5 8,46,51,683V3 7,8,29,46,47,50,51,52,53,67,69
FAPRSNT_N19,47
FBPRSNT_N23,47
SECURITY_MODE 39FACTORY_LOAD 39DC_POWER_CTRL 47
I2C_flag 41
IO_3V3 14,15,16,17,22,25,26,29,30,32,34,35,36,37,38,43,57,69,70
IO_1V8 12,21,22,25,29,30,32,33,34,36,39,40,43,63,64,65,66,68
CLKcleaner_status036,41
CLKcleaner_status136,41
IO_2V5 10,11,12,22,26,27,32,38,43,68
S10DDR_1V2 27,28,43,57,60,63,66
3V32V5
3V3
3V3
3V3
IO_3V3
IO_3V3
IO_1V8
IO_2V5
S10DDR_1V2
IO_3V3
S10DDR_1V2
S10DDR_1V2
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
31 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
31 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
31 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Q72MMBT2222A-7-F
CE
B
R212 100
R218 100
R1025 1.00K
D28 Green_LED
R942 4.7K
R938 4.7K
R217 100
R940 4.7K
Q71MMBT2222A-7-F
CE
B
D22 Green_LED
R216 100
R214 100
D62 Green_LED
D23 Green_LED
R223 10K
Q70MMBT2222A-7-F
CE
B
R937 4.7K
R820 100
D27 Green_LED
R225 100
S4PB Switch
1 2
Q69MMBT2222A-7-F
CE
B
D19 Red_LED
R219 10K
S2PB Switch
1 2
R211 100
D20 Green_LED
R222 10K
S5PB Switch
1 2
R1027 1.00K
R936 4.7K
R210 100
R943 4.7KR941 4.7K
D24 Green_LED
D21 Green_LED
R215 100
S7PB Switch
1 2
S3PB Switch
1 2
R221 10K
R821 100
R220 100
R209 100
S1PB Switch
1 2
OPEN
SW4
TDA04H0SB1
12345678
D29 Green_LED
D31 Green_LED
R1026 1.00KD30 Green_LED
D26 Green_LED
D61 Green_LED
R939 4.7K
OPEN
SW3
TDA04H0SB1
12345678
D25 Green_LED
R224 100
R213 100
R1024 1.00K
S6PB Switch
1 2
MAX_LOAD
MAX_ERROR
MAX_CONF_DONE
PGM_LED1
PGM_LED2
PGM_LED0
![Page 32: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/32.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
PCIE& FPGA Reference Clock1
CMOS
Si5358 Programmable Oscillator Use Clock Control GUI (Defaults 156.25MHz,156.25MHz,25MHz,25MHz, 25MHz, 25MHz,100MHz, 100MHz)I2C Address 70 HEX
27Mhz
100Mhz
100MHz
148.5Mhz
PCIE reference clock
I2C Address = b'1110000'
100MHz
100MHz
27Mhz
IO_1V812,21,22,25,29,30,33,34,36,39,40,43,63,64,65,66,68
CLK_3Ap 21
IO_3V314,15,16,17,22,25,26,29,30,31,34,35,36,37,38,43,57,69,70
PCIE_REFCLK_QR0_P 13PCIE_REFCLK_QR0_N 13
PCIE_REFCLK_SYN_P 9PCIE_REFCLK_SYN_N 9
CLK_50M_MAX 47
CLKUSR 22
CLOCK_I2C_SCL33,38CLOCK_I2C_SDA33,38
IO_2V510,11,12,22,26,27,38,43,68
CLK_3An 21
HDMIREFCLK_P 18HDMIREFCLK_N 18
SDI_27MHz__REFCLK1 12
USB2_1V8 7,8,47,52,68
SDI_27MHz__REFCLK 12
IO_1V81V8_PLL
IO_3V3
IO_2V5
USB2_1V8USB2_1V8USB2_1V8
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
32 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
32 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
32 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R280 DNI
R2740
C2940.1uF
R279 1.00K
C3130.1uF
C2930.1uF
R287 22.0
C3010.1uF
PLL
U25
Si52112VSS25
DIFF1 6
DIFF2 8
DIFF2 9XIN/CLKIN3XOUT2VDD1
VSS4
DIFF1 7VDD210
C1616 0.1uF
U26
Si5338A-CUSTOM
CLKIN_P1CLKIN_N2CLKIN3
I2C_LSB4FDBK_P5FDBK_N6
VDD1 7VDD2 24
VDDO3 11VDDO2 15VDDO1 16VDDO0 20
INTR 8
CLK3B 9CLK3A 10SCL12
CLK2B 13CLK2A 14
CLK1B 17CLK1A 18
SDA19
CLK0B 21CLK0A 22
RSVD_GND 23EPAD 25
R278 DNI C2990.1uF
C3000.1uF
C298 DNI
R286 10K
Y325.00MHz
13
24
R2760
U29
50MHz
VCC 4
GND2 OUT 3EN1
Y225.00MHz
13
24
C2880.1uF
R2770
C2892.2uF
C2960.1uF
R2750
L12
742792780
C1617 0.1uF
C3122.2uF
C2950.1uF
C290 DNI
C297 DNI
C291 DNI
L11
742792780C2920.1uF
C3020.1uF
CLKIN_50
CLK_DIFF1_NCLK_DIFF1_P
CLK_DIFF2_NCLK_DIFF2_P
![Page 33: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/33.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
FPGA Memomory Reference clock
125MHz
LVDS
133.33MHz133.33MHz
I2C Address = b'1110011'
133.33MHz133.33MHz
27MHz
IO_1V8 12,21,22,25,29,30,32,34,36,39,40,43,63,64,65,66,68
REFCLK_SMA_P 18REFCLK_SMA_N 18
CLOCK_I2C_SCL32,38CLOCK_I2C_SDA32,38
CLK_EMI_1P 28CLK_EMI_1N 28CLK_EMI_P 25CLK_EMI_N 25
IO_1V8
IO_1V8
Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
33 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
33 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
33 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C3400.1uF
C342 DNI
U31
Si5338B-CUSTOM
CLKIN_P1CLKIN_N2CLKIN3
I2C_LSB4FDBK_P5FDBK_N6
VDD1 7VDD2 24
VDDO3 11VDDO2 15VDDO1 16VDDO0 20
INTR 8
CLK3B 9CLK3A 10SCL12
CLK2B 13CLK2A 14
CLK1B 17CLK1A 18
SDA19
CLK0B 21CLK0A 22
RSVD_GND 23EPAD 25
C343 DNI
J201
2 3 4 5
C3360.1uF
C3380.1uF
C333 0.1uF
L17
BLM15AG221SN1
C332 0.1uF
R292 4.7K
C335 DNI
C3410.1uF
C3370.1uF
C334 DNI
J191
2 3 4 5
Y725.00MHz
13
24 C3390.1uF
1.8V_PLLB
EXTSMACLKN
EXTSMACLKP
REFCLK_SMA_CPREFCLK_SMA_CN
![Page 34: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/34.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FPGA Transceiver reference Clocks
155.52MHz (LVDS)
644.53125M (LVDS)
TBD
156.25MHz (LVDS)
625MHz (LVDS)
125MHz (LVCMOS)
125MHz (LVCMOS)
I2C Address = 74h
LVDS125MHz
REFCLK_SFPA_P 18REFCLK_SFPA_N 18
REFCLK_QSFP1_P 18REFCLK_QSFP1_N 18
IO_1V8 12,21,22,25,29,30,32,33,36,39,40,43,63,64,65,66,68IO_3V3 14,15,16,17,22,25,26,29,30,31,32,35,36,37,38,43,57,69,70
CLK_CONFIG 42
FPGA_OSC_CLK1 29MAX10_OSC_CLK1 42
CLK_ENET_FPGA_P 13CLK_ENET_FPGA_N 13
REFCLK1_FMC_P 24REFCLK1_FMC_N 24
REFCLK0_FMC_P 20REFCLK0_FMC_N 20
REFCLK0_P 13REFCLK0_N 13
LTSDA38,46 LTSCL38,46
CLK0_OEn42
CLK0_RSTn42
CLK0_FINC42
CLK0_FDEC42
IO_1V8
IO_3V3
IO_1V8IO_3V3IO_1V8
IO_1V8
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
34 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
34 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
34 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C327 0.1uF
C3490.1uF
C3470.1uF
C362 0.1uF
R30410.0K
U33
Si5341A
IN11IN12
IN214IN215
IN064 IN063
XA8XB9
X17X210
FB_IN61FB_IN62
OUT0 24OUT0 23
OUT1 28OUT1 27
OUT2 31OUT2 30
OUT3 35OUT3 34
OUT4 38OUT4 37
OUT5 42OUT5 41
OUT6 45OUT6 44
OUT7 51OUT7 50
OUT8 54OUT8 53
OUT9 59OUT9 58
I2C_SEL39
SDA18
A117
SCL16
A019
INTR 12
RST6OE11
LOL 47
SYNC5
FDEC25FINC48
IN_SEL03IN_SEL14
RSVD221 RSVD120
RSVD355RSVD456
VDD1
32VD
D246
VDD3
60
VDDA
13
VDDO
022
VDDO
126
VDDO
229
VDDO
333
VDDO
436
VDDO
540
VDDO
643
VDDO
749
VDDO
852
VDDO
957
GNDP
AD65
R303 20
C326 0.1uFR296 DNI
L19BLM15AG221SN1
C329 0.1uF
C363 0.1uF
C331 0.1uF
C3480.1uF
Y948MHz
13
24
C328 0.1uF
C330 0.1uF
C366 0.1uF
TP128
C360 0.1uF
R301 20
C3461uF
C3510.1uF
L18BLM15AG221SN1
R300 20
C361 0.1uF
C367 0.1uF
L20BLM15AG221SN1 C352
1uFC3500.1uFC345
1uF
ENET_REFCLK_CPENET_REFCLK_CN
REFCLK1_FMCB_CPREFCLK1_FMCB_CN
REFCLK0_FMCB_CPREFCLK0_FMCB_CN
![Page 35: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/35.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
1.2V
SDI Video Reference clock
I2C address "1100101"
IO_3V3 14,15,16,17,22,25,26,29,30,31,32,34,36,37,38,43,57,69,70
SDI_27MHz_REF_P 36SDI_27MHz_REF_N 36SDI_148.5MHz_REF_P 25SDI_148.5MHz_REF_N 25
SDI_SDA38 SDI_SCL38
FIN_3V341 VIN_3V341 HIN_3V341 INIT_3V341
NO_REF_3V3 41NO_ALIGN_3V3 41NO_LOCK_3V3 41
IO_3V3video_3v3
video_3v3
video_3v3
video_3v3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
35 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
35 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
35 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R85117.4K
C1577 0.1uF
TP124
C16100.1uF
U104
LMP7711MK
1output3 IN+4 IN-5 EN
2V-
6V+
C16050.1uF
TP126
R8483.09K
C15751uF
C16061uF
C15730.1uF
C15710.1uF
C157622uF
C16081uF
L50BLM15AG221SN1
C16041uF
C161547uF
C16110.1uF
R9144.70K, 1%
C1578 0.1uF
C161222uF
C16070.1uF
C16141uF
R8491.78K
U103
357LB3C027M000
VC1 Outout 4
VCC 6
GND 3
NC1_EN2
NC2_EN5
TP125
C15740.1uF
C16130.1uF
C15720.1uF
C15700.1uF
R85010KC1609
0.1uF
LMH1983
U102
NO_LOCK 11NO_ALIGN 12NO_REF 13
CLKOUT4N 14CLKOUT4P 15
FOUT417
FOUT3 22
CLKOUT3P 23CLKOUT3N 24CLKOUT2P 28CLKOUT2N 29CLKOUT1N 35CLKOUT1P 36
FOUT1 37VC_LPF 40
HIN3 VIN4 FIN5
INIT6
ADDR7 SDA8 SCL9
FOUT2 30
XOINN33 XOINP34
VDD1
1VD
D22
VDD3
10VD
D416
GND1
18VD
D919
VDD5
20
GND2
21
VDD6
31VD
D732
VDD8
38
GND3
39
CBYP
325
CBYP
426
CBYP
227
DAP
41
Video_3V3
![Page 36: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/36.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
lmk05028 CLOCK CLEANER
Z0=100ohm
Z0=100ohm
Z0=50ohm
Z0=50ohm
ledled
To Green LED
Open drain, FPGA input
Singal end clock output
I2C address "1011000"
IO_3V314,15,16,17,22,25,26,29,30,31,32,34,35,37,38,43,57,69,70
IO_1V8 12,21,22,25,29,30,32,33,34,39,40,43,63,64,65,66,68
FPGA_156.25MHZ_REF_P21FPGA_156.25MHZ_REF_N21
FPGA_122.88MHZ_REF_P21FPGA_122.88MHZ_REF_N21
SDI_27MHz_REF_N35
CLKcleaner_status0 31,41
Cleaner_SDA22,38Cleaner_SCL22,38
Cleaner_PDn41
CLKcleaner_status1 31,41
Clearner_XVRL_122.88MHZ_P 24Clearner_XVRL_122.88MHZ_N 24
Clearner_XVRR_122.88MHZ_P 20Clearner_XVRR_122.88MHZ_N 20
Clearner_FMC0_122.88MHZ_P 19Clearner_FMC0_122.88MHZ_N 19Clearner_FMC1_122.88MHZ_P 23Clearner_FMC1_122.88MHZ_N 23
Clearner_XVR_644.53125MHZ_P 13Clearner_XVR_644.53125MHZ_N 13
CLKcleaner_GPIO541 CLKcleaner_GPIO641
SDI_27MHz_REF_P35
referenceclk_2 21
referenceclk_1 21
Clearner_SDI_245MHZ_P 18Clearner_SDI_245MHZ_N 18
Clearner_SDI_297MHZ_P 18Clearner_SDI_297MHZ_N 18
Clearner_FPGA_122.88MHZ_P 21Clearner_FPGA_122.88MHZ_N 21
IO_3V3
IO_3V3
IO_3V3
IO_1V8
IO_1V8
CLEANER_VDDXO
CLEANER_VDDXO
Cleaner_GND_SIGNAL1
Cleaner_GND_SIGNAL1
IO_3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
36 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
36 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
36 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C4300.1uF
C1599 0.1uF
C4000.1uF
C44410uF
C1600 0.1uF
C1595 0.1uF
C1601 0.1uF
R917DNI
C4510.1uF
C1596 0.1uF
L352.5A, 220 Ohm FB
C1597 0.1uF
R919DNI
C1598 0.1uF
J52 1
2345
C4400.1uF
R824
4.7K
C426
0.1uF
L272.5A, 220 Ohm FB
C43510uF
C3810.1uF
L302.5A, 220 Ohm FB
C4190.1uF
C1582 0.1uF
L382.5A, 220 Ohm FB
C1618 DNI
C44110uF
L332.5A, 220 Ohm FB
C1579 0.1uF
C37910uF
C4310.1uF
C4050.1uF
R32949.9
R326
49.9C3970.1uF
R32849.9
C4220.1uF
R9180
C4430.1uF
C37810uF
U35
48MHz
VCC 4
GND2 OUT 3EN1
R823
4.7K
C4340.1uF
C4460.1uF
C41510uF
C4250.1uF C409
10uF
C402
0.1uF
R3241.00K
C4360.1uF
C1586 0.1uF
L252.5A, 220 Ohm FBC410
0.1uF
C1584 0.1uF
L312.5A, 220 Ohm FB
C4230.1uF
C1583 0.1uF
C4030.1uF
R325 22.0
L342.5A, 220 Ohm FB
C42410uF
L232.5A, 220 Ohm FB
R8560
C38010uF
C3820.1uF
L242.5A, 220 Ohm FB
C4490.1uF
C41210uF
LMK05028
U34
IN0_P1IN0_N2
IN3_P5IN3_N6
IN2_P10IN2_N11
GPIO512GPIO613
IN1_P14IN1_N15
INSEL0_117
GPIO124
INSEL1_028
OUT3_P 34
GPIO340GPIO441
XO_P43XO_N44
GPIO045
GPIO260
OUT0_P 22OUT0_N 23
OUT1_N 26OUT1_P 27
OUT2_P 31OUT2_N 32
OUT3_N 33
OUT4_P 51OUT4_N 52
OUT5_N 53OUT5_P 54
OUT6_P 57OUT6_N 58
OUT7_N 61OUT7_P 62
CAP_
DIG7
TCX0_IN18
VDD_
TCXO
19
INSEL0_020
SDA
35SC
L36
CAP_
APLL1
38LF
139
PDN
46
LF2
47CA
P_AP
LL248
STAT
US0
55ST
ATUS
156
HW_S
W_CT
RL64
VDD_
IN03
VDD_
IN34
VDD_
DIG8
VDD_
IN29
VDD_
IN116
VDDO
_021
VDDO
_125
INSEL1_129
VDDO
_2330
VDD_
APLL1
37
VDD_
XO42
VDD_
APLL2
49
VDDO
_4550
VDDO
_659
VDDO
_763
DAP_
GND
65
C39910uF
C4140.1uF
L292.5A, 220 Ohm FB
C1588 0.1uF
C1589 0.1uF
C1590 0.1uF
C42110uF
C1591 0.1uF
R826
4.7K
C1592 0.1uF
C44710uF
C1587 0.1uFR830
100
L372.5A, 220 Ohm FB
C1580 0.1uF
R8224.7K
C43810uF
C4130.1uF
C4170.1uF
C4420.1uF
C40410uF
C39810uF
C4280.1uF
L322.5A, 220 Ohm FB
C4370.1uF
J51 1
2345
R3270
C1593 0.1uF
C1594 0.1uF
C4200.1uF
L362.5A, 220 Ohm FB
C42910uF
J21
2X5_100mil
1 13 35 57 7
22446688
9 91010
C4330.1uF
C45010uF
C4480.1uF
R323
49.9
C1581 0.1uF
C4080.1uF
R825
4.7K
C4110.1uF
R829
100
L262.5A, 220 Ohm FB
C43210uF
R8184.7K
C4450.1uF
C41810uF
R828
49.9
L282.5A, 220 Ohm FB
R8194.7K
C4390.1uF
C1585 0.1uF
C1640
DNI
C401
0.1uF
C4160.1uF
R839
100
CLEANER_VDDX0CLEANER_VDDTCXOCLEANER_VDDAPLL2CLEANER_VDDAPLL1CLEANER_VDDDIGCLEANER_VDDIN3CLEANER_VDDIN2CLEANER_VDDIN1CLEANER_VDDIN0 CLEANER_VDDO7CLEANER_VDDO6CLEANER_VDDO45CLEANER_VDDO23CLEANER_VDDO1CLEANER_VDDO0
CLEA
NER_
XO_N
CLEA
NER_
OSC_
EN
Cleaner_IN0_PCleaner_IN0_N
Cleaner_IN1_PCleaner_IN1_N
Cleaner_IN2N
Cleaner_IN3
cleaner_hw_cntrl
cleaner_IN2P
![Page 37: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/37.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
UART Port B
IO_3V314,15,16,17,22,25,26,29,30,31,32,34,35,36,38,43,57,69,70
UART1_TX41
UART1_RX41
IO_3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
37 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
37 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
37 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C4550.1uF
C4520.1uF
C4530.1uF
C4540.1uF
C4560.1uF
U36
MAX3221
EN_n1
FORCEOFF_N16C1+ 2
C1- 4
C2+ 5
C2- 6
V+ 3
V- 7
RIN 8ROUT9
DIN11 DOUT 13
INVALID10FORCEON12
GND14VCC15
J22
61800925023
594837261
10 11
DB9_TXDB9_RX
![Page 38: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/38.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
I2C ADDRESS:b'1101000'
I2C ADDRESS:b'1010001'
I2C ADDRESS:b'1001100' I2C MUX
PMBus
S10_PMBUSDIS_N41
LTSDA 34,46LTSCL 34,46
IO_3V3 14,15,16,17,22,25,26,29,30,31,32,34,35,36,37,43,57,69,70
EXTB_SCL 9,19,23EXTB_SDA 9,19,23
OVERTEMPn 46TSENSE_ALERTn 46
PMbus_SDA_3V3 29,50,54,58,59,62PMbus_SCL_3V3 29,50,54,58,59,62
S10_2L_SDA25,30,41 S10_2L_SCL25,30,41 CLOCK_I2C_SCL 32,33CLOCK_I2C_SDA 32,33
PMbus_ALERTn46,50,54,58,59,62
IO_2V5 10,11,12,22,26,27,32,43,68
IO_5V 10,11,15,46,49
HDMI_LINE_SDA 15HDMI_LINE_SCL 15
HDMI_TX_SDA15 HDMI_TX_SCL15
SODIMM_I2C_SDA 27SODIMM_I2C_SCL 27
Cleaner_SCL22,36 Cleaner_SDA22,36
SDI_SDA35 SDI_SCL35
TEMPDIODE_P30
TEMPDIODE_N30
VIDEO_I2C_B_SDA25VIDEO_I2C_B_SCL25
IO_5V
IO_3V3
IO_3V3
IO_3V3IO_3V3
IO_3V3
IO_3V3
IO_3V3
IO_3V3
IO_3V3IO_3V3
IO_3V3
IO_2V5IO_2V5
IO_2V5
IO_3V3
IO_5V
IO_5V
IO_5V IO_3V3 IO_2V5
IO_3V3
IO_3V3
IO_3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
38 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
38 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
38 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R357
4.7K
C4670.1uF
U38
FXMA2102UMX
A02A13 B0 7
B1 6
VCCA1GND4OE5
VCCB 8
R352 0
R333 0
R339
4.7K
C4600.1uF
C4610.1uF
BT1
12
C4590.1uF
R3404.7K
C468 0.1uFR359 4.7K
U37
MAX1619
ADD16ADD010
SMBCLK 14SMBDATA 12DXP3
DXN4
VCC1
OVERTn 9ALERTn 11
STBYn15 GND1 2GND2 7GND3 8
NC15NC213NC316
R817 DNI
U41
24LC32A
A01A12A23GND4
VCC 8WP 7
SCL 6SDA 5
C4572200pf
R337
DNI
U39
FXMA2102UMX
A02A13 B0 7
B1 6
VCCA1GND4OE5
VCCB 8
R360 0
R350 0
R334 200
C4660.1uF
R3424.7K
U40
FXMA2102UMX
A02A13 B0 7
B1 6
VCCA1GND4OE5
VCCB 8
R335 0R847 0
R816 DNI
C4640.1uF
R332 0
R3414.7K
C4630.1uF
R344 0
R349 0
R351 0
R355DNI
R345 0
C4620.1uF
U42
DS1339C
SDA16SCL1
GND15
VCC3 VBACKUP 14
SQW/INT 2
NC5 4NC6 5NC7 6NC8 7NC9 8
NC10 9NC410 NC311 NC212 NC113
R343 0
R353DNI
R356DNI
R354DNI
R358 0
C4580.1uF
R330
4.7K
R336 0
R846 0
J23
2X6
11 2 233 4 455 6 677 8 899 10 10
12 121111
R331
4.7K
C14890.1uF
R338
DNI
R346 0
C4650.1uF
VBAT
Bus1_SDABus1_SCL
![Page 39: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/39.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
System MAX10 Controller (NO ADC Support) (VCCIO = 1.8V) (VCCIO = 1.8V)
(VCCIO = 1.8V)
1V8_IO_MUX029 1V8_IO_MUX129 1V8_IO_MUX229 1V8_IO_MUX329 1V8_IO_MUX4291V8_IO_MUX529 1V8_IO_MUX629 1V8_IO_MUX729 1V8_IO_MUX829 1V8_IO_MUX929
1V8_IO_MUX1029 1V8_IO_MUX1129 1V8_IO_MUX1229 1V8_IO_MUX1329 1V8_IO_MUX23291V8_IO_MUX2429
1V8_IO_MUX2529
1V8_IO_MUX26 29
1V8_IO_MUX2729 IO_1V8 12,21,22,25,29,30,32,33,34,36,40,43,63,64,65,66,68
M10B_JTAG_TDO8
M10B_JTAG_TCK8 M10B_JTAG_TMS8M10B_JTAG_TDI8
FLASH_ADDR13 40
FLASH_ADDR6 40
FLASH_ADDR9 40
FLASH_ADDR12 40
FLASH_ADDR15 40
FLASH_ADDR18 40FLASH_ADDR19 40FLASH_ADDR21 40FLASH_ADDR23 40FLASH_ADDR25 40
FLASH_ADDR1 40FLASH_ADDR3 40FLASH_ADDR5 40
FLASH_ADDR8 40
FLASH_ADDR11 40
FLASH_ADDR16 40
FLASH_ADDR2 40FLASH_ADDR4 40
FLASH_ADDR7 40
FLASH_ADDR10 40
FLASH_ADDR14 40
FLASH_ADDR17 40
FLASH_ADDR20 40FLASH_ADDR22 40FLASH_ADDR24 40FLASH_ADDR26 40
FLASH_DATA040FLASH_DATA140 FLASH_DATA240 FLASH_DATA340 FLASH_DATA440 FLASH_DATA540FLASH_DATA640 FLASH_DATA740 FLASH_DATA840 FLASH_DATA940 FLASH_DATA1040
FLASH_DATA1140 FLASH_DATA1240 FLASH_DATA1340 FLASH_DATA1440 FLASH_DATA1540
SECURITY_MODE 31
FACTORY_LOAD31IO_1V8
IO_1V8
IO_1V8
IO_1V8
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
39 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
39 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
39 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R368 10.0K
MAX 10 LEFT BANKSBANK-2BANK-1A
BANK-1B
10M50DAF484
U43A
DIFFIO_RX_L1N/ADC1IN1F5DIFFIO_RX_L1P/ADC1IN2F4DIFFIO_RX_L2N/ADC2IN1E4DIFFIO_RX_L2P/ADC2IN8E3DIFFIO_RX_L3N/ADC1IN3J8DIFFIO_RX_L3P/ADC1IN4J9DIFFIO_RX_L4N/ADC2IN3G4DIFFIO_RX_L4P/ADC2IN4F3DIFFIO_RX_L5P/ADC1IN6H3DIFFIO_RX_L5N/ADC1IN5J4DIFFIO_RX_L6N/ADC2IN5H4DIFFIO_RX_L6P/ADC2IN6G3DIFFIO_RX_L7N/ADC1IN7K5DIFFIO_RX_L7P/ADC1IN8K6DIFFIO_RX_L8P/ADC2IN2J3DIFFIO_RX_L8N/ADC2IN7K4
DIFFIO_RX_L15NK8
VREFB1N0C1
DIFFIO_RX_L19NK2DIFFIO_RX_L19PL2
DIFFIO_RX_L23NG1DIFFIO_RX_L21PF2
DIFFIO_RX_L23PF1
DIFFIO_RX_L21NE1
DIFFIO_RX_L24NM4DIFFIO_RX_L24PM3DIFFIO_RX_L25NK1DIFFIO_RX_L25PL1
DIFFIO_RX_L16PD2
IO_BANK1D1
DIFFIO_RX_L29N P4DIFFIO_RX_L29P P5DIFFIO_RX_L37N N3DIFFIO_RX_L37P N2DIFFIO_RX_L39N R4DIFFIO_RX_L39P R5DIFFIO_RX_L40N T1DIFFIO_RX_L40P T2DIFFIO_RX_L41N N8DIFFIO_RX_L41P N9DIFFIO_RX_L42N P1DIFFIO_RX_L42P N1DIFFIO_RX_L43N T3DIFFIO_RX_L43P U2DIFFIO_RX_L44N U1DIFFIO_RX_L44P V1DIFFIO_RX_L45N U4DIFFIO_RX_L45P U5DIFFIO_RX_L46N U3DIFFIO_RX_L46P V3DIFFIO_RX_L47N P8DIFFIO_RX_L47P R7DIFFIO_RX_L48N W1DIFFIO_RX_L48P W2DIFFIO_RX_L60N R1DIFFIO_RX_L60P R2
VREFB2N0 M2IO_BANK2 M1
DIFFIO_RX_L16ND3
DIFFIO_RX_L20NL8DIFFIO_RX_L20PL9
DIFFIO_RX_L22NH1DIFFIO_RX_L22PJ1
R370 10.0K
R366 1KR9650R9630
R361 DNI
R364 DNIR367 10.0K
R363 10.0KR362 10.0K
R9660R369 10.0K
R9640
MAX 10 ConfigurationBANK-1B BANK-8
10M50DAF484
U43F
DIFFIO_RX_L15P/JTAGENK9DIFFIO_RX_L17P/TCKG2DIFFIO_RX_L17N/TMSH2DIFFIO_RX_L18N/TDIL4DIFFIO_RX_L18P/TDOM5
DIFFIO_RX_T42N/DEV_CLRN D9DIFFIO_RX_T44P/DEV_OE D10
NCONFIG H9CONFIG_SEL H10
DIFFIO_RX_T48N/CRC_ERROR F7DIFFIO_RX_T50P/NSTATUS G9
DIFFIO_RX_T50N/CONF_DONE F8
R365 10.0KMAX10_CONFIG_SEL
![Page 40: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/40.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Flash Memory
- When using a single x16 flash device a word consists of 16 data bits so addressing starts with FM_A1 mapped to address bit 1 in software.
FLASH 1-Gbit
For Avalon Stream x16 Configuration
H = 1.20mmPlace on Bottom side
FLASH_CLK41FLASH_RESETn41 FLASH_CEn041 FLASH_CEn141FLASH_OEn41 FLASH_WEn41 FLASH_ADVn41
FLASH_RDYBSYn0 41 FLASH_RDYBSYn1 41FLASH_ADDR2639,40
FLASH_ADDR1039,40FLASH_ADDR839,40
FLASH_ADDR1139,40
FLASH_ADDR439,40FLASH_ADDR639,40
FLASH_ADDR2539,40
FLASH_ADDR239,40
FLASH_ADDR2039,40
FLASH_ADDR2339,40
FLASH_ADDR539,40
FLASH_ADDR939,40
FLASH_ADDR1239,40FLASH_ADDR1439,40FLASH_ADDR1639,40FLASH_ADDR1839,40
FLASH_ADDR2139,40
FLASH_ADDR2439,40
FLASH_ADDR139,40FLASH_ADDR339,40
FLASH_ADDR1339,40FLASH_ADDR1539,40FLASH_ADDR1739,40FLASH_ADDR1939,40
FLASH_ADDR2239,40
FLASH_ADDR739,40
FLASH_ADDR139,40 FLASH_ADDR239,40 FLASH_ADDR339,40 FLASH_ADDR439,40 FLASH_ADDR539,40 FLASH_ADDR639,40 FLASH_ADDR739,40 FLASH_ADDR839,40 FLASH_ADDR939,40 FLASH_ADDR1039,40 FLASH_ADDR1139,40 FLASH_ADDR1239,40 FLASH_ADDR1339,40 FLASH_ADDR1439,40 FLASH_ADDR1539,40 FLASH_ADDR1639,40 FLASH_ADDR1739,40 FLASH_ADDR1839,40 FLASH_ADDR1939,40 FLASH_ADDR2039,40 FLASH_ADDR2139,40 FLASH_ADDR2239,40 FLASH_ADDR2339,40 FLASH_ADDR2439,40 FLASH_ADDR2539,40 FLASH_ADDR2639,40FLASH_DATA14 39,40
FLASH_DATA3 39,40FLASH_DATA5 39,40FLASH_DATA7 39,40
FLASH_DATA1 39,40
FLASH_DATA4 39,40FLASH_DATA6 39,40
FLASH_DATA8 39,40FLASH_DATA9 39,40FLASH_DATA10 39,40FLASH_DATA11 39,40FLASH_DATA12 39,40FLASH_DATA13 39,40FLASH_DATA15 39,40
FLASH_DATA0 39,40FLASH_DATA2 39,40
FLASH_DATA0 39,40FLASH_DATA1 39,40FLASH_DATA2 39,40FLASH_DATA3 39,40FLASH_DATA4 39,40FLASH_DATA5 39,40FLASH_DATA6 39,40FLASH_DATA7 39,40FLASH_DATA8 39,40FLASH_DATA9 39,40FLASH_DATA10 39,40FLASH_DATA11 39,40FLASH_DATA12 39,40FLASH_DATA13 39,40FLASH_DATA14 39,40FLASH_DATA15 39,40
IO_1V8 12,21,22,25,29,30,32,33,34,36,39,43,63,64,65,66,68IO_1V8
IO_1V8
IO_1V8
IO_1V8
IO_1V8
IO_1V8 IO_1V8 IO_1V8 IO_1V8 IO_1V8
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
40 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
40 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardC
40 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C4700.1uF
C4800.1uF
C4710.1uFR375 10.0K
C4790.1uF
C4690.1uF
C4750.1uFR374 10.0K C478
0.1uF
R372 10.0K C4760.1uF
C4770.1uF
R371 10.0K
PC28FxxxP30B85FLASHU45
PC28F00AG18
A1A1A2B1A3C1A4D1A5D2A6A2A7C2A8A3A9B3A10C3A11D3A12C4A13A5A14B5A15C5A16D7A17D8A18A7A19B7A20C7A21C8A22A8NC(64M)/A23G1
CE#B4OE#F8WE#G8
WP#C6
VCC A6
RESET#D4
VCC H3
D0 F2D1 E2D2 G3D3 E4D4 E5D5 G5D6 G6D7 H7
D8 E1D9 E3
D10 F3D11 F4D12 F5D13 H5D14 G7D15 E7
WAIT F7
GND B2
GND H4GND H2CLKE6
ADV#F6
NC/A26(1G)B8
RFU3 E8RFU2 F1RFU1 G2RFU0 H1
NC(64M,128M)/A24H8NC/A25(512M)B6
VPP A4
VCCQ D6VCCQ D5
VCCQ G4
GND H6
C4730.1uF
R376 10.0K
PC28FxxxP30B85FLASHU44
PC28F00AG18
A1A1A2B1A3C1A4D1A5D2A6A2A7C2A8A3A9B3A10C3A11D3A12C4A13A5A14B5A15C5A16D7A17D8A18A7A19B7A20C7A21C8A22A8NC(64M)/A23G1
CE#B4OE#F8WE#G8
WP#C6
VCC A6
RESET#D4
VCC H3
D0 F2D1 E2D2 G3D3 E4D4 E5D5 G5D6 G6D7 H7
D8 E1D9 E3
D10 F3D11 F4D12 F5D13 H5D14 G7D15 E7
WAIT F7
GND B2
GND H4GND H2CLKE6
ADV#F6
NC/A26(1G)B8
RFU3 E8RFU2 F1RFU1 G2RFU0 H1
NC(64M,128M)/A24H8NC/A25(512M)B6
VPP A4
VCCQ D6VCCQ D5
VCCQ G4
GND H6
C4740.1uF
C4720.1uF
R373 10.0K
FLASH_RESETn
FLASH_OEn
FLASH_WPn FLASH_WPn
FLASH_CLKFLASH_RESETnFLASH_OEnFLASH_WEnFLASH_ADVn
FLASH_WEnFLASH_WPnFLASH_RDYBSYn0FLASH_RDYBSYn1
![Page 41: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/41.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
System MAX10 Controller 2
(VCCIO = 1.8V) (VCCIO = 1..8V) (VCCIO = 1.8V) (VCCIO = 3.3V)
SFPA_MOD0_PRSNTn 14
AVST_D022 AVST_D122AVST_D222 AVST_D322 AVST_D422 AVST_D522 AVST_D622AVST_D722 AVST_D822 AVST_D922 AVST_D1022 AVST_D1122AVST_D1222 AVST_D1322 AVST_D1422 AVST_D1522 AVST_VALID22AVST_CLK22
FLASH_CLK40FLASH_RESETn40 FLASH_CEn040 FLASH_OEn40 FLASH_WEn40 FLASH_ADVn40FLASH_CEn140
FLASH_RDYBSYn140 FLASH_RDYBSYn040
FBHBP7 23FBHBN7 23
FBHBP9 23FBHBN9 23
FBHBP10 23FBHBN10 23
FBHBP11 23FBHBN11 23FBHBP12 23FBHBN12 23FBHBP13 23FBHBN13 23
FBHBP14 23FBHBN14 23
FBHBP15 23FBHBN15 23
FBHBP16 23FBHBN16 23
NPERSTL029NPERSTR029 NPERSTL229 NPERSTR229
1V8_IO_MUX1829 1V8_IO_MUX1929 1V8_IO_MUX2029
1V8_IO_MUX2129
1V8_IO_MUX2229
1V8_IO_MUX14 29
1V8_IO_MUX15 29
1V8_IO_MUX16 29
1V8_IO_MUX17 29
SD_TX_GPIO112 SD_TX_GPIO212 SD_TX_GPIO312SDI_TX_MOSI12 SDI_TX_SCLK12 SDI_TX_CS12 SDI_TX_MISO12 SD_RX_GPIO012
SD_RX_GPIO212 SD_RX_GPIO312 SDI_RX_MOSI12 SDI_RX_SCLK12 SDI_RX_CS12SDI_RX_MISO12
MAX_LOAD31MAX_CONF_DONE31
FPGA_PR_REQUEST22 FPGA_PR_DONE22SD_TX_GPIO012
FPGA_PR_ERROR22
PGM_SEL 31
FPGA_nSTATUS29 FPGA_nCONFIG29 CONF_DONE29
Cleaner_PDn 36UART1_RX 37UART1_TX 37ZQSFP1_ModprsL 17ZQSFP1_ResetL 17ZQSFP1_LPmode 17ZQSFP1_intL 17ZQSFP1_ModselL 17
SFPA_LOS 14SFPA_TXFAULT 14SFPA_TXDISABLE 14SFPA_RATESEL0 14SFPA_RATESEL1 14
HDMI_HPDn 15
DVI_TX_IN_CECn 15
HDMI_VFlagn 15
DVI_TX_CEC_OUT_N 15
HDMI_POWER_ON 15
ZQSFP0_ModprsL 16ZQSFP0_ResetL 16ZQSFP0_LPmode 16ZQSFP0_intL 16ZQSFP0_ModselL 16
PCIE_WAKE_N 9PCIE_PERSTn 9PCIE_PRSNT2n 8,9,46
CLKcleaner_GPIO5 36CLKcleaner_GPIO6 36
FIN_3V3 35VIN_3V3 35HIN_3V3 35INIT_3V3 35NO_REF_3V3 35NO_ALIGN_3V3 35NO_LOCK_3V3 35
FBCLK2M2CP23FBCLK2M2CN23
FBCLK2BIDIRN23
FBCLK3BIDIRP23FBCLK3BIDIRN23
FBSYNM2CN23 FBSYNM2CP23
PCIEA_EP_PERSTn 19PCIEA_WAKEn 19
PCIEB_EP_PERSTn 23PCIEB_WAKEn 23
AVST_Ready29
S10I2CEN_FPGA 25S10I2CEN_HPS 30
S10PMBUSEN 29S10_PMBUSDIS_N 38S10_2L_SDA 25,30,38S10_2L_SCL 25,30,38
FPGA_MAX10_IO022 FPGA_MAX10_IO122 FPGA_MAX10_IO222 FPGA_MAX10_IO322FPGA_MAX10_IO522 FPGA_MAX10_IO622 FPGA_MAX10_IO722 FPGA_MAX10_IO822 FPGA_MAX10_IO922FPGA_MAX10_IO1022 FPGA_MAX10_IO1122 FPGA_MAX10_IO1222 FPGA_MAX10_IO1322 FPGA_MAX10_IO1422
ClK_50M_FPGA22
Global_resetn22
MAX10B_RESETn47
FBCLK2BIDIRP23
FACLK2M2CN19 FACLK2M2CP19
CLKcleaner_status0 31,36CLKcleaner_status1 31,36
SDM_MAXB_IO029Logic_RESETn31 I2C_flag31
FBHAN123 FBHAP123
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
41 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
41 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
41 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
BANK-7 BANK-8MAX 10 TOP BANKS
10M50DAF484
U43D
DIFFIO_RX_T10NA17DIFFIO_RX_T10PA18DIFFIO_RX_T15NC15DIFFIO_RX_T15PC16DIFFIO_RX_T16NA16DIFFIO_RX_T16PB16DIFFIO_RX_T17NJ13DIFFIO_RX_T17PH14DIFFIO_RX_T18NC13DIFFIO_RX_T18PC14DIFFIO_RX_T19NB14DIFFIO_RX_T19PA14DIFFIO_RX_T1NE15DIFFIO_RX_T1PE16DIFFIO_RX_T20NE13DIFFIO_RX_T20PD14DIFFIO_RX_T21PE12DIFFIO_RX_T21ND13DIFFIO_RX_T22NJ12DIFFIO_RX_T22PH13DIFFIO_RX_T23NA12DIFFIO_RX_T23PA13DIFFIO_RX_T24ND12DIFFIO_RX_T24PC12DIFFIO_RX_T25NA10DIFFIO_RX_T25PA11DIFFIO_RX_T26NC10DIFFIO_RX_T26PC11DIFFIO_RX_T27NB11DIFFIO_RX_T27PB12DIFFIO_RX_T28NJ11DIFFIO_RX_T28PH12DIFFIO_RX_T31NB8DIFFIO_RX_T31PA9DIFFIO_RX_T2NC17DIFFIO_RX_T2PD17DIFFIO_RX_T30NC9DIFFIO_RX_T30PB10DIFFIO_RX_T29PA7DIFFIO_RX_T29NA8DIFFIO_RX_T5NF15DIFFIO_RX_T5PF16DIFFIO_RX_T6NB19DIFFIO_RX_T6PC19DIFFIO_RX_T7NB17DIFFIO_RX_T7PC18DIFFIO_RX_T8NA19DIFFIO_RX_T8PA20DIFFIO_RX_T9NE14DIFFIO_RX_T9PD15
IO_BANK7A15 VREFB7N0B15
DIFFIO_RX_T39N C7DIFFIO_RX_T39P C8DIFFIO_RX_T41N A6DIFFIO_RX_T41P B7DIFFIO_RX_T42P D8DIFFIO_RX_T43N A4DIFFIO_RX_T43P A5DIFFIO_RX_T44N E9DIFFIO_RX_T45P A2DIFFIO_RX_T45N A3DIFFIO_RX_T46P B3DIFFIO_RX_T46N B4
DIFFIO_RX_T49N D5DIFFIO_RX_T49P C5DIFFIO_RX_T51N B1DIFFIO_RX_T51P B2
DIFFIO_RX_T53P C3VREFB8N0 D7IO_BANK8 C6
DIFFIO_RX_T47P B5DIFFIO_RX_T47N C4DIFFIO_RX_T48P E8
DIFFIO_RX_T53N C2
BANK-5 BANK-6MAX 10 RIGHT BANKS
10M50DAF484
U43C
DIFFIO_RX_R19NU19DIFFIO_RX_R19PV18
DIFFIO_RX_R1N/RDNU17 DIFFIO_RX_R1P/RUPU18
DIFFIO_RX_R20NW22DIFFIO_RX_R20PY22DIFFIO_RX_R21NW20DIFFIO_RX_R21PW19DIFFIO_RX_R22NY21DIFFIO_RX_R22PY20DIFFIO_RX_R23NU20DIFFIO_RX_R23PV20DIFFIO_RX_R24NV22DIFFIO_RX_R24PV21DIFFIO_RX_R25N/DQ1RR14DIFFIO_RX_R25P/DQ1RR15DIFFIO_RX_R26NT22DIFFIO_RX_R26PT21DIFFIO_RX_R27N/DM1RT18DIFFIO_RX_R27P/DQ1RT19DIFFIO_RX_R28N/DQ1RR20DIFFIO_RX_R28P/DQ1RT20DIFFIO_RX_R29NU22DIFFIO_RX_R29PU21DIFFIO_RX_R2NAA22DIFFIO_RX_R2PAA21DIFFIO_RX_R30N/DQ1RP14DIFFIO_RX_R30P/DQ1RP15DIFFIO_RX_R31NN22DIFFIO_RX_R31PP21DIFFIO_RX_R32N/DQSN1RP18DIFFIO_RX_R32P/DQS1RR18DIFFIO_RX_R33N/DQ1RP20DIFFIO_RX_R33P/DQ1RP19DIFFIO_RX_R34NL22DIFFIO_RX_R34PM21DIFFIO_RX_R35NM22DIFFIO_RX_R35PN21
IO_BANK5R22 VREFB5N0P22
DIFFIO_RX_R39N H21DIFFIO_RX_R39P H22DIFFIO_RX_R41N J21DIFFIO_RX_R41P J22DIFFIO_RX_R42N G19DIFFIO_RX_R42P G20DIFFIO_RX_R43N F22DIFFIO_RX_R43P G22
DIFFIO_RX_R44N/DQ2R M14DIFFIO_RX_R44P/DQ2R M15
DIFFIO_RX_R45N E21DIFFIO_RX_R45P E22
DIFFIO_RX_R46N/DM2R N19DIFFIO_RX_R46P/DQ2R N18DIFFIO_RX_R47P/DQ2R M20DIFFIO_RX_R47N/DQ2R N20
DIFFIO_RX_R48N F20DIFFIO_RX_R48P F21
VREFB6N0 D21
DIFFIO_RX_R49P D22DIFFIO_RX_R51N/DQ2R L18DIFFIO_RX_R51P/DQ2R M18DIFFIO_RX_R52N/DQ2R L20DIFFIO_RX_R52P/DQ2R L19
DIFFIO_RX_R53N F18DIFFIO_RX_R53P E19DIFFIO_RX_R54N E20DIFFIO_RX_R54P F19
DIFFIO_RX_R55N/DQSN3R K15DIFFIO_RX_R55P/DQS3R K14
DIFFIO_RX_R56N D19DIFFIO_RX_R56P C20
DIFFIO_RX_R57N/DQ3R J18DIFFIO_RX_R57P/DQ3R K18DIFFIO_RX_R58N/DQ3R K20DIFFIO_RX_R58P/DQ3R K19
DIFFIO_RX_R59N E17DIFFIO_RX_R59P F17DIFFIO_RX_R60N B21DIFFIO_RX_R60P B22
DIFFIO_RX_R61N/DM3R J15DIFFIO_RX_R61P/DQ3R J14
DIFFIO_RX_R62N A21DIFFIO_RX_R62P B20
DIFFIO_RX_R63N/DQ3R H18DIFFIO_RX_R63P/DQ3R H19DIFFIO_RX_R64N/DQ3R H20DIFFIO_RX_R64P/DQ3R J20
DIFFIO_RX_R70N/CK#_6 E18DIFFIO_RX_R70P/CK_6 D18
DIFFIO_RX_R49N C22
IO_BANK6 C21
![Page 42: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/42.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
System MAX10 Controller 3
(VCCIO = 1.8V)
(VCCIO = 1.8V)
(VCCIO = 1.8V)
(VCCIO = 1.8V)
(VCCIO = 3.3V)
(VCCIO = 1.8V) (VCCIO = 1V8)
50MHz ClockMAX10B_CLK47
FBHAP1723 FBHAN1723
FBHAP223 FBHAN223
FBHAP323FBHAN323
FBHAP423 FBHAN423
FBHAP523 FBHAN523
FBHAP623 FBHAN623
FBHAP723 FBHAN723
FBHAP923FBHAN923
FBHAP1023 FBHAN1023
FBHAP1123 FBHAN1123
FBHAP1223 FBHAN1223
FBHAP1323 FBHAN1323
FBHAP1423FBHAN1423
FBHAP1523 FBHAN1523
FBHAP1623 FBHAN1623
FBHAP1823 FBHAN1823
FBHBP023 FBHBN023
FBHBP123FBHBN123
FBHBP223 FBHBN223
FBHBP323 FBHBN323
FBHBP423 FBHBN423
FBHBP523 FBHBN523
CLK_CONFIG34MAX10_OSC_CLK134
PGM_LED0 31
PGM_LED1 31PGM_LED2 31
FBCLKDIR23
FBSYNC2MP 23FBSYNC2MN 23
FBCLK0M2CP23 FBCLK0M2CN23
FBCLK1M2CP23FBCLK1M2CN23
FBCLKC2MP 23FBCLKC2MN 23
FACLKC2MP 19FACLKC2MN 19
FASYNC2MP 19FASYNC2MN 19
MAX10B_USB_CLK8
MSEL029MSEL129MSEL229
CLK0_RSTn 34CLK0_FINC 34CLK0_FDEC 34CLK0_OEn 34
PGM_CONFIG 31
FBHAP0 23FBHAN0 23FBHAN20 23FBHAP20 23FBHAN22 23FBHAP22 23FBHAN23 23FBHAP23 23FBHBP17 23FBHBN17 23
FBHBP18 23FBHBN18 23
FBHBP19 23FBHBN19 23
FBHBP20 23FBHBN20 23
FBHBP21 23FBHBN21 23
FBHBP6 23FBHBN6 23FBHAN8 23FBHAP8 23FBHAN19 23FBHAP19 23FBHAN21 23FBHAP21 23MATOMBIO4 47MATOMBIO5 47
MATOMBIO6 47MATOMBIO7 47
MATOMBIO0 47MATOMBIO1 47MATOMBIO2 47MATOMBIO3 47SDM_MAXB_IO1 29SDM_MAXB_IO2 29
SDM_MAXB_IO4 29SDM_MAXB_IO3 29
SDM_MAXB_IO529 SDM_MAXB_IO629
FBHBP8 23FBHBN8 23
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
42 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
42 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
42 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
BANK-2MAX 10 CLOCK
BANK-3
BANK-4
BANK-6
BANK-8
10M50DAF484
U43E
DIFFIO_RX_L28N/CLK0NN4DIFFIO_RX_L28P/CLK0PN5DIFFIO_RX_L36N/CLK1NM8DIFFIO_RX_L36P/CLK1PM9
DIFFIO_TX_RX_B18N/CLK6NV9DIFFIO_TX_RX_B18P/CLK6PV10DIFFIO_TX_RX_B20N/CLK7NR11DIFFIO_TX_RX_B20P/CLK7PP11
DIFFIO_RX_R38N/CLK2NN15DIFFIO_RX_R38P/CLK2PN14DIFFIO_RX_R40N/CLK3NK21DIFFIO_RX_R40P/CLK3PK22
DIFFIO_RX_T38N/CLK4NE10DIFFIO_RX_T38P/CLK4PE11DIFFIO_RX_T40P/CLK5PJ10DIFFIO_RX_T40N/CLK5NH11
DIFFIO_RX_L38N/DPCLK0 P3DIFFIO_RX_L38P/DPCLK1 R3
DIFFIO_RX_L59N/PLL_L_CLKOUTN T5DIFFIO_RX_L59P/PLL_L_CLKOUTP T6
DIFFIO_TX_RX_B57N/PLL_B_CLKOUTN W17DIFFIO_TX_RX_B57P/PLL_B_CLKOUTP V17
DIFFIO_RX_R50N/DPCLK2/DQSn2R L15DIFFIO_RX_R50P/DPCLK3/DQS2R L14
DIFFIO_RX_R69N/PLL_R_CLKOUTN G17DIFFIO_RX_R69P/PLL_R_CLKOUTP H17
DIFFIO_RX_T52N/PLL_T_CLKOUTN E6DIFFIO_RX_T52P/PLL_T_CLKOUTP D6
J56
CON3
123
BANK-3 BANK-4MAX 10 BOTTOM BANKS
10M50DAF484
U43B
DIFFIO_RX_B10NY7DIFFIO_RX_B10PY8DIFFIO_RX_B12NAB2DIFFIO_RX_B12PAB3DIFFIO_RX_B14NY3DIFFIO_RX_B14PY4DIFFIO_RX_B17NAA5DIFFIO_RX_B17PAB5DIFFIO_RX_B19NAB6DIFFIO_RX_B19PAB7DIFFIO_RX_B21NAA8DIFFIO_RX_B21PAB8DIFFIO_RX_B23NAA9DIFFIO_RX_B23PAB9DIFFIO_RX_B2NV4DIFFIO_RX_B2PV5DIFFIO_RX_B4NY1DIFFIO_RX_B4PY2DIFFIO_RX_B6NAA1DIFFIO_RX_B6PAA2DIFFIO_RX_B8NY5DIFFIO_RX_B8PY6DIFFIO_TX_RX_B11NW9DIFFIO_TX_RX_B11PW10DIFFIO_TX_RX_B13NW7DIFFIO_TX_RX_B13PW8DIFFIO_TX_RX_B15NR10DIFFIO_TX_RX_B15PP10DIFFIO_TX_RX_B16NAA6DIFFIO_TX_RX_B16PAA7DIFFIO_TX_RX_B1NW5DIFFIO_TX_RX_B1PW6DIFFIO_TX_RX_B22NY10DIFFIO_TX_RX_B22PAA10DIFFIO_TX_RX_B3NU6DIFFIO_TX_RX_B3PU7DIFFIO_TX_RX_B5NW4DIFFIO_TX_RX_B5PW3DIFFIO_TX_RX_B7NV7DIFFIO_TX_RX_B7PV8DIFFIO_TX_RX_B9NR9DIFFIO_TX_RX_B9PP9VREFB3N0AA3IO_BANK3AB4
DIFFIO_RX_B25N W11DIFFIO_RX_B25P Y11DIFFIO_RX_B27N AB10DIFFIO_RX_B27P AB11DIFFIO_RX_B29N AB12DIFFIO_RX_B29P AB13DIFFIO_RX_B35N W12DIFFIO_RX_B35P W13DIFFIO_RX_B38N AA14DIFFIO_RX_B38P AB15DIFFIO_RX_B40N AA15DIFFIO_RX_B40P Y16DIFFIO_RX_B42N AB16DIFFIO_RX_B42P AA16DIFFIO_RX_B44N AB19DIFFIO_RX_B44P AB20DIFFIO_RX_B46N AA19DIFFIO_RX_B46P Y18DIFFIO_RX_B50N AB21DIFFIO_RX_B50P AA20DIFFIO_RX_B58N AB17DIFFIO_RX_B58P AB18
DIFFIO_TX_RX_B24N V11DIFFIO_TX_RX_B24P V12DIFFIO_TX_RX_B26N R12DIFFIO_TX_RX_B26P P12DIFFIO_TX_RX_B28N AA11DIFFIO_TX_RX_B28P AA12DIFFIO_TX_RX_B34N V13DIFFIO_TX_RX_B34P W14DIFFIO_TX_RX_B36N R13DIFFIO_TX_RX_B36P P13DIFFIO_TX_RX_B37N Y13DIFFIO_TX_RX_B37P Y14DIFFIO_TX_RX_B39N V14DIFFIO_TX_RX_B39P W15DIFFIO_TX_RX_B41N U15DIFFIO_TX_RX_B41P V16DIFFIO_TX_RX_B43N AA17DIFFIO_TX_RX_B43P Y17DIFFIO_TX_RX_B45N V15DIFFIO_TX_RX_B45P W16DIFFIO_TX_RX_B49N Y19DIFFIO_TX_RX_B49P W18
VREFB4N0 AA13IO_BANK4 AB14
Testsignal_1Testsignal_2
![Page 43: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/43.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
System MAX10 Controller 4 IO_1V8 12,21,22,25,29,30,32,33,34,36,39,40,63,64,65,66,68IO_3V3 14,15,16,17,22,25,26,29,30,31,32,34,35,36,37,38,57,69,70
IO_2V5 10,11,12,22,26,27,32,38,68
S10DDR_1V2 27,28,31,57,60,63,66
1p2V_VCCDPLL
1p2V_VCCDPLL
1p2V_VCCINT
1p2V_VCCINT
2p5V_VCCAADC
2p5V_VCCAADC
2p5V_VREFADC
2p5V_VREFADC
IO_1V8IO_3V3
IO_2V5
S10DDR_1V2
S10DDR_1V2
S10DDR_1V2
S10DDR_1V2
IO_2V5
IO_2V5
IO_2V5 IO_2V5
IO_1V8
IO_1V8
S10DDR_1V2
S10DDR_1V2
IO_3V3
IO_3V3
IO_1V8
IO_1V8
IO_1V8
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
43 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
43 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
43 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C50610uF
C5110.1uF
C4980.1uF
L39BLM15AG221SN1
C4840.1uF
C5210.1uFC541
0.1uF
C5300.1uF
C5150.1uF
C5020.1uF
C5250.1uF
C4930.1uF
L42BLM15AG221SN1
L40BLM15AG221SN1
C5390.1uFC536
0.1uFC5330.1uF
C5100.1uF
C4970.1uF
C5200.1uF
C5290.1uF
FB1 120ohm, 800mA1 2
C5140.1uF
C5010.1uF
C5240.1uF
C4900.1uF
C5070.1uF
C4880.1uF
C52610uF
C508100uF
C4960.1uF
C48110uF
C5190.1uF
C4850.1uF
C5130.1uF
C5000.1uF
C5230.1uF
C4830.1uF
C5280.1uF
C4920.1uF
C5320.1uF
C5040.1uF
C5400.1uF
MAX 10 POWER
10M50DAF484
U43G
VCCN12VCCN10VCCM13VCCM12VCCM11VCCL12VCCL11VCCL10VCCK13VCCK11
VCCD_PLL1T7VCCD_PLL2G16VCCD_PLL3G7VCCD_PLL4U16
VCCA1R8VCCA2H15VCCA3H8VCCA4T15
VCCINTJ7VCCA_ADCH7
ADC_VREFH6
ANAIN1G5ANAIN2J5
VCCIO1A L6VCCIO1A K7VCCIO1B M6VCCIO1B L7
VCCIO2 R6VCCIO2 P7VCCIO2 N7VCCIO2 N6
VCCIO3 U9VCCIO3 U8VCCIO3 T9VCCIO3 T11VCCIO3 T10
VCCIO4 U14VCCIO4 U12VCCIO4 U11VCCIO4 T13VCCIO4 T12
VCCIO5 T17VCCIO5 R17VCCIO5 R16VCCIO5 P16VCCIO5 N16
VCCIO6 N17VCCIO6 M17VCCIO6 L16VCCIO6 K17VCCIO6 K16VCCIO6 J17VCCIO6 H16
VCCIO7 G14VCCIO7 G13VCCIO7 G12VCCIO7 F14VCCIO7 F12
VCCIO8 G11VCCIO8 G10VCCIO8 F9VCCIO8 F11
C5050.1uF
C5380.1uFC534
0.1uF
C4950.1uF
C5180.1uFL41
BLM15AG221SN1
C5220.1uF
C4910.1uF
C5270.1uF
C5120.1uF
C4990.1uF
C5310.1uF
C5160.1uF
C53510uF
C5030.1uF
C4890.1uF
C5090.1uF
C4870.1uF
C4820.1uF
C5370.1uF
C4860.1uF
C4940.1uF
C5170.1uF
MAX 10 GROUND
10M50DAF484
U43H
GNDY9GNDY15GNDY12GNDW21GNDV6GNDV2GNDV19GNDU13GNDU10GNDT8GNDT4GNDT16GNDT14GNDR21GNDR19GNDP6GNDP2GNDP17GNDN13GNDN11GNDM7GNDM19GNDM16GNDM10GNDL5GNDL21GNDL17GNDL13
DNUL3
GND K3GND K12GND K10
GND J6GND J2GND J19GND J16GND G8GND G6GND G21GND G18GND G15GND F13GND F10GND E7GND E2GND D4GND D20GND D16GND D11GND B9GND B6GND B18GND B13GND AB22GND AB1GND AA4GND AA18GND A22GND A1
NC2 F6NC1 E5REFGNDH5
![Page 44: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/44.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Stratix 10 SOC DEV KIT PDN Diagram
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
44 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
44 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
44 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
![Page 45: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/45.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Stratix 10 SOC Power Sequence
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
45 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
45 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
45 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
![Page 46: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/46.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Copyright (c) 2015, Altera Corporation. All Rights Reserved.
Altera Corporation, 301, Bibo Rd #888, Shanghai, China, 201203
MAX 10 PWR Manager 1
I2C Address = b'0010100'
RefVoltage = 0.3VPCIE3V3I_P 71PCIE3V3I_N 71FMA3V3I_P 71FMA3V3I_N 71FMB3V3I_P 71FMB3V3I_N 71FMAVADJI_P 71FMAVADJI_N 71FMBVADJI_P 71FMBVADJI_N 71S10_1V2I_P 60S10_1V2I_N 60S10_HPSVDDI_P 61S10_HPSVDDI_N 612V5I_P 512V5I_N 51
LTSDA34,38 LTSCL34,38
S10_EN 53S10_VCC_EN 54,55,56S10_HPS_EN 58S10_VCCeram_EN 58
S10_VCCPT_EN 59
IO3V3_Discharge 70VCCPT_discharge 70
S10_VCCPGOOD 54,55,56VCCHPSPgood 58VCCeramgood 58VCCTPgood 59VCCPTPgood 59
HILOHPS_VDDPGood 61
10V_Fail_n 5310V_good 53PMbus_ALERTn 38,50,54,58,59,62
VCCRPGOOD 62
2V5_Pgood 513V3_Pgood 505V0_Pgood 49
1V2_Pgood 60
PCIE_auxEN 69PCIE_EN 48,69FMCA_AUXEN 67FMCA_EN 48,67,68FMCB_AUXEN 67FMCB_EN 48,67,68
S10_VCCT_EN 59S10_VCCR_EN 62
IO_EN 60,61,68,69S10_1V2SENSP60
HPS_cold_RESETn 47
MAX_ERROR 31
IO_5V10,11,15,38,49
2V58,51,68
3V37,8,29,31,47,50,51,52,53,67,69
S10_VCCFAULT 54,55
S10_EN_2V4 57
HILOHPSSENSP61
TSENSE_ALERTn 38OVERTEMPn 38
FPGABoot_Presentn 29
IO_48_Power_en_3v3 30
USB2_1V8_Pgood 52USB1V8SENSP52
PCIE_PRSNT2n 8,9,41
FAC2MPgood 19FBC2MPgood 23FBM2CPgood 23FAM2CPgood 19
USBIO_disable 8
A_GND
A_GND
3V3
3V3
3V3
3V3
2V5
IO_5V
IO_5V2V53V3
3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
46 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
46 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
46 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R3781.00k MAX10 10M16SA U169
U46JREFGND__E2E2ADC_VREF__D3D3ANAIN1__D2D2
R4071.00k
R377 10
R785 49.9R916 49.9
R397 10
C548 1pF
R52311.00k
R393 49.9
C550 1pFC549 1pF
R10230
R385 49.9
MAX10 10M16SA U169
U46BIO_1A_D1/ADC1IN1/DIFFIO_RX_L1ND1IO_1A_C2/ADC1IN2/DIFFIO_RX_L1PC2IO_1A_E3/ADC1IN3/DIFFIO_RX_L3NE3IO_1A_E4/ADC1IN4/DIFFIO_RX_L3PE4IO_1A_C1/ADC1IN5/DIFFIO_RX_L5NC1IO_1A_B1/ADC1IN6/DIFFIO_RX_L5PB1IO_1A_F1/ADC1IN7/DIFFIO_RX_L7NF1IO_1A_E1/ADC1IN8/DIFFIO_RX_L7PE1
IO_1B_F4/DIFFIO_RX_L14NF4IO_1B_G4/DIFFIO_RX_L14PG4IO_1B_H2/DIFFIO_RX_L16NH2IO_1B_H3/DIFFIO_RX_L16PH3
R411100
0402
R409100
0402
R388 10 C547 1pF
R40249.9K
R392 49.9
C5530.1uF
R40349.9K
C543 1pFC544220pF
MAX10 10M16SA U169
U46FIO_6_F12/DIFFIO_RX_R22P F12IO_6_E12/DIFFIO_RX_R22N E12
IO_6_C13 C13IO_6_F8/DIFFIO_RX_R31P F8
IO_6_B12/DIFFIO_RX_R32P B12IO_6_E9/DIFFIO_RX_R31N E9
IO_6_B11/DIFFIO_RX_R32N B11IO_6_C12/DIFFIO_RX_R33P C12IO_6_B13/DIFFIO_RX_R34P B13IO_6_C11/DIFFIO_RX_R33N C11IO_6_A12/DIFFIO_RX_R34N A12IO_6_E10/DIFFIO_RX_R35P E10IO_6_D9/DIFFIO_RX_R35N D9
IO_6_D12/DIFFIO_RX_R37P D12IO_6_D11/DIFFIO_RX_R37N D11
C552220pF
R383 10
R394 10
C546 1pF
R4081.00k
R7871.00k U47
LTC2497
CN0 8CN1 9CN2 10CN3 11CH4 12CH5 13CH6 14CH7 15CH8 16CH9 17
CH10 18CH11 19CH12 20CH13 21CH14 22CH15 23
GND1 31GND2 32GND3 33GND4 34GND5 39GND6 1GND7 4GND8 6
COM 7
NC5
SCL2 SDA3MUXOUTP24 MUXOUTN27
ADCINN26ADCINP25
VCC28
REFN30REFP29
CA036 CA137 CA238
f035
R4061.00k
R401 49.9R400 10
R523049.9K
MAX10 10M16SA U169
U46GIO_8_A8/DIFFIO_RX_T27P A8IO_8_A9/DIFFIO_RX_T27N A9
IO_8_B10/DIFFIO_RX_T28P B10IO_8_A10/DIFFIO_RX_T29P A10IO_8_A11/DIFFIO_RX_T29N A11
IO_8_E8/DIFFIO_RX_T30N E8IO_8_A7/DIFFIO_RX_T31P A7IO_8_A6/DIFFIO_RX_T31N A6IO_8_B6/DIFFIO_RX_T32P B6IO_8_A4/DIFFIO_RX_T33P A4IO_8_B5/DIFFIO_RX_T32N B5IO_8_A3/DIFFIO_RX_T33N A3IO_8_E6/DIFFIO_RX_T34P E6IO_8_B3/DIFFIO_RX_T35P B3IO_8_B4/DIFFIO_RX_T35N B4
IO_8_A5 A5IO_8_A2/DIFFIO_RX_T38P A2IO_8_B2/DIFFIO_RX_T38N B2
C542 1pF
R379 10
R4101.00k
R4051.00k
C551 1pF
C55410uF
R384 49.9
R40449.9KR786
49.9K
R390 49.9R387 49.9
MAX10 10M16SA U169
U46DIO_3_L5/DIFFIO_TX_RX_B1N L5
IO_3_M4/DIFFIO_RX_B2N M4IO_3_L4/DIFFIO_TX_RX_B1P L4
IO_3_M5/DIFFIO_RX_B2P M5IO_3_K5/DIFFIO_TX_RX_B3N K5
IO_3_N4/DIFFIO_RX_B4N N4IO_3_J5/DIFFIO_TX_RX_B3P J5
IO_3_N5/DIFFIO_RX_B4P N5IO_3_N6/DIFFIO_TX_RX_B5N N6
IO_3_N7/DIFFIO_RX_B6N N7IO_3_M7/DIFFIO_TX_RX_B5P M7
IO_3_N8/DIFFIO_RX_B6P N8IO_3_J6/DIFFIO_TX_RX_B13N J6
IO_3_M8/DIFFIO_RX_B14N M8IO_3_K6/DIFFIO_TX_RX_B13P K6
IO_3_M9/DIFFIO_RX_B14P M9IO_3_J7/DIFFIO_TX_RX_B15N J7IO_3_K7/DIFFIO_TX_RX_B15P K7
IO_3_N12 N12IO_3_M13/DIFFIO_TX_RX_B16N M13
IO_3_N10/DIFFIO_RX_B17N N10IO_3_M12/DIFFIO_TX_RX_B16P M12
IO_3_N9/DIFFIO_RX_B17P N9IO_3_M10/DIFFIO_TX_RX_B22N M10IO_3_L10/DIFFIO_TX_RX_B22P L10
R382 10 C545 1pF R381 49.9
R396 49.9
R391 10
R386 49.9
R398 49.9
R389 49.9
R399 49.9
R380100
0402
R395 49.9
LTSDALTSCL
![Page 47: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/47.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MAX10 PWR Manager 2
M10A_JTAG_TMS8
M10A_JTAG_TDO8M10A_JTAG_TCK8 M10A_JTAG_TDI8
MAX10A_CLK 8
3V3 7,8,29,31,46,50,51,52,53,67,69
USB2_1V8 7,8,32,52,68
MAIN_12V 48,49,50,53,68
ENET_DISABLE_N22
CLK_50M_MAX 32
BQSPI_RESETN29
HPS_cold_RESETn 46
MAX10B_CLK42
DC_POWER_CTRL31 HPS_DC_RESET_n30 HPS_DC_presetn30
FAPRSNT_N 19,31FBPRSNT_N 23,31BF_Presentn 29
FPGAboot_RESETN 29
HPS_NRST29
HPS_warm_RESET1n8
MAX10B_RESETn 41
MATOMBIO4 42MATOMBIO5 42MATOMBIO6 42MATOMBIO7 42
MATOMBIO0 42MATOMBIO1 42MATOMBIO2 42MATOMBIO3 42USBMAX_MAX10A_IO0 8
USBMAX_MAX10A_IO18
USBMAX_MAX10A_IO2 8USBMAX_MAX10A_IO3 8
3V3
MAX10_VCCIO1A3V3USB2_1V8
MAX10_VCCA
3V3
A_GND
MAX10_VCCA3V3 3V3 MAX10_VCCIO1A
3V3
3V3
USB2_1V8
3V3 3V3
MAIN_12V
MAIN_12V
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
47 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
47 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
47 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R4220
C5550.1uF
C5670.1uF
C5650.1uF
MAX10 10M16SA U169
U46IIO_1B_E5/JTAGENE5IO_1B_G1/TMS/DIFFIO_RX_L11NG1IO_1B_G2/TCK/DIFFIO_RX_L11PG2IO_1B_F5/TDI/DIFFIO_RX_L12NF5IO_1B_F6/TDO/DIFFIO_RX_L12PF6IO_8_B9/DEV_CLRN/DIFFIO_RX_T28NB9IO_8_D8/DEV_OE/DIFFIO_RX_T30PD8IO_8_D7/CONFIG_SELD7INPUT_ONLY_8_E7/NCONFIGE7IO_8_D6/CRC_ERROR/DIFFIO_RX_T34ND6IO_8_C4/NSTATUS/DIFFIO_RX_T36PC4IO_8_C5/CONF_DONE/DIFFIO_RX_T36NC5
C5630.1uF
FB2220ohm, 2.0A
1 2
C5740.1uF
S20PB Switch
1 2J16
FAN_ConnPWM 1TACH 212V 3GND 4
C5720.1uF
U48
MAX811
GND 1
RESET 2VCC4
MR3
C5700.1uF
C56810uF
R4160
R419 10.0K
R4140
C5600.1uF
C5580.1uF
C5560.1uF
C5660.1uF
R417 10.0K
R412 10.0K
C5640.1uF
R42020K
C5620.1uF
R418 10.0K
C5750.1uFC57310uF
L43
BLM15AG221SN1300mA
MAX10 10M16SA U169
U46AVCCIO1A__F2F2VCCIO1B__G3G3VCCIO2__K3K3VCCIO2__J3J3VCCIO3__L8L8VCCIO3__L7L7VCCIO3__L6L6VCCIO5__J11J11VCCIO5__H11H11VCCIO6__G11G11VCCIO6__F11F11VCCIO8__C8C8VCCIO8__C7C7VCCIO8__C6C6VCCA1__K4K4VCCA2__D10D10VCCA3__D4D4VCCA4__K9K9
VCC_ONE__H7H7VCC_ONE__G8G8VCC_ONE__G6G6VCC_ONE__F7F7
R421 100K
MAX10 10M16SA U169
U46HIO_2_G5/CLK0N/DIFFIO_RX_L20N G5IO_2_H6/CLK0P/DIFFIO_RX_L20P H6IO_2_H5/CLK1N/DIFFIO_RX_L22N H5IO_2_H4/CLK1P/DIFFIO_RX_L22P H4
IO_2_N2/DPCLK0/DIFFIO_RX_L24N N2IO_2_N3/DPCLK1/DIFFIO_RX_L24P N3
IO_3_M11/CLK6N/DIFFIO_TX_RX_B18N M11IO_3_L11/CLK6P/DIFFIO_TX_RX_B18P L11IO_3_J8/CLK7N/DIFFIO_TX_RX_B20N J8IO_3_K8/CLK7P/DIFFIO_TX_RX_B20P K8
IO_6_G9/CLK2P/DIFFIO_RX_R18P G9IO_6_G10/CLK2N/DIFFIO_RX_R18N G10IO_6_F13/CLK3P/DIFFIO_RX_R20P F13IO_6_E13/CLK3N/DIFFIO_RX_R20N E13IO_6_F9/DPCLK3/DIFFIO_RX_R30P F9
IO_6_F10/DPCLK2/DIFFIO_RX_R30N F10IO_8_C10/CLK5P/DIFFIO_RX_T26P C10IO_8_C9/CLK5N/DIFFIO_RX_T26N C9
IO_1B_H1/VREFB1N0 H1IO_2_L1/VREFB2N0 L1
IO_3_N11/VREFB3N0 N11IO_5_K13/VREFB5N0 K13IO_6_D13/VREFB6N0 D13
IO_8_B7/VREFB8N0 B7
C5710.1uF
MAX10 10M16SA U169
U46CIO_2_M3/PLL_L_CLKOUTN/DIFFIO_RX_L31NM3IO_2_L3/PLL_L_CLKOUTP/DIFFIO_RX_L31PL3
IO_2_J1/DIFFIO_RX_L21NJ1IO_2_J2/DIFFIO_RX_L21PJ2IO_2_M1/DIFFIO_RX_L23NM1IO_2_M2/DIFFIO_RX_L23PM2IO_2_L2L2IO_2_K1/DIFFIO_RX_L32NK1IO_2_K2/DIFFIO_RX_L32PK2
C5690.1uF
MAX10 10M16SA U169
U46EIO_5_K10/RUP/DIFFIO_RX_R1P K10IO_5_J10/RDN/DIFFIO_RX_R1N J10
IO_5_K11/DIFFIO_RX_R2P K11IO_5_L12/DIFFIO_RX_R2N L12
IO_5_K12/DIFFIO_RX_R11P K12IO_5_L13 L13
IO_5_J12/DIFFIO_RX_R11N J12IO_5_J9/DIFFIO_RX_R12P J9
IO_5_J13/DIFFIO_RX_R13P J13IO_5_H10/DIFFIO_RX_R12N H10IO_5_H13/DIFFIO_RX_R13N H13
IO_5_H9/DIFFIO_RX_R14P H9IO_5_G13/DIFFIO_RX_R15P G13
IO_5_H8/DIFFIO_RX_R14N H8IO_5_G12/DIFFIO_RX_R15N G12
MAX10 10M16SA U169
U46KGND__A1A1GND__A13A13GND__B8B8GND__C3C3GND__D5D5GND__E11E11GND__F3F3GND__G7G7GND__H12H12GND__J4J4GND__L9L9GND__M6M6GND__N1N1GND__N13N13
R4150
FB3220ohm, 2.0A
1 2
C56110uF
R4130
C5590.1uF
C5570.1uF
PB_COLD_RESETn COLD_RESETn
Fan_contrl
![Page 48: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/48.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
12V ATX INPUT (12.5A)
24A 1A
4A
1A
18A
Input connector for 280 Watt AC/DC Adapter 12V Power PMOS Switches
3v/ms
3v/ms
3v/ms
3v/ms
FMCB_EN46,67,68
PCIE_EN46,69
FMCA_EN46,67,68
FMCB_12V 23
PCIE_12V 9
FMCA_12V 19
MAIN_12V 47,49,50,53,68
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
48 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
48 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
48 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R450
1.00k R45210K
SW7SW_SLIDE_DPDT
12365
4
R43710
C579330uF25V
R445100K
R4321.00k
Q13MMBT2222A-7-F
CE
B
Q20MMBT2222A-7-F
CE
B
Q10DMP3098L
S D
G
Q15Si7635DP
1567
4
823
C578330uF25V
R42310
Q18MMBT2222A-7-F
CE
B
TP15
TP14
R78949.9K
R446100K
TP18
C5801uF
Q16
DMP3098L
S
D
G
R43849.9K
R42549.9K
Q11
DMP3098L
S
D
G
TP17
TP19
Q12MMBT2222A-7-F
CE
B
C5820.1uF
C5761uF
TP16
C581330uF25V
R44110
C5831uF R444
10
Q9Si7633DP
1567
4
823
J25
PCIe 2x4 ATX
12V 112V 212V 3
GND8SENSE14 SENSE06
GND5GND7
Q21MMBT2222A-7-F
CE
B
R42749.9K
C577330uF25V
R42649.9K
TP20
C5841uFR442
49.9K
R4481.00k
Q17
DMP3098L
S
D
G
R43610
R44349.9K
R45110K
C5860.1uF
R42849.9KD49
B530C
R449
1.00k
R43010
R42410
R44049.9K
R43949.9K
R4471.00k
R433100K
R431100K
R43510K
Q14DMP3098L
S D
G
Q19MMBT2222A-7-F
CE
B
J55
PCIe 2x3 ATX
12V_1 112V_2 212V_3 3
GND44SNS05GND66
TP13
R42910
C5850.1uF
R434
1.00k
Adapter_DC_12V
MAIN_GATE
![Page 49: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/49.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
5.0V
12V to 5V Power Supply
MAIN_12V 47,48,50,53,68
IO_5V10,11,15,38,46
5V0_Pgood 46
5V_INTVCC
5V_INTVCC
MAIN_12V
MAIN_12V
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardCustom
49 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardCustom
49 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardCustom
49 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C59647uF
R4630
U49
LTM4625
FREQA4
PHMODEB2
MODEC4
FBB1
TRACK/SSA2
COMPA1
RUNA3
PGOO
DC2
VOUT1 C1
PGND
1B3
VIN1 D5
SVIN
C5INT
VCC
E4
SGNDB4
CLKO
UTB5
CLKIN
A5
VIN2 E5
VOUT2 D1
VOUT3 D2
VOUT4 E1
VOUT5 E2
PGND
2C3
PGND
3D3
PGND
4D4
PGND
6E3
C592
0.1uFR457
100K
C58922uF
TP25
R456
100K
R46249.9K
C5880.1uF
C59547uF
C5980.1uF
R4648.25K1% C599DNI
R454
10
C59447uF
C59122uF
TP22
R453100K
TP23
C5871uF TP21
R459 DNI
R461100K
C59347uF
C59022uF
C597100pf
R455DNI
TP24
R460DNI
R458 DNI
![Page 50: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/50.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
I2C ADDRESS:b'1001110'
6A
20A
12V to 3V3 Converter
PMbus_SDA_3V3 29,38,54,58,59,62PMbus_SCL_3V3 29,38,54,58,59,62
PMbus_ALERTn 38,46,54,58,59,62
3V37,8,29,31,46,47,51,52,53,67,69
MAIN_12V47,48,49,53,68
3V3_Pgood 46
GND_SIGNAL2
GND_SIGNAL2
GND_SIGNAL2
GND_SIGNAL2
GND_SIGNAL2
GND_SIGNAL2
3V3
3V3
MAIN_12V
MAIN_12V
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
50 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
50 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
50 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
TP33
TP31
R470
10K
TP32
C603330uF6.3V
R485 22.6K
R465DNIC601100uF
R480DNI
C60722uF
C614100uF
C6082200pF
C613100uF
C605DNI
R486 DNI
TP26
R4780
TP36
TP29
TP27 C602
100uF
C611330uF6.3V
C612100uF
R48110K
R4820
R4794.75K
R484 12.7K
R475
10K
C60622uF
C600100uF
R483 22.6K
R471
10K
R466
0
TP30
R476
10K
TP28
C604100uF
R487 22.6K
R467
DNI
TP35
R473
10K
R4880
R468 DNI
R469
10K
C610DNI
C60968pF
R474
10K
R4900
TP34
R4720
U50LTM4676A
VOUT0_1A1VOUT0_2A2VOUT0_3A3
VOUT0_10D1
ISNS0b-E1
ISNS0b+F1
ISNS1
b-G1
ISNS1
b+H1
VOUT
1_1J1
VOUT
1_2J2
VOUT
1_3J3
VOUT
1_4K1
VOUT0_4B1VOUT0_5B2VOUT0_6B3
VOUT0_11D2
ISNS0a-E2
ISNS0a+F2
ISNS1
a-G2
ISNS1
a+H2
VOUT
1_5K2
VOUT
1_6K3
VOUT
1_7L1
VOUT
1_8L2
VOUT0_7C1VOUT0_8C2VOUT0_9C3
VOUT0_12D3
GND1
A4GN
D2A6
GND3
A7GN
D4A8
VOUT
1_9L3
VOUT
1_10
M1VO
UT1_1
1M2
VOUT
1_12
M3
GND5
A9GN
D6A1
0GN
D7B4
GND8
B5
ASEL G4
FSWPHCFG H4
GND9
B6GN
D10
B7GN
D11
B8GN
D12
B9
GPIO0 E4
GPIO1 F4
SNUB0A5
GND1
3C4
TSNS0bC5TSNS0aD5
ALERT E5
RUN0 F5
VOUT0CFG G5
VTRIM0CFG H5TS
NS1a
J5TS
NS1b
K5
GND1
4C6
SNUB
1M5
GND1
5C7
GND1
6C8
GND1
7C9
SDA D6SCL E6
RUN1 F6
VOUT1CFG G6
VTRIM1CFG H6
VDD25 J6
WP K6
GND1
8D4
GND2
0E3
GND2
1F3
GND2
2F1
0GN
D23
G3GN
D24
G10
SYNC E7
GND4
5M9
GND4
6M1
0
SHARE_CLK H7
VDD33 J7
GND2
5G1
1GN
D26
G12
GND3
9L8
GND3
8L7
GND4
0L9
GND2
7H3
COMP0bD8COMP0aE8
SGND
3F7
SGND
4F8
COMP
1aH8
COMP
1bJ8
GND2
8H1
0GN
D29
J4
GND4
4M8
VOSNS0+D9
VOSNS0-E9
INTVCC_1 F9INTVCC_2 G9
VOSN
S1H9
VORB
1J9
GND3
0J10
GND3
5L4
GND3
6L5
GND3
1K4
SW0B10
DNC2
E11
VORB0+D10
VORB0-E10
GND3
7L6
GND3
2K7
GND3
3K8
GND3
4K9
DNC1
C10
SW1
L10
GND4
1M4
VINH0_4B12 VINH0_3B11 VINH0_2A12 VINH0_1A11
DNC4
K10
VINL_2F12
GND4
2M6
DNC3
H11
VINH1
_1H1
2VIN
H1_2
J11VIN
H1_3
J12VIN
H1_4
K11
VINH0_9E12 VINH0_8D12 VINH0_7D11 VINH0_6C12 VINH0_5C11
VINL_1F11
GND4
3M7
VINH1
_5K1
2VIN
H1_6
L11VIN
H1_7
L12VIN
H1_8
M11
VINH1
_9M1
2
SGND
1G7
SGND
2G8
GND1
9D7
R477DNI
R489 DNI
INTVCC_5V_2
3V3_SENSE+
VDD33_2
COMP02
VDD25_2
SHARE_CLK2
3V3_SENSE-
SYNC_2
![Page 51: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/51.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206 1206
0402
0402
0402
0402
VIN = 2.4 - 6.6 VDC
A single through-hole test point connects the AGNDpin to the GND plane.
Connect the output cap to the GND plane through multiple vias
Connect the input cap to the GND plane through multiple vias.(see the Gerber files)
X5RX5R2A
2A
3V3 to 2V5 Converter
2V5_Pgood 46
3V3 7,8,29,31,46,47,50,52,53,67,69
2V58,46,68
2V5I_P46
2V5I_N463V3
2V5
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
51 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
51 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
51 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R493
86.6k
R496200k
TP38
C61515nF
R4920
C61615pF
R491
100kTP37
U51EN6337QI
NC(SW)71
NC(SW)62
NC33
NC44
VOUT5
VOUT6
VOUT
7
VOUT
8
VOUT
9
VOUT
10
VOUT
11
NC(SW
)12
PGND
13
PGND
14
PGND
15
PGND
16
PGND
17
PGND
18
PVIN
19
NC25 25
NC24 24
NC23 23
NC22 22
PVIN 21
PVIN 20
NC(SW
)138
NC(SW
)237
NC(SW
)336
NC(SW
)435
NC(SW
)534
AVIN
33
AGND
32
VFB
31
SS30
RLLM
29
POK
28
ENAB
LE27
LLM/SY
NC26
GND_
PAD
39
R494DNI
C6171uF
C619 22uF
TP39
R495 10K
R4990
R498
0.001
C618 47uF
R497 10K
C620 47uF
PDEN
2V5out
![Page 52: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/52.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
Connect the input and output caps to the GND plane through mulitple vias.(Please see the Gerber files.)X5R
X5R
X5R
0201X5R
1206 X5R
1206 X5RA single through-hole viaconnects the AGNDpin to the GND plane.
0402
0402 0402
0201
0402
3.3V to 1.8V Converter
8A5A 3V3 7,8,29,31,46,47,50,51,53,67,69
USB1V8SENSP46
USB2_1V87,8,32,47,68
USB2_1V8_Pgood 46
USB2_1V83V3
3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
52 71Tuesday, May 09, 2017150-0321308 (6XX-44382R)
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
52 71Tuesday, May 09, 2017150-0321308 (6XX-44382R)
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
52 71Tuesday, May 09, 2017150-0321308 (6XX-44382R)
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R94480.6K
C16430.22uF
TP132
R946160k
U106EN63A0QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC19
19
VOUT
20
VOUT
21
VOUT
22
VOUT
23
VOUT
24
VOUT
25
VOUT
26
VOUT
27
VOUT
28
NC29
29
NC(SW
)3030
NC(SW
)3131
PGND
32
PGND
33
PGND
34
PGND
35
PGND
36
PGND
37
S_IN 56
BGND 55
VDDB 54
NC53 53
NC52 52
PVIN 51
PVIN 50
PVIN 49
PVIN 48
PVIN 47
PVIN 46
PVIN 45
PVIN 44
PVIN 43
NC76
76
NC75
75
NC74
74
NC73
73
NC72
72
NC(SW
)7171
NC(SW
)7070
EN_P
B69
FQAD
J68
NC(XR
EF)
67
VSEN
SE66
SS65
EAOU
T64
VFB
63
M/S62
AGND
61
AVIN
60
ENAB
LE59
POK
58
PGND
38S_
OUT
57
PVIN 42
PVIN 41
PVIN 40
PVIN 39
NC1515
NC1616
NC1717
NC1818
GND_
PAD
77
C1642 15nF
R949 DNI
C1645 47uF
C1648 47uF
C16440.22uF
R94515k
R951
5.49kTP129
R9470
R9350
C164627pF C1649 47uF
R948100
C1647 47uF
R952
100kTP130
TP131
C1650 47uF
R9530
R950 10K
![Page 53: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/53.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
Typical 12V good threshold voltage is 10.62V. Typcial 12V bad threshold voltage is 10.11V
18A 12A 10AS10 12V,3V3 and 1V8 PMOS Switches
J26 needs be shorted if MAX10 is not programmed
S10_12V 30,54,55,56,58,59,62MAIN_12V47,48,49,50,68
S10_EN46
S10_main_3V3 57,60,61
10V_Fail_n 4610V_good 46
3V37,8,29,31,46,47,50,51,52,67,69
3V3
3V3
S10_12V 3V3MAIN_12V
MAIN_12V
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
53 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
53 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
53 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R5111.00k
Q23
SiRA00DP
1567
4
823
R50210
R509
10K
R51310K
Q24MMBT2222A-7-F
CE
B
R504100K
R50610K
R50325.5K
R51210K
R50149.9K
TP45
Q25MMBT2222A-7-F
CE
B
C6220.01uF
J26
CON2
12
U52
TPS3700
OUTA 1
OUTB 6
VDD 5
INA+3
INB-4
GND2
R500100K
TP44
R50849.9
TP46
R5051.00k
TP41
R51010K
Q22Si7633DP
1567
4
823
R507100K
TP42
C6230.1uF
Q26MMBT2222A-7-FC
EB
C6240.1uF
TP40
C6211uF
TP43
![Page 54: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/54.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
744301025
744301025
I2C Address: 0X5A,0X5B and 0X47Check Phase define
0.9V
0.9V
500Hz
Need 0.85V core voltage
12V to Core 1S10_12V30,53,55,56,58,59,62
PMbus_ALERTn38,46,50,58,59,62
PMbus_SCL_3V329,38,50,58,59,62PMbus_SDA_3V329,38,50,58,59,62
LT3884_SYNC55,56
S10_VCC_EN46,55,56
S10_VCC 55,56,63,65,66
S10_VCCPGOOD 46,55,56
S10_VCCFAULT 46,55
VIN1 55,56
LT3884_ITH55,56
VCC_SENSE 63
VSS_SENSE 63
VDD25
S10_VCC
S10_VCC
GND_SIGNAL_core
GND_SIGNAL_core
EXTVCCINTVCC1
VDD25
VDD33VIN1
VIN1
VDD33
INTVCC1
INTVCC1
VDD33
VDD33
VIN1
VIN1
VIN1
VIN1
S10_12V
S10_12V
GND_SIGNAL_core
GND_SIGNAL_core
GND_SIGNAL_coreGND_SIGNAL_core
GND_SIGNAL_core
GND_SIGNAL_core
GND_SIGNAL_core
VSENSE+53
VSENSE-53VSENSE- 53VSENSE+ 53
VSENSE+ 53VSENSE- 53
SW0
SW1
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardCustom
54 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardCustom
54 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardCustom
54 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R519DNI
R5140.001
R528715
Q32BSG0811ND
4
5
3
1
10
72
8
6
9
R5510
C6380.01uF
R54824.9K
R5405.76K
C6252.2uF
C149422uF
Q28BSG0811ND
4
5
3
1
10
72
8
6
9
R54510K
R5360
R9570.001
R53724.9K
R5340
R53811.3K
C149922uF
R535715
D50
CMDSH-3
C149722uF
R55224.9K
R55010K
R5290
R53010
R543
DNI
TP127
R54624.9K
C632 DNI
C62710uF
1210
R52110K
C62910uF1210
TP134
C637 330pF
R5535.76K
C626 1uF
+C15061000uF2.5V7343
R518
0
R531
DNI
R5475.76K
C6340.1uF
Q31MMST3906-7-F
SOT-323
R54124.9K
C633 10uF1210
R533 DNI
R523DNI
R5495.76K
C149622uF
L45 0.25uH
D51
CMDSH-3
C1503100uF
C1505100uF
R5261K
Q30BSG0811ND
4
5
3
1
10
72
8
6
9 C150022uF
C6400.22uF
Q27BSG0811ND
4
5
3
1
10
72
8
6
9
U53LTC3884EUK
TG1 35
SW1 34
BOOST1 36
IIN-
47
PGND
41
BOOST0 43SW0 45
ITH_R05
SYNC11
SCL12
SDA13
ALERTB14
SHARE_CLK27
RUN017
RUN118
ITH_R130
ITH129
TSNS010
TSNS19
ASEL019
ASEL120
VDD3
328
ITH06
WP26
VDD2
525
IIN+
46
FAULT0 15
FAULT1 16
BG1 37
ISENSE1+ 3
VOUT1_CFG22 VSENSE1- 31VSENSE1+ 32
ISENSE1- 4
VSENSE0+ 1ISENSE0- 8ISENSE0+ 7
BG0 42
VOUT0_CFG21
VSENSE0- 2
49GN
D
FREQ_CFG23
PHASE_CFG24
PGOO
D133
PGOO
D048
TG0 44INTVC
C38
VIN39
EXTVCC40
C6350.22uF
+C15071000uF2.5V7343
R517
0
R5224.7K
C1501100uF
C149822uF
R5425.76K
C1502100uF
Q29MMST3906-7-F
SOT-323
R525
DNI
C6410.01uF
+C15081000uF2.5V7343
R5270
R52010
R5161
R532 DNI
C628150uF7343P
C149522uF
C149322uF
TP135
C1504100uF
R524
DNI
+C15091000uF2.5V7343
R7920
C6390.1uF
C631 10uF1210
L44 0.25uH
C636 6800pf
C63010uF1210
R53924.9K
ASEL0ASEL1VOUT0_CFGVOUT1_CFG
FREQ_CFGPHASE_CFG
WP1
SHARE_CLK
TG0
BST0
TG1
BST1BG1
RUN
![Page 55: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/55.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DCR SENSINGLOWDCRNORMAL
744301025
744301025
Check EXTVCC
12V to Core 2VIN154,56
S10_12V30,53,54,56,58,59,62
LT3884_SYNC54,56
S10_VCCPGOOD46,54,56
S10_VCC_EN46,54,56
LT3884_ITH54,56
S10_VCC 54,56,63,65,66
S10_VCCFAULT46,54
LTC3874_AC_DC56
LTC3874_ILIM56
INTVCC2
INTVCC2INTVCC2 INTVCC2
EXTVCCINTVCC2
INTVCC2
VIN1
VIN1
VIN1
VIN1
S10_12V S10_12V
VIN1
GND_SIGNAL_core
GND_SIGNAL_core
GND_SIGNAL_core
GND_SIGNAL_core
SW2
SW3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardCustom
55 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardCustom
55 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardCustom
55 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C151822uF
+C15171000uF2.5V7343
U54LTC3874EUFD
MODE01
ISENSE0+ 2
ISENSE0- 3RUN04
RUN15
ISENSE1- 6ISENSE1+ 7
MODE18
ITH19
FREQ10
ILIM11
SYNC12
PHASMD13
TG1 14
SW1 15
BOOST1 16
BG1 17
EXTV
CC18
INTVC
C19
VIN20
BG0 21BOOST0 22
SW0 23TG0 24
FAULT1 25
LOWDCR27
ITH028
GND
29FAULT0 26 C1522
22uF
L47 0.25uH
R56310K
C152422uF
C643
4.7uF
R558 0
R5542
C6450.1uF
C152122uF
+C15151000uF2.5V7343
R5660
L46 0.25uH
C152322uF
R559 0
R794
10K
R568
DNI
R556715
C1510100uF
C152022uF
R793
10K
R56720K
D52
CMDSH-3R555 0
C642 1uF
C1511100uF
C1513100uF
Q36BSG0811ND
4
5
3
1
10
72
8
6
9
R5570
Q34BSG0811ND
4
5
3
1
10
72
8
6
9
C151922uF
R560
DNI
C6480.22uF
+C15161000uF2.5V7343
C1512100uF
R565715
Q35BSG0811ND
4
5
3
1
10
72
8
6
9
C6460.22uF
C647 22pF
R561 100K
R5620 D53
CMDSH-3
C152522uF
+C15141000uF2.5V7343
Q33BSG0811ND
4
5
3
1
10
72
8
6
9
C6490.1uF
C644
4.7uF
BST2
TG2
TG3
BST3BG3
![Page 56: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/56.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
744301025
744301025
12V to Core 3
LT3884_SYNC54,55S10_VCCPGOOD46,54,55
S10_VCC_EN46,54,55
LT3884_ITH54,55
LTC3874_AC_DC55
S10_12V30,53,54,55,58,59,62
VIN154,55S10_VCC54,55,63,65,66
S10_VCCFAULT46,54,55
LTC3874_ILIM55
GND_SIGNAL_core
INTVCC3
INTVCC3
INTVCC3
VIN1
VIN1
VIN1
VIN1
EXTVCCINTVCC3
S10_12V
VIN1
S10_12V
GND_SIGNAL_core
GND_SIGNAL_core
GND_SIGNAL_core
SW4
SW5
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardCustom
56 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardCustom
56 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardCustom
56 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R575
DNI
C153022uF
R571715
R570 0
C152722uFC652
4.7uF
C6570.1uF
C152622uF
C6560.22uF
C1536100uF
R583
DNI
Q40BSG0811ND
4
5
3
1
10
72
8
6
9
R576 100K
+C15381000uF2.5V7343
C153322uF
+C15391000uF2.5V7343
R574 0
C650 1uF
C1535100uF
+C15401000uF2.5V7343
+C15411000uF2.5V7343
C6540.22uF
C153222uF
D54
CMDSH-3
R57910K
L48 0.25uH
C6530.1uF
C651
4.7uF
L49 0.25uH
C1534100uF
R5780
U55LTC3874EUFD
MODE01
ISENSE0+ 2
ISENSE0- 3RUN04
RUN15
ISENSE1- 6ISENSE1+ 7
MODE18
ITH19
FREQ10
ILIM11
SYNC12
PHASMD13
TG1 14
SW1 15
BOOST1 16
BG1 17
EXTV
CC18
INTVC
C19
VIN20
BG0 21BOOST0 22
SW0 23TG0 24
FAULT1 25
LOWDCR27
ITH028
GND
29FAULT0 26
C152922uF
R5692
R5820
Q37BSG0811ND
4
5
3
1
10
72
8
6
9
R57720K
C153122uF
R581715
D55
CMDSH-3
C655 22pF
C152822uF
Q38BSG0811ND
4
5
3
1
10
72
8
6
9
R573 0
Q39BSG0811ND
4
5
3
1
10
72
8
6
9
R5720
C1537100uF
TG5
BST5BG5
BST4
TG4
![Page 57: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/57.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VTT & 2V4 Power
connect GNDsthrough a single via
2.4V
CAD Notes:
DDR4 SODIMM VTT, VREF
5A
0.4AS10_Main_3V353,60,61 S10_2V4 63
S10_EN_2V446
IO_3V314,15,16,17,22,25,26,29,30,31,32,34,35,36,37,38,43,69,70
0V6_DDR4_DIMM_VTT 27
S10DDR_1V227,28,31,43,60,63,66
S10_2V4
GND_2V4
GND_2V4
S10DDR_1V2
IO_3V3
0V6_DDR4_DIMM_VREF 0V6_DDR4_DIMM_VTT
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
57 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
57 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
57 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R592 10.0K
U58
TPS51200
VIN10EN7PGOOD9
REFOUT6
GND_
PAD
11PG
ND4
GND
8
VLDOIN 2REFIN 1
VO 3VOSNS 5
TP137
C6642.2uF
R9130R590DNI
R59410.0K
C67610uF
C66510uF
C67410uF
R58810.0K
C6720.1uF
C66910uF
U57
EP5348UI
NC(SW
)01
NC(SW
)113
NC(SW
)214
NC0
3
PGND 2
VFB 4
AGND 5
VOUT0 6VOUT1 7
NC1
8NC
29
ENABLE10
AVIN11PVIN12
TP138
R59310.0K
C6711.0nF
C6670.1uF
C6704.7uF
C67710uF
C6662.2uF
R59166.5K
C67510uF
C6635pF
TP139
TP136
C67310uF
R589200k
C66810uF
![Page 58: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/58.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
4.5A
18A
I2C ADDRESS:b'1000010'
Need be open-drain output
12V to VCCERAM & VCCHPS
6A0.95V
0.9V
0.95V
0.9V
S10_12V30,53,54,55,56,59,62
S10_HPS_EN 46
PMbus_SDA_3V3 29,38,50,54,59,62PMbus_SCL_3V3 29,38,50,54,59,62
PMbus_ALERTn 38,46,50,54,59,62
VCCHPSPgood 46
S10_HPS63
S10_VCCeram_EN 46
VCCeramgood 46
S10_VCCERAM 63,65
GND_SIGNALHPS
GND_SIGNALHPS
GND_SIGNALHPS
GND_SIGNALHPS
GND_SIGNALHPS
GND_SIGNALHPS
S10_12V
S10_VCCERAM
S10_12V
S10_HPS
GND_SIGNALHPS
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
58 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
58 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
58 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
TP53
C683100uF
R61310K
R6000
R616 DNI
R596
0
R605
10K
TP50
R601
10K
C694330uF6.3V
C68622uF
R6200
R6220
C68722uF
C692DNI
C681100uF
R609DNI
R604
DNI
C684
100uF
U59LTM4677
VOUT0_1A1VOUT0_2A2VOUT0_3A3
VOUT0_10D1
ISNS0b-E1
ISNS0b+F1
ISNS1
b-G1
ISNS1
b+H1
VOUT
1_1J1
VOUT
1_2J2
VOUT
1_3J3
VOUT
1_4K1
VOUT0_4B1VOUT0_5B2VOUT0_6B3
VOUT0_11D2
ISNS0a-E2
ISNS0a+F2
ISNS1
a-G2
ISNS1
a+H2
VOUT
1_5K2
VOUT
1_6K3
VOUT
1_7L1
VOUT
1_8L2
VOUT0_7C1VOUT0_8C2VOUT0_9C3
VOUT0_12D3
GND1
A4GN
D2A6
GND3
A7GN
D4A8
VOUT
1_9L3
VOUT
1_10
M1VO
UT1_1
1M2
VOUT
1_12
M3
GND5
A9GN
D6A1
0GN
D7B4
GND8
B5
ASEL G4
FSWPHCFG H4
GND9
B6GN
D10
B7GN
D11
B8GN
D12
B9
GPIO0 E4
GPIO1 F4
SNUB0A5
GND1
3C4
TSNS0bC5TSNS0aD5
ALERT E5
RUN0 F5
VOUT0CFG G5
VTRIM0CFG H5TS
NS1a
J5TS
NS1b
K5
GND1
4C6
SNUB
1M5
GND1
5C7
GND1
6C8
GND1
7C9
SDA D6SCL E6
RUN1 F6
VOUT1CFG G6
VTRIM1CFG H6
VDD25 J6
WP K6
GND1
8D4
GND2
0E3
GND2
1F3
GND2
2F1
0GN
D23
G3GN
D24
G10
SYNC E7
GND4
5M9
GND4
6M1
0
SHARE_CLK H7
VDD33 J7
GND2
5G1
1GN
D26
G12
GND3
9L8
GND3
8L7
GND4
0L9
GND2
7H3
COMP0bD8COMP0aE8
SGND
3F7
SGND
4F8
COMP
1aH8
COMP
1bJ8
GND2
8H1
0GN
D29
J4
GND4
4M8
VOSNS0+D9
VOSNS0-E9
INTVCC_1 F9INTVCC_2 G9
VOSN
S1H9
VORB
1J9
GND3
0J10
GND3
5L4
GND3
6L5
GND3
1K4
SW0B10
DNC2
E11
VORB0+D10
VORB0-E10
GND3
7L6
GND3
2K7
GND3
3K8
GND3
4K9
DNC1
C10
SW1
L10
GND4
1M4
VINH0_4B12 VINH0_3B11 VINH0_2A12 VINH0_1A11
DNC4
K10
VINL_2F12
GND4
2M6
DNC3
H11
VINH1
_1H1
2VIN
H1_2
J11VIN
H1_3
J12VIN
H1_4
K11
VINH0_9E12 VINH0_8D12 VINH0_7D11 VINH0_6C12 VINH0_5C11
VINL_1F11
GND4
3M7
VINH1
_5K1
2VIN
H1_6
L11VIN
H1_7
L12VIN
H1_8
M11
VINH1
_9M1
2
SGND
1G7
SGND
2G8
GND1
9D7
TP140
R619 1.65K
C696100uF
TP60
C6881800pF
C680330uF6.3V
TP52
R621 DNI
C691DNI
TP59
R606
DNI
R615 1.65K
TP47
C697100uF
TP58
R597
DNI
R6140
R59917.8K
C695100uF
R6100
TP141
R602
10K
C685DNI
D57SL03-GS08
C682100uF
C678100uF
TP56
TP48
R618 12.7K
TP49
TP57
TP54
R603
DNI
R607
10K
C679330uF6.3V
R595DNI
R612DNI
C693330uF6.3V
C689DNI
R608
10K
TP51
TP55
C6901800pF
D56SL03-GS08R61117.8K
R922
10K
R598 DNI
R617 1.65K
VDD25_VCCERAMHPS_Vsense+
HPS_Vsense-
VDD33_VCCERAM
HPS_COMP0
INTVCC_5V_VCCERAM
VCCERAM_COMP02
![Page 59: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/59.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
4.5A
18A 1.8V output
I2C ADDRESS:b'1000110'
Need be open-drain output
12V to VCCT & VCCPT
18A1.125V
1.799V
S10_12V30,53,54,55,56,58,62
S10_VCCPT29,63,66,68,70
S10_VCCT_EN 46
PMbus_SDA_3V3 29,38,50,54,58,62PMbus_SCL_3V3 29,38,50,54,58,62
PMbus_ALERTn 38,46,50,54,58,62
VCCTPgood 46
S10_VCCT63,66
S10_VCCPT_EN 46
VCCPTPgood 46
GND_SIGNALVCCT
GND_SIGNALVCCT
GND_SIGNALVCCT
GND_SIGNALVCCT
GND_SIGNALVCCT
GND_SIGNALVCCT
S10_12V
S10_VCCPT
S10_12V
S10_VCCT
GND_SIGNALVCCT
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
59 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
59 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
59 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R6480
D59SL03-GS08
R628
10K
R649 32.4K
R6360
R63917.8K
R6380
TP68
R6420
C716100uF
TP67
TP73
R796 5.23K
TP69
R637DNI
TP63
C7081800pF
R634
10KR6
3510K
TP62
R624
0
C70922uF
R640DNI
C699100uF
R64110K
C70622uF
C705DNI
R645 2.43K
TP142
C717100uF
D58SL03-GS08
C715100uF
TP64
TP66
R625
DNI
R647 5.23K
C700
100uF
U60LTM4677
VOUT0_1A1VOUT0_2A2VOUT0_3A3
VOUT0_10D1
ISNS0b-E1
ISNS0b+F1
ISNS1
b-G1
ISNS1
b+H1
VOUT
1_1J1
VOUT
1_2J2
VOUT
1_3J3
VOUT
1_4K1
VOUT0_4B1VOUT0_5B2VOUT0_6B3
VOUT0_11D2
ISNS0a-E2
ISNS0a+F2
ISNS1
a-G2
ISNS1
a+H2
VOUT
1_5K2
VOUT
1_6K3
VOUT
1_7L1
VOUT
1_8L2
VOUT0_7C1VOUT0_8C2VOUT0_9C3
VOUT0_12D3
GND1
A4GN
D2A6
GND3
A7GN
D4A8
VOUT
1_9L3
VOUT
1_10
M1VO
UT1_1
1M2
VOUT
1_12
M3
GND5
A9GN
D6A1
0GN
D7B4
GND8
B5
ASEL G4
FSWPHCFG H4
GND9
B6GN
D10
B7GN
D11
B8GN
D12
B9
GPIO0 E4
GPIO1 F4
SNUB0A5
GND1
3C4
TSNS0bC5TSNS0aD5
ALERT E5
RUN0 F5
VOUT0CFG G5
VTRIM0CFG H5TS
NS1a
J5TS
NS1b
K5
GND1
4C6
SNUB
1M5
GND1
5C7
GND1
6C8
GND1
7C9
SDA D6SCL E6
RUN1 F6
VOUT1CFG G6
VTRIM1CFG H6
VDD25 J6
WP K6
GND1
8D4
GND2
0E3
GND2
1F3
GND2
2F1
0GN
D23
G3GN
D24
G10
SYNC E7
GND4
5M9
GND4
6M1
0
SHARE_CLK H7
VDD33 J7
GND2
5G1
1GN
D26
G12
GND3
9L8
GND3
8L7
GND4
0L9
GND2
7H3
COMP0bD8COMP0aE8
SGND
3F7
SGND
4F8
COMP
1aH8
COMP
1bJ8
GND2
8H1
0GN
D29
J4
GND4
4M8
VOSNS0+D9
VOSNS0-E9
INTVCC_1 F9INTVCC_2 G9
VOSN
S1H9
VORB
1J9
GND3
0J10
GND3
5L4
GND3
6L5
GND3
1K4
SW0B10
DNC2
E11
VORB0+D10
VORB0-E10
GND3
7L6
GND3
2K7
GND3
3K8
GND3
4K9
DNC1
C10
SW1
L10
GND4
1M4
VINH0_4B12 VINH0_3B11 VINH0_2A12 VINH0_1A11
DNC4
K10
VINL_2F12
GND4
2M6
DNC3
H11
VINH1
_1H1
2VIN
H1_2
J11VIN
H1_3
J12VIN
H1_4
K11
VINH0_9E12 VINH0_8D12 VINH0_7D11 VINH0_6C12 VINH0_5C11
VINL_1F11
GND4
3M7
VINH1
_5K1
2VIN
H1_6
L11VIN
H1_7
L12VIN
H1_8
M11
VINH1
_9M1
2
SGND
1G7
SGND
2G8
GND1
9D7
C703100uF
R623DNIC702100uF
C714330uF6.3V
R630
DNI
C711DNI
C707DNI
R644 DNI
TP143
R6500
R626 DNI
TP74
C698100uF
R629
10K
R633
DNI
TP71
C7101800pF
R646 9.09K
R62717.8KTP65
TP70
R923
10K
TP61
R631
DNI
C704330uF6.3V
TP72
C701330uF6.3V
R632
10K
C712DNI
C713330uF6.3V
S10VCCT_SENSE+
S10VCCT_SENSE-
VCCTCOMP01
VCCPTCOMP02
![Page 60: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/60.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
12061206
0402
Connect the input and output caps to the GND plane through mulitple vias.(Please see the Gerber files.)X5R
X5R
X5R
0201X5R
1206 X5R
1206 X5R
A single through-hole viaconnects the AGNDpin to the GND plane.
4A
0402
0402 0402
0201Feedback network configured for 3.3Vin /1.0Vout 1.2V
10A
0402
3.3V to 1.2V Converter
1.2V output
S10_Main_3V3 53,57,61
S10DDR_1V227,28,31,43,57,63,66
S10_1V2SENSP46
IO_EN 46,61,68,69
1V2_Pgood 46
S10_1V2I_P46
S10_1V2I_N46
S10_Main_3V3S10_1V2
S10_Main_3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
60 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
60 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
60 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C723 47uF
TP79 R665191K
TP75
C720 47uFC721 47uF
R658100
R661 10K
C7251uF
TP76
R65710K
R659
0.00025
R662160k
R654
100k
R65649.9
R652 10K
R666976K
C72227pF
R655 DNIR6530
R6600
TP78
R663 10K
U61EN63A0QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC19
19
VOUT
20
VOUT
21
VOUT
22
VOUT
23
VOUT
24
VOUT
25
VOUT
26
VOUT
27
VOUT
28
NC29
29
NC(SW
)3030
NC(SW
)3131
PGND
32
PGND
33
PGND
34
PGND
35
PGND
36
PGND
37
S_IN 56
BGND 55
VDDB 54
NC53 53
NC52 52
PVIN 51
PVIN 50
PVIN 49
PVIN 48
PVIN 47
PVIN 46
PVIN 45
PVIN 44
PVIN 43
NC76
76
NC75
75
NC74
74
NC73
73
NC72
72
NC(SW
)7171
NC(SW
)7070
EN_P
B69
FQAD
J68
NC(XR
EF)
67
VSEN
SE66
SS65
EAOU
T64
VFB
63
M/S62
AGND
61
AVIN
60
ENAB
LE59
POK
58
PGND
38S_
OUT
57
PVIN 42
PVIN 41
PVIN 40
PVIN 39
NC1515
NC1616
NC1717
NC1818
GND_
PAD
77
R651
3.57k
R66412k
TP77
C724 47uF
C718 15nF
C726 47uF
C7190.22uF
S10_1V2OUT
PFEN
![Page 61: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/61.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1206
1206 1206
0402 0402
0201
0402
0402
VIN = 2.5 - 6.6VDC
Connect the input and output caps to the GND plane through mulitple vias.
A single through-holevia/test point connects AGND pin to the GND plane.
X5RX5R
X5R
0201X5R
0402
1206 X5R
0402
1.102V
1V2SET
1V5SET
1V35SET
3A1.5A
3.3V to HPS HILO VDD converter
HILOHPS_VDD26,63,66
HILOHPS_VDDPGood 46
IO_EN 46,60,68,69
S10_Main_3V3 53,57,60
HILOHPSSENSP46
HILOHPS_1V2_SETn26
HILOHPS_1V35_SETn26
HILOHPS_1V5_SETn26
S10_HPSVDDI_P46
S10_HPSVDDI_N46
HILOHPS_VDD
S10_Main_3V3
S10_Main_3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
61 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
61 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
61 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C732 22uF
C727 15nFR668 10K
R676 10K
R673
390K
R675 10K
R670 DNI
TP83
R669
976K
C7280.22uF
U62EN6360QI
NC11
NC22
NC33
NC44
NC55
NC66
NC77
NC88
NC99
NC1010
NC1111
NC1212
NC1313
NC1414
NC15
15
VOUT
16
VOUT
17
VOUT
18
VOUT
19
VOUT
20
VOUT
21
VOUT
22
VOUT
23
VOUT
24
NC25
25
NC(SW
)2626
NC(SW
)2727
PGND
28
PGND
29
PGND
30
PGND
31
PGND
32
PGND
33
S_IN 48
BGND 47
VDDB 46
NC45 45
NC44 44
PVIN 43
PVIN 42
PVIN 41
PVIN 40
PVIN 39
PVIN 38
PVIN 37
PVIN 36
PVIN 35
NC68
68
NC67
67
NC66
66
NC65
65
NC64
64
NC(SW
)6363
NC(SW
)6262
EN_P
B61
FQAD
J60
NC59
59
VSEN
SE58
SS57
EAOU
T56
VFB
55
M/S54
AGND
53
AVIN
52
ENAB
LE51
POK
50
PGND
34S_
OUT
49
GND_
PAD
69
TP85
R788
100k
TP81
C73022pF
R674
240K
R671
5.49kR6720
R6670
R683191K
C735 22uF
TP80
R68215k
TP84
C731 47uFR680160k
R6790
C734 47uFC7330.22uF
C7291uF
TP82
R677
0.001R678100
HILOHPS_VDDOUT
PIEN
![Page 62: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/62.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
4.5A
30A 1.125V output
I2C ADDRESS:b'1000011' Need be open-drain output
12V to VCCR Converter
1.125V
1.125V
S10_12V30,53,54,55,56,58,59
S10_VCCR 63,65
VCCRSENSE63
VCCR_GNDSENSE63
S10_VCCR_EN 46
PMbus_SDA_3V3 29,38,50,54,58,59PMbus_SCL_3V3 29,38,50,54,58,59
PMbus_ALERTn 38,46,50,54,58,59
VCCRPGOOD 46
GND_SIGNALVCCR
GND_SIGNALVCCR
GND_SIGNALVCCR
GND_SIGNALVCCR
GND_SIGNALVCCR
GND_SIGNALVCCR
S10_12V
S10_VCCR
S10_12V
S10_VCCR
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
62 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
62 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
62 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C748DNI
R7100
R692
10K
TP87
R6950
TP88
R690
DNI
R688
10K
C737100uF
R684DNI
R7110
R689
10K
R706 9.09KC753100uF
R686
DNI
TP90
R69817.8K
R709 9.09K
U63LTM4677
VOUT0_1A1VOUT0_2A2VOUT0_3A3
VOUT0_10D1
ISNS0b-E1
ISNS0b+F1
ISNS1
b-G1
ISNS1
b+H1
VOUT
1_1J1
VOUT
1_2J2
VOUT
1_3J3
VOUT
1_4K1
VOUT0_4B1VOUT0_5B2VOUT0_6B3
VOUT0_11D2
ISNS0a-E2
ISNS0a+F2
ISNS1
a-G2
ISNS1
a+H2
VOUT
1_5K2
VOUT
1_6K3
VOUT
1_7L1
VOUT
1_8L2
VOUT0_7C1VOUT0_8C2VOUT0_9C3
VOUT0_12D3
GND1
A4GN
D2A6
GND3
A7GN
D4A8
VOUT
1_9L3
VOUT
1_10
M1VO
UT1_1
1M2
VOUT
1_12
M3
GND5
A9GN
D6A1
0GN
D7B4
GND8
B5
ASEL G4
FSWPHCFG H4
GND9
B6GN
D10
B7GN
D11
B8GN
D12
B9
GPIO0 E4
GPIO1 F4
SNUB0A5
GND1
3C4
TSNS0bC5TSNS0aD5
ALERT E5
RUN0 F5
VOUT0CFG G5
VTRIM0CFG H5TS
NS1a
J5TS
NS1b
K5
GND1
4C6
SNUB
1M5
GND1
5C7
GND1
6C8
GND1
7C9
SDA D6SCL E6
RUN1 F6
VOUT1CFG G6
VTRIM1CFG H6
VDD25 J6
WP K6
GND1
8D4
GND2
0E3
GND2
1F3
GND2
2F1
0GN
D23
G3GN
D24
G10
SYNC E7
GND4
5M9
GND4
6M1
0
SHARE_CLK H7
VDD33 J7
GND2
5G1
1GN
D26
G12
GND3
9L8
GND3
8L7
GND4
0L9
GND2
7H3
COMP0bD8COMP0aE8
SGND
3F7
SGND
4F8
COMP
1aH8
COMP
1bJ8
GND2
8H1
0GN
D29
J4
GND4
4M8
VOSNS0+D9
VOSNS0-E9
INTVCC_1 F9INTVCC_2 G9
VOSN
S1H9
VORB
1J9
GND3
0J10
GND3
5L4
GND3
6L5
GND3
1K4
SW0B10
DNC2
E11
VORB0+D10
VORB0-E10
GND3
7L6
GND3
2K7
GND3
3K8
GND3
4K9
DNC1
C10
SW1
L10
GND4
1M4
VINH0_4B12 VINH0_3B11 VINH0_2A12 VINH0_1A11
DNC4
K10
VINL_2F12
GND4
2M6
DNC3
H11
VINH1
_1H1
2VIN
H1_2
J11VIN
H1_3
J12VIN
H1_4
K11
VINH0_9E12 VINH0_8D12 VINH0_7D11 VINH0_6C12 VINH0_5C11
VINL_1F11
GND4
3M7
VINH1
_5K1
2VIN
H1_6
L11VIN
H1_7
L12VIN
H1_8
M11
VINH1
_9M1
2
SGND
1G7
SGND
2G8
GND1
9D7
TP92
C738
100uF
C741100uF
C74522uF
TP94
R685
0
C747DNI
C739330uF6.3V
C749330uF6.3V
R693
DNI
C742100uF
C74422uF
R70010K
TP99
TP96
R6970
TP144
TP93
D60SL03-GS08
TP89
R795 2.43K
C740330uF6.3V
R691
DNI
TP86
TP95
R702DNI
R705 2.43K
TP97
R704 DNI
R694
10K
C750330uF6.3V
R699DNI
R7010
R707 2.43K
C743DNI
C736100uF
C751100uF
R687 DNI
C7461800pF
TP98
C752100uF
R708DNI
TP91
R696DNI
VCCR_SENSE+
VCCR_SENSE-
VCCRCOMP01
![Page 63: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/63.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCC_SENSE 54
VSS_SENSE 54
S10_2V4 57
S10_VCCR 62,65
S10_VCCT 59,66
S10_VCCERAM 58,65S10_VCC 54,55,56,65,66
S10_HPS 58
S10_VCCAPLL 64,65
S10_VCCPT 29,59,66,68,70HILOHPS_VDD 26,61,66
S10DDR_1V2 27,28,31,43,57,60,66
IO_1V812,21,22,25,29,30,32,33,34,36,39,40,43,64,65,66,68
HPS_PLLDIG 64
S10_VCCHL 66
S10_VCCHR 66
VCCRSENSE 62
VCCR_GNDSENSE62
S10_HPS_VCCL 66
S10_VCC S10_VCC
S10_VCCHL
S10_VCCR
S10_VCCT
S10_VCCERAM
S10_VCCERAM
S10_VCCAPLL
S10_VCCPLLDIG_SDM
S10_VCCR
S10_VCCT
S10_VCCERAMS10_VCC
S10_VCCPTHILOHPS_VDD
HILOHPS_VDD
S10DDR_1V2
HILOHPS_VDD
S10_VCCPT
IO_1V8
IO_1V8 IO_1V8
S10_VCCPT
S10_VCCHR
S10_VCCPT
S10_HPS_VCCL
S10DDR_1V2
S10_VCC
S10_HPS_VCCL
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
63 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
63 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
63 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
FB5220ohm, 2.0A
1 2R717 240
FB6
10A, RDC 4mOhm
R716 240
R955
DNI
R713 0
R721DNIC7610.47uF
1SX280LU3F50E3VGS1
U15MVCCY34VCCY33VCCY32VCCY31VCCY30VCCY29VCCY28VCCY27VCCY26VCCY25VCCY24VCCY23VCCY22VCCY21VCCY20VCCY19VCCY18VCCY17VCCY16VCCAM33VCCAM32VCCAM31VCCAM30VCCAM29VCCAM28VCCAM26VCCAM25VCCAM24VCCAM19VCCAM18VCCAM17VCCAL32VCCAL30VCCAL29VCCAL27VCCAL26VCCAL25VCCAL24VCCAL23VCCAL22VCCAL21
VCCP AL19
VCCAL17VCCAK34VCCAK33VCCAK32
VCCP AK31
VCCAK29VCCAK28VCCAK27VCCAK26VCCAK24VCCAK23VCCAK22VCCAK21
VCCP AK19VCCP AK18
VCCAK17VCCAK16VCCAJ35
VCCP AJ31VCCP AJ30
VCCAJ29VCCAJ28VCCAJ26VCCAJ25VCCAJ24VCCAJ23VCCAJ21VCCAJ20VCCAJ19
VCCP AJ18
VCCAJ16VCCAJ15
VCCAH21 VCCAH27 VCCAH28
VCCP AH30VCCP AH31
VCCAH15
VCC AG28VCC AG23VCC AG19VCC AG15VCC AF35VCC AF32VCC AF31VCC AF30VCC AF29VCC AF27VCC AF22VCC AF21VCC AF20VCC AF19VCC AE34VCC AE31VCC AE27VCC AE23VCC AE19VCC AD33VCC AD31VCC AD30VCC AD29VCC AD28VCC AD26VCC AD25VCC AD24VCC AD23VCC AD21VCC AD20VCC AD19VCC AD18VCC AC32VCC AC31VCC AC30VCC AC28VCC AC27VCC AC26VCC AC25VCC AC23VCC AC22VCC AC21VCC AC20VCC AC18VCC AC17VCC AC16VCC AB33VCC AB32
VCCP AB30
VCC AB29VCC AB28VCC AB27VCC AB25VCC AB24VCC AB23VCC AB22
VCCP AB20VCCP AB19VCCP AB18
VCC AB17VCC AA35VCC AA34
VCCP AA32VCCP AA31VCCP AA30
VCC AA29VCC AA27VCC AA26VCC AA25VCC AA24VCC AA22VCC AA21
VCCP AA20
VCC AA17VCC AA16VCC AA15
VCCP AA19
VCCAH22
VCCAH25
VCCAH18
VCCAH23
VCCAH20 VCCAH26
VCCL_HPSL29 VCCL_HPSL30 VCCL_HPSM28 VCCL_HPSM29 VCCL_HPSM30VCCW31 VCCW19 VCCAN30 VCCAL20
R719 0
FB4120ohm, 800mA
1 2
R954
0.00025
R7200
C7560.47uF
FB7
10A, RDC 4mOhm
1SX280LU3F50E3VGS1
U15N
VREFB3JN0 U16
VCCIO2ABC29VCCIO2ABB31VCCIO2AAY30
VCCIO2BAY35VCCIO2BAV34VCCIO2BAT33
VCCIO2CAR35VCCIO2CAP37VCCIO2CAN34
VCCIO2FAU26VCCIO2FAT28VCCIO2FAP27
VCCIO2LV29VCCIO2LU26VCCIO2LT28
VCCIO2MT33VCCIO2MR35VCCIO2MN34
VCCIO2NL33VCCIO2NJ32VCCIO2NH34
VCCIO3ABB16VCCIO3AAY15VCCIO3AAW17
VCCIO3BAU16VCCIO3BAT13VCCIO3BAR15
VCCIO3CAU21VCCIO3CAR20VCCIO3CAP22
VCCIO3IU21VCCIO3IT23VCCIO3IP22
VCCIO3V AG14VCCIO3V AF14
VCCIO3V AF36VCCIO3V AG36
VCCIO_SDM AU23
VREFB2AN0 AV31
VREFB2BN0 AT31
VREFB2CN0 AN32
VREFB2FN0 AR29
VREFB2LN0 V31
VREFB2MN0 P31
VREFB2NN0 M32
VREFB3AN0 AU19
VREFB3BN0 AU18
VREFB3CN0 AP19
VREFB3IN0 V20
VREFB3KN0 P19
VCCIO3JT18VCCIO3JR15VCCIO3JN14
VCCIO3KM16VCCIO3KK15VCCIO3KJ17
VCCIO3LK20VCCIO3LH19VCCIO3LG21
VREFB3LN0 M19
VCCLSENSE AG24GNDSENSE AF24
C7540.1uF
J27
CON2
12
1SX280LU3F50E3VGS1
U15L
VCCA_PLL AF26VCCA_PLL AF25
VCCH_GXBR AN11
VCCPT AE22
VCCH_GXBL AN39VCCH_GXBL AJ39VCCH_GXBL AJ36VCCH_GXBL U39VCCH_GXBL N39VCCH_GXBL AA39
VCCH_GXBR AJ11VCCH_GXBR U11VCCH_GXBR N11VCCH_GXBR AA11VCCH_GXBL AB38VCCH_GXBL AH38
VCCR_GXBL1CAR41VCCR_GXBL1CAR40VCCR_GXBL1CAR39VCCR_GXBL1DAL41VCCR_GXBL1DAL40VCCR_GXBL1DAL39VCCR_GXBL1EAL38VCCR_GXBL1EAL37VCCR_GXBL1EAL36VCCR_GXBL1FAG41VCCR_GXBL1FAG40VCCR_GXBL1FAG39VCCR_GXBL1KAC41VCCR_GXBL1KAC40VCCR_GXBL1KAC39VCCR_GXBL1LW38VCCR_GXBL1LW37VCCR_GXBL1LW36VCCR_GXBL1MW41VCCR_GXBL1MW40VCCR_GXBL1MW39VCCR_GXBL1NR41VCCR_GXBL1NR40VCCR_GXBL1NR39
VCCR_GXBR4CAR9VCCR_GXBR4CAR11VCCR_GXBR4CAR10VCCR_GXBR4DAL9VCCR_GXBR4DAL11VCCR_GXBR4DAL10VCCR_GXBR4EAL14VCCR_GXBR4EAL13VCCR_GXBR4EAL12VCCR_GXBR4FAG9VCCR_GXBR4FAG11VCCR_GXBR4FAG10VCCR_GXBR4KAC9VCCR_GXBR4KAC11VCCR_GXBR4KAC10VCCR_GXBR4LW14VCCR_GXBR4LW13VCCR_GXBR4LW12VCCR_GXBR4MW9VCCR_GXBR4MW11VCCR_GXBR4MW10VCCR_GXBR4NR9VCCR_GXBR4NR11VCCR_GXBR4NR10
VCCERAM Y15VCCERAM W35VCCERAM W34VCCERAM W33VCCERAM W30VCCERAM W27VCCERAM W23VCCERAM W21VCCERAM W16VCCERAM W15VCCERAM V35VCCERAM V34VCCERAM V16VCCERAM V15VCCERAM V14VCCERAM U35VCCERAM AN35VCCERAM AN31VCCERAM AN16VCCERAM AN15VCCERAM AM35VCCERAM AM34VCCERAM AM27VCCERAM AM23VCCERAM AM20VCCERAM AM15VCCERAM AL35VCCERAM AL34VCCERAM AL16VCCERAM AL15VCCERAM AK35VCCERAM AK15
VCCT_GXBL1CAN41VCCT_GXBL1CAN40
VCCT_GXBL1DAJ41 VCCT_GXBL1DAJ40
VCCT_GXBL1EAE41 VCCT_GXBL1EAE40
VCCT_GXBL1FAJ38 VCCT_GXBL1FAJ37
VCCT_GXBL1KAA41 VCCT_GXBL1KAA40
VCCT_GXBL1LU38 VCCT_GXBL1LU37
VCCT_GXBL1MU41 VCCT_GXBL1MU40
VCCT_GXBL1NN41 VCCT_GXBL1NN40
VCCT_GXBR4CAN9VCCT_GXBR4CAN10
VCCT_GXBR4DAJ9 VCCT_GXBR4DAJ10
VCCT_GXBR4EAE9 VCCT_GXBR4EAE10
VCCT_GXBR4FAJ13 VCCT_GXBR4FAJ12
VCCT_GXBR4KAA9 VCCT_GXBR4KAA10
VCCT_GXBR4LU13 VCCT_GXBR4LU12
VCCT_GXBR4MU9 VCCT_GXBR4MU10
VCCT_GXBR4NN9 VCCT_GXBR4NN10
VCCPT AE21
VCCPLLDIG_SDM AT22
VCCH_GXBR AJ14
VCCH_GXBR T12VCCH_GXBR AH12
VCCPLL_SDM AU22
VCCADC AY23
VCCPT AG33VCCPT AG32VCCPT AG30VCCPT AG29VCCPT AG27VCCPT AG25VCCPT AG22VCCPT AG20VCCPT AG18VCCPT AG17VCCPT AE33VCCPT AE32VCCPT AE29VCCPT AE28VCCPT AE26VCCPT AE24
VCCPT AE18VCCPT AE17
VCCBAT AV22VCCFUSEWR_SDM AV23
R715 240
C7620.47uF
R714 240
R712 0
C75510uF
C7600.1uF
FB8220ohm, 2.0A1 2
R718 0
C75910uF
C7570.1uFC758
0.47uF
VCCLSENSEGNDSENSE
VSS_SENSEVCC_SENSE
![Page 64: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/64.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S10 GNDHPS_PLLDIG 63
S10_VCCAPLL 63,65
IO_1V8 12,21,22,25,29,30,32,33,34,36,39,40,43,63,65,66,68
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
64 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
64 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
64 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
1SX280LU3F50E3VGS1
U15SGNDAB47GNDAB46GNDAB43GNDAB42GNDAB4GNDAB39GNDAB37GNDAB31GNDAB3GNDAB26GNDAB21GNDAB16GNDAE13GNDAE12GNDAB11GNDAA6GNDAA5GNDAA49GNDAA48GNDAA45GNDAA44GNDAA38GNDAA37GNDAA36GNDAA33GNDAA28GNDAA23
GND AA2GND AA18GND AA14GND AA13GND AA12GND AA1GND A9GND A6GND A5GND A47GND A46GND A45GND A44GND A41GND A40GND A4GND A39GND A33GND A3GND A28GND A23GND A2GND A18GND A13GND A11GND A10GND BH1
1SX280LU3F50E3VGS1
U15OVCCIO_HPSN28VCCPLLDIG_HPSP28VCCPLL_HPSR28GNDY8GNDY7GNDY47GNDY46GNDY43GNDY42GNDY4GNDY39GNDY36GNDY35GNDY3GNDY14GNDY11GNDW6GNDW5GNDW49GNDW48GNDW45GNDW44GNDW32GNDW29GNDW28GNDW26GNDW25GNDW24GNDW22GNDW20GNDW2GNDW17GNDW1GNDV8GNDV7GNDV47GNDV46GNDV43GNDV42GNDV4GNDV39GNDV36GNDV33GNDV3GNDV19GNDV11GNDU6GNDU5GNDU49GNDU48GNDU45GNDU44GNDU36GNDU31GNDU2GNDU15GNDU14GNDU1GNDT8GNDT7GNDT47GNDT46GNDT43GNDT42GNDT4GNDT39GNDT38GNDT37GNDT36GNDT3GNDT14GNDT13GNDT11GNDR6GNDR5GNDR49GNDR48
GND R30GND R25GND R20GND R2GND R12GND R1GND P8GND P7GND P47GND P46GND P43GND P42GND P4GND P39GND P32GND P3GND P27GND P17GND P11GND N6GND N5GND N49GND N48GND N45GND N44GND N38GND N29GND N24GND N2GND N19GND N12GND N1GND M9GND M8GND M7GND M47GND M46GND M43GND M42GND M41GND M40GND M4GND M39GND M36GND M31GND M3GND M26GND M21GND M11GND M10GND L9GND L6GND L5GND L49GND L48GND L45GND L44GND L41GND L38GND L28GND L23GND L2GND L18GND L13GND L1GND K9GND K8GND K7GND K47GND K46GND K43GND K42GND K41GND K4GND K35GND K30GND K3
GNDR45GNDR44GNDR38
GND K25GND J9GND J6
1SX280LU3F50E3VGS1
U15RGNDAP46GNDAP43GNDAP42GNDAP4GNDAP39GNDAP38GNDAP32GNDAP3GNDAP17GNDAP11GNDAN6GNDAN5GNDAN49GNDAN48GNDAN45GNDAN44GNDAN38GNDAN37GNDAN36GNDAN29GNDAN24GNDAN2GNDAN19GNDAN14GNDAN13GNDAN12GNDAN1GNDAM8GNDAM7GNDAM47GNDAM46GNDAM43GNDAM42GNDAM4GNDAM39GNDAM36GNDAM3GNDAM22GNDAM21GNDAM16GNDAM14GNDAM11GNDAL6GNDAL5GNDAL49GNDAL48GNDAL45GNDAL44GNDAL33GNDAL31GNDAL28GNDAL2GNDAL18GNDAL1GNDAK8GNDAK7GNDAK47GNDAK46GNDAK43GNDAK42GNDAK4GNDAK39GNDAK36GNDAK30GNDAK3GNDAK25GNDAK20GNDAK14GNDAK11GNDAJ6GNDAJ5GNDAJ49GNDAJ48GNDAJ45GNDAJ44GNDAJ32GNDAJ27GNDAJ22GNDAJ2GNDAJ17GNDAJ1GNDAH8GNDAH7GNDAH47GNDAH46GNDAH43GNDAH42
GND AH36GND AH35GND AH34GND AH3GND AH29GND AH24GND AH19GND AH14GND AH13GND AH11GND AG6GND AG5GND AG49GND AG48GND AG45GND AG44GND AG31GND AG26GND AG21GND AG2GND AG16GND AG1GND AF8GND AF7GND AF47GND AF46GND AF43GND AF42GND AF4GND AF39GND AG38GND AF33GND AF3GND AF28GND AF23GND AF18GND AG12GND AF11GND AE6GND AE5GND AE49GND AE48GND AE45GND AE44GND AE39GND AE38GND AE35GND AE30GND AE25GND AE20GND AE2GND AE15GND AE11GND AE1GND AD8GND AD7GND AD47GND AD46GND AD43GND AD42GND AD4GND AD39GND AC38GND AD37GND AD32GND AD3GND AD27GND AD22GND AD17GND AD13GND AC12GND AD11GND AC6GND AC5GND AC49GND AC48GND AC45GND AC44GND AC37GND AC34GND AC29GND AC24GND AC2GND AC19GND AC13GND AC1GND AB8GNDAH4
GNDAH39 GND AB7
GND AH37
1SX280LU3F50E3VGS1
U15QGNDBE9GNDBE6GNDBE5GNDBE49GNDBE48GNDBE45GNDBE44GNDBE41GNDBE35GNDBE30GNDBE25GNDBE20GNDBE2GNDBE15GNDBE1GNDBD9GNDBD8GNDBD7GNDBD47GNDBD46GNDBD43GNDBD42GNDBD41GNDBD4GNDBD37GNDBD32GNDBD3GNDBD27GNDBD22GNDBD17GNDBD12GNDBC9GNDBC6GNDBC5GNDBC49GNDBC48GNDBC45GNDBC44GNDBC41GNDBC39GNDBC34GNDBC24GNDBC2GNDBC19GNDBC14GNDBC1GNDBB9GNDBB8GNDBB7GNDBB47GNDBB46GNDBB43GNDBB42GNDBB41GNDBB4GNDBB36GNDBB3GNDBB26GNDBB21GNDBB11GNDBA9GNDBA6GNDBA5GNDBA49GNDBA48GNDBA45GNDBA44GNDBA41GNDBA38GNDBA33GNDBA28GNDBA23GNDBA2GNDBA18GNDBA13GNDBA1GNDB8GNDB7GNDB49GNDB48GNDB47GNDB46GNDB43GNDB42GNDB4GNDB39GNDB36
GND B21GND B2GND B16GND B11GND AY9GND AY8GND AY7GND AY47GND AY46GND AY43GND AY42GND AY41GND AY4GND AY3GND AY25GND AY20GND AY10GND AW9GND AW6GND AW5GND AW49GND AW48GND AW45GND AW44GND AW41GND AW37GND AW32GND AW27GND AW22GND AW2GND AW12GND AW1GND AV9GND AV8GND AV7GND AV47GND AV46GND AV43GND AV42GND AV41GND AV4GND AV39GND AV3GND AV29GND AV24GND AV19GND AV14GND AU9GND AU6GND AU5GND AU49GND AU48GND AU45GND AU44GND AU41GND AU40GND AU39GND AU36GND AU31GND AU2GND AU11GND AU10GND AU1GND AT8GND AT7GND AT47GND AT46GND AT43GND AT42GND AT4GND AT39GND AT3GND AT23GND AT18GND AT11GND AR6GND AR5GND AR49GND AR48GND AR45GND AR44GND AR38GND AR30GND AR25GND AR2GND AR12GND AR1
GNDB31GNDB3GNDB26
GND AP8GND AP7GND AP47
1SX280LU3F50E3VGS1
U15PGNDJ5GNDJ49GNDJ48GNDJ45GNDJ44GNDJ41GNDJ37GNDJ27GNDJ22GNDJ2GNDJ12GNDJ1GNDH9GNDH8GNDH7GNDH47GNDH46GNDH43GNDH42GNDH41GNDH4GNDH39GNDH3GNDH29GNDH24GNDH14GNDG9GNDG6GNDG5GNDG49GNDG48GNDG45GNDG44GNDG41GNDG36GNDG31GNDG26GNDG2GNDG16GNDG11GNDG1GNDF9GNDF8GNDF7GNDF47GNDF46GNDF43GNDF42GNDF41GNDF4GNDF38GNDF33GNDF3GNDF28GNDF23GNDF18GNDF13GNDE9GNDE6GNDE5GNDE49GNDE48GNDE45GNDE44GNDE41GNDE35GNDE30GNDE25GNDE20GNDE2GNDE15GNDE1GNDD9GNDD8GNDD7GNDD47GNDD46GNDD43GNDD42GNDD41GNDD4GNDD37GNDD32GNDD3GNDD27GNDD22GNDD17
GND C5GND C49GND C48GND C45GND C44GND C41GND C40GND C39GND C34GND C29GND C24GND C2GND C19GND C14GND C11GND C10GND C1GND BJ9GND BJ6GND BJ47GND BJ44GND BJ41GND BJ40GND BJ39GND BJ37GND BJ32GND BJ3GND BJ27GND BJ22GND BJ17GND BJ12GND BJ11GND BJ10GND BH8GND BH7GND BH6GND BH5GND BH49GND BH48GND BH47GND BH46GND BH45GND BH44GND BH43GND BH42GND BH4GND BH39GND BH34GND BH3GND BH29GND BH24GND BH2GND BH19GND BH14GND BH11GND BG9GND BG6GND BG5GND BG49GND BG48GND BG45GND BG44GND BG41GND BG40GND BG39GND BG36GND BG31GND BG26GND BG21GND BG2GND BG16GND BG11GND BG10GND BG1GND BF9GND BF8GND BF7GND BF47GND BF46GND BF43GND BF42GND BF41GND BF4GND BF38GND BF33GND BF3GND BF28
GNDD12GNDC9GNDC6
GND BF23GND BF18GND BF13
![Page 65: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/65.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Decoupling 1S10_VCC 54,55,56,63,66
S10_VCCR 62,63
S10_VCCERAM 58,63
S10_VCCAPLL 63,64
IO_1V8 12,21,22,25,29,30,32,33,34,36,39,40,43,63,64,66,68
S10_VCC
S10_VCCAPLL
IO_1V8
S10_VCC
S10_VCC
S10_VCCR
S10_VCCR
S10_VCCR
S10_VCCERAM
S10_VCCERAM
Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
65 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
65 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
65 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C10004.7uf
C15454.7uF
C9914.7uf
C11644.7uF
C11364.7uF
C111222nf
C8540.1uF
C8594.7uF
C9974.7uf
C8854.7uF
C112722nf
C8154.7uF
C115422nf
C7854.7uF
C8944.7uF C901
4.7uF
C1557100uF
C8490.1uF
C8694.7uF
C9324.7uF
C11384.7uF
C9194.7uF
C8384.7uF
C9224.7uF
C112122nf
C7664.7uF
C10064.7uf C1093
4.7uF
C9114.7uF
C8934.7uF
C7884.7uF
C114722nf
C8644.7uF
C1555100uF
C7654.7uF
C162647uF
C8574.7uF
C8060.1uF
C8000.1uF
C9554.7uf
C15434.7uF
C8234.7uF
C8294.7uF
C9334.7uF
C113222nf
C7784.7uF
C9704.7uf
C163047uF
C8274.7uF
C8954.7uF
C10144.7uf
C8404.7uF
C8550.1uF
C111722nf
C10894.7uF
C8344.7uF
C8864.7uF
C8284.7uF
C115222nf
C7754.7uF
C9174.7uF
C9544.7uf
C11394.7uF
C8454.7uF
C162847uF
C9534.7uf
C7834.7uF
C8914.7uF
C8460.1uF
C10034.7uf
C951100uF
C10874.7uF
C112022nf
C9864.7uf
C10074.7uf
C10124.7uf
C8704.7uF
C109722nf
C10084.7uf
C110522nf
C7944.7uF
C163747uF
C9424.7uF
C8424.7uF
C11714.7uF
C7914.7uF
C110622nf
C8924.7uF C900
4.7uF
C7990.1uF
C111022nf
C10814.7uF
C10014.7uf
C110022nf
C9054.7uF
C163547uF
C111122nf
C8530.1uF
C8394.7uF
C8804.7uF
C8244.7uF
C9364.7uF
C8254.7uF
C7954.7uF
C8024.7uF
C8324.7uF
C9714.7uf
C8354.7uF
C8010.1uF
C9044.7uF
C8904.7uF
C7644.7uF
C9154.7uF
C11334.7uF
C163347uF
C112622nf
C11424.7uF
C11404.7uF
C162547uF
C8314.7uF
C8654.7uF
C9404.7uF
C10024.7uf
C8894.7uF C898
4.7uF
C8214.7uF
C8510.1uF
C1076100uF
C10864.7uF
C1553100uF
C9624.7uf
C163147uF
C7824.7uF
C9034.7uF
C8084.7uF
C110722nf
C8364.7uF
C7704.7uF
C9634.7uf
C9124.7uF
C10834.7uF
C9444.7uF
C9614.7uf
C9294.7uF
C9214.7uF
C8470.1uF
C111922nf
C115122nf
C8684.7uF
C11374.7uF
C113022nf
C950100uF
C8774.7uF
C114922nf
C7674.7uF
C109822nf
C9064.7uFC923
4.7uF
C11444.7uF
C7984.7uF
C7874.7uF
C9354.7uF
C10134.7uf
C15464.7uF
C109622nf
C10094.7uf
C9204.7uF
C952100uF
C9964.7uf
C113122nf
C8444.7uF
C9694.7uf
C9924.7uf
C109422nf
C8224.7uF
C7634.7uF
C1558100uF
C7684.7uF
C7814.7uF
C15444.7uF
C109522nf
C8114.7uF
C10914.7uF
C11664.7uF
C7694.7uF
C8974.7uF
C8034.7uF
C9674.7uf
C8164.7uF
C9164.7uF
C11344.7uF
C162447uF
C11654.7uF
C112322nf
C9304.7uF
C8434.7uF
C8634.7uF
C9094.7uF
C1556100uF
C7804.7uF
C9384.7uF
C109922nf
C11704.7uF
C8194.7uF
C9314.7uF
C9074.7uF
C112822nf
C8204.7uF
C10824.7uF
C9264.7uF
C10104.7uf
C9934.7uf
C8264.7uF
C8144.7uF
C8964.7uF
C9994.7uf
C8604.7uF
C7724.7uF
C9254.7uF
C8824.7uF
C110822nf
C9944.7uf
C8044.7uF
C112422nf
C7764.7uF
C15424.7uF
C8834.7uF
C15474.7uF
C7934.7uF
C9394.7uF
C114822nf
C9594.7uf
C162947uF
C10924.7uF
C9434.7uFC934
4.7uF
C111322nf
C8814.7uF
C9584.7uf
C11354.7uF
C9724.7uf
C10844.7uF
C7974.7uF
C8754.7uF
C8994.7uF
C8480.1uF
C163847uF
C11724.7uF
C8884.7uF
C10054.7uf
C9644.7uf
C162747uF
C8874.7uF
C8074.7uF
C111522nf
C8674.7uF
C110322nf
C8624.7uF
C9684.7uf
C8124.7uF
C163647uF
C110922nf
C8764.7uF
C9244.7uF
C8184.7uF
C1077100uF
C9144.7uF
C111422nf
C10904.7uF
C9084.7uF
C11454.7uF
C16540.1uF
C9414.7uF
C114622nf
C8584.7uF
C9954.7uf
C162347uF
C9664.7uf
C9274.7uF
C8844.7uF
C163447uF
C7964.7uF
C8520.1uF
C112922nf
C7734.7uF
C9104.7uF
C8744.7uF
C11434.7uF
C111822nf
C110122nf
C8304.7uF
C9134.7uF
C9604.7uf
C8374.7uF
C8414.7uF
C7864.7uF
C8784.7uF
C110222nf
C9024.7uF
C1554100uF
C9374.7uF
C163247uF
C8714.7uF
C11414.7uF
C9984.7uf
C8614.7uF
C7904.7uF
C112522nf
C110422nf
C9564.7uf
C115022nf
C9574.7uf
C8094.7uF
C8664.7uF
C8134.7uF
C10114.7uf
C7744.7uF
C9654.7uf
C8734.7uF
C115322nf
C10884.7uF
C8334.7uF
C7794.7uF
C9884.7uf
C9454.7uF
C112222nf
C8104.7uF
C7774.7uF
C8500.1uF
C7844.7uF
C8724.7uF
C9894.7uf
C9184.7uF
C111622nf
C9874.7uf
C9904.7uf
C7714.7uF
C8054.7uF
C8560.1uF
C7924.7uF
C8794.7uF
C10854.7uF
C8174.7uF
C7894.7uF
C9284.7uF
![Page 66: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/66.jpg)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Decoupling 2
0402 0201
0201
S10_VCCPT 29,59,63,68,70
S10_VCCT 59,63 S10_VCC 54,55,56,63,65
S10_VCCHL 63 S10_VCCHR 63
IO_1V8 12,21,22,25,29,30,32,33,34,36,39,40,43,63,64,65,68
HILOHPS_VDD 26,61,63
S10DDR_1V2 27,28,31,43,57,60,63
S10_HPS_VCCL 63
S10_VCCT
IO_1V8
S10_VCC
S10_VCCPT
S10_VCCHLS10_VCCHR
HILOHPS_VDD
S10DDR_1V2
S10_HPS_VCCL
Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
66 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
66 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
66 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C12404.7uf
C130722nf
C15494.7uf
C12294.7uf
C12181000uF
C12241000uFC1230
4.7uf
C14514.7uf
C127622nf
C13840.1uF
C14384.7uf
C15524.7uf
C130522nf
C14454.7uf
C13974.7uf
C12201000uF
C14374.7uf
C12374.7uf
C14474.7uf
C1315100uF
C130322nf
C13850.1uF C1395
4.7uf
C12221000uF
C12191000uF
C14154.7uf
C130122nf
C13614.7uf
C13750.1uF
C14544.7uf
C13734.7uf
C13790.1uF
C12334.7uf
C14464.7uf
C14114.7uf
C12131000uF
C129922nf
C13594.7uf
C14600.1uF
C14444.7uf
C12364.7uf
C14364.7uf
C14094.7uf
C13780.1uF
C13574.7uf
C13384.7uf
C13364.7uf
C13714.7uf
C13820.1uF
C14014.7uf
C13554.7uf
C12344.7uf
C13870.1uF
C12384.7uf
C14580.1uF
C12354.7uf
C16530.1uF
C12324.7uf
C14554.7uf
C12284.7uf
C131022nf
C12271000uF
C12261000uF
C14434.7uf
C12211000uF
C1417100uF
C130822nf
C15504.7uf
C13374.7uf
C14534.7uf
C14524.7uf
C14404.7uf
C13760.1uF
C15484.7uf
C12314.7uf
C130622nf
C13740.1uF
C12161000uF
C12251000uF
C13984.7uf
C14424.7uf
C130422nf
C127722nf
C13964.7uf
C13394.7uf
C130222nf
C12151000uF
C13860.1uF C1380
4.7uf
C13830.1uF
C14144.7uf
C130022nf
C13604.7uf
C12434.7uf
C13810.1uF
C13344.7uf
C14614.7uf
C13880.1uF
C14104.7uf
C129822nf
C13584.7uf
C12231000uFC1241
4.7uf
C14484.7uf
C13724.7uf
C13890.1uF
C12171000uF
C13414.7uf
C14084.7uf
C13564.7uf
C13404.7uf
C14504.7uf
C127822nf
C14394.7uf
C14590.1uF
C13544.7uf
C13770.1uF
C12141000uF
C14570.1uF
C14414.7uf
C14004.7uf
C1314100uF
C12394.7uf
C130922nf
C15514.7ufC1416
100uF
C12424.7uf
C14494.7uf
C13354.7uf
![Page 67: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/67.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
3A
0.02A
3A
0.02A
FMC 3.3V PMOS SwitchesFMCB_3V3 71
FMCB_aux3V3 23
FMCA_3V3 71
FMCA_aux3V3 19
FMCA_EN46,48,68FMCB_EN46,48,68
FMCA_AUXEN46
FMCB_AUXEN46
3V37,8,29,31,46,47,50,51,52,53,69
3V3
3V3
3V3
3V3
Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
67 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
67 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
67 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R732100K
R72210
R72810
Q45
SiSS23DN
1567
4
823
TP104TP106
C14741uF
R733100K
TP102
R73110
Q44
DMG2305UX
S
D
G
C14751uF
R727100K
TP101
Q41
SiSS23DN
1567
4
823
TP103
C14731uF
R72510
Q42
SiSS23DN
1567
4
823
R73010R729
10 C14761uF
Q43
DMG2305UX
S
D
G
TP105
R72410
TP107
TP100
Q47
DMG2305UX
S
D
G
R726100K
Q48
DMG2305UX
S
D
G
Q46
SiSS23DN
1567
4
823
R72310
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8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
2.5V and 1.8V IO Switches5A 5A
5A 5A
4A 4A4A 4A
IO_EN46,60,61,69
FMCAVADJ_SW 71FMCBVADJ_SW 71
2V58,46,51 IO_2V5 10,11,12,22,26,27,32,38,43S10_VCCPT29,59,63,66,70 IO_1V8 12,21,22,25,29,30,32,33,34,36,39,40,43,63,64,65,66
FMCA_EN46,48,67
FMCB_EN46,48,67
MAIN_12V47,48,49,50,53
USB2_1V87,8,32,47,52
2V5
MAIN_12VMAIN_12V
S10_VCCPT
USB2_1V8
MAIN_12VMAIN_12V
USB2_1V8
Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
68 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
68 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA0
Stratix 10 SoC FPGA Development Kit BoardB
68 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
Q55SiRA00DP
1567
4
823
R74110K Q52MMBT2222A-7-F
CE
B
R744100K
Q56SiRA00DP
1567
4
823
R747100K
Q54MMBT2222A-7-F
CE
B
R737100K
R74010K
Q50SiRA00DP
1567
4
823
R7461.00k
R734100K
Q49SiRA00DP
1567
4
823
R7491.00k
TP114
R7391.00k
C14790.01uF
TP115
C14800.01uF
TP111
C14780.01uF
C14770.01uF
TP112
R74210K
TP110
TP113
R75210K
TP109
Q57MMBT2222A-7-F
CE
B
R75310K
Q58MMBT2222A-7-F
CE
B
TP108
Q53MMBT2222A-7-F
CE
B
R745
10K
R735
10K
Q59MMBT2222A-7-F
CE
B
Q51MMBT2222A-7-F
CE
B
R748
10K
Q60MMBT2222A-7-F
CE
B
R75010K
R738
10K
R75110K
R7361.00k
R74310K
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8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
3A
0.375A
3A3A3.3V IO SwitchesPCIE_3V3 71
PCIE_aux3V3 9
PCIE_EN46,48
PCIE_auxEN46
IO_3V314,15,16,17,22,25,26,29,30,31,32,34,35,36,37,38,43,57,70
IO_EN46,60,61,68
3V37,8,29,31,46,47,50,51,52,53,67
3V33V3
3V3
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
69 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
69 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
69 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R75949.9K
C14831uF
Q66
DMG2305UX
S
D
G
R761 10
TP116
TP121
R75710
TP117
Q62
SiSS23DN
1567
4
823
R758100K
Q64
DMG2305UX
S
D
G
Q63
DMG2305UX
S
D
G
R755 10R754 10 C14821uF
TP123
Q61
SiSS23DN
1567
4
823
R76210
R763100K
TP119R75610
C14811uF TP118
Q65
SiSS23DN
1567
4
823
![Page 70: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/70.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
50us Discharge time
3.3V and 1.8V Discharge Load
IO3V3_discharge46
IO_3V314,15,16,17,22,25,26,29,30,31,32,34,35,36,37,38,43,57,69
VCCPT_discharge46
S10_VCCPT29,59,63,66,68
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
70 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
70 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
70 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
R76810K
R7690.5
R764
10
drain-tabQ67
RJK0301DPB-02#J0
4
531 2
drain-tabQ68
RJK0301DPB-02#J0
4
531 2
R76610K
R7670.5
R765
10
![Page 71: s10 soc devkit 05 5 drc 2017 - intel.com · 6 vrf 'hy .lw 5hvhw %orfn 7lwoh 6l]h 'rfxphqw 1xpehu 5hy 'dwh 6khhwri $ 6wudwl[ 6r& )3*$ 'hyhorsphqw .lw %rdug %)ulgd\ 0d\ ;; 5](https://reader042.fdocuments.net/reader042/viewer/2022031304/5bec1c7509d3f2ed1c8b741f/html5/page/71.jpg)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
User DC card 3.3V Current Sensors
PCIE3V3I_P46 PCIE3V3I_N46
PCIE_DC_3V3 9
PCIE_3V3 69
FMA3V3I_P46 FMA3V3I_N46
FMCA_DC_3V3 19
FMCA_3V3 67
FMB3V3I_P46FMB3V3I_N46
FMCB_DC_3V3 23
FMCB_3V3 67
FMAVADJI_P46 FMCAVADJ_SW 68FMAVADJI_N46
FMCAVADJ 19
FMBVADJI_P46 FMCBVADJ_SW 68FMBVADJI_N46
FMCBVADJ 23
Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
71 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
71 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.Title
Size Document Number Rev
Date: Sheet ofA1
Stratix 10 SoC FPGA Development Kit BoardB
71 71Tuesday, May 09, 2017150-0321319 (6XX-44468R )
Intel Corporation,101 innovation Dr, San Jose, CA 95134
Copyright (c) 2014, Intel Corporation. All Rights Reserved.
C14841uF
R782 10K
C14871uF
R7740.01
R770 10K
R773 10K
C14881uF
R772 10K
R7710.01
R776 10K
C14861uF
R7800.01
R781 10K
R778 10K
R7770.01
R7830.01
R779 10K
R775 10K
R784 10K
C14851uF
![*5((1:22' 35(&,286 0(7$/6 352-(&7 ... - Golden Dawn Minerals%orfn 0rgho ([whqwv dqg %orfn 6l]h *udgh (vwlpdwlrq 0rgho 9dolgdwlrq](https://static.fdocuments.net/doc/165x107/5e79c505844be91e29619fcc/5122-35286-076-352-7-golden-dawn-minerals-orfn-0rgho.jpg)
