S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 27: Datapath...
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Transcript of S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 27: Datapath...
S. Reda EN160 SP’07
Design and Implementation of VLSI Systems(EN0160)
Lecture 27: Datapath Subsystems 1/3
Prof. Sherief RedaDivision of Engineering, Brown University
Spring 2007
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160 SP’07
Project update
• Phase I: Turn your standard cells to Mike today. Mike will iterate with you for the next couple of days and distribute the library file/report on Wednesday April 11.
• Phase 2: Write precisely the interface (input/output) of your module in the CPU and write in plain english or pseudo-code what your module should do/output for different input combinations. Turn this in to Brian by Monday (April 16). Brian will verify everything and distribute the report on April 18.
S. Reda EN160 SP’07
Answer to a FAQ on the standard cell DRC• Why do we get the “not enough metal density” DRC warning?
• CMP (chemical mechanical polishing) is executed for each layer before buildup of other layers
• How can metal fill insertion helps in smoothing surfaces?
Post-CMP ILD thickness
Area fillfeatures
Wafer
Wafer carrier
Rotating platen
Polishing slurry
Slurry dispenser
Polishing pad
Downforce
S. Reda EN160 SP’07
Adders
• Addition is the most commonly used arithmetic operation• It is often the speed limiting element• Careful optimization of the adder is of the utmost
importance• Optimization can be carried out at the circuit or logic
level
S. Reda EN160 SP’07
Half and full adder
S. Reda EN160 SP’07
A N-bit adder can be constructed by cascading 1-bit FA
Worst case delay linear with the number of bits
Goal: Make the fastest possible carry path circuit
FA FA FA FA
A0 B0
S0
A1 B1
S1
A2 B2
S2
A3 B3
S3
Ci,0 Co,0
(Ci,1)
Co,1 Co,2
td = O(N)
tadder = (N-1)tcarry + tsum
S. Reda EN160 SP’07
Full adder Boolean equations
S A B Ci =
A= BCi ABCi ABCi ABCi+ + +
Co AB BCi ACi+ +=
A B
Cout
Sum
Cin Fulladder
out ( , , )
S A B C
C MAJ A B C
S. Reda EN160 SP’07
An implementation that requires 28 transistors
A B
B
A
Ci
Ci A
X
VDD
VDD
A B
Ci BA
B VDD
A
B
Ci
Ci
A
B
A CiB
Co
VDD
S. Reda EN160 SP’07
Problems with the design
A B
B
A
Ci
Ci A
X
VDD
VDD
A B
Ci BA
B VDD
A
B
Ci
Ci
A
B
A CiB
Co
VDD
Cons
• Large area• Tall transistor stacks • Large intrinsic capacitance for Co
Nevertheless
• Ci is connected to the transistor closest to the output
S. Reda EN160 SP’07
Inversion (self-dual property)
A B
S
CoCi FA
A B
S
CoCi FA
S A B Ci S A B Ci
=
Co A B Ci Co A B Ci
=
S. Reda EN160 SP’07
Minimize critical path (carry) by reducing the number of inverters
• FA’ does not have an output inverter
A3
FA FA FA
Even cell Odd cell
FA
A0 B0
S0
A1 B1
S1
A2 B2
S2
B3
S3
Ci,0 Co,0 Co,1 Co,3Co,2, , , ,
S. Reda EN160 SP’07
Can we do better? PGK design
• For a full adder, define what happens to carry
– Generate: Cout = 1 independent of C
• G = A • B
– Propagate: Cout = C
• P = A B
– Kill: Cout = 0 independent of C
• K = ~A • ~B
S. Reda EN160 SP’07
The mirror adder
VDD
Ci
A
BBA
B
A
A BKill
Generate"1"-Propagate
"0"-Propagate
VDD
Ci
A B Ci
Ci
B
A
Ci
A
BBA
VDD
SCo
24 transistors
S. Reda EN160 SP’07
Mirror adder stick diagram
CiA B
VDD
GND
B
Co
A Ci Co Ci A B
S