RTD INTERFACE SIMULATION USING IN-AMP

inCIRCUIT MAKER 2000

Submitted by:

MUHAMMAD TALHASE # 014

Submitted to: Noman Masud

Submission date:8-AUG-2005

Due Date:8-AUG-2005

Department of Electrical Engineering

Pakistan Institute of Engineering & Applied SciencesNilore, Islamabad, Pakistan

Table Of Contents

1 Introduction..................................................................................................................12 Design Steps................................................................................................................1

2.1 RTD Interface......................................................................................................12.2 IN-AMP Interface................................................................................................3

3 Cascading All Stages...................................................................................................63.1 Simulation Results...............................................................................................7

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Table Of Figures

Figure 1 RTD-Buffer Interface............................................................................................2Figure 2 The Out out of stage 1 when RTD=280 Ohm.......................................................2Figure 3 Out put of Stage1 when RTD=60 Ohm.................................................................3Figure 4 Output of Stage 2 when RTD= 280 Ohm.............................................................3Figure 5 Output of Stage 2 when RTD=60 Ohm................................................................4Figure 6 Schematic of In-Amp Configured for the gain of 10............................................4Figure 7 Output of Linear Amplifier when RTD= 60 Ohm................................................5Figure 8 Output of Linear Amplifier when RTD= 280 Ohm..............................................6Figure 9 Schematic of RTD Interface for Data Acquisition System..................................7Figure 10 Verification of results..........................................................................................7Figure 11 Simulation result when RTD Resistance is 280 Ohm........................................8Figure 12 Simulation result when RTD resistance is 60 Ohm............................................8

Table Of Tables

Table 1 Temperature & Resistance Range........................................................................1Table 2 Outputs of Stage 2 ( In-Amp).................................................................................4Table 3 Desired Range of Linear Amplifier.......................................................................5Table 4 Resistances for linear Amplifier.............................................................................5

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ABSTRACT

In practical scenarios control engineer may encounter with a situation where he have to develop an interface circuit for the sensor. This sort of situation arose when a system specification requirement changes from user point of view, and control engineer has to alter the current system and develop a compatible interface circuit. In order to incorporate these requirements control engineer must able to tackle the problem and he should know about the difficulties and the limitations of such interface.

The purpose of this project is to teach us about the tools and techniques that are used to develop the necessary interface for the new system from scratch or to modify the existing interface circuit.

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1 Introduction

The purpose of the project is to simulate the temperature sensor interfacing circuit employing the resistance temperature detector (RTD), we used the PT-100 sensor for this simulation. Circuit maker 2000 is used as a tool for this purpose.The basic principle of RTD is that as the temperature changes the resistance of the device changes, usually RTDs are positive temperature co-efficient. The design procedure consists of following essential steps

2 Design StepsDesign consists of the four major steps

RTD Buffer & Precision Power supply Interface IN-Amp Interface Linear Amplifier Interface

2.1 RTD Interface

The first step in the development of the project is to select the temperature range for the application we are designing for, here we have selected the temperature -100 to 500 The corresponding resistance from the datasheet is given as:

Temperature Resistance-100 oC. 60.26 Ohm 500 oC. 280.98 Ohm

Table 1 Temperature & Resistance Range

In the next step we have to design a buffer amplifier in the shown configuration to provide a necessary interface to the instrumentation amplifier, it should be noted that the high precision voltage source should be used to make the circuit work effectively, the output of this stage if fed to the IN-Amp stage, the configuration for the circuit is shown in the schematic given below:

1

B

A

To In-Amp

+V

V15V

+

U2AD820

+V

V210V

R1280k

RG5k

Figure 1 RTD-Buffer Interface

here we have employed the single supply rail-to-rail op-amp AD 820, V1 is the high precision voltage source.

When the RTD value is maximum i.e. the 281-Ohm the voltage at the terminal A is 5.2811 V.

When the RTD value is minimum i.e. the 60 Ohm the voltage at the terminal A is 5.0621 V.

the simulated output at are given as:

0.000us 0.500us 1.000us 1.500us 2.000us 2.500us 3.000us 3.500us 4.000us 4.500us 5.000us

5.500 V

5.400 V

5.300 V

5.200 V

5.100 V

A: u1_3

Figure 2 The Out out of stage 1 when RTD=280 Ohm

2

0.000us 0.500us 1.000us 1.500us 2.000us 2.500us 3.000us 3.500us 4.000us 4.500us 5.000us

5.300 V

5.200 V

5.100 V

5.000 V

4.900 V

A: u1_3

Figure 3 Out put of Stage1 when RTD=60 Ohm

2.2 IN-AMP InterfaceIn this stage we have to select the IN-Amp and the corresponding gain of the In-Amp. As it is desired to have the CMRR of > 50 db, so we select the AD620 IN-Amp which is capable of providing the CMRR of 100 db at the gain of 10, data sheet attached, so we go for the gain of 10.From the data sheet we have the relation:

RG= 49.4K/(G-1)

By setting the gain of 10, we find the resistance RG to be 5.5K Ohm. The IN Amp is used in the configuration shown. When the input AD620 is cascaded with the previous circuit we obtain the following outputs.

0.000ps 25.00ps 50.00ps 75.00ps 100.0ps 125.0ps 150.0ps 175.0ps 200.0ps

2.8055 V

2.8005 V

2.7955 V

2.7905 V

2.7855 V

A: r7_1

Measurement Cursors

1 r7_1 X: 0.0000 Y: 2.7955

Figure 4 Output of Stage 2 when RTD= 280 Ohm

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0.000ns 0.250ns 0.500ns 0.750ns 1.000ns 1.250ns 1.500ns 1.750ns

614.425mV

609.425mV

604.425mV

599.425mV

594.425mV

589.425mV

584.425mV

A: r7_1

Measurement Cursors

1 r7_1 X: 0.0000 Y: 599.43m

Figure 5 Output of Stage 2 when RTD=60 Ohm

+VV4

-15V

+V

V315 V

IN+IN- V+

V-OUTREF

RGRG

U1AD620

R35.5K

Figure 6 Schematic of In-Amp Configured for the gain of 10

The corresponding voltages of the AD620 are Voltage at the Output of AD620 Resistance of RTD0.6 Volts 60.26 Ohm2.8 Volts 280.98 Ohm

Table 2 Outputs of Stage 2 ( In-Amp)

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Since we are required to develop the data acquisition system so these voltages levels should be calibrated to the compatible form we need to develop a linear amplifier for this purpose. The linear amplifier configuration is given as

Input OutputMinimum 0.6 V 0 VMaximum 2.8 V 10 V

Table 3 Desired Range of Linear Amplifier

By inserting the values in the following equation , and solving ,we obtain the value of M and B

Output= M*Input + B

We found that

M= 4.545B= -2.727

Since M=(1+ R f /( R G+R 1|| R 2 ));B=VR e f (R 2 ( R f /( R G+R 1|| R 2 ))/( R 1+ R 2)

By the above equations we found the following values of resistors

Obtained Value Selected ValueR1 11.99 K 15 KR2 1K 1 KRf 10 K 10 KRg 3.00412K 2.98K

Table 4 Resistances for linear Amplifier

The results of the simulated circuit are given as:

0.000ns 0.250ns 0.500ns 0.750ns 1.000ns 1.250ns 1.500ns 1.750ns

4.8783mV

4.8758mV

4.8733mV

4.8708mV

4.8683mV

A: u2_6

Measurement Cursors

1 u2_6 X: 0.0000 Y: 4.8733m

Figure 7 Output of Linear Amplifier when RTD= 60 Ohm

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0.000ps 25.00ps 50.00ps 75.00ps 100.0ps 125.0ps 150.0ps 175.0ps 200.0ps

10.20 V

10.10 V

10.00 V

9.900 V

9.800 V

A: u2_6

Measurement Cursors

1 u2_6 X: 0.0000 Y: 9.9599

Figure 8 Output of Linear Amplifier when RTD= 280 Ohm

3 Cascading All StagesIn the end all of the above steps are combined and the different parts are cascaded to simulate the overall circuit. The resistances of linear amplifies are infractions, therefore we take the standard resistances by omitting the fractional part.The linear amplifier is coupled via 1K resistor.In the final simulation we have simulated the circuit and viewing the output of all the blocks on the single graph to understand what is going on in each block simultaneously. The schematic of the system is shown along with the simulation graphs.

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To ADC

C

B

A

+V

V610V

+

U2AD820

+V

VRef10V

+VV4

-15V

+V

V315 V

IN+IN- V+

V-OUTREF

RGRG

U1AD620

+V

V25V

+V

V110V

+

U3AD820

R31k

R112k

R21k

2.98KRg

Rf15k

RG15.5K

RTD

280

R45k

Figure 9 Schematic of RTD Interface for Data Acquisition System

3.1 Simulation ResultsThe following results are verified from the following simulation curvesResistance of RTD O/p of Buffer (at

probe A)O/p of IN-Amp (at probe B)

O/p of Linear Amplifier (at probe C)

60 Ohm 5.06 V 0.6 V 0.004 V280 Ohm 5.28 V 2.79 V 9.96 V

Figure 10 Verification of results

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0.000fs 25.00fs 50.00fs 75.00fs 100.0fs 125.0fs 150.0fs 175.0fs 200.0fs

10.00 V

9.000 V

8.000 V

7.000 V

6.000 V

5.000 V

4.000 V

3.000 V

2.000 V

A: u1_3

B: u1_6C: u2_6

Measurement Cursors

1 u2_6 X: 0.0000 Y: 9.9599

Figure 11 Simulation result when RTD Resistance is 280 Ohm

0.000us 0.500us 1.000us 1.500us 2.000us 2.500us 3.000us 3.500us 4.000us 4.500us 5.000us

6.000 V

5.000 V

4.000 V

3.000 V

2.000 V

1.000 V

0.000 V

A: u1_3

B: u1_6C: u2_6

Measurement Cursors

1 u2_6 X: 0.0000 Y: 4.8733m

Figure 12 Simulation result when RTD resistance is 60 Ohm

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