1Gueorgui ANTCHEV PH-TOT TOTEM Collaboration Meeting – June 2007

RP Motherboard – “RPMBRD”

- Block Diagram , Characteristics, Status

- “VFAT Mezzanine”

- “CC Mezzanine”

- “LVDS Repeater”

2Gueorgui ANTCHEV PH-TOT TOTEM Collaboration Meeting – June 2007

RP Motherboard – “RPMBRD” (1)

Block Diagram

PT100

For DOHM

For DOHM

T1, MCLK, I2C, Scan

Data Out, S

RP Hybrids 1 … 10

VFAT 1

DetectorVFAT 2

VFAT 3

VFAT 4

Data Out, S

T1, MCLK, I2C, Scan

QPLLPLL25Buffers

T1,MCLK

CCUM RAD MON

LV,HV

I2C

S (1,3,5,7,9)CC ODD

S (2,4,6,8,10)CC EVEN

LVDSto

CMOS GOH 4

GOH 5

TR VFAT

Trigger

LVDSto

CMOS

VFAT 1

DetectorVFAT 2

VFAT 3

VFAT 4

VFAT 1

DetectorVFAT 2

VFAT 3

VFAT 4

VFAT 1

DetectorVFAT 2

VFAT 3

VFAT 4

LVDSto

CMOS

40 LVDS Data Out

GOH 1

GOH 2

GOH 3

LVDSto

CMOS

LVDSto

CMOS

TR Data Out

RE

PE

AT

ER

S

3Gueorgui ANTCHEV PH-TOT TOTEM Collaboration Meeting – June 2007

RP Motherboard – “RPMBRD” (2)

Coincidence Chips: - 10 x 16 Trigger Outputs

S (1,3,5,7,9)

CC ODD

S (2,4,6,8,10)

CC EVEN

LVDSto

CMOS

GOH 4

GOH 5

TR VFATLVDS Trigger

LVDSto

CMOS

TR Data Out

RE

PE

AT

ER

S

RE

PE

AT

ER

S

LVDS with Repeaters - 32 Outputs

Optical via - GOH4 and GOH5 - Data Valid from: TR VFAT or CCU or TR VFAT S1 bit

Trigger VFAT: - receive 32 Trigger Outputs from LVDS to CMOS converters; - receive T1 from PLL25; - send TR Data Out to the Data Stream (via GOH3); - send TR Data Valid to GOH4 and GOH5;

TR Data Valid

Zoom on Trigger outputs

4Gueorgui ANTCHEV PH-TOT TOTEM Collaboration Meeting – June 2007

RP Motherboard – “RPMBRD” (3)

Cassette + Front Panel + Layout

- Pending final verification before production of few prototypes;

5Gueorgui ANTCHEV PH-TOT TOTEM Collaboration Meeting – June 2007

VFAT and CC mezzanines

VFAT Mezzanine:

- Also Trigger VFAT (for RP Motherboard);- One chip with 32 inputs;- Standard 50pins output connector

- Several PCB produced, 1 mounted and under test

CC Mezzanine:

- One Coincidence Chip (CC) – on Hungary responsibilities;- 80 LVDS inputs;- 16 LVDS outputs;- I2C control

- Design review – done, remarks sent to designer, waiting for answer

6Gueorgui ANTCHEV PH-TOT TOTEM Collaboration Meeting – June 2007

LVDS Repeater

LVDS Repeater:

- Repeat 16 LVDS signal lines;- Chip in package;- D-SUB 37pins male/female connectors;- Placed inside plastic hood;

- Schematic – done- Chip package definition and layout - pending

7Gueorgui ANTCHEV PH-TOT TOTEM Collaboration Meeting – June 2007

Conclusions

RP Motherboard – “RPMBRD”:

- Design is finish, Final verification;

- Production, Order of Components and Tests – pending;

- “VFAT Mezzanine” – prototype produced, to be tested;

- “CC Mezzanine” – waiting for answer, no price, no delivery date yet ...

- “LVDS Repeater” – package definition and layout pending