Implementation of high speed 8-bit Vedic multiplier using barrel shifter

Abstract

Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique

technique of calculations based on 16 Sutras (Formulae). A high speed complex multiplier

design using Vedic Mathematics is presented in this paper. The idea for designing the multiplier

and adder unit is adopted from ancient Indian mathematics "Vedas". On account of those

formulas, the partial products and sums are generated in one step which reduces the carry

propagation from LSB to MSB. The implementation of the Vedic mathematics and their

application to the complex multiplier ensure substantial reduction of propagation delay. The

functionality of these circuits was checked and performance parameters like propagation delay

and power consumption were calculated using Xilinx. The propagation delay of the resulting

(16X16) complex multiplier is compared with array multiplier.

This paper describes the implementation of an 8-bit Vedic multiplier enhanced in terms of

propagation delay when compared with conventional multiplier like array multiplier, Braun

multiplier, modified booth multiplier and Wallace tree multiplier. In our design we have utilized

8-bit barrel shifter which requires only one clock cycle for ‘n’ number of shifts. The design is

implemented and verified using ISE Simulator.The propagation delay comparison was extracted

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from the synthesis report and static timing report as well. The design could achieve propagation

delay of 6.781ns using barrel shifter in base selection module and multiplier.

Vedic Multiplier Architecture

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Tools used:

Software

• Modelsim for simulation

• Xilinx12.1i for synthesis

Language used

• VERILOG

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