rk lect3.ppt
Transcript of rk lect3.ppt
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Introduction to
CMOS VLSIDesign
Lecture 3:CMOS Transistor Theory
David Harris
Harvey Mudd College
Spring 2004
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CMOS VLSI Design3: CMOS Transistor Theory Slide 2
Outline
Introduction
MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics Gate and Diffusion Capacitance
Pass Transistors
RC Delay Models
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CMOS VLSI Design3: CMOS Transistor Theory Slide 3
Introduction
So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships Transistor gate, source, drain all have capacitance
I = C (DV/Dt) -> Dt = (C/I) DV
Capacitance and current determine speed
Also explore what a degraded level really means
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CMOS VLSI Design3: CMOS Transistor Theory Slide 4
MOS Capacitor
Gate and body form MOS capacitor
Operating modes
Accumulation
Depletion Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body+-
Vg
< 0
(b)
+-
0 < Vg
< Vt
depletion region
(c)
+-
Vg
> Vt
depletion region
inversion region
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CMOS VLSI Design3: CMOS Transistor Theory Slide 5
Terminal Voltages
Mode of operation depends on Vg, Vd, Vs
Vgs = Vg Vs Vgd = Vg Vd Vds = Vd Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage
Hence Vds 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
Vg
Vs
Vd
Vgd
Vgs
Vds
+-
+
-
+
-
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CMOS VLSI Design3: CMOS Transistor Theory Slide 6
nMOS Cutoff
No channel
Ids = 0
+-
Vgs
= 0
n+ n+
+-
Vgd
p-type body
b
g
s d
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CMOS VLSI Design3: CMOS Transistor Theory Slide 7
nMOS Linear
Channel forms
Current flows from d to s
e- from s to d
Ids increases with Vds Similar to linear resistor
+-
Vgs
> Vt
n+ n+
+-
Vgd
= Vgs
+
-
Vgs
> Vt
n+ n+
+
-
Vgs
> Vgd
> Vt
Vds = 0
0 < Vds
< Vgs
-Vt
p-type body
p-type body
b
g
s d
b
g
s dIds
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CMOS VLSI Design3: CMOS Transistor Theory Slide 8
nMOS Saturation
Channel pinches off
Ids independent of Vds We say current saturates
Similar to current source
+-
Vgs
> Vt
n+ n+
+-
Vgd
< Vt
Vds > Vgs-Vt
p-type body
b
g
s d Ids
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CMOS VLSI Design3: CMOS Transistor Theory Slide 9
I-V Characteristics
In Linear region, Ids depends on
How much charge is in the channel?
How fast is the charge moving?
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CMOS VLSI Design3: CMOS Transistor Theory Slide 10
Channel Charge
MOS structure looks like parallel plate capacitorwhile operating in inversion
Gate oxide channel
Qchannel
=
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs-
drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
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CMOS VLSI Design3: CMOS Transistor Theory Slide 11
Channel Charge
MOS structure looks like parallel plate capacitorwhile operating in inversion
Gate oxide channel
Qchannel = CV
C =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs-
drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
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CMOS VLSI Design3: CMOS Transistor Theory Slide 12
Channel Charge
MOS structure looks like parallel plate capacitorwhile operating in inversion
Gate oxide channel
Qchannel = CV
C = Cg = oxWL/tox = CoxWL
V =
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs-
drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
Cox = ox / tox
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CMOS VLSI Design3: CMOS Transistor Theory Slide 13
Channel Charge
MOS structure looks like parallel plate capacitorwhile operating in inversion
Gate oxide channel
Qchannel = CV
C = Cg = oxWL/tox = CoxWL
V = Vgc Vt = (Vgs Vds/2) Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs-
drain
Vds
channel-
Vg
Vs
Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2
gate oxide
(good insulator, ox
= 3.9)
polysilicon
gate
Cox = ox / tox
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CMOS VLSI Design3: CMOS Transistor Theory Slide 14
Carrier velocity
Charge is carried by e- Carrier velocity vproportional to lateral E-field
between source and drain
v=
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CMOS VLSI Design3: CMOS Transistor Theory Slide 15
Carrier velocity
Charge is carried by e- Carrier velocity vproportional to lateral E-field
between source and drain
v= mE m called mobility
E =
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CMOS VLSI Design3: CMOS Transistor Theory Slide 16
Carrier velocity
Charge is carried by e- Carrier velocity vproportional to lateral E-field
between source and drain
v= mE m called mobility
E = Vds/L
Time for carrier to cross channel:
t=
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CMOS VLSI Design3: CMOS Transistor Theory Slide 17
Carrier velocity
Charge is carried by e- Carrier velocity vproportional to lateral E-field
between source and drain
v= mE m called mobility
E = Vds/L
Time for carrier to cross channel:
t= L / v
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CMOS VLSI Design3: CMOS Transistor Theory Slide 18
nMOS Linear I-V
Now we know How much charge Qchannel is in the channel
How much time teach carrier takes to cross
dsI
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CMOS VLSI Design3: CMOS Transistor Theory Slide 19
nMOS Linear I-V
Now we know How much charge Qchannel is in the channel
How much time teach carrier takes to cross
channel
dsQI
t
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CMOS VLSI Design3: CMOS Transistor Theory Slide 20
nMOS Linear I-V
Now we know How much charge Qchannel is in the channel
How much time teach carrier takes to cross
channel
ox 2
2
ds
dsgs t ds
dsgs t ds
QIt
W VC V V V
L
VV V V
m
ox=
WC
L m
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CMOS VLSI Design3: CMOS Transistor Theory Slide 21
nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current
dsI
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CMOS VLSI Design3: CMOS Transistor Theory Slide 22
nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current
2dsat
ds gs t dsat
VI V V V
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CMOS VLSI Design3: CMOS Transistor Theory Slide 23
nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain When Vds > Vdsat = Vgs Vt
Now drain voltage no longer increases current
2
2
2
dsatds gs t dsat
gs t
VI V V V
V V
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CMOS VLSI Design3: CMOS Transistor Theory Slide 24
nMOS I-V Summary
2
cutoff
linear
saturatio
0
2
2n
gs t
dsds gs t ds ds dsat
gs t ds dsat
V V
VI V V V V V
V V V V
Shockley1st order transistor models
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CMOS VLSI Design3: CMOS Transistor Theory Slide 25
Example
We will be using a 0.6 mm process for your project From AMI Semiconductor
tox = 100
m = 350 cm2/V*s
Vt = 0.7 V
Plot Ids vs. Vds Vgs = 0, 1, 2, 3, 4, 5
Use W/L = 4/2 l
14
2
8
3.9 8.85 10350 120 /
100 10ox
W W WC A V
L L L m m
0 1 2 3 4 50
0.5
1
1.5
2
2.5
Vds
Ids
(mA)
Vgs
= 5
Vgs
= 4
Vgs
= 3
Vgs
= 2
Vgs = 1
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CMOS VLSI Design3: CMOS Transistor Theory Slide 26
pMOS I-V
All dopings and voltages are inverted for pMOS Mobility mp is determined by holes
Typically 2-3x lower than that of electrons mn 120 cm2/V*s in AMI 0.6 mm process
Thus pMOS must be wider to provide same current
In this class, assume mn / mp = 2
*** plot I-V here
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CMOS VLSI Design3: CMOS Transistor Theory Slide 27
Capacitance
Any two conductors separated by an insulator havecapacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source and drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it isassociated with source/drain diffusion
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CMOS VLSI Design3: CMOS Transistor Theory Slide 28
Gate Capacitance
Approximate channel as connected to source Cgs = oxWL/tox = CoxWL = CpermicronW
Cpermicron is typically about 2 fF/mm
n+ n+
p-type body
W
Ltox
SiO2
gate oxide
(good insulator, ox
= 3.90)
polysilicon
gate
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CMOS VLSI Design3: CMOS Transistor Theory Slide 29
Diffusion Capacitance
Csb, Cdb Undesirable, calledparasiticcapacitance
Capacitance depends on area and perimeter
Use small diffusion nodes
Comparable to Cg
for contacted diff
Cg for uncontacted
Varies with process
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CMOS VLSI Design3: CMOS Transistor Theory Slide 30
Pass Transistors
We have assumed source is grounded What if source > 0?
e.g. pass transistor passing VDD
VDD
VDD
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CMOS VLSI Design3: CMOS Transistor Theory Slide 31
Pass Transistors
We have assumed source is grounded What if source > 0?
e.g. pass transistor passing VDD V
g= V
DD If Vs > VDD-Vt, Vgs < Vt Hence transistor would turn itself off
nMOS pass transistors pull no higher than VDD-Vtn
Called a degraded 1 Approach degraded value slowly (low Ids)
pMOS pass transistors pull no lower than Vtp
VDD
VDD
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CMOS VLSI Design3: CMOS Transistor Theory Slide 32
Pass Transistor Ckts
VDD
VDD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
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CMOS VLSI Design3: CMOS Transistor Theory Slide 33
Pass Transistor Ckts
VDD
VDD V
s
= VDD
-Vtn
VSS
Vs
= |Vtp
|
VDD
VDD-Vtn VDD-VtnV
DD-V
tn
VDD
VDD
VDD
VDD
VDD
VDD
-Vtn
VDD-2Vtn
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CMOS VLSI Design3: CMOS Transistor Theory Slide 34
Effective Resistance
Shockley models have limited value Not accurate enough for modern transistors
Too complicated for much hand analysis
Simplification: treat transistor as resistor
Replace Ids(Vds, Vgs) with effective resistance R
Ids = Vds/R
R averaged across switching of digital gate
Too inaccurate to predict current at any given time But good enough to predict RC delay
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CMOS VLSI Design3: CMOS Transistor Theory Slide 35
RC Delay Model
Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance
Unit nMOS has resistance R, capacitance C
Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
kg
s
d
g
s
d
kCkC
kC
R/k
kg
s
d
g
s
d
kC
kC
kC
2R/k
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CMOS VLSI Design3: CMOS Transistor Theory Slide 36
RC Values
Capacitance C = Cg = Cs = Cd = 2 fF/mm of gate width
Values similar across many processes
Resistance
R 6 KW*mm in 0.6um process
Improves with shorter channel lengths
Unit transistors
May refer to minimum contacted device (4/2 l) Or maybe 1 mm wide device
Doesnt matter as long as you are consistent
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CMOS VLSI Design3: CMOS Transistor Theory Slide 37
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
2
1A
Y 2
1
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CMOS VLSI Design3: CMOS Transistor Theory Slide 38
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
C
CR
2C
2C
R
2
1A
Y
C
2C
Y2
1
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CMOS VLSI Design3: CMOS Transistor Theory Slide 39
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
C
CR
2C
2C
R
2
1A
Y
C
2C
C
2C
C
2C
RY
2
1
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CMOS VLSI D i3 CMOS T i t Th Slid 40
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
C
CR
2C
2C
R
2
1A
Y
C
2C
C
2C
C
2C
RY
2
1
d = 6RC