Revision History VAR-DT8MCustomBoard Document Carrier ......Cover A3 Wednesday, December 23, 2020 1...
Transcript of Revision History VAR-DT8MCustomBoard Document Carrier ......Cover A3 Wednesday, December 23, 2020 1...
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PAGE NO. SCHEMATIC PAGE
CONTENT
VAR-DT8MCustomBoardRevision History
SchematicS are for reference only.Variscite LTD provides no warranty for the use of these schematics.Schematics are subject to change without notice.
Disclaimer:
INITIAL1.0
Document Carrier
1.0
1.11.1 1st Release
Schottky_SSMINI - Replace symbol (swapped pin 1 and 2 to match silk) e.g. D1DART_J1.31 - Update connector for NVCC_ENET pinR110 - Assemble for PMIC_ON_REQ to go low for >130msBASE_PER_3V8 - feedback taken from SOM_VBAT (close to SOM) -Rev1.1. add on wire R159 and R156 - Remove to allow FPF2193 auto restartR176 - Replaced to 17.8K to allow for 5.4V power supplyC157 - Added on input power eFUSE - filter glitchesR65 - Remove - Part of boot config - not required.Open Solder mask and add thermal pad under SOM
1.2 1.2
Description
1.3 1.3 Added support for Basler MIPI-CSI cameraDP - Align with NXP reference design DART-MX8M-MINI notes/block diagram and symbol added.Added CAN-FD to SPI bridge circuitry
1.4 1.3A Limit DMIC_DATA to 1.8V swing using a voltage divider Overdriving DMIC_DATA (>1.8V) (applicable only when recording DMIC input) will generate noise on Headphone output.
Added DisplayPort connector J20 and remove disclaimer note1.3B1.5
1.41.6 Fix Layout for DMIC_DATA voltage divider
Add page 13. to Content list
Correct DART-MX8M and DART-MX8M-MINI J2 symbols for pin names on J2.2 and J2.14; See Pinmux changes for HPLOUT & DMIC_CLK nets.
1.41.7
Modify U44 MCP2517FDT CAN-FD controller to MCP2518FDT due to previous NRNDAdded assembly note on page 13
1.8 1.4A
1.9 1.4B
* DART-MX8MP Block Diagram & Connectors added * HDMI AC coupling and level termination modified to fit iMX8M-Plus - Note added on HDMI/DP page * Add note in DART-MX8MP Connector page for: - SAI1 and SAI5 pads voltage level - PMIC_ON_REQ * Add note for DART-MX8MP USB1_ID and USB2_ID usage in page 8.* Add note for Reset Button functionality with DART-MX8M-PLUS-V1.0A engineering samples in page 9.* Add note for DART-MX8MP boot configuration on page 11.
1.4C2.0
* C67 C76 updated - USB HUB Crystal capacitors* C181 C182 updated CAN BUS Crytal capacitors* PCIe RX caps replaced with 0 ohm resistors* Update manufacturer PN for: U33 Q2 Q6* Added U33 manufacturer PN status note.
2.1 1.4DAssemble R65 - required by DART-MX8MP-V1.1 powerup See note on page 5.
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
01. Cover
A3
1 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
01. Cover
A3
1 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
01. Cover
A3
1 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
02A. BLOCK DIAGRAM - DART-MX8M
03A. DART-MX8M
04. POWER, RTC, BOARDID
05. ETH, USD, AUDIO,MIPI-CSI
06. HDMI, DP
07. PCIE, NAND, UART DBG
08. USB C OTG, USB HOST
09. LVDS, TOUCH, JTAG, GP SWS
10. HEADERS, MECHANICS
11. BOOT CONFIG & MODE
12. PINMUX J1 & J2 & J3
13. CAN FD INTERFACE
02B. BLOCK DIAGRAM - DART-MX8M-MINI
03B. DART-MX8M-MINI
02C. BLOCK DIAGRAM - DART-MX8M-PLUS
03C. DART-MX8M-PLUS
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5
4
4
3
3
2
2
1
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D D
C C
B B
A A
Serial Camera 4 lanes x2Board to Board
Connection
JTAGConnector
DART-MX8M
HDMI Connector
DP
Connector
RJ45
Mini-PCIe Socket
RX/TX+LEDs
uSD
USB 2.0/3.0 #2
Stereo JackHeadphones
CLK + DATA
Line In Stereo Jack
JTAG
WLAN / BT
MIPI CSI-2
HDMI OUT
M4
4x UART
GigabitEthernet PHY
USB 3.0 OTG x2
SD
Audio
Codec
JTAG
UART1USB Type
Micro-AB
UART2FTDI Header
UART3/4Ext. Header
I2C2 Cap. TouchFFC / FPC
I2C3 / I2C4Ext. Header
3x I2C
SPDIF
ECSPI x3
SAI 1/2/5/6
System Ctrl
QSPIx2/NAND
RTCRTC
BATI2C2
Ext. Header SPDIF
Conn. ECSPI1
Ext. Header
Resistive
Touch Controller
Header
SAI1BOOT_CFG
RESISTORs
SAI
UserButtons/LEDs
Buttons/LEDS
GPIOs
Boot, Reset, ON/OFF
Header GPIOs
NAND
Test Points
LVDS DUAL CH OR
MIPI DSI DISP
DC-DC
OPV/OCP
DC-DCCtrl
SOM_SNVS_3V3
3.3V_SOM
5V DC Power Jack
LCD Connector
HDMI REF CLK
Ctrl
Mini-PCIe Socket
PCIe #2
PCIe x 2Gen2
USB2.0#4
PCIe #1
USB 3 HUB
USB Type-A
Host
USB Type-A
Host
USB Type-C OTG
SD
DMIC
POWER
x2PCIe Clock
Generator
USB2.0/3.0 #1
USB2.0/3.0 #2
USB2.0/3#1
I2C3
Optional
USB2.0#3
USB to UART
USB
3.3V_ Base
VBAT_SOM
HDMI/DP MUX
DOC Rev 1.7
CAN FD Controller
CANPHY
Ext. Header
02A. Block Diagram - DART-MX8M
I2C BUS ADDRESS:
I2C2:
Important Notes:
I2C4:
0xXX Header J12
0x54 BOARD ID EEPROM Page0
0x55 BOARD ID EEPROM Page1
0x68 RTC
1. Length match for HS signals according to SOM DS2. USB routed as 90 ohm Diff pairs3. PCIe/SATA routed as 85 ohm Diff pairs4. LVDS routed as 100 ohm Diff pairs5. Other fast changing signals routed as 50 ohm
0x38 CAPACITIVE TOUCH CTRLR
0x60 SOM - Int. power ctrl.
I2C3:
0x2D USB3 HUB
0x3D USB-C CC Logic PTN5150AHXMP
0x3C CSI P1 Camera (1V8) OV5640
0xXX mPCIe J23 & J32
I2C1: Internal to SOM
0x3C CSI P2 Camera (1V8) OV5640
PU - 10K on U8 10K on custom
PU - 5K on SOM
PU - 10K on U8 10K on custom
0xXX Header J12
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
02A. Block Diagram with DART-MX8M
A3
2 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
02A. Block Diagram with DART-MX8M
A3
2 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
02A. Block Diagram with DART-MX8M
A3
2 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Serial Camera 4 lanesBoard to Board
Connection
JTAGConnector
DART-MX8M-MINI
RJ45RX/TX+LEDs
uSD
USB 2.0 #2
Stereo JackHeadphones
CLK + DATA
Line In Stereo Jack
JTAG
WLAN / BT
MIPI CSI-2 x1
With H.264 Enc.
M4
4x UART
GigabitEthernet PHY
USB 2.0 OTG x2
SD
Audio
Codec
JTAG
UART1USB Type
Micro-AB
UART2FTDI Header
UART3/4Ext. Header
I2C2 Cap. TouchFFC / FPC
I2C3 / I2C4Ext. Header
3x I2C
SPDIF
ECSPI x3
SAI 1/2/5/6PDM
System Ctrl
QSPIx1/GPIOs
RTCRTC
BATI2C2
Ext. Header SPDIF
Conn. ECSPI1
Ext. Header
Resistive
Touch Controller
Header
SAI1BOOT_CFG
RESISTORs
SAI + PDM
UserButtons/LEDs
Buttons/LEDS
GPIOs
Boot, Reset, ON/OFF
Header GPIOs
Test Points
LVDS DUAL CH OR
MIPI DSI DISP
DC-DC
OPV/OCP
DC-DCCtrl
5V DC Power Jack
LCD Connector
Mini-PCIe Socket
PCIe x 1Gen2
PCIe #1
USB 3 HUB
USB Type-A
Host
USB Type-A
Host
USB Type-C OTG
SD
DMIC
POWER
x1PCIe Clock
Generator
USB2.0 #1
USB2.0 #2
USB2.0#1
I2C3
Optional
USB2.0#3
USB to
UARTUSB
3.3V_ Base
VBAT_SOM
NAND
eMMC
DOC Rev 1.1
CAN FD Controller
CANPHY
Ext. Header
02B. Block Diagram - DART-MX8M-MINI
I2C BUS ADDRESS:
I2C2:
Important Notes:
I2C4:
0xXX Header J12
0x54 BOARD ID EEPROM Page0
0x55 BOARD ID EEPROM Page1
0x68 RTC
1. Length match for HS signals according to SOM DS2. USB routed as 90 ohm Diff pairs3. PCIe/SATA routed as 85 ohm Diff pairs4. LVDS routed as 100 ohm Diff pairs5. Other fast changing signals routed as 50 ohm
0x38 CAPACITIVE TOUCH CTRLR
0x1A SOM - Int. CODEC
I2C3:
0x2D USB3 HUB
0x3D USB-C CC Logic PTN5150AHXMP
0x3C CSI P1 Camera (1V8) OV5640
0xXX mPCIe J23 & J32
I2C1: Internal to SOM
0x3C CSI P1 Camera (1V8) OV5640
PU - 10K on U8 10K on custom
PU - 5K on SOM
PU - 10K on U8 10K on custom
0xXX Header J12
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
02B. Block Diagram with DART-MX8M-MINI
A3
3 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
02B. Block Diagram with DART-MX8M-MINI
A3
3 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
02B. Block Diagram with DART-MX8M-MINI
A3
3 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Serial Camera 4 lanesx2
Board to Board Connection
JTAGConnector
DART-MX8M-PLUS
RJ45RX/ TX+LEDs
uSD
USB 2.0 #2
Stereo JackHeadphones
CLK + DATA
Line In Stereo Jack
JTAG
WLAN / BTMIPI CSI-2 x2
With H.264 Enc.
M74x UART
GigabitEthernet PHY
USB 3.0 OTG x2
SD
AudioCodec
JTAG
UART1USB Type
Micro-AB
UART2FTDI Header
UART3/ 4Ext. Header
I2C2 Cap. TouchFFC / FPC
I2C3/I2C4/I2C5/I2C6 Ext. Header
5x I2C
SPDIF
SAI 1/2/5/6/ 7PDM 4ch
System Ctrl
QSPIx1/GPIOs
RTCRTCBAT
I2C2
Ext. Header SPDIF
Header
BOOTMODE
BOOT_MODERESISTORs
SAI + PDM
UserButtons/LEDs
Buttons/LEDS
GPIOsCAN-FD x2
Boot, Reset, ON/OFF
Header
Test Points
LVDS0
DC-DC
OPV/OCP
DC-DCCtrl
5V DC Power Jack
Mini-PCIe Socket
PCIe x 1Gen2
PCIe #1
USB 3 HUB
USB Type-A Host
USB Type-A Host
USB Type-C OTG
SD
DMIC
POWER
x1PCIe Clock Generator
USB2.0/3.0 #1
USB2.0/3.0 #2
USB2.0/3#1
I2C3 Optional
USB2.0#3
USB to UART
USB
3.3V_ Base
VBAT_SOM
eMMC
ECSPI x3Conn. ECSPI1
Ext. Header
Resistive Touch
Controller
CAN FD Controller
CANPHY
Ext. Header
HDMIHDMI OUT HDMI/DP MUXCtrl
LCD Connector1
LCD Connector2
LVDS1
MIPI-DSI Test Points
02C. Block Diagram - DART-MX8M-PLUS
I2C BUS ADDRESS:
I2C2:
Important Notes:
I2C4:
0xXX Header J12
0x54 BOARD ID EEPROM Page0
0x55 BOARD ID EEPROM Page1
0x68 RTC
1. Length match for HS signals according to SOM DS2. USB routed as 90 ohm Diff pairs3. PCIe/SATA routed as 85 ohm Diff pairs4. LVDS routed as 100 ohm Diff pairs5. Other fast changing signals routed as 50 ohm
0x38 CAPACITIVE TOUCH CTRLR
I2C3:
0x2D USB3 HUB
0x3D USB-C CC Logic PTN5150AHXMP
0x3C CSI P1 Camera (1V8) OV5640
0xXX mPCIe J23 & J32
I2C1: Internal to SOM
0x3C CSI P1 Camera (1V8) OV5640
PU - 10K on U8 10K on custom
PU - 5K on SOM
PU - 10K on U8 10K on custom
0xXX Header J12
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
02B. Block Diagram with DART-MX8M-MINI
A3
4 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
02B. Block Diagram with DART-MX8M-MINI
A3
4 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
02B. Block Diagram with DART-MX8M-MINI
A3
4 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
03A - DART-MX8M Connectors
QSPI A/NAND
SD2WiFi Shared
ETH/MDIO
PCIe
CTRL:ON/OFF, POR,PMIC_ON, PMIC_STBY
SAI5 RX
SAI2 RX/TX
WDOG + I2C2
CODEC/SAI3
UART4 Shared w/BT
SAI1BOOT CFG
UART
SPDIF
CSI2
USB1
5V
SOM VBAT
USB2 LEFT
LVDS/DSI
LVDS/DSI
GPIO1
Note: Pinname with /*/ prefix denotes a HW assy option.
BOTTOMHDMI
QSPI B/NAND
ETH/MDIO
PCIe
CSI1
I2C4
WIFI HOST WAKE
TOP
JTAG
SAI1BOOT CFG
ECSPI1
6 Gbps
UART
BOOT MODE
SOM SNVS DOMAIN I/P PWR V = 3.0V:3.6V I < 5mA
5V
SOM INT VDDIO O/P PWR V = 3.3V I < 50mA
SOM INT HDMI PHY O/P PWR V = 1.8V I < 10mA
SOM INT 3.3V REG O/P PWR V = 3.3V I < 50mA Source VBAT
SOM INT SD CARD O/P PWR V = 3.3V/1.8V
DART-MX8M_J1CB
DART-MX8M_J2CB
DART-MX8M_J3CB
GND
SOM_VBAT
GND GND
AGND
GND GND
GND GND
SOM_VBAT
SOM_SNVS
SOM_NVCC_3V3
NVCC_SD2_1V8_3V3
SOM_VDD_PHY_1V8
SOM_VBAT_3V3
NVCC_ENET
ETH_TRX1_PETH_TRX1_NETH_TRX0_NETH_TRX0_PETH_TRX2_P
ENET_MDIO ETH_TRX2_NETH_TRX3_PETH_TRX3_N
I2C4_SDAPMIC_ON_REQ
POR_B
PMIC_STBY_REQ
NAND_DATA01NAND_CE0_B
NAND_DATA07 NAND_READY_BNAND_DATA06 NAND_DQSNAND_DATA04 NAND_ALE
NAND_RE_B NAND_WP_BNAND_DATA05 NAND_WE_B
NAND_CLE NAND_DATA03NAND_CE2_B NAND_DATA00
NAND_DATA02
PCIE2_REF_CLKNPCIE2_REF_CLKP
PCIE1_RXNPCIE1_RXP
PCIE2_TXNPCIE2_TXP
CONN_SD2_DATA2CONN_SD2_DATA1
CONN_SD2_DATA3CONN_SD2_DATA0
JTAG_TCKJTAG_TMS
JTAG_nTRSTJTAG_TDIJTAG_TDO
HDMI_DDC_SCLHDMI_DDC_SDA
HDMI_CEC BT_UART4_TXBT_UART4_CTS_BBT_UART4_RXBT_UART4_RTS_B
I2C2_SDA
SAI5_RXFSSAI5_RXD0SAI5_RXD2SAI5_RXCSAI5_RXD1SAI5_RXD3
SAI5_MCLKSAI2_RXFSSAI2_RXCSAI2_TXFSSAI2_MCLK
SAI1_RXFS SAI2_TXCSAI1_RXC SAI2_RXD0
SAI1_RXD1(GPIO4_IO03) SAI2_TXD0SAI1_RXD0(GPIO4_IO02) SAI1_RXD3(GPIO4_IO05)SAI1_RXD2(GPIO4_IO04) SAI1_TXFS(GPIO4_IO10)
SAI1_TXD0(GPIO4_IO12)SAI1_TXC(GPIO4_IO11)
SAI1_TXD2(GPIO4_IO14)
SAI1_MCLK(GPIO4_IO20)
SPDIF_RX
GPIO1_IO11SPDIF_EXT_CLK
USB2_RXN SPDIF_TXUSB2_RXP
GPIO1_IO13(USB1_OTG_OC)USB2_TXN I2C3_SDAUSB2_TXP USB2_ID
I2C3_SCLUSB2_DP GPIO1_IO14USB2_DN GPIO1_IO12
USB1_RXN GPIO1_IO03USB1_RXP USB1_ID
GPIO1_IO06USB1_TXNUSB1_TXP GPIO1_IO05
GPIO1_IO01(PWM1_OUT)USB1_DPUSB1_DN
GPIO1_IO00
ENET_MDC
LED_ACT
ENET_TX_CTL_BYPLED_LINK10_100LED_LINK1000
I2C4_SCL
CSI_P1_DN2
CSI_P1_DP0
CSI_P1_DP1CSI_P1_DN3
CSI_P1_DN0
CSI_P1_DP3
CSI_P1_DN1
CSI_P1_CKN
CSI_P1_DP2
CSI_P1_CKP
CONN_SD2_CLK
CONN_SD2_CMD
UART4_TXD(GPIO5_IO29)UART4_RXD(GPIO5_IO28)
CSI_P2_DN3
CSI_P2_DN0
CSI_P2_CKP
CSI_P2_DP1
CSI_P2_DP2
CSI_P2_DN1
CSI_P2_DN2
CSI_P2_CKN
CSI_P2_DP3
CSI_P2_DP0
HDMI_TX0_LN0_P
HDMI_TX2_LN2_N
HDMI_TX1_LN1_N
HDMI_TX0_LN0_N
HDMI_CLK_LN3_N
HDMI_TX1_LN1_P
HDMI_CLK_LN3_P
HDMI_TX2_LN2_P
HDMI_AUXNHDMI_AUXP
HDMI_HPD
HDMI_REFCLKNHDMI_REFCLKP
EN_SOM_VBAT_3V3CONN_SD2_CD_B
CONN_SD2_nRST
HPLOUTHPROUT
DMIC_CLKDMIC_DATA
HPOUTFBLINEIN1_LPLINEIN1_RP
LVDS1_CLK_N
LVDS2_CLK_DSI_TX2_N
LVDS1_TX2_P
LVDS1_TX3_NLVDS1_TX3_P
LVDS2_CLK_DSI_TX2_P
LVDS1_TX2_N
LVDS2_TX2_DSI_CLK_P
LVDS1_CLK_P
LVDS2_TX2_DSI_CLK_N
LVDS1_TX0_N
LVDS2_DSI_TX0_NLVDS2_DSI_TX1_P
LVDS2_DSI_TX0_P
LVDS2_DSI_TX1_N
LVDS1_TX1_N
LVDS2_DSI_TX3_N
LVDS1_TX1_P
LVDS2_DSI_TX3_P
LVDS1_TX0_P
GPIO1_IO15
ECSPI1_SS0ECSPI1_SCLK
ECSPI1_MOSIECSPI1_MISO
BOOT_MODE0BOOT_MODE1
GPIO1_IO08
USB1_VBUS
USB2_VBUS
ONOFF
UART1_RXDUART1_TXD
UART2_TXD
UART3_RXDUART2_RXD
UART3_TXD
GPIO1_IO02(nWDOG)
GPIO1_IO10
SAI1_RXD5(GPIO4_IO07)
SAI1_RXD4(GPIO4_IO06)SAI1_TXD1(GPIO4_IO13)
SAI1_TXD3(GPIO4_IO15)SAI1_TXD5(GPIO4_IO17)
SAI1_TXD6(GPIO4_IO18)
SAI1_TXD4(GPIO4_IO16)SAI1_TXD7(GPIO4_IO19)
SAI1_RXD6(GPIO4_IO08)SAI1_RXD7(GPIO4_IO09)
I2C2_SCL
BT_HOST_WAKEWIFI_HOST_WAKE
SD2_WP(GPIO2_IO20)
PCIE1_REF_CLKPPCIE1_REF_CLKN
PCIE1_TXPPCIE1_TXN
PCIE2_RXPPCIE2_RXN
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project1.4D-R2.1
03. DART-MX8M Connectors
A2
5 17Wednesday, December 23, 2020Oded A. VPC0331
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project1.4D-R2.1
03. DART-MX8M Connectors
A2
5 17Wednesday, December 23, 2020Oded A. VPC0331
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project1.4D-R2.1
03. DART-MX8M Connectors
A2
5 17Wednesday, December 23, 2020Oded A. VPC0331
DART-MX8M_J2 CB
V1
DF40C-90DS-0_4V_51
J2
JTAG_TCK1
JTAG_TMS3
JTAG_TRST_B5
JTAG_TDI7
JTAG_TDO9
BOOT_MODE111
BOOT_MODE013
HDMI_DDC_SCL15
HDMI_DDC_SDA17
HDMI_CEC19
HDMI_HPD21
GND23
HDMI_AUX_P25
HDMI_AUX_N27
HDMI_TX_M_LN_129
HDMI_TX_P_LN_131
HDMI_TX_P_LN_033
HDMI_TX_M_LN_035
HDMI_REFCLK_N37
HDMI_REFCLK_P39
VDD_PHY_1V841
HDMI_TX_P_LN_243
HDMI_TX_M_LN_245
GND47
HDMI_TX_P_LN_349
HDMI_TX_M_LN_351
GND53
SAI1_RXFS/SAI5_RXFS/////GPIO4_IO0055
SAI1_RXC/SAI5_RXC/////GPIO4_IO0157
SAI1_RXD1/SAI5_RXD1/////GPIO4_IO03//////BOOT_CFG0159
SAI1_RXD0/SAI5_RXD0/////GPIO4_IO02//////BOOT_CFG0061
SAI1_RXD2/SAI5_RXD2/////GPIO4_IO04//////BOOT_CFG0263
SAI1_RXD4/SAI6_TXC//SAI6_RXC/////GPIO4_IO06//////BOOT_CFG0465
SAI1_TXD1/SAI5_TXD1/////GPIO4_IO13//////BOOT_CFG0967
SAI1_RXD5/SAI6_TXD0//SAI6_RXD0///SAI1_RXFS/////GPIO4_IO07//////BOOT_CFG0569
SAI1_TXD5/SAI6_RXD0//SAI6_TXD0/////GPIO4_IO17//////BOOT_CFG1371
SAI1_TXD3/SAI5_TXD3/////GPIO4_IO15//////BOOT_CFG1173
GND75
ECSPI1_SCLK/UART3_RX/////GPIO5_IO0677
ECSPI1_SS0/UART3_RTS_B/////GPIO5_IO0979
ECSPI1_MISO/UART3_CTS_B/////GPIO5_IO0881
ECSPI1_MOSI/UART3_TX/////GPIO5_IO0783
UART2_RXD/ECSPI3_MISO/////GPIO5_IO2485
UART3_RXD/UART1_CTS_B/////GPIO5_IO2687
UART3_TXD/UART1_RTS_B/////GPIO5_IO2789
SAI3_RXD/GPT1_COMPARE1//SAI5_RXD0/////GPIO4_IO30/*/HPLOUT2
SAI3_TXC/GPT1_COMPARE2//SAI5_RXD2/////GPIO5_IO00/*/HPROUT4
SAI3_RXFS/GPT1_CAPTURE1//SAI5_RXFS/////GPIO4_IO28/*/HPOUTFB6
SAI3_RXC/GPT1_CAPTURE2//SAI5_RXC/////GPIO4_IO29/*/LINEIN1_LP8
SAI3_TXFS/GPT1_CLK//SAI5_RXD1/////GPIO4_IO31/*/LINEIN1_RP10
AGND12
SAI3_TXD/GPT1_COMPARE3//SAI5_RXD3/////GPIO5_IO01/*/DMIC_CLK14
SAI3_MCLK/PWM4_OUT//SAI5_MCLK/////GPIO5_IO02/*/DMIC_DATA16
GND18
ECSPI2_MOSI/UART4_TX/////GPIO5_IO1120
ECSPI2_MISO/UART4_CTS_B/////GPIO5_IO1222
ECSPI2_SCLK/UART4_RX/////GPIO5_IO1024
ECSPI2_SS0/UART4_RTS_B/////GPIO5_IO1326
GPIO1_IO02/WDOG_B28
I2C2_SDA/ENET1_1588_EVENT1_OUT/////GPIO5_IO1730
I2C2_SCL/ENET1_1588_EVENT1_IN/////GPIO5_IO1632
SAI5_RXFS/SAI1_TXD0/////GPIO3_IO1934
SAI5_RXD0/SAI1_TXD2/////GPIO3_IO2136
SAI5_RXD2/SAI1_TXD4//SAI1_TXFS///SAI5_TXC/////GPIO3_IO2338
SAI5_RXC/SAI1_TXD1/////GPIO3_IO2040
SAI5_RXD1/SAI1_TXD3//SAI1_TXFS///SAI5_TXFS/////GPIO3_IO2242
SAI5_RXD3/SAI1_TXD5//SAI1_TXFS///SAI5_TXD0/////GPIO3_IO2444
SAI5_MCLK/SAI1_TXC//SAI4_MCLK/////GPIO3_IO2546
SAI2_RXFS/SAI5_TXFS/////GPIO4_IO2148
SAI2_RXC/SAI5_TXC/////GPIO4_IO2250
SAI2_TXFS/SAI5_TXD1/////GPIO4_IO2452
SAI2_MCLK/SAI5_MCLK/////GPIO4_IO2754
SAI2_TXC/SAI5_TXD2/////GPIO4_IO2556
SAI2_RXD0/SAI5_TXD0/////GPIO4_IO2358
SAI2_TXD0/SAI5_TXD3/////GPIO4_IO2660
SAI1_RXD3/SAI5_RXD3/////GPIO4_IO05//////BOOT_CFG0362
SAI1_TXFS/SAI5_TXFS/////GPIO4_IO1064
SAI1_RXD6/SAI6_TXFS//SAI6_RXFS/////GPIO4_IO08//////BOOT_CFG0666
SAI1_RXD7/SAI6_MCLK//SAI1_TXFS///SAI1_TXD4/////GPIO4_IO09//////BOOT_CFG0768
SAI1_TXD0/SAI5_TXD0/////GPIO4_IO12//////BOOT_CFG0870
SAI1_TXC/SAI5_TXC/////GPIO4_IO1172
SAI1_TXD4/SAI6_RXC//SAI6_TXC/////GPIO4_IO16//////BOOT_CFG1274
SAI1_TXD7/SAI6_MCLK/////GPIO4_IO19//////BOOT_CFG1576
SAI1_TXD2/SAI5_TXD2/////GPIO4_IO14//////BOOT_CFG1078
SAI1_TXD6/SAI6_RXFS//SAI6_TXFS/////GPIO4_IO18//////BOOT_CFG1480
SAI1_MCLK/SAI5_MCLK//SAI1_TXC/////GPIO4_IO2082
GND84
UART2_TXD/ECSPI3_SS0/////GPIO5_IO2586
UART1_RXD/ECSPI3_SCLK/////GPIO5_IO2288
UART1_TXD/ECSPI3_MOSI/////GPIO5_IO2390
DF40C-90DS-0_4V_51
J3
1UART4_TXD/UART2_RTS_B//PCIE2_CLKREQ_B/////GPIO5_IO29
3UART4_RXD/UART2_CTS_B//PCIE1_CLKREQ_B/////GPIO5_IO28
5NC/*/LVDS1_TX2_P
7NC/*/LVDS1_TX2_N
9GND
11NC/*/LVDS1_CLK_P
13NC/*/LVDS1_CLK_N
15GND
17NC/*/LVDS1_TX3_P
19NC/*/LVDS1_TX3_N
21GND
23DSI_TX2_P/*/LVDS2_CLK_P
25DSI_TX2_N/*/LVDS2_CLK_N
27GND
29DSI_CLK_N/*/LVDS2_TX2_N
31DSI_CLK_P/*/LVDS2_TX2_P
33GND
35USB2_RXN
37USB2_RXP
39GND
41USB2_TXN
43USB2_TXP
45GND
47USB2_DP
49USB2_DN
51GND
53USB1_RXN
55USB1_RXP
57GND
59USB1_TXN
61USB1_TXP
63GND
65USB1_DP
67USB1_DN
69VBAT_3V3
71VBAT
73VBAT
75VBAT
77VBAT
79VBAT
81VBAT
83VBAT
85VBAT
87VBAT
89VBAT
2NC/*/LVDS1_TX0_P
4NC/*/LVDS1_TX0_N
6NC/*/LVDS1_TX1_P
8NC/*/LVDS1_TX1_N
10GND
12DSI_TX0_P/*/LVDS2_TX0_P
14DSI_TX0_N/*/LVDS2_TX0_N
16DSI_TX1_P/*/LVDS2_TX1_P
18DSI_TX1_N/*/LVDS2_TX1_N
20DSI_TX3_P/*/LVDS2_TX3_P
22DSI_TX3_N/*/LVDS2_TX3_N
24GND
26USB2_VBUS
28SPDIF_RX/PWM2_OUT/////GPIO5_IO04
30GPIO1_IO11/USB2_OTG_ID/////PMIC_READY
32SPDIF_EXT_CLK/PWM1_OUT/////GPIO5_IO05
34GND
36SPDIF_TX/PWM3_OUT/////GPIO5_IO03
38GPIO1_IO15/USB2_OTG_OC/////PWM4_OUT//////CLKO2
40GPIO1_IO13/USB1_OTG_OC/////PWM2_OUT
42I2C3_SDA/PWM3_OUT//GPT3_CLK/////GPIO5_IO19
44USB2_ID
46I2C3_SCL/PWM4_OUT//GPT2_CLK/////GPIO5_IO18
48GPIO1_IO14/USB2_OTG_PWR/////PWM3_OUT
50GPIO1_IO12/USB1_OTG_PWR
52GPIO1_IO10/USB1_OTG_ID
54GPIO1_IO03/USDHC1_VSELECT//////XTAL_OK
56USB1_ID
58GPIO1_IO06/////SD1_CD_B//////EXT_CLK3
60GPIO1_IO08/ENET1_1588_EVENT0_IN/////SD2_RESET_B
62GPIO1_IO05/M4_NMI/////PMIC_READY
64GPIO1_IO01/PWM1_OUT/////REF_CLK_24M//////EXT_CLK2
66USB1_VBUS
68GND
70CSI_P2_CKN
72CSI_P2_CKP
74GND
76CSI_P2_DN3
78CSI_P2_DP3
80CSI_P2_DN1
82CSI_P2_DP1
84CSI_P2_DN0
86CSI_P2_DP0
88CSI_P2_DN2
90CSI_P2_DP2
C19
100uF
C23
100uF
C24
100uF
DF40C-90DS-0_4V_51
J1
GPIO1_IO00/ENET_PHY_REF_CLK_ROOT/////REF_CLK_32K1
ENET_TX_CTL/////GPIO1_IO22/*/NC3
ENET_TXC/////GPIO1_IO23/*/LED_LINK10_1005
ENET_RXC/////GPIO1_IO25/*/LED_LINK10007
ENET_RX_CTL/////GPIO1_IO24/*/LED_ACT9
ENET_MDIO/////GPIO1_IO1711
ENET_MDC/////GPIO1_IO1613
NVCC_SNVS_3V315
I2C4_SCL/PWM2_OUT//PCIE1_CLKREQ_B/////GPIO5_IO2017
I2C4_SDA/PWM1_OUT//PCIE2_CLKREQ_B/////GPIO5_IO2119
GND21
/*/BT_HOST_WAKE23
/*/WIFI_HOST_WAKE25
NVCC_3V327
SD2_WP/////GPIO2_IO2029
NVCC_ENET31
GND33
NAND_DATA07/QSPIB_DATA3/////GPIO3_IO1335
NAND_DATA06/QSPIB_DATA2/////GPIO3_IO1237
NAND_DATA04/QSPIB_DATA0/////GPIO3_IO1039
NAND_RE_B/QSPIB_DQS/////GPIO3_IO1541
NAND_DATA05/QSPIB_DATA1/////GPIO3_IO1143
NAND_CLE/QSPIB_SCLK/////GPIO3_IO0545
NAND_CE2_B/QSPIB_SS0_B/////GPIO3_IO0347
GND49
PCIE1_REF_CLKN51
PCIE1_REF_CLKP53
GND55
PCIE1_TXN57
PCIE1_TXP59
GND61
PCIE2_RXN63
PCIE2_RXP65
GND67
CSI_P1_DP369
CSI_P1_DN371
CSI_P1_DP173
CSI_P1_DN175
CSI_P1_DN277
CSI_P1_DP279
CSI_P1_DP081
CSI_P1_DN083
GND85
CSI_P1_CKP87
CSI_P1_CKN89
ENET_TD1/////GPIO1_IO20/*/ETH_TRX1_P2
ENET_TD0/////GPIO1_IO21/*/ETH_TRX1_N4
ENET_TD2/////GPIO1_IO19/*/ETH_TRX0_N6
ENET_TD3/////GPIO1_IO18/*/ETH_TRX0_P8
ENET_RD0/////GPIO1_IO26/*/ETH_TRX2_P10
ENET_RD1/////GPIO1_IO27/*/ETH_TRX2_N12
ENET_RD2/////GPIO1_IO28/*/ETH_TRX3_P14
ENET_RD3/////GPIO1_IO29/*/ETH_TRX3_N16
GND18
ONOFF20
PMIC_ON_REQ22
POR_B24
PMIC_STBY_REQ26
SD2_RESET_B/////GPIO2_IO1928
GND30
NAND_DATA01/QSPIA_DATA1/////GPIO3_IO0732
NAND_CE0_B/QSPIA_SS0_B/////GPIO3_IO0134
NAND_READY_B/////GPIO3_IO1636
NAND_DQS/QSPIA_DQS/////GPIO3_IO1438
NAND_ALE/QSPIA_SCLK/////GPIO3_IO0040
NAND_WP_B/////GPIO3_IO1842
NAND_WE_B/////GPIO3_IO1744
NAND_DATA03/QSPIA_DATA3/////GPIO3_IO0946
NAND_DATA00/QSPIA_DATA0/////GPIO3_IO0648
NAND_DATA02/QSPIA_DATA2/////GPIO3_IO0850
GND52
PCIE2_REF_CLKN54
PCIE2_REF_CLKP56
GND58
PCIE1_RXN60
PCIE1_RXP62
GND64
PCIE2_TXN66
PCIE2_TXP68
GND70
EN_VBAT_3V372
SD2_CD_B/////GPIO2_IO01274
GND76
SD2_DATA2/////GPIO2_IO1778
SD2_DATA1/////GPIO2_IO1680
SD2_CLK/////GPIO2_IO1382
SD2_DATA3/////GPIO2_IO1884
SD2_DATA0/////GPIO2_IO1586
SD2_CMD/////GPIO2_IO1488
NVCC_SD2_1V8_3V390
SOM used w/"WBD" [ ]
QSPIA_DATA1 [QSPIA_DATA1_1V8]QSPIA_SS0_B [QSPIA_SS0_B_1V8]
QSPIB_DATA3 [ ] GPIO3_IO16 [ ]QSPIB_DATA2 [ ] QSPIA_DQS [QSPIA_DQS_1V8]QSPIB_DATA0 [] QSPIA_SCLK [QSPIA_SCLK_1V8]QSPIB_DQS [ENET_MDIO] GPIO3_IO18 [ ]QSPIB_DATA1 [] GPIO3_IO17 [ ]QSPIB_SCLK [] QSPIA_DATA3 [QSPIA_DATA3_1V8]QSPIB_SS0_B [] QSPIA_DATA0 [QSPIA_DATA0_1V8]
QSPIA_DATA2 [QSPIA_DATA2_1V8]
BOOT_CFG01GP_LED1/CSI_P2_TRIGBOOT_CFG00CSI_BUF_EN_B BOOT_CFG03 CAPTOUCH_RSTnBOOT_CFG02GP_LED3 CSI_P2_SYNCBOOT_CFG04SW_BACK BOOT_CFG06 CSI_P1_PWRENBOOT_CFG09SW_HOME BOOT_CFG07 CSI_P2_PWRENBOOT_CFG05PCIe_1_nRST BOOT_CFG08 CSI_P2_RST_BBOOT_CFG13GP_LED4 CSI_P1_OPTBOOT_CFG11SW_VOLDN BOOT_CFG12 CSI_P1_TRIG
BOOT_CFG15 PCIe_2_nRSTBOOT_CFG10 GP_LED2BOOT_CFG14 SW_VOLUP
CSI_P1_SYNC
CSI_P2_OPTCSI_P1_RST_B
SOM used w/"LD" [ ]SOM used w/"WBD"
RTC_IRQn
CAN_CS_BUSB1_TYPEC_INTnRES_TOUCH_PENIRQn
CAN_INT_BSOM used w/"WBD" [ ]HDMI_SW_GPU_SELLVDS_PWM
CAP_TOUCH_INTn
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
03B - DART-MX8M-MINI Connectors
QSPI A/NAND
SD2WiFi Shared
ETH/MDIO
PCIe
CTRL:ON/OFF, POR,PMIC_ON, PMIC_STBY
SAI5 RX
SAI2 RX/TX
WDOG + I2C2
CODEC/SAI3
UART4 Shared w/BT
SAI1BOOT CFG
UART
SPDIF
CSI2
USB1
5V
SOM VBAT
USB2
LEFT
LVDS/DSI
LVDS/DSI
GPIO1
Note: Pinname with /*/ prefix denotes a HW assy option.
BOTTOM
ETH/MDIO
PCIe
CSI1
I2C4
WIFI HOST WAKE
TOP
JTAG
SAI1BOOT CFG
ECSPI1
UART
BOOT MODE
SOM SNVS DOMAIN I/P PWR V = 3.0V:3.6V I < 5mA
5V
SOM INT VDDIO O/P PWR V = 3.3V I < 50mA
SOM INT SD CARD O/P PWR V = 3.3V/1.8V
DART-MX8M-MINI_J1CB
DART-MX8M-MINI_J2CB
DART-MX8M-MINI_J3CB
*** Dotted nets - Functionality differ from DART-MX8M. ***
GND GND
AGND
GND GND
GND GND
SOM_VBAT
SOM_SNVS
SOM_NVCC_3V3
NVCC_SD2_1V8_3V3
SOM_VDD_PHY_1V8
SOM_VBAT_3V3
NVCC_ENET
ETH_TRX1_PETH_TRX1_NETH_TRX0_NETH_TRX0_PETH_TRX2_P
ENET_MDIO ETH_TRX2_NETH_TRX3_PETH_TRX3_N
I2C4_SDAPMIC_ON_REQ
POR_B
PMIC_STBY_REQ
NAND_DATA01NAND_CE0_B
NAND_DATA07 NAND_READY_BNAND_DATA06 NAND_DQSNAND_DATA04 NAND_ALE
NAND_RE_B NAND_WP_BNAND_DATA05 NAND_WE_B
NAND_CLE NAND_DATA03NAND_CE2_B NAND_DATA00
NAND_DATA02
PCIE2_REF_CLKNPCIE2_REF_CLKP
PCIE1_RXNPCIE1_RXP
PCIE2_TXNPCIE2_TXP
CONN_SD2_DATA2CONN_SD2_DATA1
CONN_SD2_DATA3CONN_SD2_DATA0
JTAG_TCKJTAG_TMS
JTAG_nTRSTJTAG_TDIJTAG_TDO
BT_UART4_TXBT_UART4_CTS_BBT_UART4_RXBT_UART4_RTS_B
I2C2_SDA
SAI5_RXFSSAI5_RXD0SAI5_RXD2SAI5_RXCSAI5_RXD1SAI5_RXD3
SAI5_MCLKSAI2_RXFSSAI2_RXCSAI2_TXFSSAI2_MCLK
SAI1_RXFS SAI2_TXCSAI1_RXC SAI2_RXD0
SAI1_RXD1(GPIO4_IO03) SAI2_TXD0SAI1_RXD0(GPIO4_IO02) SAI1_RXD3(GPIO4_IO05)SAI1_RXD2(GPIO4_IO04) SAI1_TXFS(GPIO4_IO10)
SAI1_TXD0(GPIO4_IO12)SAI1_TXC(GPIO4_IO11)
SAI1_TXD2(GPIO4_IO14)
SAI1_MCLK(GPIO4_IO20)
SPDIF_RX
GPIO1_IO11SPDIF_EXT_CLK
SPDIF_TX
GPIO1_IO13(USB1_OTG_OC)I2C3_SDA
USB2_ID
I2C3_SCLGPIO1_IO14GPIO1_IO12
GPIO1_IO03USB1_IDGPIO1_IO06
GPIO1_IO05GPIO1_IO01(PWM1_OUT)
GPIO1_IO00
ENET_MDC
LED_ACT
ENET_TX_CTL_BYPLED_LINK10_100LED_LINK1000
I2C4_SCL
CSI_P1_DN2
CSI_P1_DP0
CSI_P1_DP1CSI_P1_DN3
CSI_P1_DN0
CSI_P1_DP3
CSI_P1_DN1
CSI_P1_CKN
CSI_P1_DP2
CSI_P1_CKP
CONN_SD2_CLK
CONN_SD2_CMD
UART4_TXD(GPIO5_IO29)UART4_RXD(GPIO5_IO28)
EN_SOM_VBAT_3V3CONN_SD2_CD_B
CONN_SD2_nRST
HPLOUTHPROUT
DMIC_CLKDMIC_DATA
HPOUTFBLINEIN1_LPLINEIN1_RP
LVDS1_CLK_N
LVDS2_CLK_DSI_TX2_N
LVDS1_TX2_P
LVDS1_TX3_NLVDS1_TX3_P
LVDS2_CLK_DSI_TX2_P
LVDS1_TX2_N
LVDS2_TX2_DSI_CLK_P
LVDS1_CLK_P
LVDS2_TX2_DSI_CLK_N
LVDS1_TX0_N
LVDS2_DSI_TX0_NLVDS2_DSI_TX1_P
LVDS2_DSI_TX0_P
LVDS2_DSI_TX1_N
LVDS1_TX1_N
LVDS2_DSI_TX3_N
LVDS1_TX1_P
LVDS2_DSI_TX3_P
LVDS1_TX0_P
GPIO1_IO15
ECSPI1_SS0ECSPI1_SCLK
ECSPI1_MOSIECSPI1_MISO
BOOT_MODE0BOOT_MODE1
GPIO1_IO08
USB1_VBUS
USB2_VBUS
ONOFF
UART1_RXDUART1_TXD
UART2_TXD
UART3_RXDUART2_RXD
UART3_TXD
GPIO1_IO02(nWDOG)
GPIO1_IO10
SAI1_RXD5(GPIO4_IO07)
SAI1_RXD4(GPIO4_IO06)SAI1_TXD1(GPIO4_IO13)
SAI1_TXD3(GPIO4_IO15)SAI1_TXD5(GPIO4_IO17)
SAI1_TXD6(GPIO4_IO18)
SAI1_TXD4(GPIO4_IO16)SAI1_TXD7(GPIO4_IO19)
SAI1_RXD6(GPIO4_IO08)SAI1_RXD7(GPIO4_IO09)
I2C2_SCL
BT_HOST_WAKEWIFI_HOST_WAKE
SD2_WP(GPIO2_IO20)
HDMI_DDC_SCLHDMI_DDC_SDA
HDMI_CEC
HDMI_HPD
HDMI_AUXPHDMI_AUXN
HDMI_TX1_LN1_NHDMI_TX1_LN1_PHDMI_TX0_LN0_PHDMI_TX0_LN0_N
HDMI_REFCLKNHDMI_REFCLKP
HDMI_TX2_LN2_PHDMI_TX2_LN2_N
HDMI_CLK_LN3_PHDMI_CLK_LN3_N
CSI_P2_CKNCSI_P2_CKP
CSI_P2_DN3CSI_P2_DP3CSI_P2_DN1CSI_P2_DP1CSI_P2_DN0CSI_P2_DP0CSI_P2_DN2CSI_P2_DP2
USB2_RXNUSB2_RXP
USB2_TXNUSB2_TXP
USB2_DPUSB2_DN
USB1_RXNUSB1_RXP
USB1_TXNUSB1_TXP
USB1_DPUSB1_DN
PCIE1_TXNPCIE1_TXP
PCIE2_RXNPCIE2_RXP
PCIE1_REF_CLKPPCIE1_REF_CLKN
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project1.4D-R2.1
03B. DART-MX8M Connectors
A2
6 17Wednesday, December 23, 2020Oded A. VPC0331
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project1.4D-R2.1
03B. DART-MX8M Connectors
A2
6 17Wednesday, December 23, 2020Oded A. VPC0331
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project1.4D-R2.1
03B. DART-MX8M Connectors
A2
6 17Wednesday, December 23, 2020Oded A. VPC0331
DF40C-90DS-0_4V_51
J3-DT8M-MINI
NETLIST_IGNORE = True BOM_IGNORE = True
UART4_TXD/UART2_RTS_B/////GPIO5_IO291
UART4_RXD/UART2_CTS_B//PCIE1_CLKREQ_B/////GPIO5_IO283
NC/*/LVDS1_TX2_P5
NC/*/LVDS1_TX2_N7
GND9
NC/*/LVDS1_CLK_P11
NC/*/LVDS1_CLK_N13
GND15
NC/*/LVDS1_TX3_P17
NC/*/LVDS1_TX3_N19
GND21
DSI_TX2_P/*/LVDS2_CLK_P23
DSI_TX2_N/*/LVDS2_CLK_N25
GND27
DSI_CLK_N/*/LVDS2_TX2_N29
DSI_CLK_P/*/LVDS2_TX2_P31
GND33
NC35
NC37
GND39
NC41
NC43
GND45
USB2_D_P47
USB2_D_N49
GND51
NC53
NC55
GND57
NC59
NC61
GND63
USB1_D_P65
USB1_D_N67
NC69
VBAT71
VBAT73
VBAT75
VBAT77
VBAT79
VBAT81
VBAT83
VBAT85
VBAT87
VBAT89
NC/*/LVDS1_TX0_P2
NC/*/LVDS1_TX0_N4
NC/*/LVDS1_TX1_P6
NC/*/LVDS1_TX1_N8
GND10
DSI_TX0_P/*/LVDS2_TX0_P12
DSI_TX0_N/*/LVDS2_TX0_N14
DSI_TX1_P/*/LVDS2_TX1_P16
DSI_TX1_N/*/LVDS2_TX1_N18
DSI_TX3_P/*/LVDS2_TX3_P20
DSI_TX3_N/*/LVDS2_TX3_N22
GND24
USB2_VBUS26
SPDIF_RX/PWM2_OUT/////GPIO5_IO0428
GPIO1_IO11/USB2_OTG_ID30
SPDIF_EXT_CLK/PWM1_OUT/////GPIO5_IO0532
GND34
SPDIF_TX/PWM3_OUT/////GPIO5_IO0336
GPIO1_IO15/USB2_OTG_OC/////PWM4_OUT//////CLKO138
GPIO1_IO13/USB1_OTG_OC/////PWM2_OUT40
I2C3_SDA/PWM3_OUT//GPT3_CLK/////GPIO5_IO1942
USB2_ID44
I2C3_SCL/PWM4_OUT//GPT2_CLK/////GPIO5_IO1846
GPIO1_IO14/USB2_OTG_PWR/////PWM3_OUT//////CLKO148
GPIO1_IO12/USB1_OTG_PWR50
GPIO1_IO10/USB1_OTG_ID52
GPIO1_IO03/USDHC1_VSELECT54
USB1_ID56
GPIO1_IO06/ENET1_MDC/////SD1_CD_B//////EXT_CLK358
GPIO1_IO08/ENET1_1588_EVENT0_IN/////SD2_RESET_B60
GPIO1_IO05/M4_NMI/////PMIC_READY62
GPIO1_IO01/PWM1_OUT/////REF_CLK_24M//////EXT_CLK264
USB1_VBUS66
GND68
NC70
NC72
GND74
NC76
NC78
NC80
NC82
NC84
NC86
NC88
NC90
V1
CONN_DART-MX8MM_J2_CB
J2-DT8M-MINI
NETLIST_IGNORE = True BOM_IGNORE = True
JTAG_TCK1
JTAG_TMS3
JTAG_TRST_B5
JTAG_TDI7
JTAG_TDO9
BOOT_MODE111
BOOT_MODE013
NC15
NC17
NC19
NC21
GND23
NC25
NC27
NC29
NC31
NC33
NC35
NC37
NC39
NC41
NC43
NC45
GND47
NC49
NC51
GND53
SAI1_RXFS/SAI5_RXFS/////GPIO4_IO0055
SAI1_RXC/SAI5_RXC/////GPIO4_IO0157
SAI1_RXD1/SAI5_RXD1///PDM_BIT1/////GPIO4_IO03//////BOOT_CFG0159
SAI1_RXD0/SAI5_RXD0//SAI1_TXD1///PDM_BIT0/////GPIO4_IO02//////BOOT_CFG0061
SAI1_RXD2/SAI5_RXD2///PDM_BIT2/////GPIO4_IO04//////BOOT_CFG0263
SAI1_RXD4/SAI6_TXC//SAI6_RXC/////GPIO4_IO06//////BOOT_CFG0465
SAI1_TXD1/SAI5_TXD1/////GPIO4_IO13//////BOOT_CFG0967
SAI1_RXD5/SAI6_TXD0//SAI6_RXD0///SAI1_RXFS/////GPIO4_IO07//////BOOT_CFG0569
SAI1_TXD5/SAI6_RXD0//SAI6_TXD0/////GPIO4_IO17//////BOOT_CFG1371
SAI1_TXD3/SAI5_TXD3/////GPIO4_IO15//////BOOT_CFG1173
GND75
ECSPI1_SCLK/UART3_RXD/////GPIO5_IO0677
ECSPI1_SS0/UART3_RTS_B/////GPIO5_IO0979
ECSPI1_MISO/UART3_CTS_B/////GPIO5_IO0881
ECSPI1_MOSI/UART3_TXD/////GPIO5_IO0783
UART2_RXD/ECSPI3_MISO/////GPIO5_IO2485
UART3_RXD/UART1_CTS_B/////GPIO5_IO2687
UART3_TXD/UART1_RTS_B/////GPIO5_IO2789
SAI3_RXD/GPT1_COMPARE1//SAI5_RXD0/////GPIO4_IO30/*/HPLOUT2
SAI3_TXC/GPT1_COMPARE2//SAI5_RXD2////UART2_TXD/////GPIO5_IO00/*/HPROUT4
SAI3_RXFS/GPT1_CAPTURE1//SAI5_RXFS///SAI3_RXD1/////GPIO4_IO28/*/HPOUTFB6
SAI3_RXC/GPT1_CLK//SAI5_RXC////UART2_CTS_B/////GPIO4_IO29/*/LINEIN1_LP8
SAI3_TXFS/GPT1_CAPTURE2//SAI5_RXD1///SAI3_TXD1////UART2_RXD/////GPIO4_IO31/*/LINEIN1_RP10
AGND12
SAI3_TXD/GPT1_COMPARE3//SAI5_RXD3/////GPIO5_IO01/*/DMIC_CLK14
SAI3_MCLK/PWM4_OUT//SAI5_MCLK/////GPIO5_IO02/*/DMIC_DATA16
GND18
ECSPI2_MOSI/UART4_TXD/////GPIO5_IO1120
ECSPI2_MISO/UART4_CTS_B/////GPIO5_IO1222
ECSPI2_SCLK/UART4_RXD/////GPIO5_IO1024
ECSPI2_SS0/UART4_RTS_B/////GPIO5_IO1326
GPIO1_IO02/WDOG_B/////WDOG_ANY28
I2C2_SDA/ENET1_1588_EVENT1_OUT/////GPIO5_IO1730
I2C2_SCL/ENET1_1588_EVENT1_IN/////GPIO5_IO1632
SAI5_RXFS/SAI1_TXD0/////GPIO3_IO1934
SAI5_RXD0/SAI1_TXD2////PDM_BIT0/////GPIO3_IO2136
SAI5_RXD2/SAI1_TXD4//SAI1_TXFS///SAI5_TXC////PDM_BIT2/////GPIO3_IO2338
SAI5_RXC/SAI1_TXD1////PDM_CLK/////GPIO3_IO2040
SAI5_RXD1/SAI1_TXD3//SAI1_TXFS///SAI5_TXFS////PDM_BIT1/////GPIO3_IO2242
SAI5_RXD3/SAI1_TXD5//SAI1_TXFS///SAI5_TXD0////PDM_BIT3/////GPIO3_IO2444
SAI5_MCLK/SAI1_TXC/////GPIO3_IO2546
SAI2_RXFS/SAI5_TXFS//SAI5_TXD1///SAI2_RXD1////UART1_TXD/////GPIO4_IO2148
SAI2_RXC/SAI5_TXC////UART1_RXD/////GPIO4_IO2250
SAI2_TXFS/SAI5_TXD1///SAI2_TXD1////UART1_CTS_B/////GPIO4_IO2452
SAI2_MCLK/SAI5_MCLK/////GPIO4_IO2754
SAI2_TXC/SAI5_TXD2/////GPIO4_IO2556
SAI2_RXD0/SAI5_TXD0////UART1_RTS_B/////GPIO4_IO2358
SAI2_TXD0/SAI5_TXD3/////GPIO4_IO2660
SAI1_RXD3/SAI5_RXD3///PDM_BIT3/////GPIO4_IO05//////BOOT_CFG0362
SAI1_TXFS/SAI5_TXFS/////GPIO4_IO1064
SAI1_RXD6/SAI6_TX_SYNC//SAI6_RXFS/////GPIO4_IO08//////BOOT_CFG0666
SAI1_RXD7/SAI6_MCLK//SAI1_TXFS///SAI1_TXD4/////GPIO4_IO09//////BOOT_CFG0768
SAI1_TXD0/SAI5_TXD0/////GPIO4_IO12//////BOOT_CFG0870
SAI1_TXC/SAI5_TXC/////GPIO4_IO1172
SAI1_TXD4/SAI6_RXC//SAI6_TXC/////GPIO4_IO16//////BOOT_CFG1274
SAI1_TXD7/SAI6_MCLK///PDM_CLK/////GPIO4_IO19//////BOOT_CFG1576
SAI1_TXD2/SAI5_TXD2/////GPIO4_IO14//////BOOT_CFG1078
SAI1_TXD6/SAI6_RXFS//SAI6_TXFS/////GPIO4_IO18//////BOOT_CFG1480
SAI1_MCLK/SAI5_MCLK//SAI1_TXC///PDM_CLK/////GPIO4_IO2082
GND84
UART2_TXD/ECSPI3_SS0/////GPIO5_IO2586
UART1_RXD/ECSPI3_SCLK/////GPIO5_IO2288
UART1_TXD/ECSPI3_MOSI/////GPIO5_IO2390
DF40C-90DS-0_4V_51
J1-DT8M-MINI
NETLIST_IGNORE = True BOM_IGNORE = True
GPIO1_IO00/ENET_PHY_REF_CLK_ROOT_OUT/////REF_CLK_32K//////EXT_CLK11
ENET_TX_CTL/////GPIO1_IO22/*/NC3
ENET_TXC/ENET_TX_ER/////GPIO1_IO23/*/LED_LINK10_1005
ENET_RXC/ENET_RX_ER/////GPIO1_IO25/*/LED_LINK10007
ENET_RX_CTL/////GPIO1_IO24/*/LED_ACT9
ENET_MDIO/////GPIO1_IO1711
ENET_MDC/////GPIO1_IO1613
NVCC_SNVS_1V815
I2C4_SCL/PWM2_OUT//PCIE1_CLKREQ_B/////GPIO5_IO2017
I2C4_SDA/PWM1_OUT/////GPIO5_IO2119
GND21
/*/BT_HOST_WAKE23
/*/WIFI_HOST_WAKE25
NVCC_3V327
SD1_DATA7/////GPIO2_IO09_1V829
NVCC_ENET31
GND33
CLKIN1_1V835
CLKIN2_1V837
NC39
GPIO1_IO07/ENET_MDIO//////EXT_CLK441
NC43
CLKOUT1_1V845
CLKOUT2_1V847
GND49
PCIE1_REF_CLK_N51
PCIE1_REF_CLK_P53
GND55
PCIE1_TX_N57
PCIE1_TX_P59
GND61
NC63
NC65
GND67
CSI_P1_D3_P69
CSI_P1_D3_N71
CSI_P1_D1_P73
CSI_P1_D1_N75
CSI_P1_D2_N77
CSI_P1_D2_P79
CSI_P1_D0_P81
CSI_P1_D0_N83
GND85
CSI_P1_CK_P87
CSI_P1_CK_N89
2ENET_TD1/////GPIO1_IO20/*/ETH_TRX1_PENET_TD0/////GPIO1_IO21/*/ETH_TRX1_N
4
ENET_TD2/ENET_TX_CLK_IN|ENET_REF_CLK_ROOT_OUT/////GPIO1_IO19/*/ETH_TRX0_N6
ENET_TD3/////GPIO1_IO18/*/ETH_TRX0_P8
ENET_RD0/////GPIO1_IO26/*/ETH_TRX2_P10
ENET_RD1/////GPIO1_IO27/*/ETH_TRX2_N12
ENET_RD2/////GPIO1_IO28/*/ETH_TRX3_P14
ENET_RD3/////GPIO1_IO29/*/ETH_TRX3_N16
GND18
ONOFF_1V820
PMIC_ON_REQ_1V822
POR_B_1V824
PMIC_STBY_REQ_1V826
SD2_RESET_B/////GPIO2_IO1928
GND30
NAND_DATA01/QSPIA_DATA1_1V8/////GPIO3_IO07_1V832
NAND_CE0_B/QSPIA_SS0_B_1V8/////GPIO3_IO01_1V834
NC36
NAND_DQS/QSPIA_DQS_1V8/////GPIO3_IO14_1V838
NAND_ALE/QSPIA_SCLK_1V8/////GPIO3_IO00_1V840
NC42
NC44
NAND_DATA03/QSPIA_DATA3_1V8/////GPIO3_IO09_1V846
NAND_DATA00/QSPIA_DATA0_1V8/////GPIO3_IO06_1V848
NAND_DATA02/QSPIA_DATA2_1V8/////GPIO3_IO08_1V850
GND52
NC54
NC56
GND58
PCIE1_RX_N60
PCIE1_RX_P62
GND64
NC66
NC68
GND70
NC72
SD2_CD_B/////GPIO2_IO01274
GND76
SD2_DATA2/////GPIO2_IO1778
SD2_DATA1/////GPIO2_IO1680
SD2_CLK/////GPIO2_IO1382
SD2_DATA3/////GPIO2_IO1884
SD2_DATA0/////GPIO2_IO1586
SD2_CMD/////GPIO2_IO1488
NVCC_SD2_1V8_3V390
SOM used w/"WBD" [ ]
QSPIA_DATA1 [QSPIA_DATA1_1V8]QSPIA_SS0_B [QSPIA_SS0_B_1V8]
QSPIB_DATA3 [ ] GPIO3_IO16 [ ]QSPIB_DATA2 [ ] QSPIA_DQS [QSPIA_DQS_1V8]QSPIB_DATA0 [] QSPIA_SCLK [QSPIA_SCLK_1V8]QSPIB_DQS [ENET_MDIO] <CB_Function> GPIO3_IO18 [ ]QSPIB_DATA1 [] GPIO3_IO17 [ ]QSPIB_SCLK [] QSPIA_DATA3 [QSPIA_DATA3_1V8]QSPIB_SS0_B [] QSPIA_DATA0 [QSPIA_DATA0_1V8]
QSPIA_DATA2 [QSPIA_DATA2_1V8]
BOOT_CFG01GP_LED1/CSI_P2_TRIGBOOT_CFG00CSI_BUF_EN_B BOOT_CFG03 CAPTOUCH_RSTnBOOT_CFG02GP_LED3 CSI_P2_SYNCBOOT_CFG04SW_BACK BOOT_CFG06 CSI_P1_PWRENBOOT_CFG09SW_HOME BOOT_CFG07 CSI_P2_PWRENBOOT_CFG05PCIe_1_nRST BOOT_CFG08 CSI_P2_RST_BBOOT_CFG13GP_LED4 CSI_P1_OPTBOOT_CFG11SW_VOLDN BOOT_CFG12 CSI_P1_TRIG
BOOT_CFG15 PCIe_2_nRSTBOOT_CFG10 GP_LED2BOOT_CFG14 SW_VOLUP
CSI_P1_SYNC
CSI_P2_OPTCSI_P1_RST_B
SOM used w/"LD" [ ]SOM used w/"WBD"
RTC_IRQn
CAN_CS_BUSB1_TYPEC_INTnRES_TOUCH_PENIRQn
CAN_INT_BSOM used w/"WBD" [ ]HDMI_SW_GPU_SELLVDS_PWM
CAP_TOUCH_INTn
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
03C - DART-MX8M-PLUS Connectors
QSPI A
SD2
ETH/MDIO
PCIe 1
SAI5
SAI2 RX/TX
WDOG + I2C2
CODEC/SAI3
UART4 Shared w/BT
UART
SPDIF
CSI2
USB1
SOM VBAT
USB2 LEFT
LVDS/DSI
LVDS/DSI
GPIO1
Note: Pinname with /*/ prefix denotes a HW assy option.
BOTTOM
ETH/MDIO
PCIe1
CSI1
I2C4WIFI HOST WAKE
TOP
JTAG
ECSPI1
UART
BOOT MODE
*** Dotted nets - Functionality differ from DART-MX8M. ***
SOM SNVS DOMAIN I/P PWR V = 3.0V:3.6V I < 5mA
SOM INT VDDIO O/P PWR V = 3.3V I < 50mA
SOM INT SD CARD O/P PWR V = 3.3V/1.8V
5V
5V
Level according to PIN 41 output
SAI1Level according to PIN 41 output SAI1
Level according to PIN 41 output
HDMI
PIN J3.41:NVCC_SAI1_SAI5
Power for PADS SAI1_xx and SAI5_xx set by PMIC ON DART-MX8MP;Set to 3.3V in u-boot!
DSI
DSIDSI
BOOT MODE3
NOTE: DART-MX8MP-V1.0 J1.22PMIC_ON_REQ cannot be forcedlow; Version V1.1 will be replaced with PMIC_RST.
GND
GND
SOM_VBAT
SOM_VDD_PHY_1V8
SOM_VBAT_3V3
SOM_SNVS
SOM_NVCC_3V3
NVCC_ENET
GND
NVCC_SD2_1V8_3V3
GND
AGND
GND
GND
JTAG_TCKJTAG_TMS
JTAG_nTRSTJTAG_TDIJTAG_TDO
SAI1_RXFSSAI1_RXC
SAI1_RXD1(GPIO4_IO03)SAI1_RXD0(GPIO4_IO02)SAI1_RXD2(GPIO4_IO04)
UART4_TXD(GPIO5_IO29)UART4_RXD(GPIO5_IO28)
LVDS1_CLK_N
LVDS2_CLK_DSI_TX2_N
LVDS1_TX2_P
LVDS1_TX3_NLVDS1_TX3_P
LVDS2_CLK_DSI_TX2_P
LVDS1_TX2_N
LVDS2_TX2_DSI_CLK_P
LVDS1_CLK_P
LVDS2_TX2_DSI_CLK_N
ECSPI1_SS0ECSPI1_SCLK
ECSPI1_MOSIECSPI1_MISO
BOOT_MODE0BOOT_MODE1
UART3_RXDUART2_RXD
UART3_TXD
SAI1_RXD5(GPIO4_IO07)
SAI1_RXD4(GPIO4_IO06)SAI1_TXD1(GPIO4_IO13)
SAI1_TXD3(GPIO4_IO15)SAI1_TXD5(GPIO4_IO17)
HDMI_DDC_SCLHDMI_DDC_SDA
HDMI_CEC
HDMI_HPD
HDMI_AUXPHDMI_AUXN
HDMI_TX1_LN1_NHDMI_TX1_LN1_PHDMI_TX0_LN0_PHDMI_TX0_LN0_N
HDMI_REFCLKNHDMI_REFCLKP
HDMI_TX2_LN2_PHDMI_TX2_LN2_N
HDMI_CLK_LN3_PHDMI_CLK_LN3_N
USB2_RXNUSB2_RXP
USB2_TXNUSB2_TXP
USB2_DPUSB2_DN
USB1_RXNUSB1_RXP
USB1_TXNUSB1_TXP
USB1_DPUSB1_DN
GPIO1_IO00ENET_TX_CTL_BYPLED_LINK10_100LED_LINK1000LED_ACTENET_MDIO
ENET_MDC
I2C4_SCLI2C4_SDA
BT_HOST_WAKEWIFI_HOST_WAKE
SD2_WP(GPIO2_IO20)
NAND_DATA07NAND_DATA06NAND_DATA04
NAND_RE_BNAND_DATA05
NAND_CLENAND_CE2_B
CSI_P1_DP3CSI_P1_DN3CSI_P1_DP1CSI_P1_DN1CSI_P1_DN2CSI_P1_DP2CSI_P1_DP0CSI_P1_DN0
CSI_P1_CKPCSI_P1_CKN
ETH_TRX1_PETH_TRX1_NETH_TRX0_NETH_TRX0_PETH_TRX2_PETH_TRX2_NETH_TRX3_PETH_TRX3_N
ONOFFPMIC_ON_REQ
POR_B
PMIC_STBY_REQCONN_SD2_nRST
NAND_DATA01NAND_CE0_BNAND_READY_BNAND_DQSNAND_ALENAND_WP_BNAND_WE_BNAND_DATA03NAND_DATA00NAND_DATA02
EN_SOM_VBAT_3V3CONN_SD2_CD_B
CONN_SD2_DATA2CONN_SD2_DATA1
CONN_SD2_CLKCONN_SD2_DATA3CONN_SD2_DATA0
CONN_SD2_CMD
HPLOUTHPROUTHPOUTFBLINEIN1_LPLINEIN1_RP
DMIC_CLKDMIC_DATA
BT_UART4_TXBT_UART4_CTS_BBT_UART4_RXBT_UART4_RTS_B
GPIO1_IO02(nWDOG)I2C2_SDA
I2C2_SCLSAI5_RXFSSAI5_RXD0SAI5_RXD2SAI5_RXCSAI5_RXD1SAI5_RXD3
SAI5_MCLKSAI2_RXFSSAI2_RXCSAI2_TXFSSAI2_MCLKSAI2_TXCSAI2_RXD0SAI2_TXD0
SAI1_RXD3(GPIO4_IO05)SAI1_TXFS(GPIO4_IO10)
SAI1_RXD6(GPIO4_IO08)SAI1_RXD7(GPIO4_IO09)SAI1_TXD0(GPIO4_IO12)SAI1_TXC(GPIO4_IO11)
SAI1_TXD4(GPIO4_IO16)SAI1_TXD7(GPIO4_IO19)SAI1_TXD2(GPIO4_IO14)
SAI1_TXD6(GPIO4_IO18)SAI1_MCLK(GPIO4_IO20)
UART2_TXDUART1_RXDUART1_TXD
LVDS1_TX0_PLVDS1_TX0_NLVDS1_TX1_PLVDS1_TX1_N
LVDS2_DSI_TX0_PLVDS2_DSI_TX0_NLVDS2_DSI_TX1_PLVDS2_DSI_TX1_NLVDS2_DSI_TX3_PLVDS2_DSI_TX3_N
USB2_VBUSSPDIF_RX
GPIO1_IO11SPDIF_EXT_CLK
SPDIF_TX
GPIO1_IO15GPIO1_IO13(USB1_OTG_OC)
I2C3_SDAUSB2_ID
I2C3_SCLGPIO1_IO14GPIO1_IO12GPIO1_IO10GPIO1_IO03USB1_IDGPIO1_IO06
GPIO1_IO08GPIO1_IO05GPIO1_IO01(PWM1_OUT)
USB1_VBUS
CSI_P2_CKNCSI_P2_CKP
CSI_P2_DN3CSI_P2_DP3CSI_P2_DN1CSI_P2_DP1CSI_P2_DN0CSI_P2_DP0CSI_P2_DN2CSI_P2_DP2
PCIE2_TXPPCIE2_TXN
PCIE1_RXNPCIE1_RXP
PCIE2_REF_CLKPPCIE2_REF_CLKN
PCIE2_RXN
PCIE1_REF_CLKN
PCIE2_RXP
PCIE1_REF_CLKP
PCIE1_TXNPCIE1_TXP
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project1.4D-R2.1
03B. DART-MX8M Connectors
A2
7 17Wednesday, December 23, 2020Oded A. VPC0331
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project1.4D-R2.1
03B. DART-MX8M Connectors
A2
7 17Wednesday, December 23, 2020Oded A. VPC0331
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project1.4D-R2.1
03B. DART-MX8M Connectors
A2
7 17Wednesday, December 23, 2020Oded A. VPC0331
DART-MX8MP_J1 CB
V0
DF40C-90DS-0_4V_51
J1-DT8M-PLUS
NETLIST_IGNORE = TRUE BOM_IGNORE = True
GPIO1_IO00/ENET_PHY_REF_CLK_ROOT///ISP_FL_TRIG_0/////REF_CLK_32K//////EXT_CLK11
ENET_QOS_RGMII_TX_CTL//SAI6_MCLK///SPDIF1_OUT/////GPIO1_IO22//////SD3_D0/*/NC3
ENET_QOS_RGMII_TXC/ENET_QOS_TX_ER//SAI7_TXD0/////GPIO1_IO23//////SD3_D1/*/ETH_LED_LINK10_1005
ENET_QOS_RGMII_RXC/ENET_QOS_RX_ER//SAI7_TXC///PDM_BIT2/////GPIO1_IO25//////SD3_D3/*/ETH_LED_LINK10007
ENET_QOS_RGMII_RX_CTL//SAI7_TXFS///PDM_BIT3/////GPIO1_IO24//////SD3_D2/*/ETH_LED_ACT9
ENET_QOS_MDIO//SAI6_TXFS///PDM_BIT3/////GPIO1_IO17//////SD3_D511
ENET_QOS_MDC//SAI6_TXD0/////GPIO1_IO16//////SD3_STROBE13
NVCC_SNVS_1V815
I2C4_SCL/PWM2_OUT//PCIE1_CLKREQ_B///ECSPI2_MISO/////GPIO5_IO2017
I2C4_SDA/PWM1_OUT///ECSPI2_SS0/////GPIO5_IO2119
GND21
NC/*/BT_HOST_WAKE23
NC/*/WIFI_HOST_WAKE25
NVCC_3V327
SD1_RESET_B/ENET1_TX_CLK_IN,ENET_REF_CLK_ROOT_OUT///I2C3_SCL////UART3_RTS_B/////GPIO2_IO1029
NVCC_ENET31
GND33
DSI1_CLK_N/*/NC35
DSI1_CLK_P/*/NC37
DSI1_D0_N/*/NC39
DSI1_D0_P/*/NC41
DSI1_D1_N/*/NC43
DSI1_D1_P/*/NC45
GPIO1_IO09/ENET_QOS_1588_EVENT0_OUT//PWM2_OUT///ISP_SHUTTER_OPEN_1////SD3_RESET_B/////SDMA2_EXT_EVENT047
GND49
PCIE1_REF_CLK_N51
PCIE1_REF_CLK_P53
GND55
PCIE1_TX_N57
PCIE1_TX_P59
GND61
NC63
NC65
GND67
CSI1_D3_P69
CSI1_D3_N71
CSI1_D1_P73
CSI1_D1_N75
CSI1_D2_N77
CSI1_D2_P79
CSI1_D0_P81
CSI1_D0_N83
GND85
CSI1_CLK_P87
CSI1_CLK_N89
ENET_QOS_RGMII_TD1//SAI6_RXFS///PDM_BIT0/////GPIO1_IO20//////SD3_CD_B/*/ETH_TRX1_P2
ENET_QOS_RGMII_TD0//SAI6_RXC///PDM_CLK/////GPIO1_IO21//////SD3_WP/*/ETH_TRX1_N4
ENET_QOS_RGMII_TD2/ENET_QOS_TX_CLK_IN,ENET_QOS_REF_CLK_ROOT_OUT//SAI6_RXD0///PDM_BIT1/////GPIO1_IO19//////SD3_D7/*/ETH_TRX0_N6
ENET_QOS_RGMII_TD3//SAI6_TXC///PDM_BIT2/////GPIO1_IO18//////SD3_D6/*/ETH_TRX0_P8
ENET_QOS_RGMII_RD0//SAI7_RXD0///PDM_BIT1/////GPIO1_IO26//////SD3_D4/*/ETH_TRX2_P10
ENET_QOS_RGMII_RD1//SAI7_RXFS///PDM_BIT0/////GPIO1_IO27//////SD3_RESET_B/*/ETH_TRX2_N12
ENET_QOS_RGMII_RD2//SAI7_RXC///PDM_CLK/////GPIO1_IO28//////SD3_CLK/*/ETH_TRX3_P14
ENET_QOS_RGMII_RD3//SAI7_MCLK///SPDIF1_IN/////GPIO1_IO29//////SD3_CMD/*/ETH_TRX3_N16
GND18
ONOFF_1V820
PMIC_ON_REQ_1V822
POR_B_1V824
PMIC_STBY_REQ_1V826
SD2_RESET_B/////GPIO2_IO19//////SYSTEM_RESET28
GND30
NAND_D01_1V8/QSPI_A_D1_1V8//SAI3_TXFS_1V8///ISP_PRELIGHT_TRIG_0_1V8////UART4_TX_1V8/////GPIO3_IO07_1V832
NAND_CE0_B_1V8/QSPI_A_SS0_B_1V8//SAI3_TXD0_1V8///ISP_SHUTTER_TRIG_0_1V8////UART3_TX_1V8/////GPIO3_IO01_1V834
NC36
NAND_DQS_1V8/QSPI_A_DQS_1V8//SAI3_MCLK_1V8///ISP_SHUTTER_OPEN_0_1V8////I2C3_SCL_1V8/////GPIO3_IO14_1V838
NAND_ALE_1V8/QSPI_A_SCLK_1V8//SAI3_TXC_1V8///ISP_FL_TRIG_0_1V8////UART3_RX_1V8/////GPIO3_IO00_1V840
DSI1_D2_N/*/NC42
DSI1_D2_P/*/NC44
NAND_D03_1V8/QSPI_A_D3_1V8//SD3_WP_1V8///UART4_RTS_B_1V8////ISP_FL_TRIG_1_1V8/////GPIO3_IO09_1V846
NAND_D00_1V8_1V8/QSPI_A_D0_1V8//SAI3_RXD0_1V8///ISP_FLASH_TRIG_0_1V8////UART4_RX_1V8/////GPIO3_IO06_1V848
NAND_D02_1V8/QSPI_A_D2_1V8//SD3_CD_B_1V8///UART4_CTS_B_1V8////I2C4_SDA_1V8/////GPIO3_IO08_1V850
GND52
NC54
NC56
GND58
PCIE1_RX_N60
PCIE1_RX_P62
GND64
DSI1_D3_N/*/NC66
DSI1_D3_P/*/NC68
GND70
BOOT_MODE372
SD2_CD_B/////GPIO2_IO1274
GND76
SD2_D2//ECSPI2_SS0///SPDIF1_OUT////PDM_BIT2/////GPIO2_IO1778
SD2_D1//I2C4_SCL///UART2_TX////PDM_BIT1/////GPIO2_IO1680
SD2_CLK//ECSPI2_SCLK///UART4_RX/////GPIO2_IO1382
SD2_D3//ECSPI2_MISO///SPDIF1_IN////PDM_BIT3/////GPIO2_IO18//////EARLY_RESET84
SD2_D0//I2C4_SDA///UART2_RX////PDM_BIT0/////GPIO2_IO1586
SD2_CMD//ECSPI2_MOSI///UART4_TX////PDM_CLK/////GPIO2_IO1488
NVCC_SD2_1V8_3V390
DART-MX8MP_J3 CB
V0
DF40C-90DS-0_4V_51
J3-DT8M-PLUS
BOM_IGNORE = TRUE NETLIST_IGNORE = TRUE
UART4_TX/UART2_RTS_B///GPT1_CAPTURE1////I2C6_SDA/////GPIO5_IO291
UART4_RX/UART2_CTS_B//PCIE1_CLKREQ_B///GPT1_COMPARE1////I2C6_SCL/////GPIO5_IO283
LVDS0_D2_P5
LVDS0_D2_N7
GND9
LVDS0_CLK_P11
LVDS0_CLK_N13
GND15
LVDS0_D3_P17
LVDS0_D3_N19
GND21
LVDS1_CLK_P/*/DSI1_D2_P23
LVDS1_CLK_N/*/DSI1_D2_N25
GND27
LVDS1_D2_N/*/DSI1_CLK_N29
LVDS1_D2_P/*/DSI1_CLK_P31
GND33
USB2_RX_N35
USB2_RX_P37
GND39
USB2_TX_N41
USB2_TX_P43
GND45
USB2_D_P47
USB2_D_N49
GND51
USB1_RX_N53
USB1_RX_P55
GND57
USB1_TX_N59
USB1_TX_P61
GND63
USB1_D_P65
USB1_D_N67
NC69
VBAT71
VBAT73
VBAT75
VBAT77
VBAT79
VBAT81
VBAT83
VBAT85
VBAT87
VBAT89
LVDS0_D0_P2
LVDS0_D0_N4
LVDS0_D1_P6
LVDS0_D1_N8
GND10
LVDS1_D0_P/*/DSI1_D0_P12
LVDS1_D0_N/*/DSI1_D0_N14
LVDS1_D1_P/*/DSI1_D1_P16
LVDS1_D1_N/*/DSI1_D1_N18
LVDS1_D3_P/*/DSI1_D3_P20
LVDS1_D3_N/*/DSI1_D3_N22
GND24
USB2_VBUS26
SPDIF1_IN/PWM2_OUT//I2C5_SDA///GPT1_COMPARE2////FLEXCAN1_RX/////GPIO5_IO0428
GPIO1_IO11/USB2_OTG_ID//PWM2_OUT////SD3_VSELECT30
SPDIF1_EXT_CLK/PWM1_OUT///GPT1_COMPARE3/////GPIO5_IO0532
GND34
SPDIF1_OUT/PWM3_OUT//I2C5_SCL///GPT1_COMPARE1////FLEXCAN1_TX/////GPIO5_IO0336
GPIO1_IO15/USB2_OTG_OC////SD3_WP/////PWM4_OUT//////CCM_CLKO238
GPIO1_IO13/USB1_OTG_OC/////PWM2_OUT40
I2C3_SDA/PWM3_OUT//GPT3_CLK///ECSPI2_MOSI/////GPIO5_IO1942
USB2_ID44
I2C3_SCL/PWM4_OUT//GPT2_CLK///ECSPI2_SCLK/////GPIO5_IO1846
GPIO1_IO14/USB2_OTG_PWR////SD3_CD_B/////PWM3_OUT//////CCM_CLKO148
GPIO1_IO12/USB1_OTG_PWR/////SDMA2_EXT_EVENT150
GPIO1_IO10/USB1_OTG_ID//PWM3_OUT52
GPIO1_IO07/ENET_QOS_MDIO///ISP_FLASH_TRIG_1/////SD1_WP//////CCM_EXT_CLK454
USB1_ID56
GPIO1_IO06/ENET_QOS_MDC///ISP_SHUTTER_TRIG_1/////SD1_CD_B//////CCM_EXT_CLK358
GPIO1_IO08/ENET_QOS_1588_EVENT0_IN//PWM1_OUT///ISP_PRELIGHT_TRIG_1////ENET_QOS_1588_EVENT0_AUX_IN/////SD2_RESET_B60
GPIO1_IO05/M7_NMI///ISP_FL_TRIG_1/////CCM_PMIC_READY62
GPIO1_IO01/PWM1_OUT///ISP_SHUTTER_TRIG_0/////CCM_REF_CLK_24M//////CCM_EXT_CLK264
USB1_VBUS66
GND68
CSI2_CLK_N70
CSI2_CLK_P72
GND74
CSI2_D3_N76
CSI2_D3_P78
CSI2_D1_N80
CSI2_D1_P82
CSI2_D0_N84
CSI2_D0_P86
CSI2_D2_N88
CSI2_D2_P90
DART-MX8MP_J2 CB
V0
DF40C-90DS-0_4V_51
J2-DT8M-PLUS
NETLIST_IGNORE = TRUE BOM_IGNORE = TRUE
JTAG_TCK1
JTAG_TMS3
JTAG_MODE5
JTAG_TDI7
JTAG_TDO9
BOOT_MODE111
BOOT_MODE213
HDMI_DDC_SCL///I2C5_SCL////FLEXCAN1_TX/////GPIO3_IO2615
HDMI_DDC_SDA///I2C5_SDA////FLEXCAN1_RX/////GPIO3_IO2717
HDMI_CEC///I2C6_SCL////FLEXCAN2_TX/////GPIO3_IO2819
HDMI_HPD/HDMI_HPD_O///I2C6_SDA////FLEXCAN2_RX/////GPIO3_IO2921
GND23
EARC_P_UTIL25
EARC_N_HPD27
HDMI_TX1_N29
HDMI_TX1_P31
HDMI_TX0_P33
HDMI_TX0_N35
NC37
NC39
NVCC_SAI1_SAI541
HDMI_TX2_P43
HDMI_TX2_N45
GND47
HDMI_TXC_P49
HDMI_TXC_N51
GND53
SAI1_RXFS/SAI5_RXFS////ENET1_1588_EVENT0_IN/////GPIO4_IO0055
SAI1_RXC/SAI5_RXC///PDM_CLK////ENET1_1588_EVENT0_OUT/////GPIO4_IO0157
SAI1_RXD1/SAI5_RXD1///PDM_BIT1////ENET1_1588_EVENT1_OUT/////GPIO4_IO0359
SAI1_RXD0/SAI5_RXD0//SAI1_TXD1///PDM_BIT0////ENET1_1588_EVENT1_IN/////GPIO4_IO0261
SAI1_RXD2/SAI5_RXD2///PDM_BIT2////ENET1_MDC/////GPIO4_IO0463
SAI1_RXD4/SAI6_TXC//SAI6_RXC////ENET1_RGMII_RD0/////GPIO4_IO0665
SAI1_TXD1/SAI5_TXD1////ENET1_RGMII_TD1/////GPIO4_IO1367
SAI1_RXD5/SAI6_TXD0//SAI6_RXD0///SAI1_RXFS////ENET1_RGMII_RD1/////GPIO4_IO0769
SAI1_TXD5/SAI6_RXD0//SAI6_TXD0////ENET1_RGMII_TXC/////GPIO4_IO1771
SAI1_TXD3/SAI5_TXD3////ENET1_RGMII_TD3/////GPIO4_IO1573
GND75
ECSPI1_SCLK/UART3_RX//I2C1_SCL///SAI7_RXFS/////GPIO5_IO0677
ECSPI1_SS0/UART3_RTS_B//I2C2_SDA///SAI7_TXFS/////GPIO5_IO0979
ECSPI1_MISO/UART3_CTS_B//I2C2_SCL///SAI7_RXD0/////GPIO5_IO0881
ECSPI1_MOSI/UART3_TX//I2C1_SDA///SAI7_RXC/////GPIO5_IO0783
UART2_RX/ECSPI3_MISO///GPT1_COMPARE3/////GPIO5_IO2485
UART3_RX/UART1_CTS_B//SD3_RESET_B///GPT1_CAPTURE2////FLEXCAN2_TX/////GPIO5_IO2687
UART3_TX/UART1_RTS_B//SD3_VSELECT///GPT1_CLK////FLEXCAN2_RX/////GPIO5_IO2789
SAI3_RXD0/SAI2_RXD3//SAI5_RXD0////UART2_RTS_B/////GPIO4_IO30//////PDM_BIT1/*/HPLOUT2
SAI3_TXC/SAI2_TXD2//SAI5_RXD2///GPT1_CAPTURE1////UART2_TX/////GPIO5_IO00//////PDM_BIT2/*/HPROUT4
SAI3_RXFS/SAI2_RXD1//SAI5_RXFS///SAI3_RXD1////SPDIF1_IN/////GPIO4_IO28//////PDM_BIT0/*/HPOUTFB6
SAI3_RXC/SAI2_RXD2//SAI5_RXC///GPT1_CLK////UART2_CTS_B/////GPIO4_IO29//////PDM_CLK/*/LINEIN1_LP8
SAI3_TXFS/SAI2_TXD1//SAI5_RXD1///SAI3_TXD1////UART2_RX/////GPIO4_IO31//////PDM_BIT3/*/LINEIN1_RP10
AGND12
SAI3_TXD0/SAI2_TXD3//SAI5_RXD3///GPT1_CAPTURE2////SPDIF1_EXT_CLK/////GPIO5_IO01//////BOOT_MODE5/*/DMIC_CLK14
SAI3_MCLK/PWM4_OUT//SAI5_MCLK////SPDIF1_OUT/////GPIO5_IO02//////SPDIF1_IN/*/DMIC_DATA16
GND18
ECSPI2_MOSI/UART4_TX//I2C3_SDA///SAI7_TXD0/////GPIO5_IO1120
ECSPI2_MISO/UART4_CTS_B//I2C4_SCL///SAI7_MCLK////CCM_CLKO1/////GPIO5_IO1222
ECSPI2_SCLK/UART4_RX//I2C3_SCL///SAI7_TXC/////GPIO5_IO1024
ECSPI2_SS0/UART4_RTS_B//I2C4_SDA////CCM_CLKO2/////GPIO5_IO1326
GPIO1_IO02/WDOG1_WDOG_B///ISP_FLASH_TRIG_0/////WDOG1_WDOG_ANY///////SJC_DE_B28
I2C2_SDA/ENET_QOS_1588_EVENT1_OUT//SD3_WP///ECSPI1_SS0/////GPIO5_IO1730
I2C2_SCL/ENET_QOS_1588_EVENT1_IN//SD3_CD_B///ECSPI1_MISO////ENET_QOS_1588_EVENT1_AUX_IN/////GPIO5_IO1632
SAI5_RXFS/SAI1_TXD0//PWM4_OUT///I2C6_SCL/////GPIO3_IO1934
SAI5_RXD0/SAI1_TXD2//PWM2_OUT///I2C5_SCL////PDM_BIT0/////GPIO3_IO2136
SAI5_RXD2/SAI1_TXD4//SAI1_TXFS///SAI5_TXC////PDM_BIT2/////GPIO3_IO23//////FLEXCAN1_RX38
SAI5_RXC/SAI1_TXD1//PWM3_OUT///I2C6_SDA////PDM_CLK/////GPIO3_IO2040
SAI5_RXD1/SAI1_TXD3//SAI1_TXFS///SAI5_TXFS////PDM_BIT1/////GPIO3_IO22//////FLEXCAN1_TX42
SAI5_RXD3/SAI1_TXD5//SAI1_TXFS///SAI5_TXD0////PDM_BIT3/////GPIO3_IO24//////FLEXCAN2_TX44
SAI5_MCLK/SAI1_TXC//PWM1_OUT///I2C5_SDA/////GPIO3_IO25//////FLEXCAN2_RX46
SAI2_RXFS/SAI5_TXFS//SAI5_TXD1///SAI2_RXD1////UART1_TX/////GPIO4_IO21//////PDM_BIT248
SAI2_RXC/SAI5_TXC///FLEXCAN1_TX////UART1_RX/////GPIO4_IO22//////PDM_BIT150
SAI2_TXFS/SAI5_TXD1//ENET_QOS_1588_EVENT3_OUT///SAI2_TXD1////UART1_CTS_B/////GPIO4_IO24//////PDM_BIT252
SAI2_MCLK/SAI5_MCLK//ENET_QOS_1588_EVENT3_IN///FLEXCAN2_RX////ENET_QOS_1588_EVENT3_AUX_IN/////GPIO4_IO27//////SAI3_MCLK54
SAI2_TXC/SAI5_TXD2///FLEXCAN1_RX/////GPIO4_IO25//////PDM_BIT156
SAI2_RXD0/SAI5_TXD0//ENET_QOS_1588_EVENT2_OUT///SAI2_TXD1////UART1_RTS_B/////GPIO4_IO23//////PDM_BIT358
SAI2_TXD0/SAI5_TXD3//ENET_QOS_1588_EVENT2_IN///FLEXCAN2_TX////ENET_QOS_1588_EVENT2_AUX_IN/////GPIO4_IO26//////BOOT_MODE460
SAI1_RXD3/SAI5_RXD3///PDM_BIT3////ENET1_MDIO/////GPIO4_IO0562
SAI1_TXFS/SAI5_TXFS////ENET1_RGMII_RX_CTL/////GPIO4_IO1064
SAI1_RXD6/SAI6_TXFS//SAI6_RXFS////ENET1_RGMII_RD2/////GPIO4_IO0866
SAI1_RXD7/SAI6_MCLK//SAI1_TXFS///SAI1_TXD4////ENET1_RGMII_RD3/////GPIO4_IO0968
SAI1_TXD0/SAI5_TXD0////ENET1_RGMII_TD0/////GPIO4_IO1270
SAI1_TXC/SAI5_TXC////ENET1_RGMII_RXC/////GPIO4_IO1172
SAI1_TXD4/SAI6_RXC//SAI6_TXC////ENET1_RGMII_TX_CTL/////GPIO4_IO1674
SAI1_TXD7/SAI6_MCLK///PDM_CLK////ENET1_TX_ER/////GPIO4_IO1976
SAI1_TXD2/SAI5_TXD2////ENET1_RGMII_TD2/////GPIO4_IO14//////BOOT_MODE078
SAI1_TXD6/SAI6_RXFS//SAI6_TXFS////ENET1_RX_ER/////GPIO4_IO1880
SAI1_MCLK/SAI5_MCLK//SAI1_TXC////ENET1_TX_CLK_IN,ENET_REF_CLK_ROOT_OUT/////GPIO4_IO2082
GND84
UART2_TX/ECSPI3_SS0///GPT1_COMPARE2/////GPIO5_IO2586
UART1_RX/ECSPI3_SCLK/////GPIO5_IO2288
UART1_TX/ECSPI3_MOSI/////GPIO5_IO2390
BOOT_CFG01GP_LED1/CSI_P2_TRIGBOOT_CFG00CSI_BUF_EN_BBOOT_CFG02GP_LED3BOOT_CFG04SW_BACKBOOT_CFG09SW_HOMEBOOT_CFG05PCIe_1_nRSTBOOT_CFG13GP_LED4BOOT_CFG11SW_VOLDN
CSI_P2_OPTCSI_P1_RST_B
SOM used w/"WBD" [ ]
QSPIB_DATA3 [ ]QSPIB_DATA2 [ ]QSPIB_DATA0 []QSPIB_DQS [ENET_MDIO]QSPIB_DATA1 []QSPIB_SCLK []QSPIB_SS0_B []
QSPIA_DATA1 [QSPIA_DATA1_1V8]QSPIA_SS0_B [QSPIA_SS0_B_1V8]
GPIO3_IO16 [ ]QSPIA_DQS [QSPIA_DQS_1V8]QSPIA_SCLK [QSPIA_SCLK_1V8]
GPIO3_IO18 [ ]GPIO3_IO17 [ ]
QSPIA_DATA3 [QSPIA_DATA3_1V8]QSPIA_DATA0 [QSPIA_DATA0_1V8]QSPIA_DATA2 [QSPIA_DATA2_1V8]
BOOT_CFG03 CAPTOUCH_RSTnCSI_P2_SYNC
BOOT_CFG06 CSI_P1_PWRENBOOT_CFG07 CSI_P2_PWRENBOOT_CFG08 CSI_P2_RST_B
CSI_P1_OPTBOOT_CFG12 CSI_P1_TRIGBOOT_CFG15 PCIe_2_nRSTBOOT_CFG10 GP_LED2BOOT_CFG14 SW_VOLUP
CSI_P1_SYNC
SOM used w/"LD" [ ]SOM used w/"WBD"
RTC_IRQn
CAP_TOUCH_INTnCAN_CS_BUSB1_TYPEC_INTnRES_TOUCH_PENIRQn
CAN_INT_BSOM used w/"WBD" [ ]HDMI_SW_GPU_SELLVDS_PWM
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
04. Power, RTC,Board ID
OD O/P
EN > 1.6V = Logic High
RESET & WATCHDOG
3.3V/3A BASE
ASSY OPTION
5VDC/4A POWER JACK
3.45V/3A FROM PWR JACK
FAN : 5V/0.2ASD POWER
DISCHARGE FET
POWER SW/(ON/OFF)
1.8V/0.3A BASE
CB 5V
30V/ms Slewrate based on int. circuitryIlim ~5AImon ~ 2.5V @Iout=5ADMODE Not usedVin < 5.5V Vout @ Imax = 5.2V
PWR JACK 5V IN OVP/OCP
RTC BATTERY
Notes:1. SOM RTC (SOM_SNVS_3V3 domain) consumes about 5mA vs. 1uA on ISL120572. Does not recommend using iMX8M RTC circuitry
BOARD ID
3.3V FROM SOM
SOM PWR
(3.3-1.2)*0.35=0.7W 0.35A estimated2HS+1SS USB
USB3 HUB POWER
POR_B is typically driven by the PMIC. If areset button is used, it should be connected to theenable pin of the PMIC and/or other powersupply chips instead of directly connected toPOR_B pin of the CPU. Note that when POR_Bis asserted (low) on the i.MX8, outputPMIC_ON_REQ remains asserted (high)
90K PU
Equ. PU 17.35K
NOTE:1. SOM_NVCC_3V3 output from SOM, powers it's GPIOs2. SOC I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This can cause internal latch-up and malfunctions due to reverse current flows.3. PMIC_ON_REQ used to shut custom board by SOC before SOM_NVCC_3V3(SOM VDDIOs Int. power) .4. PMIC_ON_REQ measure >=2.5V w/R47 > 68K - DT8M PMIC_ON_REQ measure 1.85V w/R47 > 68K - DT8M-Mini5. BASE_PER_3V3 should rise >5ms after SOM_NVCC_3V3 for backflow prevention and boot config latch.
CT=VDD RSTn delay 180ms to 420ms Need to allow RC delay on SOM to dischargeSOM requires >130ms for PS ctrl RCs to reach 0V
PMIC_ON_REQ USED TO TURN OFF Custom 3.3V 3.3V on DT8M 1.8V on DT8M-Mini
Vth>=2.79V
SENSE:>2.79V ~370ms after NVCC_SNVS_3V3
Note: Need to ensure 1.2V rise before OR with 3.3V
Idd < 6uA
Note: Will prevent back flow into an unpowered IO pin.
3.3V FROM SOM
CURRENT MEASURMENT RESISTOR R0603
3.0V:3.6V TO SOM
Voltage divider w/TPS3808G01
SOM SNVS
PMIC_STBY_REQCAN BE USED TO SHUT BASE POWERIN STANDBY MODE
Supply to mPCIe Slot 2
1.5V/0.3A #2 BASE
Supply to mPCIe Slot 1
1.5V/0.3A #1 BASE
R145 21K=3.4V / 20.3K = 3.5V / 20.5K=3.45V / 18K=3.8V 6.8uH + 1M RT For EMI consideration
REMOTE FEEDBACKREQUIRED FOR LONG POWER LINES
CURRENT MEASURMENT RESISTOR R1210
NOT REQUIRED FOR DART-MX8M-MINI
GND
GND
GND
GND
BASE_PER_3V8
GND
GND
GND
VCC_5V
GND
SOM_VBAT
SW_3P3_SD2
GND
GND
BASE_PER_3V8
GND
VCC_PJ_IN
BASE_PER_1V8BASE_PER_3V3
GND
VCC_5V BASE_PER_3V3
GND
GND
GND
GND
VCC_5V
GND
GND
GND GND
BASE_PER_3V3
BASE_PER_3V3
BASE_PER_3V3
GND
GND
GND
GND
GND
VCC_PJ_INVCC_5V_PJ
GND
GND
GND
SOM_NVCC_3V3
USB3_HUB_3V3BASE_PER_3V3
USB3_HUB_1V2
GND
GND
GND
NVCC_SD2_1V8_3V3
GND
VCC_5V_PJ
GND
SOM_VBAT_3V3 SOM_SNVS
SOM_NVCC_3V3
SOM_SNVSSOM_VBAT
GND
SOM_VBAT_3V3 SOM_SNVS
GND
VCC_5V BASE_PER_3V8
BASE_PER_3V3 BASE_PER_1V5#1 BASE_PER_3V3 BASE_PER_1V5#2
GND GNDGND GND
VCC_5V_PJ
BASE_PER_3V8 BASE_PER_3V3
BASE_PER_1V8
BASE_PER_1V5#2
BASE_PER_1V5#1
SOM_NVCC_3V3
SW_3P3_SD2
USB3_HUB_1V2
VCC_5V
VCC_5V
SOM_VBAT
CONN_SD2_nRST
SW_RSTnI2C2_SDA
I2C2_SCL
PMIC_ON_REQ
GPIO1_IO02(nWDOG)
PMIC_ON_REQ
GPIO1_IO15
I2C2_SDAI2C2_SCL
PMIC_STBY_REQ
PMIC_ON_REQ
PMIC_STBY_REQ
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project1.4D-R2.1
04. Power, RTC,Board ID
A2
8 17Wednesday, December 23, 2020Oded A. VPC0331
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project1.4D-R2.1
04. Power, RTC,Board ID
A2
8 17Wednesday, December 23, 2020Oded A. VPC0331
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project1.4D-R2.1
04. Power, RTC,Board ID
A2
8 17Wednesday, December 23, 2020Oded A. VPC0331
C1572.2uF 50V
R11047K C112
100nF
U23
ISL12057IUZ
Vcc8
GND4
XI1
XO2
IRQ2#3
SDA5
SCL6
Fout7
C1081uF
R73 1M
R1430R
NC
L2
6.8uH
1 2
J4DC 2.0mm
1234
C117
2.2uF
U12
TLV70218DBVR
VIN1
EN3
GND2
VOUT5
NC4
U31
TPS25942ARVCT
DMODE1
PGOOD2
PGTH3
OUT14
OUT25
OUT36
OU
T4
7
OU
T5
8
IN5
9
IN4
10
IN311
IN212
IN113
EN/UVLO14
OVP15
GND16
ILIM
17
dV
dT
18
IMO
N1
9
F/L
/T/
20
EP
21
C46
4.7uF
R1300R
Q1FDV301N
NC
1
32
C11533nF
NC
C14510nFNC
C135
560pFC441uF
TP_PS6
TP_PS12
R14010K
SW8
5MS1S102AM6QES
R14947K
Q32N7002P
3
1
2R15 0.0R
R1210_v2
D27TPD1E10B09DPYR
C144
100nF
R133 1M
R1080R
U11
RT8070ZQW
COMP1
SS2
EN3
VIN4
LX5
RT6
FB7
PGOOD8
GND9
R861M
J24
HDR2.54_2x1_Shrouded
NC
12
C96560pF
D1730V,100mA
C451uF
C174470pF
R17218K 1%
C119
100nF
R146100K
U21
RT8070ZQW
COMP1
SS2
EN3
VIN4
LX5
RT6
FB7
PGOOD8
GND9
R151100K
NC
R10521.5K 1%
TP_PS9
R7268K 1%
R167 0.0RR1210_v2
NC
U5
TLV70215DBVR
VIN1
EN3
GND2
VOUT5
NC4
R81120R 1%
C68
10uF
D34
R16410KNC
FB5
120R 1.2A
C118
10uF
U28
TLV1117LV12DCYR
GN
D1
VIN3
VOUT2
VOUT4
C1074.7uF
C581uF
TP_PS11
D2630V,100mA
R183
510R
R6921.5K 1%
D24BAT54C
1
3
2
R47100K
R184
510R
TP_PS13
C147
10uF
D930V,100mA
ADD= 0xAx
'1' = WP
U15BR24G04NUX-3TTR
A01
A12
A23
VSS4
SDA5SCL6WP7VCC8
PA
D9
Y2
32.768KHz12
C132
10nF
D30
PGB1010603MR
C129
100nF
NC
TP_PS8
U6
TLV70215DBVR
VIN1
EN3
GND2
VOUT5
NC4
TP_PS7R17910K
D35
FB1
120R 1.2A
C69
10nF
TP_PS5
TP_PS10
R5733K
TP_PS4
R141
2.2K 1%
R14449.9R 1%
J40
2 Pin Terminal Block
NC12
JBT1CR1225-HOLDER
+1
-3
++
2
R80100K
R1320R
R40200K
C140
4.7uF
TP_PS3
C105
47uF
12
Q6
TPS27081A
1
3
26
5
4
R1040R
TP_PS2
TP_PS1
D23
30V,100mA
R17886.6K 1%
C63
47uF
12
R17617.8K 1%
C971uF
R139
10K
SOT23-6
U13
TPS3808G30DBVT
SENSE5
CT4
MR3
VC
C6
VS
S2
RST1
D1830V,100mA
R142
68K 1%
L1
6.8uH
1 2
C78
47uF1
2
R119100K
C143
4.7uF
R145
20.5K 1%
C85
560pF C106
47uF
12
C10
100nF
R1370R
NC
R118100K
NC
C89
47uF
12
C47
4.7uF
WD_SENSE
SS_U10
RT_U10
PG_U10
L_U10
FB_U10
CMP_U10
FAN_PWRSD2_PWR_EN
SD2_DIS
SS_U32
RT_U32
L_U32
FB_U32
CMP_U32PG_U32
VOVP_SET
COIN_IN
VCC_RTCRTC_IN
XI
XO
EN_U10
WD_MRn
MAIN_nRST
nWDOG_C
RST_CT
SW_RST_R
RTC_IRQn RTC_IRQn
WD_SENSE
BASE_EN
BASE_EN
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RJ45
DDR 50 Mhz
Headphones
Line In
Gigabit Ethernet2uSD CARD
AUDIO
DIGITAL MIC
Fed via FETFor Reset Func.
<300mA
05. ETH, uSD, AUDIO, MIPI-CSIGiga Ethernet Differential Pair,Follow Giga Ethernet routingguidelines.Differential Impedance: 100 ohms
LAYOUT NOTE:
CODEC HPOUTFB need to short with AGND on connector
LAYOUT NOTE:
PU included on SOM - Not a must.
Differential Impedance:100 ohms SE 50 ohms
Connects to Variscite Custom MIPI-CSI2 Camera Board Qualified with x2 OV5640.
Edge connector footprint
NOTE:
MIPI-CSI0 + MIPI-CSI1 HS mode: DIFFLP mode: SELane rate 1.5Gbps
1. I2C and GPIO run @ 1.8V 2. Camera reference clock generated on camera board
LAYOUT NOTE:
PU 10K IN TXS0104
PU included in TXS0103
Place close to SOM connector
LAYOUT NOTE:
SDR104
Optional Anlaog Mic BiasNot qualified!
To Camera
From Camera
To Camera
Note: Camera control signals shared with HeaderTo use on the header disable buffer.
3.3V tolerant input
Note:R185 short and R186 can be removed manually to test DART-MX8M-MINIPDM
NOTE: In case no "EC" on SOM Must feed NVCC_ENET with either 1.8/2.5/3.3V
Note for U40 + R65 (Applicable for DART-MX8MP only):SAI1 and SAI5 IO power are fed from 1.8V during power up phase until U-BOOT initialize internal LDO setting SAI1 and SAI5 IO power to the required level (1.8V to 3.3V) per custmer interface.
During this phase drivers with low output impedance MUST NOT drive SAI1 and SAI5 IOs High.U40 is the only driver connected directly to SAI1 IO's and without R65 to disable it, have the potential to drive High level during power up phase.
SW_3P3_SD2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AGND
GND GND
GND GNDAGND
GND
BASE_PER_3V3
NVCC_SD2_1V8_3V3
BASE_PER_3V3 BASE_PER_3V3
BASE_PER_1V8 BASE_PER_1V8
GND GND
BASE_PER_1V8 BASE_PER_3V3
GND
GND
BASE_PER_1V8
SOM_VDD_PHY_1V8
NVCC_SD2_1V8_3V3
BASE_PER_3V3 BASE_PER_1V8
GND
BASE_PER_3V3 BASE_PER_1V8
GND
GND
GND
BASE_PER_3V3
GND GND
NVCC_ENET
GND
LED_ACT
LED_LINK10_100
LED_LINK1000
HPLOUT
HPROUT
LINEIN1_RP
LINEIN1_LP
DMIC_CLK
DMIC_DATA
HPOUTFB
ETH_TRX1_PETH_TRX1_N
ETH_TRX0_NETH_TRX0_P
ETH_TRX2_PETH_TRX2_N
ETH_TRX3_PETH_TRX3_N
CONN_SD2_DATA2
CONN_SD2_DATA1
CONN_SD2_DATA3
CONN_SD2_DATA0
CONN_SD2_CD_B
CONN_SD2_CMD
CONN_SD2_CLK
CSI_P1_DP0CSI_P1_DN0
CSI_P1_CKPCSI_P1_CKN
CSI_P1_DP1 CSI_P2_DN3
CSI_P1_DN1 CSI_P2_DP3
CSI_P1_DP2 CSI_P2_DN2
CSI_P1_DN2 CSI_P2_DP2
CSI_P1_DP3 CSI_P2_DN1
CSI_P1_DN3 CSI_P2_DP1
CSI_P2_CKNCSI_P2_CKP
CSI_P2_DN0CSI_P2_DP0
I2C2_SDA
I2C2_SCLI2C4_SDA
I2C4_SCL
SAI1_RXD6(GPIO4_IO08)
SAI1_RXD7(GPIO4_IO09)
UART4_RXD(GPIO5_IO28)
UART4_TXD(GPIO5_IO29)
SAI1_MCLK(GPIO4_IO20)
SAI1_TXFS(GPIO4_IO10)SAI1_TXC(GPIO4_IO11)
SAI1_TXD0(GPIO4_IO12)
SAI1_TXD4(GPIO4_IO16)
SAI1_RXD0(GPIO4_IO02)
SAI1_RXD1(GPIO4_IO03)
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
05. ETH, uSD, AUDIO, MIPI-CSI
A3
9 17Thursday, December 24, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
05. ETH, uSD, AUDIO, MIPI-CSI
A3
9 17Thursday, December 24, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
05. ETH, uSD, AUDIO, MIPI-CSI
A3
9 17Thursday, December 24, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
D29IP4220CZ6
4
25
3
16
C133
100nF
Green
Orange
Yellow
J5
RTA-164AAK1A
L1Y-
L2Y+
L4G_O_2
L3G_O_1
TR1+R1
TR1-R2
TR2+R3
TR2-R4
TR3+R7
TR3-R8
TR4+R9
TR4-R10
SH1SH1
SH2SH2
TRCT1R5
TRCT2R6
C124
470pF
J9
uSD Connector
CD/DAT32 CMD3 VDD4 CLK5 VSS6 DAT07
DAT21
DAT18
SHL10
SHL13
CD9
SHL11SHL12
R62 4.7K
C10010uF
C114
100nF
R109 0R
VCCA<= VCCB
U8
TXS0104ERGYR
VCCA1
A12
A23
A34
A45
NC06
GND7
OE8 NC1
9B410B311B212B113VCCB14
EP15
C120
470pF
C155
4.7uF
R605.6K 1%
NC
J22
STEREO JACK12
3
C84
220pF
C10110uF
C123
100nF
VCC
GND
U43
SN74LV1T125DCKR
1
2
3 4
5
R12522R 1%
C65100nF
U32
SPM0423HD4H-WB
VDD6
L/R2
GND3
GND1
DATA5
CLK4
R16810KNC
D28IP4220CZ6
4
25
3
16 R123120R 1%
C121
470pFR17310K
R82 2.2K 1%NC
'0'-B->A
U41SN74AVC4T245
VCCA1
1DIR2
2DIR3
1A14
1A25
2A16
2A27
GND8
GND92B2102B1111B2121B1132OE#141OE#15VCCB16
PA
D17
C178100nF
C156
100nF
J21
STEREO JACK12
3
TP1
R186
475R 1%
'0'-B->A
U40SN74AVC4T245
VCCA1
1DIR2
2DIR3
1A14
1A25
2A16
2A27
GND8
GND92B2102B1111B2121B1132OE#141OE#15VCCB16
PA
D17
J11HSEC8-130-01-SM-DV-A-MATING
13579
11131517192123252729313335373941434547495153555759
24681012141618202224262830323436384042444648505254565860
VCC
GND
U42
SN74LV1T125DCKR
1
2
3 4
5
D15
TP
D1
E1
0B
09
DP
YR
R1310R
R6510K
C125
10uF
R85 4.7K
R150 0R
R985.6K 1%
NCC98
220pF
C48100nF
D22
TP
D1
E1
0B
09
DP
YR
C122
100nF
C1411uF
R122120R 1%
C1671nF 2KV
D19
TP
D1
E1
0B
09
DP
YR
R63 2.2K 1%NC
C177100nF
D25
TP
D1
E1
0B
09
DP
YR
C176100nF
R1850RNC
R195475R 1%
R3022R 1%
C142
100nF
R13822R 1%
ETH_TRCT1ETH_TRCT2
CONN_SD2_CLK_R
CONN_SD2_DATA2
LINEIN1_LP_C
LINEIN1_RP_C
LLINEIN_C
HPLOUT_C
HPROUT_C
RLINEIN_C
CONN_SD2_DATA0
CONN_SD2_CLK_R
CONN_SD2_CMD
CONN_SD2_DATA3
I2C4_SDA_1V8I2C4_SCL_1V8
CSI_P2_PWREN_1V8CSI_P2_RST_B_1V8CSI_P2_OPT_1V8CSI_P2_SYNC_1V8
CSI_P2_TRIG_1V8
CSI_P1_TRIG_1V8
CSI_P1_SYNC_1V8CSI_P1_OPT_1V8CSI_P1_RST_B_1V8CSI_P1_PWREN_1V8
I2C2_SCL_1V8I2C2_SDA_1V8
I2C2_SDA_1V8I2C2_SCL_1V8I2C4_SDA_1V8I2C4_SCL_1V8
CSI_P1_PWREN_1V8
CSI_P2_PWREN_1V8
BOOT_CFG06CSI_P1_PWREN
BOOT_CFG07CSI_P2_PWREN
CONN_SD2_DATA1
CONN_SD2_CD_B
CSI_P1_RST_B
CSI_P2_OPT
CSI_P1_SYNC CSI_P1_SYNC_1V8
CSI_P2_SYNC_1V8CSI_P1_OPT_1V8
CSI_P2_OPT_1V8
CSI_P2_RST_B_1V8
CSI_P1_RST_B_1V8
CSI_P2_TRIG_1V8
CSI_P1_TRIG_1V8
CSI_P2_SYNCCSI_P1_OPT
BOOT_CFG08CSI_P2_RST_BBOOT_CFG12CSI_P1_TRIG
BOOT_CFG00CSI_BUF_EN_B
BOOT_CFG01GP_LED1/CSI_P2_TRIG
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDMI PORT
LAYOUT NOTE:DifferentialImpedance:100 ohms
Level Shifting Bias
Runs from Int. 3.3V LDOfed by VCC(5V0)
See IP4786CZ32 DS PP23 for CEC_STBY pin strapping
06. HDMI, eDP
DifferentialImpedance:100 ohms
LAYOUT NOTE:
HDMI 2.0a specification (HDMI.org)DisplayPort 1.3 standard (VESA.org)Embedded DisplayPort 1.4 standard
HDMI PORT+ Level Termination
Compatible PN:DIODES: NX5427001ZMICROCHIP: DSC1104/24
AC coupled differential low swing clock (HCSL levels)
HDMI REFCLK for DART-MX8M Only!
HDMI/eDP/DP SWITCH
ONLY ESD
DP PORT
SEL:L = A (HDMI)H = B (eDP/DP)GPU_SEL = Sel data tunneling
HEAC: As of HDMI 1.4+ (HDMI Ethernet Channel and Audio Return Channel)
Power with CEC_STBY = HIGH is 3mW (DDC + CEC idle / no current on HDMI_5V0_CON)
Power with CEC_STBY = LOW is 1mW
DP port
Note : HDMI pull down must not be applied until VDD_PHY_1V8 is up. Implemtation uses fact that BASE_PER_3V3 rises after all SOM power rails are up.At boot time GPIO drives U3 switch to B state.
LAYOUT NOTE:Place close to SOM connector
GPIO1_IO05After reset default PD 90K enabled in SOCSHOULD BE DRIVEN BY DTSH = OFF : DP/eDP L = ON : HDMI
R26 PU should ensure SOC HDMI lines are not loaded with 604Ohm termination prior to HDMI PHY powered. TI: TS3DV621
Note: Required for demonstration purposes only.
DART-MX8M VS. DART-MX8M-PLUSHDMI AC COUPLING AND LEVEL TERMINATION PORT
DART-MX8M: NXP design requires AC coupling and level termination on HDMI path;DART-MX8MP: NXP reference requires DC coupling with no level termination;
Current design, as DC coupled and no termination, testedok with resolutions up to 4K with DART-MX8M HDMI and DP path;
Customers designing for DART-MX8M should include C72-C75 C79-C82 as 100nF and R16-R19 R21 R25 R27 R29 as 604 Ohm
NOTE:
GND
GND
GND
GND
VCC_5V
GND GND
GND
GND
BASE_PER_3V3
BASE_PER_3V3
GND
GND GND
GND
GND GNDGND
GND GND
BASE_PER_3V3
BASE_PER_3V3
GND
BASE_PER_3V3
GND
GND
BASE_PER_3V3
GND
GND
BASE_PER_3V3
GND
HDMI_DDC_SCLHDMI_DDC_SDA
HDMI_TX2_LN2_P
HDMI_TX2_LN2_N
HDMI_CLK_LN3_P
HDMI_CLK_LN3_N
HDMI_TX1_LN1_P
HDMI_TX1_LN1_N
HDMI_TX0_LN0_P
HDMI_TX0_LN0_N
HDMI_CEC
HDMI_REFCLKP
HDMI_HPD
HDMI_AUXPHDMI_AUXN
GPIO1_IO05
HDMI_REFCLKN
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
06. HDMI , eDP
A3
10 17Wednesday, December 23, 2020Oded A. VPC0331 <Approved By>
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
06. HDMI , eDP
A3
10 17Wednesday, December 23, 2020Oded A. VPC0331 <Approved By>
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
06. HDMI , eDP
A3
10 17Wednesday, December 23, 2020Oded A. VPC0331 <Approved By>
VAR-DT8MCustomBoard
C730R
R27604 1%
NC
U4TPD4EUSB30
D1+1
D1-2
GND3
D2+4
D2-5
NC110
NC29
GND8
NC37
NC46
R441M
R37100K
C51
100nF
R25604 1%
NC
TP16
C222.2uF,0402,10V, X5R
C29
100nF
C50100nF
R21604 1%
NC
R39100K
C800R
C41
1uF
C49100nF
R19604 1%
NC
R38
100K
U3
PI3WVR12412ZHE
GN
D1
1
GPU_SEL2
D0-3
D0+4
DDC/AUX_HPD_SEL5
D1-6
D1+7
D2-8
D2+9
D3-10
D3+11
VD
D1
12
SDA/AUX-13
SCL/AUX+14
HPD_B15
HPD_A16
GN
D2
17
HPD18
SDA_B/AUX-_B19SCL_B/AUX+_B20
VD
D2
21
GN
D3
22
SCL_A/AUX+_A23SDA_A/AUX-_A24
OE25
D3+B26D3-B27
D2+B28D2-B29
D1+B30D1-B31
D0+B32D0-B33
VD
D3
34
D3+A35D3-A36
D2+A37D2-A38
D1+A39D1-A40
D0+A41D0-A42
GN
D_E
P43
C720R
R6849.9R 1%
NC
HCSL
OSC2
DSC1104CE2-027.0000T
VCC6
GND3
Q4
Q5
NC2
OE1
R18604 1%
NC
C11
100nF
C790R
R6749.9R 1%
NC
R102100K
R17604 1%
NC
C820R
U2
IP4786CZ32
TMDS_D2+1
TMDS_D2-2
TMDS_D1+3
TMDS_D1-4
TMDS_D0+5
TMDS_D0-6
TMDS_CK+7
TMDS_CK-8
DD
C_C
LK
_S
YS
9
DD
C_D
AT
_S
YS
10
TMDS_CK-_CON17TMDS_CK+_CON18
TMDS_D0-_CON19TMDS_D0+_CON20
TMDS_D1-_CON21TMDS_D1+_CON22
TMDS_D2-_CON23TMDS_D2+_CON24
VC
C(5
V0)
11
HP
D_C
ON
12
HD
MI_
5V
0_C
ON
13
DD
C_D
AT
_C
ON
14
DD
C_C
LK
_C
ON
15
UT
ILIT
Y_C
ON
16
CE
C_C
ON
25
ES
D_B
YP
SS
26
VC
C(S
YS
)27
CE
C_S
TB
Y28
CE
C_S
YS
29
NC
230
NC
131
HP
D_S
YS
32
GN
D_P
AD
33
C750R
R16604 1%
NC
R24
100KNC
C99
100nF
C810R
C740R
J20DP1RD20JQ1R400
LANE 0 _P1
GND2
LANE 0 _N3
LANE 1 _P4
GND5
LANE 1 _N6
LANE 2 _P7
GND8
LANE 2 _N9
LANE 3 _P10
GND11
LANE 3 _N12
CONFIG113
CONFIG214
AUX CH _P15
GND16
AUX CH _N17
HOT PLUG_DET18
3.3V RETURN19
3.3V20
ME
CH
1M
EC
H1
ME
CH
2M
EC
H2
ME
CH
3M
EC
H3
ME
CH
4M
EC
H4
U9TPD4EUSB30
D1+1
D1-2
GND3
D2+4
D2-5
NC110
NC29
GND8
NC37
NC46
U7TPD4EUSB30
D1+1
D1-2
GND3
D2+4
D2-5
NC110
NC29
GND8
NC37
NC46
C271uF
C70
10uF
J19
HDMI CONN
DAT2+1
DAT2-3
DAT2_S2
DAT1+4
DAT1_S5 DAT1-6
DAT0+7
DAT0_S8 DAT0-9
CLK+10
CLK-12
CLK_S11
CEC13
NC14
SCL15
SDA16
DDC/CEC GND17 +5V18
SHLDMTG2
SHLDMTG3
SHLDMTG4
SHLDMTG1
DET19
R830R
R264.7K
R840R
R411M
C281uF
R187
1M
R29604 1%
PCB Footprint = R0402_v0
NC
HDMI_CON_CK_PHDMI_CON_CK_N
HDMI_5V_CONHDMI_HPD_CON
HDMI_5V_CON
HDMI_SCL_CONHDMI_SDA_CON
HDMI_HPD_AHDMI_CEC_CON
HD
MI_
CE
C_
CO
N
HD
MI_
HP
D_
CO
N
HDMI_CON_D2_NHDMI_CON_D2_P
HDMI_CON_D1_NHDMI_CON_D1_P
HDMI_CON_D0_PHDMI_CON_D0_N
HDMI_D3_P
HDMI_D3_N
HDMI_D2_P
HDMI_D2_N
HDMI_REFCLKP_R
HDMI_HPD/HEAC-_CN
HDMI_Utility/HEAC+_CN
DP_D0_B_PDP_D0_B_N
DP_D1_B_PDP_D1_B_N
DP_D2_B_PDP_D2_B_N
DP_D3_B_PDP_D3_B_N
DP_AUX_B_C_PDP_AUX_B_C_N
DP_HPD_B
HDMI_D3_A_NHDMI_D3_A_P
HDMI_D2_A_PHDMI_D2_A_N
HDMI_D1_A_PHDMI_D1_A_N
HDMI_D0_A_PHDMI_D0_A_N
HDMI_SCL_CONHDMI_SDA_CON
HDMI_HPD_A
DP_HPD_B
DP_AUX_B_PDP_AUX_B_N
DP_AUX_B_C_P
DP_AUX_B_C_N
DP_CFG1DP_CFG2
HDMIeDP_OE
HDMI_D0_A_PHDMI_D0_A_N
HDMI_D1_A_NHDMI_D1_A_P
HDMI_D2_A_NHDMI_D2_A_P
HDMI_D3_A_NHDMI_D3_A_P
DP_D2_B_NDP_D2_B_P
DP_D1_B_NDP_D1_B_P
DP_D0_B_P
DP_D3_B_NDP_D3_B_P
DP_D0_B_N
HDMI_AUX_A_N HDMI_HPD/HEAC-_CN
HDMI_Utility/HEAC+_CNHDMI_AUX_A_P
HDMI_SW_GPU_SEL
HDMI_REFCLKN_R
HDMI_D0_P
HDMI_D0_N
HDMI_D1_P
HDMI_D1_N
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIe 1.1/2.1 compliant with PCIe Express GEN2.2.5/5 Gbps lanes2.0: 8b/10b encoding
PCIe compliant 100MHz OSC with HCSL signaling
Differential Impedance:100 ohmsLAYOUT NOTE:
Layout Note:Place parallel termination resistorsclose to the mPCIe connector
LAYOUT NOTE:PCIE Differential Pairs, Follow PCIe routing guidelines.Differential Impedance: 85 ohmsLength match +/-5mil
Layout Note:Place parallel termination resistorsas close to the SOM connector as possible.
Layout Note Place AC caps close to the connector
mPCIexp CS
1.5V_LDO Current limited to 300mA
O.D. signal
USB2.0 480Mbps
PCIe CLK DIST.
USB UART DEBUG
out
out
in
in
07. PCIe, NAND, USB DEBUG
LAYOUT NOTE:USB 2.0 Differential Pair, annotatedwith a ring around the pair. FollowUSB 2.0 routing guidelines.Differential Impedance: 90 ohms
Layout Note:Place parallel termination resistorsas close to the SOM connector as possible.
Layout Note Place AC caps close to the TX connector
Customboard 5V power supply is limited to 3A, sharedwith Board's USB devices. Do not connect devices which exceed current limitation.
PCIE Differential Pairs, Follow PCIe routing guidelines.Differential Impedance: 85 ohmsLength match +/-5mil
O.D. signal
mPCIexp ON PS
LAYOUT NOTE:
Layout Note:Place parallel termination resistorsclose to the mPCIe connector
1.5V_LDO Current limited to 300mA
Differential Impedance:100 ohms
PCIe compliant 100MHz OSC with HCSL signaling
PCIe CLK DIST.
LAYOUT NOTE:
USB 2.0 Differential Pair, annotatedwith a ring around the pair. FollowUSB 2.0 routing guidelines.Differential Impedance: 90 ohms
LAYOUT NOTE:
USB 2.0 Differential Pair, annotatedwith a ring around the pair. FollowUSB 2.0 routing guidelines.Differential Impedance: 90 ohms
LAYOUT NOTE:
PS mPCIe components placed on CSShare caps with CS mPCIe connector.
Customboard 5V power supply is limited to 3A, sharedwith Board's USB devices. Do not connect devices which exceed current limitation.
QSPI TEST POINTS ON PS
40K PUINT.
40K PUINT.
Install to disable clock.
Remove to Enable clock.
NAND
GND
GND
GND
GND
GND GND
GND
GND
BASE_PER_3V3BASE_PER_1V5#1
BASE_PER_3V3
DEBUG_VBUS_C3V3OUT DEBUG_VBUS
GNDGND
GNDGND GND
GND GND
BASE_PER_3V3
BASE_PER_1V5#2
BASE_PER_3V3
GND
GND
GNDGND
GND
GND
GND GND
SOM_NVCC_3V3
BASE_PER_3V3
GND
GND GND
GND
BASE_PER_3V3
GND
I2C4_SCL
PCIE2_REF_CLKNPCIE2_REF_CLKP
PCIE2_TXN
PCIE2_TXP
PCIE2_RXP
PCIE2_RXN
PCIE1_REF_CLKPPCIE1_REF_CLKN
PCIE1_TXN
PCIE1_TXP
PCIE1_RXN
PCIE1_RXP
USB_mPCIe1_DMUSB_mPCIe1_DP
I2C4_SDA
I2C4_SCLI2C4_SDA
UART1_RXD
SAI1_RXD5(GPIO4_IO07)
USB_mPCIe2_DMUSB_mPCIe2_DP
NAND_CLE NAND_DATA00NAND_ALE NAND_DATA01
NAND_DATA02NAND_DATA03
NAND_CE0_B NAND_DATA04NAND_RE_B NAND_DATA05NAND_WE_B NAND_DATA06
NAND_DATA07NAND_WP_B
NAND_READY_BNAND_DQS
SAI1_TXD7(GPIO4_IO19)
UART1_TXD
NAND_CE2_BNAND_READY_B
NAND_RE_BNAND_CE0_B
NAND_CLENAND_ALE
NAND_WE_BNAND_WP_B
NAND_DATA07NAND_DATA06NAND_DATA05NAND_DATA04
NAND_DQSNAND_DATA03NAND_DATA02NAND_DATA01NAND_DATA00
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
07. PCIe, NAND, USB DEBUG
A2
11 17Wednesday, December 23, 2020Oded A. VPC0331 <Approved By>
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
07. PCIe, NAND, USB DEBUG
A2
11 17Wednesday, December 23, 2020Oded A. VPC0331 <Approved By>
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
07. PCIe, NAND, USB DEBUG
A2
11 17Wednesday, December 23, 2020Oded A. VPC0331 <Approved By>
C21
100uF
QSPIA_DATA3-TP1
R9522R 1%
C37
100nF
J32
MM60-52B1-E1-R650
NC
WAKE#1
COEX13
COEX25
CLKREQ#7
GND19
REFCLK-11
REFCLK+13
GND215
Reserved/UIM_C817
Reserved/UIM_C419
GND321
PERn023
PERp025
GND427
GND529
PETn031
PETp033
GND635
GND1437
+3.3Vaux139
+3.3Vaux241
GND1343
Reserved745
Reserved847
Reserved949
Reserved1051
3.3V_12
GND74
1.5V_16
UIM_PWR8
UIM_DATA10
UIM_CLK12
UIM_RESET14
UIM_VPP16
GND818
W_DISABLE#20
PERST#22
+3.3Vaux24
GND926
1.5V_228
SMB_CLK30
SMB_DATA32
GND1034
USB_D-36
USB_D+38
GND1140
LED_WWAN#42
LED_WLAN#44
LED_WPAN#46
1.5V_348
GND1250
3.3V_252
R1249.9R 1%
FB4120R 1.2A
QSPIB_SS0_B-TP1
C26
100nF
R9722R 1%
C165
100nF
R3
31
0K
NC
U16
AB-557-03-HCHC-F-L-C-T
1OE
2NC_2
3NC_3
4V
SS
5NC_5
6NC_6
7NC_7
8CLK1+
9CLK1-
10CLK0-
11CLK0+
12
VD
D1
13
VD
D0
15
EP
14NC_14
QSPIA_DATA2-TP1
C170
100nF
GPIO3_IO16-TP1
R9622R 1%
C25
100nF
C168100nF
U35FT230XQ
TXD15
RTS#16
VC
CIO
1
RXD2
GN
D1
3
CTS#4
CBUS25
CBUS314
CBUS012
CBUS111
GN
D3
VCC10
RESET#9
EP
AD
17
3V
3O
UT
8
USBDM7
USBDP6
C116
2.2uF
C38
4.7uF R3
41
0K
NC
C1
72
22
0n
FN
C
TP3
QSPIA_DATA1-TP1
R1880RNC
QSPIB_DQS-TP1
R949.9R 1%
C111
100nF
C32
100nF
TP8
C1
71
22
0n
FN
C
R1484.7KNC
R3
14
9.9
R 1
%
R2
34
9.9
R 1
%
FB6120R 1.2A
C39
4.7uF
C110
2.2uF
C36
100nF
QSPIA_SS0_B-TP1
QSPIA_DATA0-TP1
C33
100nF
C173
4.7uF
NC
R3
24
9.9
R 1
%
QSPIB_DATA3-TP1
QSPIB_SCLK-TP1C35
100nF
R1204.7K
FB2120R 1.2A
R18210K
U38TPD4EUSB30
D1+1
D1-2
GND3
D2+4
D2-5
NC110
NC29
GND8
NC37
NC46
C12
100uF
RTS
C34
4.7uF
BASE_PER_3V3-TP1
QSPIA_SCLK-TP1
C42
100nF
QSPIB_DATA2-TP1
R1900RNC
GND-TP1
C31
100uF
J23
MM60-52B1-E1-R650
WAKE#1
COEX13
COEX25
CLKREQ#7
GND19
REFCLK-11
REFCLK+13
GND215
Reserved/UIM_C817
Reserved/UIM_C419
GND321
PERn023
PERp025
GND427
GND529
PETn031
PETp033
GND635
GND1437
+3.3Vaux139
+3.3Vaux241
GND1343
Reserved745
Reserved847
Reserved949
Reserved1051
3.3V_12
GND74
1.5V_16
UIM_PWR8
UIM_DATA10
UIM_CLK12
UIM_RESET14
UIM_VPP16
GND818
W_DISABLE#20
PERST#22
+3.3Vaux24
GND926
1.5V_228
SMB_CLK30
SMB_DATA32
GND1034
USB_D-36
USB_D+38
GND1140
LED_WWAN#42
LED_WLAN#44
LED_WPAN#46
1.5V_348
GND1250
3.3V_252
GPIO3_IO17-TP1
R1349.9R 1%
R1049.9R 1%
QSPIB_DATA1-TP1
GPIO3_IO18-TP1
C20
100uF
C130R
C170R
R11422R 1%
C134
2.2uF
C40
100nF U39
MT29F4G08ABADAWP
NC
SE6
R/B7
RE8 CE9
VC
C3
_3
12
GN
D1
13
CLE16
ALE17
WE18
WP19
IO029
IO130
IO231
IO332
GN
D3
6V
CC
3_
32
37
IO441
IO542
IO643
IO744
N22 N11 N4
4
N55
N1414
N1515
N2020
N2121
N2222
N2323
N2626
N33
N2727
N2828
N3
33
3
N3
43
4
N3535
N3838
N3939
N4040N45
45
N4646
N4747
N4848 N10
10
N1111
N2424
N2525
C140R
QSPIB_DATA0-TP1
C160R
R11522R 1%
C169
100nF
C1604.7uF
C18
4.7uF
'0'-B->A
U37SN74AVC4T245
VCCA1
1DIR2
2DIR3
1A14
1A25
2A16
2A27
GND8
GND92B2102B1111B2121B1132OE#141OE#15VCCB16
PA
D1
7
C126
2.2uF
R2
24
9.9
R 1
%
R11722R 1%
QSPIA_DQS-TP1
J10
USB MICRO AB
VCC1
DATAN2
DATAP3
ID4
GND5
S6
S7
S1
1S
10
C162
100nF
C43
100nF
R9422R 1%
U20
AB-557-03-HCHC-F-L-C-T
1OE
2NC_2
3NC_3
4V
SS
5NC_5
6NC_6
7NC_7
8CLK1+
9CLK1-
10CLK0-
11CLK0+
12
VD
D1
13
VD
D0
15
EP
14NC_14
C128
100nF
R11622R 1%
PWR_OSC_PCIE1
PCIE1_REFCLK100M_PPCIE1_REFCLK100M_N
OSC_PCIE1_CLK1_POSC_PCIE1_CLK1_N
OSC_PCIE1_CLK0_NOSC_PCIE1_CLK0_P
PCIE1_REFCLK100M_NPCIE1_REFCLK100M_P
PCIe1_CTXM
PCIe1_CRXPPCIe1_CRXM
PCIe1_CTXP
UART_BRDG_TXDUART_BRDG_RXD
USB_DEBUG_DPUSB_DEBUG_DM
USB_DEBUG_DP_CUSB_DEBUG_DM_C
PWR_OSC_PCIE2
OSC_PCIE2_CLK0_POSC_PCIE2_CLK0_N
OSC_PCIE2_CLK1_P PCIE2_REFCLK100M_P
PCIe2_CRXM
OSC_PCIE2_CLK1_N PCIE2_REFCLK100M_N
PCIe2_CRXP
DART_MX8MP = DSI_D3_NPCIe2_CTXM
DART_MX8MP = DSI_D3_P PCIe2_CTXP
PCIE2_REFCLK100M_PPCIE2_REFCLK100M_N
BOOT_CFG05 PCIe_1_nRST
BOOT_CFG15 PCIe_2_nRST
UART_BRDG_RTSUART_BRDG_CTS
QSPIB_SS0_B []GPIO3_IO16 [ ]QSPIB_DQS [ENET_MDIO] DART_MX8MP = DSI_D0_PQSPIA_SS0_B [QSPIA_SS0_B_1V8]QSPIB_SCLK [] DART_MX8MP = DSI_D1_PQSPIA_SCLK [QSPIA_SCLK_1V8]GPIO3_IO17 [ ] DART_MX8MP = DSI_D2_PGPIO3_IO18 [ ] DART_MX8MP = DSI_D2_N
QSPIB_DATA3 [ ] DART_MX8MP = DSI_CK_NQSPIB_DATA2 [ ] DART_MX8MP = DSI_CK_PQSPIB_DATA1 [] DART_MX8MP = DSI_D1_NQSPIB_DATA0 [] DART_MX8MP = DSI_D0_NQSPIA_DQS [QSPIA_DQS_1V8]QSPIA_DATA3 [QSPIA_DATA3_1V8]QSPIA_DATA2 [QSPIA_DATA2_1V8]QSPIA_DATA1 [QSPIA_DATA1_1V8]QSPIA_DATA0 [QSPIA_DATA0_1V8]
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB3.0 HUB
USB3 SIGNALS Place AC-coupling CAPscloser to transmit side.
Config Channel Logic Detection & Indication of Plug Orientation
USB Profile 1 = 5 V @ 2 A
1 A current limitation due to system powerlimitation of CPU Card + Base Board.
Ilim: 54K ~ 1A68K ~0.85A100K ~0.6A
VBUS DISCHARGE
28V VBUS w/PD
Active Demux
7 kV ESD immunity - HBM
SEL = L : AP - CON2 / CON1 TerminatedSEL = H : AP - CON1 / CON2 Terminated
CH1 Set AP DE/OS/EQ
CH2 Set CON DE/OS/EQ
USB TYPE C OTG
5V Source Load Switch
Need FET to withstand 28V
High ESD protection for VBUS and CC1/2 pins
USB TYPE C OTG
08. USB TYPE C, USB 3 HUB
LAYOUT NOTE:USB 3.0 Differential Pair, annotated with a dashedring around the pair. Follow USB 3.0 routing guidelines.Differential Impedance: 90 ohms
LAYOUT NOTE:USB 2.0 Diff pair, annotated with a ring around the pair. USB 3.0 Diff Pair annotated with dashed ring Follow USB 2.0/3.0 routing guidelines.Differential Impedance: 90 ohms
non-I2C mode= ADR pin float on power up
ADR/CON_DETAccording to DS should be 10K NXP eval 68K ?
Bleeder
1.2V/0.5A3.3V/0.1A
Note:1.2V should rise before or at the same time as 3.3VStraps should be valid >1ms after RST_N negate
Note: If SMCLK and SMDAT Pullups detected by HUBWill go into SMBus Slave mode and must be initialised by host to wake
200K PD = NO BATCHRG10K PD = PRT1+2 BAT CHRG
All Removable
HUB:Out Pwr to host control In Overcurrent flag
If grounded momentarly will initiate bus connect
Vil<0.9VVih>1.9VNegate >1ms after 3.3V
Vil>0.9VVih>1.9V
~7ms RSTn
~170ms 1.9V from 3.3V
5V
Pin 5 max 8VVgsth + >1VVgsth - < 0.4V
33/133 = 0.2480.248 * 5 = 1.24 > 1V Vgs th0.248 * 28 = 6.95 < 8V Pin5 Abs Max28^2 /133K < 6mW
Need to drive USB1_VBUS to 5V even if Vbus>5V
GND=HOST
HOST ONLY ROLE
Ivdd1v8 < 130mA
USB#2 PHY ALWAYS POWERED
USB#2
USB#1
ECO18P011
CIN=3pF
CL=18pF
NOTE for DART-MX8M-PLUS USB*_ID:
Though native USB ID pins are functional they require kernel patches to be supported.NXP will not include the patches in future release and recommends using any GPIO as USB ID function.
Variscite DTS using PTN5150 functionality to achieve USB1 OTG function.
NOTE FOR U33:P/N PTN36043BXY is EOL;New designs should include PTN36043ABXY
GND GND
USB_SS3_VBUS
GND
USB_SS3_VBUS
GND
GND
GND
USB_SS3_VBUS
GND
GND GNDGND
USB_SS3_VBUS
GND
VCC_5V
GND
GNDGND
GND
GND
GND
GND
BASE_PER_3V3
BASE_PER_3V3
BASE_PER_3V3
BASE_PER_1V8
BASE_PER_1V8
BASE_PER_1V8
GND
BASE_PER_3V3
GNDGND
USB3_HUB_1V2 USB3_HUB_3V3
GND
GND
GNDGND
GND
GNDGND
VCC_5V
USB3_HUB_3V3
GND
USB3_HUB_3V3
USB_SS3_VBUS
GND
VCC_5V
GND
GNDGND
USB3_PRT1_PWR
USB3_PRT1_PWR
GND GND
USB3_PRT2_PWR
VCC_5VUSB3_PRT2_PWR
GNDGND
VCC_5V
GND
GND
GND
GND
GND
USB1_ID
GPIO1_IO13(USB1_OTG_OC)
USB1_RXN
USB1_TXN
USB1_TXP
USB1_DP
USB1_DN
USB1_RXP
USB1_VBUS
USB2_VBUS
USB2_RXNUSB2_RXP
USB2_TXNUSB2_TXP
USB2_DPUSB2_DN
USB2_ID
USB_mPCIe1_DMUSB_mPCIe1_DP
I2C2_SDA
I2C2_SCLGPIO1_IO10
USB_mPCIe2_DMUSB_mPCIe2_DP
I2C3_SCL
I2C3_SDA
USB1_ID
USB2_ID
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
08. USB TYPE C, USB3 HUB
A2
12 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
08. USB TYPE C, USB3 HUB
A2
12 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
08. USB TYPE C, USB3 HUB
A2
12 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
C158100nF
Q42N7002P
3
1
2
Q72N7002P
3
1
2
C951uF
C1662.2uF 50V
C0805_v1
R1474.7K
NC
J6
USB3 TYPE C RA
GND_1A1
SSTXP1A2
SSTXN1A3
VBUS_1A4
CC1A5
DP1A6
DN1A7
SBU1A8
VBUS_2A9
SSRXN2A10
SSRXP2A11
GND_2A12
GND_4B1SSTXP2B2SSTXN2B3VBUS_4B4CC2B5DP2B6DN2B7SBU2B8VBUS_3B9SSRXN1B10SSRXP1B11GND_3B12
SH1SH1 SH3
SH3
SH2SH2
SH4SH4
C88
10nF
C153100nF
C86
100nF
R161 2.2K 1%NC
Q52N7002P
3
1
2
R770RNC
C161100nF U26
TPD4EUSB30
D1+1 D1-2 GND3 D2+4 D2-5
NC110NC29GND8NC37NC46
R17110K
C93
10nF
U24
TPD4EUSB30
D1+1 D1-2 GND3 D2+4 D2-5
NC110NC29GND8NC37NC46
R155 2.2K 1%NC
C127
2.2uF
U27
TPD4EUSB30
D1+1 D1-2 GND3 D2+4 D2-5
NC110NC29GND8NC37NC46
U36TPD4EUSB30
D1+1
D1-2
GND3
D2+4
D2-5
NC110
NC29
GND8
NC37
NC46
R17533K
C57
100nF
C52100nF
L4
MCZ1210AH900L2T
1 4
32
U25
TPD4EUSB30
D1+1 D1-2 GND3 D2+4 D2-5
NC110NC29GND8NC37NC46
U22
PTN5150AHXMP
PORT3
VBUS_DET4
ADR/CON_DET5
INTB/OUT36
SDA/OUT17
SCL/OUT28
ID9
GN
D1
0
EXT_SEL11
VD
D1
2
CC11
CC22
D33
TP
D1
E1
0B
09
DP
YR
C13947uF
12
TP14
C54100nF
C53100nF
C941uF
U33
PTN36043BXY
RX_AP_+18
RX_AP_-17
TX_AP_+15
TX_AP_-14 TX_CON_1+
6
TX_CON_1-7
RX_CON_1+2
RX_CON_1-3
TX_CON_2+12
TX_CON_2-11
RX_CON_2+9
RX_CON_2-8
SEL16
CH1_SET1/RXDE1
CH1_SET2/TXEQ4
CH2_SET1/TXDE13
CH2_SET2/RXEQ10
VD
D1
V8
5G
ND
19
C136
100nF
C154100nF
C62
100nF
R16910K
FB3
120R 1.2A
Y1
25 Mhz_TSX3225
1
2
3
4
D31
TP
D1
E1
0B
09
DP
YR
R1660RNC
R1
52
10
K
C83100nF
C159
10uF
C130
2.2uF
R18110K
TP13
R45
12K 1%
C60
4.7uF
R158510R
R12122R 1%
C67
33pF
C77100nF
U34
NX5P3090UKZ
ENA1
FAULTA2
ILIMA3
VINT1B1
VINT2B2
GN
D1
B3
VINT3C1
VBUS1C2
GN
D2
C3
VBUS2D1
VBUS3D2
GN
D3
D3
R1
35
10
K
C61100nF
C76
33pF
R1534.7K
NC
U30
FPF2193
FLAGA1
ENA2 Vout
B1Vin
B2
IsetC1
GNDC2
J8USB3 TYPE A
VBUS1
DATA_M2
DATA_P3
GND4
SS_RXM5
SS_RXP6
GND7
SS_TXM8
SS_TXP9
SH
LD
11
0
SH
LD
21
1
R7910K
C55100nF
R4922R 1%
C151100nF
R162 2.2K 1%
C59
10nF
R76200K
Q2
TPS27081A
1
3
26
5
4
C64100nF
C163100nF
R17768K 1%
R156 2.2K 1%NC
C91
10nF
C152100nF
TP4
C90
100nF
U29
FPF2193
FLAGA1
ENA2 Vout
B1Vin
B2
IsetC1
GNDC2
R1
34
10
K
R170
10K
C137
100nF
R180100K
R42
1.0K 1%
C164100nF
R780RNCR160 2.2K 1%
USB5744/2G
U10
USB2DN_DP1/PRT_DIS_P11USB2DN_DM1/PRT_DIS_M12
USB3DN_TXDP13USB3DN_TXDM14
VD
D1
2_
15
USB3DN_RXDP16USB3DN_RXDM17
USB2DN_DP2/PRT_DIS_P28USB2DN_DM2/PRT_DIS_M29
USB3DN_TXDP210USB3DN_TXDM211
VD
D1
2_
21
2
USB3DN_RXDP213USB3DN_RXDM214
VD
D1
2_
31
5
VD
D3
3_
11
6
USB2DN_DP3/PRT_DIS_P317USB2DN_DM3/PRT_DIS_M318
USB3DN_TXDP319USB3DN_TXDM320
VD
D1
2_
42
1
USB3DN_RXDP322USB3DN_RXDM323
USB2DN_DP4/PRT_DIS_P424USB2DN_DM4/PRT_DIS_M425
USB3DN_TXDP426USB3DN_TXDM427
VD
D1
2_
52
8
USB3DN_RXDP429USB3DN_RXDM430
VD
D3
3_
23
1
PRT_CTL4/GANG_PWR32
VD
D1
2_
63
3
PRT_CTL334
PRT_CTL235
PRT_CTL136
VBUS_DET37
SPI_CLK/SMCLK38
SPI_DO/SMDAT39
SPI_DI/CFG_BC_EN40
SPI_CE_N/CFG_NON_REM41
RESET_N42
VD
D1
2_
74
3
VD
D3
3_
34
4
USB2UP_DP45
USB2UP_DM46
USB3UP_TXDP47
USB3UP_TXDM48
VD
D1
2_
84
9
USB3UP_RXDP50
USB3UP_RXDM51
AT
ES
T5
2
XTALO53
XTALI/CLK_IN54
VD
D3
3_
45
5
RB
IAS
56
VS
S_
EP
AD
57
C87
100nF
C146
10nFC13847uF
12
R165510R
R154 2.2K 1%NC
C66
100nF
R1590RNC
R460R
C148
10nF
C56
100nF
R163 2.2K 1%NC
L5
MCZ1210AH900L2T
1 4
32
R7510K
C131
100nF
C14910uF
C71
100nF
J7USB3 TYPE A
VBUS1
DATA_M2
DATA_P3
GND4
SS_RXM5
SS_RXP6
GND7
SS_TXM8
SS_TXP9
SH
LD
11
0
SH
LD
21
1
C15010uF
R1
36
68
K 1
%
D32PGB1010603MR
L3MCZ1210AH900L2T
1 4
32
R157 2.2K 1%NC
R74200K
C92
100nF
R17410K
R126100K
SS_CON_TX1_N
SS_CON_TX1_P
SS_CON_TX2_P
SS_CON_TX2_N
SS_RX1_PSS_RX1_N
SS_RX2_NSS_RX2_P
SS_TX1_P
SS_TX1_N
SS_TX2_P
SS_TX2_N
USB1_C_TXP
USB1_C_TXN
USB1_C_RXP
USB1_C_RXN
SS_TX1_P
SS_RX2_PSS_RX2_N
SS_RX1_NSS_RX1_P
SS_TX1_N
USB_C_OTG_DPUSB_C_OTG_DN USB_C_OTG_DP
USB_C_OTG_DN
PTN5150A_SELCON_DET
USB_SS3_CC1USB_SS3_CC2
USB_SS3_CC1
USB_SS3_CC2
SS_TX2_PSS_TX2_N
NX5P3090_ILIMUSB1_TYPEC_OCn
USB1_ID
CON_DET
NX5P3090_EN
SS_REDRV_VDD1V8
SBU1
SBU2
PTN5150A_SEL
PTN36043_CH1SET1
PTN36043_CH1SET2
PTN36043_CH2SET1
PTN36043_CH2SET2
PTN5150A_PORT
USB1_TYPEC_INTn
USB3_XI
USB3_XO
USB3_CFG_BC_EN
USB3_CFG_NON_REM
USB2_C_RXN
USB2_C_TXP
USB2_C_TXN
USB2_C_RXP
USBHUB_VBUS_DET
USB3_RSTN
USB2_P1_TXN USB2_P1_C_TXNUSB2_P1_C_TXPUSB2_P1_TXP
USB2_P1_RXNUSB2_P1_RXP
USB2_P1_C_DN
USB2_P1_C_DP
USB2_P1_C_DPUSB2_P1_C_DN
USB2_P1_DPUSB2_P1_DN
USB2_P2_C_DN
USB2_P2_C_DNUSB2_P2_C_DP
USB2_P2_RXNUSB2_P2_RXP
USB2_P2_TXN
USB2_P2_C_TXN
USB2_P2_TXP
USB2_P2_C_TXP
USB2_P2_C_DPUSB2_P2_DPUSB2_P2_DN
USB3_PRT2_CTL_FLAGn
USB3_PRT1_CTL_FLAGn
USB3_PRT1_CTL_FLAGn
USB3_PRT2_CTL_FLAGn
USB2_P1_RXNUSB2_P1_RXP
USB2_P2_RXNUSB2_P2_RXP
USB2_P2_RXPUSB2_P2_RXN
USB2_P2_C_DPUSB2_P2_C_DN
USB2_P1_C_DPUSB2_P1_C_DN
USB2_P1_RXNUSB2_P1_RXP
I2C3_SCL_USB3HUB
I2C3_SDA_USB3HUB
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
09. LVDS, TOUCH, JTAG, GP SW & LEDs
1Khz/DC0-100% 3.3V Backllight Intensity
LVDS DISPLAY CH0
RESISTIVE TOUCH
CAPACITIVE TOUCH
GP BUTTONS
GP LEDS
ON/OFF
GPLED1
RST
LVDS CH1 DISPLAY
LAYOUT NOTE:LVDS Differential Pair, FollowLVDS routing guidelines.Differential Impedance: 100 ohms
LAYOUT NOTE:LVDS Differential Pair, FollowLVDS routing guidelines.Differential Impedance: 100 ohms
GPLED2
GPLED3
GPLED4
BACK
HOME
VOL UP
VOL DN
PU Included on SOM
JTAG
27K PU
27K PU
27K PU
27K PU
The new 10 pin smaller connector is now becoming anindustry standard.
The ARM DStream comes with a 10-pin connector. If youneed a ribbon, they can be purhased at Digikey:Samtec Inc MPN: FFSD-05-D-04.00-01-N If you need to expand to a 20-pin connector for adifferent JTAG device, the expander board can also bepurchased at Digikey:Olimex LTD MPN: ARM-JTAG-20-10
90K PD
27K PU
CPUInt.
ONOFF: A brief connection to GND in OFF mode causesthe internal power management state machine tochange state to ON. In ON mode, a briefconnection to GND generates an interrupt(intended to initiate a software-controllablepower-down). An approximate 5 second or moreconnection to GND causes a forced OFF.
Not used leave NC
LCD: GKTW70SDAE4SE5V/0.45A3.3V/0.17A
0-3.3V PWM:1KHz
https://www.digikey.com/products/en/development-boards-kits-programmers/accessories/783?k=JTAG%20adapter
SW NOTE: Need to set Int. PU in SOCon all SWitches
eMMC Activity
NOTE for J28: _P and _N sides swapped vs. J27
R1 Not assembled - avoid to avoid driving config lineEnable SOC PAD internal pull up for GPIO4_IO05
SW NOTE:
NOTE: DT8MP JTAG_nTRST is JTAG_MODE 10K PD required on SOM
Reset button not usable with DART-MX8M-Plus-V1.0A as U4 asserts PMIC_ON_REQ which is a push pull on imx8mp SOC vs. open drain on DT8M & DT8M-Mini.PMIC_ON_REQ is replaced with PMIC_RST to acieve correct functionality as off DART-MX8M-Plus-V1.1
DART-MX8MP-V1.0A Note:
GNDGND
GND
GND
GND
GND
GND
BASE_PER_3V3BASE_PER_3V3
GNDGND
BASE_PER_3V3
VCC_5V
BASE_PER_3V3 BASE_PER_3V3
GND
GNDGND
GND
GND
GND
BASE_PER_3V3
BASE_PER_3V3
VCC_5V
GND
GND
GND
GND
GND
GND
GND
SOM_NVCC_3V3
GPIO1_IO01(PWM1_OUT)
ONOFF
SW_RSTn
LVDS1_TX2_PLVDS1_TX2_N
LVDS1_CLK_PLVDS1_CLK_N
LVDS1_TX3_PLVDS1_TX3_N
LVDS1_TX0_PLVDS1_TX0_N
LVDS1_TX1_PLVDS1_TX1_N
LVDS2_DSI_TX0_PLVDS2_DSI_TX0_N
LVDS2_DSI_TX1_PLVDS2_DSI_TX1_N
LVDS2_DSI_TX3_PLVDS2_DSI_TX3_N
LVDS2_TX2_DSI_CLK_N LVDS2_TX2_DSI_CLK_PLVDS2_CLK_DSI_TX2_N
LVDS2_CLK_DSI_TX2_P
I2C2_SDA
I2C2_SCL
ECSPI1_SCLKECSPI1_SS0
ECSPI1_MOSIECSPI1_MISO
JTAG_TCK
JTAG_TDIJTAG_TDO
POR_B
JTAG_TMS
JTAG_nTRST
SAI1_RXD2(GPIO4_IO04)
SAI1_TXD5(GPIO4_IO17)
SAI1_TXD6(GPIO4_IO18)
SAI1_TXD1(GPIO4_IO13)
SAI1_TXD3(GPIO4_IO15)
GPIO1_IO14
GPIO1_IO03
SAI1_TXD2(GPIO4_IO14)
SAI1_RXD4(GPIO4_IO06)
SAI1_RXD3(GPIO4_IO05)SAI1_RXD1(GPIO4_IO03)
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
09. LVDS, TOUCH, JTAG, GP SW & LEDs
A3
13 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
09. LVDS, TOUCH, JTAG, GP SW & LEDs
A3
13 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
09. LVDS, TOUCH, JTAG, GP SW & LEDs
A3
13 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
D2TPD1E10B09DPYR
C4
470pF
SW2
FSM4JSMATR
12
34
R1270RNC
C1
100nF
C61uF
C3
470pF
R1290R
R10310K
J28
HEADER 2X1
NC12
R35 330R
SW5
FSM4JSMATR
12
34
SW3
FSM4JSMATR
12
34
M1M2
J17
4 POS FFC/FPC
123456
R1100K
NC
R43 330R
D5TPD1E10B09DPYR
C7100nF
SW6
FSM4JSMATR
12
34
SW4
FSM4JSMATR
12
34
R1240RNC
R56 330R
C15
100nF
D8TPD1E10B09DPYR
D2030V,100mA
J26
CH81202M10100
11
33
55
99
1111
1313
1515
1717
1919
22
44
66
88
1010
1212
1414
1616
1818
2020
77
C109
100nF
R71 330R
M1
M2
J18
CF20061D0R0-LF
1234
78
56
U1
TSC2046IRGVR
VCC5
IOVDD14
DCLK4
CS3
DIN2
DOUT16
GND10
PENIRQ15
AUX12
VREF13
X+6
X-8
BUSY1
Y+7
Y-9
VBAT11
PG
ND
17
D7
D11TPD1E10B09DPYR
D10
J15
CH81202M10100
11
33
55
99
1111
1313
1515
1717
1919
22
44
66
88
1010
1212
1414
1616
1818
2020
77
D16
TPD1E10B09DPYR
J29GRPB052VWVN-RC
NC
108642
97531
D14
'0'-B->A
U14
SN74AVC4T245
VCCA1
1DIR2
2DIR3
1A14
1A25
2A16
2A27
GND8
GND9 2B2
10 2B111 1B212 1B113 2OE#14 1OE#15 VCCB16
PA
D17
R128120R 1%
C9
10uF
D12
J27
HEADER 2X1
NC12
SW1
FSM4JSMATR
12
34
C113
100nF
C5
470pF
D3TPD1E10B09DPYR
C8
10uF
C2
470pF
R140RR
21
0K
TS_X-
LVDS_PWM
GPIO1_IO01(PWM1_OUT) LVDS_PWM
TS_Y+TS_X+TS_Y-
nRST_CON
JTAG_VREF
JTAG_nTRST_C
BOOT_CFG02GP_LED3BOOT_CFG13GP_LED4
BOOT_CFG09 SW_HOME
BOOT_CFG11 SW_VOLDN
BOOT_CFG14 SW_VOLUP
RES_TOUCH_PENIRQn
ECSPI1_MISO_R
CAP_TOUCH_INTnBOOT_CFG10GP_LED2
BOOT_CFG04 SW_BACK
BOOT_CFG03 CAPTOUCH_RSTnBOOT_CFG01GP_LED1/CSI_P2_TRIG
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SAI5 RX
10. HEADERS, Pull Ups
UART4 CONNECTED TOWIFI_BT ON SOM
ENET0
SAI2
UART2 FTDI PINOUT
I2C3: PU on SOM to SOM_NVCC_3V3
I2C3 I2C4
UART3FTDI_GND
FTDI_VCC_OUT
Fiducial
CHASSIS HOLES
Place on TOP
SOM MOUNTING STANDOFF
MECHANICS
SPDIF
NOTE : DISCONNECT SERIES RES TO RES_TOUCH SPI_OUT LINE OR USE DIFFERENT CS
ECSPI1
GPIO1
FTDI Adpater can be purchased @ DigiKey :https://www.digikey.com/product-detail/en/ftdi-future-technology-devices-international-ltd/TTL-232R-3V3/768-1015-ND/1836393See pinout: http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232R_CABLES.pdf
I2C PULL UP
SAI1 RXSAI1 TX
VSS0041 NUT M2
VSS0042 X SCREW CONIC HEAD M2
Layout Note:Place series resistor close to SOM connector.
SW NOTE:Requires GPIO2_IO20 configured as interrupt input
BT/WIFI HOST WAKE (1.8V SIGNALS) + POR
CAN FD
USED FOR VARISCITE TESTING
Note:Need to set SD-eMMC Selectorto OFF for remote testing
DART-MX8MPLevel according to PIN 41 output set on DART
DART-MX8MPLevel according to PIN 41 output set on DART
GND
BASE_PER_3V3
GND
GND GND
GND GND
GND
GND
VCC_5V
GND
BASE_PER_3V3
GND
GND
GND
BASE_PER_3V3
BASE_PER_1V8
GND
SAI2_MCLK
BT_UART4_CTS_B
BT_UART4_RTS_B
BT_UART4_TX
BT_UART4_RX
I2C4_SDAI2C3_SDAI2C3_SCL
UART2_TXDUART2_RXD
UART3_TXDUART3_RXD
I2C4_SCL
ENET_TX_CTL_BYP
ENET_MDIO
ENET_MDC
SPDIF_RXSPDIF_EXT_CLK
SPDIF_TX
GPIO1_IO11
GPIO1_IO15
SAI5_RXCSAI5_RXFSSAI5_RXD0SAI5_RXD1SAI5_RXD2SAI5_RXD3
SAI5_MCLK
SAI2_RXCSAI2_RXFSSAI2_RXD0
SAI2_TXCSAI2_TXFSSAI2_TXD0
SAI1_RXFSSAI1_RXC
SAI1_MCLK(GPIO4_IO20)SAI1_TXC(GPIO4_IO11)
SAI1_TXFS(GPIO4_IO10)GPIO1_IO00
ECSPI1_SCLKECSPI1_SS0ECSPI1_MOSIECSPI1_MISO
PMIC_STBY_REQ
I2C2_SDA
I2C2_SCL
I2C4_SCLI2C4_SDA
GPIO1_IO08
SAI1_TXD0(GPIO4_IO12)SAI1_RXD0(GPIO4_IO02)
GPIO1_IO12
GPIO1_IO06
SAI1_TXD4(GPIO4_IO16)
POR_B
BT_HOST_WAKESD2_WP(GPIO2_IO20)WIFI_HOST_WAKE
CAN_L
CAN_H
BOOT_CFG
ONOFFSW_RSTn
EN_SOM_VBAT_3V3
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
10. HEADERS, Mechanics, Pull Ups
A3
14 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
10. HEADERS, Mechanics, Pull Ups
A3
14 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
10. HEADERS, Mechanics, Pull Ups
A3
14 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
FD1
NC
R710K
TP2
HOLE3
TH-1.6-1.5-M2
NC
HOLE1
NC
EA
RT
H1 FD4
NC
R701.0K 1%
J14CH81102M10100
108642
97531
R510K
HOLE4
TH-1.6-1.5-M2
NCHOLE6
TH-1.6-1.5-M2
NC
J13
CH81202M10100
11
33
55
99
1111
1313
1515
1717
1919
22
44
66
88
1010
1212
1414
1616
1818
2020
77
FD3
NC
R591.0K 1%
R610K
TP5
J12
CH81202M10100
11
33
55
99
1111
1313
1515
1717
1919
22
44
66
88
1010
1212
1414
1616
1818
2020
77
HOLE2
NC
EA
RT
H1
J31
HEADER 2X1NC1
2
R81.0K 1%NC
R310K
VPC1
PCB
VPC0331
Manufacturer_PN = VPC0331
J30
HEADER 2X1NC1
2
FD2
NC
R61 1.0K 1%
R2822R 1%
HOLE7
NC
EA
RT
H1
R66 1.0K 1%
HOLE5
TH-1.6-1.5-M2
NC
J16CH81102M10100
108642
97531
J25CH81102M10100
108642
97531
HOLE8
NC
EA
RT
H1
FTDI_RTSnFTDI_RXIFTDI_TXO
FTDI_CTSnFTDI_RTSn
DART_MX8MP = FLEXCAN2_RX
SOM used w/"WBD"
SOM used w/"LD" [ ]
RTC_IRQn
DART_MX8MP = FLEXCAN1_TX
DART_MX8MP = FLEXCAN1_RX
DART_MX8MP = FLEXCAN2_TX
<CB_Function><CB_Function>
CSI_P1_SYNCCSI_P1_OPTCSI_P2_SYNC
SOM_WIFI32KSOM used w/"WBD" [ ]
SOM used w/"WBD" [ ]
BOOT_CFG08 CSI_P2_RST_BBOOT_CFG00CSI_BUF_EN_B
CAN_CS_B
CAN_INT_B
BOOT_CFG12 CSI_P1_TRIG
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Notes:a. Sampled on rising edge of POR_Bb. 90K ohm Int. SOC PD during POR_B and after on BOOT CFG[15:0] and BOOTMODE[1:0]c. BOOT_MODE[1:0] ="10" is Internal Boot - Always used.d. Active boot cfg for one dip sw sel EXTERNAL/INTERNAL
BOOT CFG PRIORITY: H Ext. SD CardL Int. eMMC or Optional DART-MX8M-MINI NAND
11. BOOT CONFIG & MODE
Note:PU removed
DART-MX8M-MINI Notes:a. Internal boot can be eMMC or NAND(when it is released) b. Boot config lines do not follow the Mini datasheet in full DART-MX8M-MINI have added logic to be compatible to DART-MX8Mc. Need to modify R90 to 10K (R89 and R107 not a must)
Note:PU on page 05.
Note:PU removed
EXT. BOOTINT. BOOT
Need to Enable PU in DTS; See pp. 5
SAI1_TXD2CustomBoard Net: BOOT_MODE0
BOOT_MODE1
DART-MX8M-PLUS Notes:a. Boot configuration set by BOOT_MODE[0..3] b. BOOT_MODE0 connected via buffer on DART-MX8MP to SAI1_TXD2
EN_SOM_VBAT_3V3
DART-MX8MP Pin: J1.72 J2.13 J2.11 J2.78
GND
SOM_NVCC_3V3
GND
GND
GND
GND
GND
GND
SOM_NVCC_3V3
SOM_NVCC_3V3
SOM_NVCC_3V3
SAI1_RXD0(GPIO4_IO02)
SAI1_RXD2(GPIO4_IO04)
BOOT_MODE1
BOOT_MODE0
SAI1_RXD1(GPIO4_IO03)
SAI1_RXD6(GPIO4_IO08)SAI1_RXD7(GPIO4_IO09)
BOOT_CFG
SAI1_RXD3(GPIO4_IO05)
SAI1_RXD5(GPIO4_IO07)SAI1_RXD4(GPIO4_IO06)
SAI1_TXD2(GPIO4_IO14)
SAI1_TXD4(GPIO4_IO16)
SAI1_TXD5(GPIO4_IO17)
SAI1_TXD0(GPIO4_IO12)
SAI1_TXD1(GPIO4_IO13)
SAI1_TXD3(GPIO4_IO15)
SAI1_TXD6(GPIO4_IO18)
SAI1_TXD7(GPIO4_IO19)
SAI1_RXD0(GPIO4_IO02)SAI1_RXD1(GPIO4_IO03)SAI1_RXD2(GPIO4_IO04)SAI1_RXD3(GPIO4_IO05)
SAI1_RXD4(GPIO4_IO06)SAI1_RXD5(GPIO4_IO07)SAI1_RXD6(GPIO4_IO08)SAI1_RXD7(GPIO4_IO09)
SAI1_TXD0(GPIO4_IO12)
SAI1_TXD1(GPIO4_IO13)SAI1_TXD2(GPIO4_IO14)
SAI1_TXD3(GPIO4_IO15)SAI1_TXD4(GPIO4_IO16)
SAI1_TXD5(GPIO4_IO17)SAI1_TXD6(GPIO4_IO18)SAI1_TXD7(GPIO4_IO19)
Title
Size Document Number Rev
Date: Sheet of
VAR-DT8MCustomBoard 1.4D-R2.1
11. BOOT CONFIG & MODE
B
15 17Wednesday, December 23, 2020
Title
Size Document Number Rev
Date: Sheet of
VAR-DT8MCustomBoard 1.4D-R2.1
11. BOOT CONFIG & MODE
B
15 17Wednesday, December 23, 2020
Title
Size Document Number Rev
Date: Sheet of
VAR-DT8MCustomBoard 1.4D-R2.1
11. BOOT CONFIG & MODE
B
15 17Wednesday, December 23, 2020
U19SN74LVC1G34DCKR
2 4
531
R5810K NC
R8910K
C102100nF
R8810KNC
R9010K R100
4.7KNC
R5510K NC
R10710K
R9210K NC
U17SN74LVC1G04DCKR
24
531
R10610K
C104100nF
D21
R5410K NC
U18SN74LVC1G34DCKR
2 4
531
R11310K NC
R11210K NC
R5210K NC
R9110K NC
R5310K NC
Pin2 is
ON Side
SW7TDA01H0SB1R
12
R11110K NC
R6410K NC
C103100nF
R9310K NC
R871.0K 1%
R99
1.0K 1%
CSI_BUF_EN_BBOOT_CFG00
CAPTOUCH_RSTnBOOT_CFG03GP_LED3BOOT_CFG02
CSI_P1_PWRENBOOT_CFG06CSI_P2_PWRENBOOT_CFG07
PCIe_1_nRSTBOOT_CFG05
BOOT_CFG01 GP_LED1/CSI_P2_TRIG
BOOT_CFG
BOOT_CFG04 SW_BACK
BOOT_CFG10 GP_LED2
BOOT_CFG12 CSI_P1_TRIG
BOOT_CFG13 GP_LED4
BOOT_CFG
BOOT_CFG08 CSI_P2_RST_B
BOOT_CFG09 SW_HOME
BOOT_CFG11 SW_VOLDN
BOOT_CFG14 SW_VOLUP
BOOT_CFG15 PCIe_2_nRST
CSI_BUF_EN_B BOOT_CFG00 0 0BOOT_CFG01GP_LED1/CSI_P2_TRIG 0 0
GP_LED3 BOOT_CFG02 0 0CAPTOUCH_RSTn BOOT_CFG03 0 0
BOOT_CFG04SW_BACK 0 0PCIe_1_nRST BOOT_CFG05 0 0CSI_P1_PWREN BOOT_CFG06 0 0CSI_P2_PWREN BOOT_CFG07 0 0
BOOT_CFG08CSI_P2_RST_B 0 0BOOT_CFG09SW_HOME 0 0BOOT_CFG10GP_LED2 0 1BOOT_CFG11SW_VOLDN 0 0BOOT_CFG12CSI_P1_TRIG 0 1BOOT_CFG13GP_LED4 1 0BOOT_CFG14SW_VOLUP 0 0BOOT_CFG15PCIe_2_nRST 0 0
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ALT0 ALT1 ALT3
12. PINMUX J1 & J2 & J3
CB_FUNCTIONALT2 ALT5ALT4 ALT IC
J1
J2
J3
NOTE:1. NOTE CB_FUNCTION FOR "SOM used", WHICH MEANS SIGNAL USED ON SOME SOMs WITH OPTIONAL OREDERABLE CONFIGURATIONS. PLEASE REFER TO SOM DATASHEET FOR FURTHER DETAILS.
2. ALT0 TO ALT6 DENOTE ALTERNATE FUNCTIONS OF SOC PINS WHEN USED.
3. ALT IC DENOTE AN ALTERNATE FUNCTION WHEN RELEVANT SOM ORDERABLE CONFIGURATION CHOOSEN. FUNCTION GENERATED BY ALTERNATIVE IC WHEN USED. WHEN DESIGN WITH ALT IC - ALT0 TO ALT6 CANNOT BE USED!
4. GREEN NETS DENOTE PINS USED FOR BOOT CONFIGURATION DURING POWER UP. CARE SHOULD BE GIVEN NOT TO DRIVE THESE LINES BEFORE RISE OF POR_B+1ms.
DART-MX8M-Mini differences:---------------------------------------------------[ ] square brackets are related alternate function to MINI only. Empty brackets means function removed.
1. PMIC_ON_REQ + PMIC_STBY_REQ + POR_B + ONOFF run @ 1.8V 2. PCIe port 2 does not exist3. MIPI-CSI port 2 does not exist4. USB3.0 does not exist on port 1 and 25. HDMI does not exist 6. QSPIB does not exist 7. QSPIA exist only with eMMC on SOM and run @ 1.8V
ALT6
CONN_SD2_CD_B
CONN_SD2_DATA2CONN_SD2_DATA1
CONN_SD2_CLK
CONN_SD2_DATA3
CONN_SD2_DATA0
CONN_SD2_CMD
ETH_TRX1_PETH_TRX1_N
ETH_TRX0_NETH_TRX0_P
ETH_TRX2_PETH_TRX2_N
ETH_TRX3_PETH_TRX3_N
GPIO1_IO00
ENET_TX_CTL_BYPLED_LINK10_100LED_LINK1000LED_ACTENET_MDIO
ENET_MDC
I2C4_SCLI2C4_SDA
CONN_SD2_nRST
NAND_DATA00NAND_DATA01NAND_DATA02NAND_DATA03NAND_DATA04NAND_DATA05NAND_DATA06NAND_DATA07NAND_CE0_BNAND_CE2_BNAND_DQSNAND_ALENAND_WP_BNAND_WE_BNAND_RE_BNAND_CLENAND_READY_B
HPLOUTHPROUTHPOUTFBLINEIN1_LPLINEIN1_RPDMIC_CLKDMIC_DATA
BT_UART4_TXBT_UART4_CTS_BBT_UART4_RXBT_UART4_RTS_BGPIO1_IO02(nWDOG)
I2C2_SDA
I2C2_SCL
ECSPI1_SCLKECSPI1_SS0ECSPI1_MISOECSPI1_MOSI
UART1_RXDUART1_TXD
UART2_RXDUART2_TXD
UART3_RXDUART3_TXD
SAI2_MCLKSAI2_RXFSSAI2_RXCSAI2_TXFSSAI2_TXCSAI2_RXD0SAI2_TXD0
SAI5_MCLKSAI5_RXFSSAI5_RXCSAI5_RXD0SAI5_RXD1SAI5_RXD2SAI5_RXD3SAI1_MCLK(GPIO4_IO20)SAI1_RXFSSAI1_RXCSAI1_TXFS(GPIO4_IO10)SAI1_TXC(GPIO4_IO11)SAI1_RXD0(GPIO4_IO02)SAI1_RXD1(GPIO4_IO03)SAI1_RXD2(GPIO4_IO04)SAI1_RXD3(GPIO4_IO05)
SAI1_RXD4(GPIO4_IO06)SAI1_RXD5(GPIO4_IO07)
SAI1_RXD6(GPIO4_IO08)SAI1_RXD7(GPIO4_IO09)SAI1_TXD0(GPIO4_IO12)
SAI1_TXD1(GPIO4_IO13)SAI1_TXD2(GPIO4_IO14)
SAI1_TXD3(GPIO4_IO15)SAI1_TXD4(GPIO4_IO16)
SAI1_TXD5(GPIO4_IO17)SAI1_TXD6(GPIO4_IO18)SAI1_TXD7(GPIO4_IO19)
UART4_TXD(GPIO5_IO29)UART4_RXD(GPIO5_IO28)
SPDIF_RXSPDIF_TXSPDIF_EXT_CLK
I2C3_SDA
I2C3_SCL
GPIO1_IO01(PWM1_OUT)GPIO1_IO03GPIO1_IO05GPIO1_IO06
GPIO1_IO08GPIO1_IO10GPIO1_IO11GPIO1_IO12GPIO1_IO13(USB1_OTG_OC)GPIO1_IO14GPIO1_IO15
LVDS2_CLK_DSI_TX2_PLVDS2_CLK_DSI_TX2_N
LVDS2_TX2_DSI_CLK_NLVDS2_TX2_DSI_CLK_P
LVDS2_DSI_TX0_PLVDS2_DSI_TX0_NLVDS2_DSI_TX1_PLVDS2_DSI_TX1_N
LVDS2_DSI_TX3_PLVDS2_DSI_TX3_N
LVDS1_TX2_PLVDS1_TX2_N
LVDS1_CLK_PLVDS1_CLK_N
LVDS1_TX3_PLVDS1_TX3_N
LVDS1_TX0_PLVDS1_TX0_NLVDS1_TX1_PLVDS1_TX1_N
SD2_WP(GPIO2_IO20)
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
12. PINMUX J1 & J2 & J3
A2
16 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
12. PINMUX J1 & J2 & J3
A2
16 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
12. PINMUX J1 & J2 & J3
A2
16 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
NAND_DATA00 QSPIA_DATA0 [QSPIA_DATA0_1V8] GPIO3_IO06 [GPIO3_IO06_1V8] [SOM used w/NAND]NAND_DATA01 QSPIA_DATA1 [QSPIA_DATA1_1V8] GPIO3_IO07 [GPIO3_IO07_1V8] [SOM used w/NAND]NAND_DATA02 QSPIA_DATA2 [QSPIA_DATA2_1V8] GPIO3_IO08 [GPIO3_IO08_1V8] [SOM used w/NAND]NAND_DATA03 QSPIA_DATA3 [QSPIA_DATA3_1V8] GPIO3_IO09 [GPIO3_IO09_1V8] [SOM used w/NAND]NAND_DATA04 [NC] QSPIB_DATA0 [ ] GPIO3_IO10 [ ]NAND_DATA05 [NC] QSPIB_DATA1 [ ] GPIO3_IO11 [ ]NAND_DATA06 [CLKIN2_1V8] QSPIB_DATA2 [ ] GPIO3_IO12 [ ]NAND_DATA07 [CLKIN1_1V8] QSPIB_DATA3 [ ] GPIO3_IO13 [ ]NAND_CE0_B QSPIA_SS0_B [QSPIA_SS0_B_1V8] GPIO3_IO01 [GPIO3_IO01_1V8] [SOM used w/NAND]NAND_CE2_B [CLKOUT2_1V8] QSPIB_SS0_B [ ] GPIO3_IO03 [ ]NAND_DQS QSPIA_DQS [QSPIA_DQS_1V8] GPIO3_IO14 [GPIO3_IO14_1V8] [SOM used w/NAND]NAND_ALE QSPIA_SCLK [QSPIA_SCLK_1V8] GPIO3_IO00 [GPIO3_IO00_1V8] [SOM used w/NAND]NAND_WP_B [NC] GPIO3_IO18 [ ]NAND_WE_B [NC] GPIO3_IO17 [ ]NAND_RE_B [GPIO1_IO07] QSPIB_DQS [ENET_MDIO] GPIO3_IO15 [ ] [EXT_CLK4] <CB_Function>NAND_CLE [CLKOUT1_1V8] QSPIB_SCLK [ ] GPIO3_IO05 [ ]NAND_READY_B [NC] GPIO3_IO16 [ ]SD2_CLK GPIO2_IO13SD2_DATA0 GPIO2_IO15SD2_DATA1 GPIO2_IO16SD2_DATA2 GPIO2_IO17SD2_DATA3 GPIO2_IO18SD2_CMD GPIO2_IO14SD2_CD_B GPIO2_IO012SD2_RESET_B GPIO2_IO19 SD2_PWR_CTRLSD2_WP [SD1_DATA7] GPIO2_IO20 [GPIO2_IO09_1V8]ENET_TD2 ENET_TX_CLK_IN|ENET_REF_CLK_ROOT_OUT GPIO1_IO19 ETH_TRX0_NENET_TD3 GPIO1_IO18 ETH_TRX0_PENET_TD0 GPIO1_IO21 ETH_TRX1_NENET_TD1 GPIO1_IO20 ETH_TRX1_PENET_RD1 GPIO1_IO27 ETH_TRX2_NENET_RD0 GPIO1_IO26 ETH_TRX2_PENET_RD3 GPIO1_IO29 ETH_TRX3_NENET_RD2 GPIO1_IO28 ETH_TRX3_PENET_TX_CTL GPIO1_IO22 NCENET_TXC ENET_TX_ER GPIO1_IO23 LED_LINK10_100ENET_RXC ENET_RX_ER GPIO1_IO25 LED_LINK1000ENET_RX_CTL GPIO1_IO24 LED_ACTENET_MDIO GPIO1_IO17 SOM used w/"EC"ENET_MDC GPIO1_IO16 SOM used w/"EC"GPIO1_IO00 ENET_PHY_REF_CLK_ROOT_OUT REF_CLK_32K EXT_CLK1 SOM used w/"WBD" [ ]I2C4_SCL PWM2_OUT GPIO5_IO20PCIE1_CLKREQ_BI2C4_SDA PWM1_OUT GPIO5_IO21PCIE2_CLKREQ_B [ ]
SAI3_RXD GPT1_COMPARE1 GPIO4_IO30SAI5_RXD0 HPLOUTSAI3_TXC GPT1_COMPARE2 GPIO5_IO00SAI5_RXD2 [UART2_TXD] HPROUTSAI3_RXFS GPT1_CAPTURE1 GPIO4_IO28SAI5_RXFS [SAI3_RXD1] HPOUTFB
SAI2_MCLK SAI5_MCLK GPIO4_IO27SAI2_RXFS SAI5_TXFS GPIO4_IO21[SAI5_TXD1] [SAI2_RXD1] [UART1_TXD]SAI2_RXC SAI5_TXC GPIO4_IO22[UART1_RXD]SAI2_TXFS SAI5_TXD1 GPIO4_IO24[SAI2_TXD1] [UART1_CTS_B]SAI2_TXC SAI5_TXD2 GPIO4_IO25SAI2_RXD0 SAI5_TXD0 GPIO4_IO23[UART1_RTS_B]SAI2_TXD0 SAI5_TXD3 GPIO4_IO26SAI5_MCLK SAI1_TXC GPIO3_IO25SAI4_MCLK [ ]SAI5_RXFS SAI1_TXD0 GPIO3_IO19SAI5_RXC SAI1_TXD1 GPIO3_IO20[PDM_CLK]SAI5_RXD0 SAI1_TXD2 GPIO3_IO21[PDM_BIT0]SAI5_RXD1 SAI1_TXD3 GPIO3_IO22SAI1_TXFS SAI5_TXFS [PDM_BIT1]SAI5_RXD2 SAI1_TXD4 GPIO3_IO23SAI1_TXFS SAI5_TXC [PDM_BIT2]SAI5_RXD3 SAI1_TXD5 GPIO3_IO24SAI1_TXFS SAI5_TXD0 [PDM_BIT3]SAI1_MCLK SAI5_MCLK GPIO4_IO20SAI1_TXC [PDM_CLK] CSI_P1_SYNCSAI1_RXFS SAI5_RXFS GPIO4_IO00
SAI3_RXC GPT1_CAPTURE2 [GPT1_CLK] GPIO4_IO29SAI5_RXC [UART2_CTS_B] LINEIN1_LPSAI3_TXFS GPT1_CLK [GPT1_CAPTURE2] GPIO4_IO31SAI5_RXD1 [SAI3_TXD1] [UART2_RXD] LINEIN1_RPSAI3_TXD GPT1_COMPARE3 GPIO5_IO01SAI5_RXD3 DMIC_CLKSAI3_MCLK PWM4_OUT GPIO5_IO02SAI5_MCLK DMIC_DATA
ECSPI2_MOSI UART4_TXD GPIO5_IO11 SOM used w/"WBD"ECSPI2_MISO UART4_CTS_B GPIO5_IO12 SOM used w/"WBD"ECSPI2_SCLK UART4_RXD GPIO5_IO10 SOM used w/"WBD"ECSPI2_SS0 UART4_RTS_B GPIO5_IO13 SOM used w/"WBD"GPIO1_IO02 WDOG_B [WDOG_ANY] WDOGn
I2C2_SDA ENET1_1588_EVENT1_OUT GPIO5_IO17I2C2_SCL ENET1_1588_EVENT1_IN GPIO5_IO16
ECSPI1_SCLK UART3_RXD GPIO5_IO06ECSPI1_SS0 UART3_RTS_B GPIO5_IO09ECSPI1_MISO UART3_CTS_B GPIO5_IO08ECSPI1_MOSI UART3_TXD GPIO5_IO07
UART1_RXD ECSPI3_SCLK GPIO5_IO22UART1_TXD ECSPI3_MOSI GPIO5_IO23UART2_RXD ECSPI3_MISO GPIO5_IO24UART2_TXD ECSPI3_SS0 GPIO5_IO25UART3_RXD UART1_CTS_B GPIO5_IO26UART3_TXD UART1_RTS_B GPIO5_IO27
SAI1_RXC SAI5_RXC GPIO4_IO01SAI1_TXFS SAI5_TXFS GPIO4_IO10 CSI_P2_SYNCSAI1_TXC SAI5_TXC GPIO4_IO11 CSI_P1_OPTSAI1_RXD0 SAI5_RXD0 GPIO4_IO02[SAI1_TXD1] [PDM_BIT0] BOOT_CFG00 CSI_BUF_EN_BSAI1_RXD1 SAI5_RXD1 GPIO4_IO03[PDM_BIT1] BOOT_CFG01 GP_LED1/CSI_P2_TRIGSAI1_RXD2 SAI5_RXD2 GPIO4_IO04[PDM_BIT2] BOOT_CFG02 GP_LED3SAI1_RXD3 SAI5_RXD3 GPIO4_IO05[PDM_BIT3] BOOT_CFG03 CAPTOUCH_RSTnSAI1_RXD4 SAI6_TXC GPIO4_IO06SAI6_RXC BOOT_CFG04 SW_BACKSAI1_RXD5 SAI6_TXD0 GPIO4_IO07SAI6_RXD0 SAI1_RXFS BOOT_CFG05 PCIe_1_nRSTSAI1_RXD6 SAI6_TX_SYNC GPIO4_IO08SAI6_RXFS BOOT_CFG06 CSI_P1_PWRENSAI1_RXD7 SAI6_MCLK GPIO4_IO09SAI1_TXFS SAI1_TXD4 BOOT_CFG07 CSI_P2_PWRENSAI1_TXD0 SAI5_TXD0 GPIO4_IO12 BOOT_CFG08 CSI_P2_RST_BSAI1_TXD1 SAI5_TXD1 GPIO4_IO13 BOOT_CFG09 SW_HOMESAI1_TXD2 SAI5_TXD2 GPIO4_IO14 BOOT_CFG10 GP_LED2SAI1_TXD3 SAI5_TXD3 GPIO4_IO15 BOOT_CFG11 SW_VOLDNSAI1_TXD4 SAI6_RXC GPIO4_IO16SAI6_TXC BOOT_CFG12 CSI_P1_TRIGSAI1_TXD5 SAI6_RXD0 GPIO4_IO17SAI6_TXD0 BOOT_CFG13 GP_LED4SAI1_TXD6 SAI6_RXFS GPIO4_IO18SAI6_TXFS BOOT_CFG14 SW_VOLUPSAI1_TXD7 SAI6_MCLK GPIO4_IO19[PDM_CLK] BOOT_CFG15 PCIe_2_nRST
UART4_TXD UART2_RTS_B GPIO5_IO29PCIE2_CLKREQ_B [ ] CSI_P2_OPTUART4_RXD UART2_CTS_B GPIO5_IO28PCIE1_CLKREQ_B CSI_P1_RST_B
SPDIF_RX PWM2_OUT GPIO5_IO04SPDIF_TX PWM3_OUT GPIO5_IO03SPDIF_EXT_CLK PWM1_OUT GPIO5_IO05 SOM used w/"WBD"
I2C3_SDA PWM3_OUT GPIO5_IO19GPT3_CLK SOM SharedI2C3_SCL PWM4_OUT GPIO5_IO18GPT2_CLK SOM Shared
GPIO1_IO01 PWM1_OUT REF_CLK_24M EXT_CLK2 LVDS_PWMGPIO1_IO03 USDHC1_VSELECT XTAL_OK [ ] RES_TOUCH_PENIRQnGPIO1_IO05 M4_NMI PMIC_READY HDMI_SW_GPU_SELGPIO1_IO06 [ENET1_MDC] SD1_CD_B EXT_CLK3 CAN_INT_BGPIO1_IO08 ENET1_1588_EVENT0_IN SD2_RESET_B SOM used w/"WBD" [ ]GPIO1_IO10 USB1_OTG_ID USB1_TYPEC_INTnGPIO1_IO11 USB2_OTG_ID PMIC_READY [ ] SOM used w/"LD" [ ]GPIO1_IO12 USB1_OTG_PWR CAN_CS_BGPIO1_IO13 USB1_OTG_OC PWM2_OUT USB1_TYPEC_OCnGPIO1_IO14 USB2_OTG_PWR PWM3_OUT [CLKO1] CAP_TOUCH_INTnGPIO1_IO15 USB2_OTG_OC PWM4_OUT CLKO2 [CLKO1] RTC_IRQn
DSI_TX2_P LVDS2_CLK_PDSI_TX2_N LVDS2_CLK_NDSI_TX0_P LVDS2_TX0_PDSI_TX0_N LVDS2_TX0_NDSI_TX1_P LVDS2_TX1_PDSI_TX1_N LVDS2_TX1_NDSI_CLK_P LVDS2_TX2_PDSI_CLK_N LVDS2_TX2_NDSI_TX3_P LVDS2_TX3_P
NC LVDS1_CLK_PNC LVDS1_CLK_NNC LVDS1_TX0_PNC LVDS1_TX0_NNC LVDS1_TX1_PNC LVDS1_TX1_NNC LVDS1_TX2_P
DSI_TX3_N LVDS2_TX3_N
NC LVDS1_TX2_NNC LVDS1_TX3_PNC LVDS1_TX3_N
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
13. CAN FD Interface
Note for U44:Recommneded PN for new design MCP2518FDT-E/SLAssembled board can have MCP2517FDT-H/SL
BASE_PER_3V3
GND
GND
BASE_PER_3V3
GND
BASE_PER_3V3
ECSPI1_SCLK
ECSPI1_MOSI
ECSPI1_MISO
GPIO1_IO12
GPIO1_IO06
CAN_H
CAN_L
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
CAN FD Interface
A4
17 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
CAN FD Interface
A4
17 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
Title
Size Document Number Rev
Date: Sheet ofApproved By:Designer:
Project
VAR-DT8MCustomBoard 1.4D-R2.1
CAN FD Interface
A4
17 17Wednesday, December 23, 2020Oded A. VPC0331
VAR-DT8MCustomBoard
20pF
Y3
20 Mhz
1
34
2
R192120R 1%
U44
MCP2518FDT-E/SL
TXCAN1
RXCAN2
CLKO/SOF3
INT4
OSC25
OSC16
VSS7
INT1/GPIO18
INT0/GPIO0/XSTBY9
SCK10
SDI11
SDO12
nCS13
VDD14
C182
33pF
R193
510R
C1791uF
C181
33pF
R194
510R
R191
10K
CANTX
CANRX
C1801uF
U45
TCAN332GD
TXD1
GND2
VCC3
RXD4
NC15
CANL6
CANH7
NC28
CAN_INT_B
CAN_TX
CAN_RX
CAN_TX_INT_B
CAN_RX_INT_B
CAN_TX_INT_B
CAN_RX_INT_B
CAN_CS_B