• Specifications

• Asic description

• Constraints

• Interface with PDM board

• Schedule

• Summary

3

ASICs

Connector

Rigid fromEC-ANODE

Connectortoward the PDM board

As close as

possible

Flex fromEC-ANODE

• Specifications: • An ASIC is assigned to each MAPMT 36 ASICs have to be distributed on the

boards of the EC-back electronic. They should also include the connectors toward the EC-anode and PDM boards as well as all the passive components needed.

• The idea is to go for 6 boards (3 pairs of boards facing each other) perpendicular to the PDM mechanical structure.

Volume for Electronics: EC_asic, Volume for Electronics: EC_asic, HV box, PDM boardHV box, PDM board

PDM FramePDM Frame

With EC_frontWith EC_frontMAPMTMAPMT

ASIC B ASIC FASIC D

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• 3 ASICs, with their associated passive components, on each side of the pcb

• 6 connectors (68 pins: 64 anodes + 4 gnd) on top side

• 1 connector (120 pins) on top side

68

pins

ASIC A

68

pins

ASIC C ASIC E

120 pins

A B C D E F68

pins

68

pins

68

pins

68

pins

5

• Specifications: Readout MAPMT signals Consumption: 1mW/channel Photon counting: 100% trigger efficiency@50fC (1/3pe, 106 Gain) Charge/time converter input range : 2pc – 200pc (10pe - 1000pe) Radiation hardness

Spatial Photomultiplier Array Counting and Integrating

ReadOut Chip

• 1st version received in October 2010• Technology: AMS 0.35µm SiGe • Dimensions : 4.6mm x 4.1mm (19 mm²)• Power supply: 0-3V• Packaging : P(C)QFP240(160)

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• 64 channels• Preamplifier with individual 8-bit gain adjustment• Photo-electron counting (10-bit DACs)

– 3 discriminator outputs : Trig_PA, Trig_FSU & Trig_VFS– Multiplexed discriminator outputs to Digital part– Many parameters available

• Charge to time converters (called KIs)– Designed in collaboration with JAXA/RIKEN– 9 outputs : 8 channels (8-pixel-Sum) + Last Dynode– Many parameters available

• Continuous Data acquisition & Readout every 2.5 s (GTU)– 8 identical digital module for PC– 1 digital module for KI

• First version of SPACIROC showed good behavior (intensive lab tests with and without MAPMT)

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• Package: CQFP 160pins by MATRA• Quantity: 100• Cost: 105€/asic• Delay:

– Package material : 2 weeks– 3 prototypes: 2 weeks– 100 asics: 2 weeks

• One test board has been produced to sort chips– Cabling ok– Firmware is the same as the previous spaciroc test board– Software should be modified to perform automatic tests

• 2 types of pcbs are foreseen:

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1 with a straight flexible partConnector on top

1 with a curved flexible partConnector on bottom

9

• Connectors choice:

• EC_asic: HIROSE FX2CA-68S-1.27DSA- Receptacle- Dimension=49mm x 7.5mm- Straight type- Through hole type

• Not exactly the same pinout for the 2 types of EC_anode

=> For EC_asic design, we need to know which connector corresponds to which type of EC_anode

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• 3 EC_unit + 2 EC_ASIC boards– Curved EC_anodes: connectors A, C, E– Straigth EC_anodes: connectors B, D, F

• One EC_asic reads half of the EC_unit

1 2 3 4 5 6 7 8 57 49 41 33 25 17 9 1 1 2 3 4 5 6 7 8 57 49 41 33 25 17 9 1 1 2 3 4 5 6 7 8 57 49 41 33 25 17 9 1

9 10 11 12 13 14 15 16 58 50 42 34 26 18 10 2 9 10 11 12 13 14 15 16 58 50 42 34 26 18 10 2 9 10 11 12 13 14 15 16 58 50 42 34 26 18 10 2

17 18 19 20 21 22 23 24 59 51 43 35 27 19 11 3 17 18 19 20 21 22 23 24 59 51 43 35 27 19 11 3 17 18 19 20 21 22 23 24 59 51 43 35 27 19 11 3

25 26 27 28 29 30 31 32 60 52 44 36 28 20 12 4 25 26 27 28 29 30 31 32 60 52 44 36 28 20 12 4 25 26 27 28 29 30 31 32 60 52 44 36 28 20 12 4

33 34 35 36 37 38 39 40 61 53 45 37 29 21 13 5 33 34 35 36 37 38 39 40 61 53 45 37 29 21 13 5 33 34 35 36 37 38 39 40 61 53 45 37 29 21 13 5

41 42 43 44 45 46 47 48 62 54 46 38 30 22 14 6 41 42 43 44 45 46 47 48 62 54 46 38 30 22 14 6 41 42 43 44 45 46 47 48 62 54 46 38 30 22 14 6

49 50 51 52 53 54 55 56 63 55 47 39 31 23 15 7 49 50 51 52 53 54 55 56 63 55 47 39 31 23 15 7 49 50 51 52 53 54 55 56 63 55 47 39 31 23 15 7

57 58 59 60 61 62 63 64 64 56 48 40 32 24 16 8 57 58 59 60 61 62 63 64 64 56 48 40 32 24 16 8 57 58 59 60 61 62 63 64 64 56 48 40 32 24 16 8

8 16 24 32 40 48 56 64 64 63 62 61 60 59 58 57 8 16 24 32 40 48 56 64 64 63 62 61 60 59 58 57 8 16 24 32 40 48 56 64 64 63 62 61 60 59 58 57

7 15 23 31 39 47 55 63 56 55 54 53 52 51 50 49 7 15 23 31 39 47 55 63 56 55 54 53 52 51 50 49 7 15 23 31 39 47 55 63 56 55 54 53 52 51 50 49

6 14 22 30 38 46 54 62 48 47 46 45 44 43 42 41 6 14 22 30 38 46 54 62 48 47 46 45 44 43 42 41 6 14 22 30 38 46 54 62 48 47 46 45 44 43 42 41

5 13 21 29 37 45 53 61 40 39 38 37 36 35 34 33 5 13 21 29 37 45 53 61 40 39 38 37 36 35 34 33 5 13 21 29 37 45 53 61 40 39 38 37 36 35 34 33

4 12 20 28 36 44 52 60 32 31 30 29 28 27 26 25 4 12 20 28 36 44 52 60 32 31 30 29 28 27 26 25 4 12 20 28 36 44 52 60 32 31 30 29 28 27 26 25

3 11 19 27 35 43 51 59 24 23 22 21 20 19 18 17 3 11 19 27 35 43 51 59 24 23 22 21 20 19 18 17 3 11 19 27 35 43 51 59 24 23 22 21 20 19 18 17

2 10 18 26 34 42 50 58 16 15 14 13 12 11 10 9 2 10 18 26 34 42 50 58 16 15 14 13 12 11 10 9 2 10 18 26 34 42 50 58 16 15 14 13 12 11 10 9

1 9 17 25 33 41 49 57 8 7 6 5 4 3 2 1 1 9 17 25 33 41 49 57 8 7 6 5 4 3 2 1 1 9 17 25 33 41 49 57 8 7 6 5 4 3 2 1

Pmt 1

Pmt 3

Pmt 2

Pmt 4

B C D

A

E F

F E

A

D C B

• Ki input: sum of 8 consecutive anodes

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1 2 3 4 5 6 7 8 57 49 41 33 25 17 9 1 1 2 3 4 5 6 7 8 57 49 41 33 25 17 9 1 1 2 3 4 5 6 7 8 57 49 41 33 25 17 9 1

9 10 11 12 13 14 15 16 58 50 42 34 26 18 10 2 9 10 11 12 13 14 15 16 58 50 42 34 26 18 10 2 9 10 11 12 13 14 15 16 58 50 42 34 26 18 10 2

17 18 19 20 21 22 23 24 59 51 43 35 27 19 11 3 17 18 19 20 21 22 23 24 59 51 43 35 27 19 11 3 17 18 19 20 21 22 23 24 59 51 43 35 27 19 11 3

25 26 27 28 29 30 31 32 60 52 44 36 28 20 12 4 25 26 27 28 29 30 31 32 60 52 44 36 28 20 12 4 25 26 27 28 29 30 31 32 60 52 44 36 28 20 12 4

33 34 35 36 37 38 39 40 61 53 45 37 29 21 13 5 33 34 35 36 37 38 39 40 61 53 45 37 29 21 13 5 33 34 35 36 37 38 39 40 61 53 45 37 29 21 13 5

41 42 43 44 45 46 47 48 62 54 46 38 30 22 14 6 41 42 43 44 45 46 47 48 62 54 46 38 30 22 14 6 41 42 43 44 45 46 47 48 62 54 46 38 30 22 14 6

49 50 51 52 53 54 55 56 63 55 47 39 31 23 15 7 49 50 51 52 53 54 55 56 63 55 47 39 31 23 15 7 49 50 51 52 53 54 55 56 63 55 47 39 31 23 15 7

57 58 59 60 61 62 63 64 64 56 48 40 32 24 16 8 57 58 59 60 61 62 63 64 64 56 48 40 32 24 16 8 57 58 59 60 61 62 63 64 64 56 48 40 32 24 16 8

8 16 24 32 40 48 56 64 64 63 62 61 60 59 58 57 8 16 24 32 40 48 56 64 64 63 62 61 60 59 58 57 8 16 24 32 40 48 56 64 64 63 62 61 60 59 58 57

7 15 23 31 39 47 55 63 56 55 54 53 52 51 50 49 7 15 23 31 39 47 55 63 56 55 54 53 52 51 50 49 7 15 23 31 39 47 55 63 56 55 54 53 52 51 50 49

6 14 22 30 38 46 54 62 48 47 46 45 44 43 42 41 6 14 22 30 38 46 54 62 48 47 46 45 44 43 42 41 6 14 22 30 38 46 54 62 48 47 46 45 44 43 42 41

5 13 21 29 37 45 53 61 40 39 38 37 36 35 34 33 5 13 21 29 37 45 53 61 40 39 38 37 36 35 34 33 5 13 21 29 37 45 53 61 40 39 38 37 36 35 34 33

4 12 20 28 36 44 52 60 32 31 30 29 28 27 26 25 4 12 20 28 36 44 52 60 32 31 30 29 28 27 26 25 4 12 20 28 36 44 52 60 32 31 30 29 28 27 26 25

3 11 19 27 35 43 51 59 24 23 22 21 20 19 18 17 3 11 19 27 35 43 51 59 24 23 22 21 20 19 18 17 3 11 19 27 35 43 51 59 24 23 22 21 20 19 18 17

2 10 18 26 34 42 50 58 16 15 14 13 12 11 10 9 2 10 18 26 34 42 50 58 16 15 14 13 12 11 10 9 2 10 18 26 34 42 50 58 16 15 14 13 12 11 10 9

1 9 17 25 33 41 49 57 8 7 6 5 4 3 2 1 1 9 17 25 33 41 49 57 8 7 6 5 4 3 2 1 1 9 17 25 33 41 49 57 8 7 6 5 4 3 2 1

Pmt 1 Pmt 2

B C D

A

E F

F E

A

D C B

• To check the routing feasibility:• Schematic simpler:

• 2 connectors: connector A (curved kapton) and connector B (straight kapton)• 2 SPACIROC• Connector 120pins

ki1 ki2

ki3 ki4

ki4 ki3

ki2 ki1

ki2 ki6

ki1 ki5

ki5 ki1

ki6 ki2

ki1 ki2

ki3 ki4

ki1 ki2

ki3 ki4

ki5 ki1

ki6 ki2

ki5 ki1

ki6 ki2

ki4 ki3

ki2 ki1

ki3

ki2 ki1

ki2 ki6

ki1 ki5

ki2 ki6

ki1 ki5

ki4

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The ASIC: SPACIROC (2/3)

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• Dimension could be 140mm x 110mm

• Modifications:

– Vertical red parts should be modified• Increase area for EC_ASIC boards

– Support structures have to be aligned with the holes like the central one otherwise cables do not pass

– Find room for the HV box boards

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• Material: Aluminum• Weight: 0.300 kg• Overall dimensions: 167mm x 128mm x 130mm• Available area for elect. : 115mm x 100mm => not enough

~ 55 mmAs short

as possible

Pair of EC-

ASIC boards

Need to study how to screw the boards: EC_asic, HV box boards and PDM board

130

130

167167128128

• Connector 120 pins should be enough

• Choice: HIROSE FX2-120P-1.27DS– Header– Dimension=82mm x 7.5mm– Right angle type– Through hole

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Input name and number of pins Output name and number of pins

avdd 4 Sr_ck 1 Clk_40n 1 Adata_ki 1 Atransmit_on 1 Adata_pc[7..0] 8 AOR_ki_sum 1 Aerror_sc 1

vdd_ki 2 Sr_in 1 Clk_40p 1 Bdata_ki 1 Btransmit_on 1 Bdata_pc[7..0] 8 BOR_ki_sum 1 Berror_sc 1

dvvd 4 sr_out 1 Clk_gtu_n 1 Cdata_ki 1 Ctransmit_on 1 Cdata_pc[7..0] 8 COR_ki_sum 1 Cerror_sc 1

VH 4 Sr_rstb 1 Clk_gtu_p 1 Ddata_ki 1 Dtransmit_on 1 Ddata_pc[7..0] 8 DOR_ki_sum 1 Derror_sc 1

gnd 14 resetb 1 Val_evt_n 1 Edata_ki 1 Etransmit_on 1 Edata_pc[7..0] 8 EOR_ki_sum 1 Eerror_sc 1

Select_sc_probe 1 Val_evt_p 1 Fdata_ki 1 Ftransmit_on 1 Fdata_pc[7..0] 8 FOR_ki_sum 1 Ferror_sc 1

Loadb_sc 1 AOR_FSU 1 COR_FSU 1 EOR_FSU 1

Select_din 1 BOR_FSU 1 DOR_FSU 1 FOR_FSU 1

• What will be the connection between the EC_ASIC and the PDM board?• Kapton or cable ?

• Who is in charge of this connection

• Week 9: 24 Jan-3 Feb– Feasibility routing inputs with 2 through hole connectors

• Week 10: 5 -9 Mar– Feasibility routing inputs with 2 surface mounted connectors– Schematic of whole EC_asic

• Week 11-14: 12 Mar- 6Apr– Routing whole EC_asic => the dimensions will be set– Schematic of a test board (test_ec_asic) to check functionalities of one EC_ASIC

• Week 15-16: Easter holidays

• Week 17-21: 23 Apr- 25May– Routing test_ec_asic board

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• Production PCBs will be done when the money is available• Cabling and component procurement will be managed by us

• LAL team manage schematic, routing and production of EC_ASIC boards

• Dimension could be as low as 140mm x 110mm (routing will be checked)

• To Be Defined:– Who can do the mechanical modifications?– Who is in charge of the connection between

EC_ASIC and the PDM board (lack of manpower and time at LAL)?

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