Rev1 HPPS Projects 2007
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POLITECNICO DI MILANO
High Performance Processors and
Systems PdM – UIC joint master 2007PdM – UIC joint master 2007
Instructor: Prof. Donatella SciutoInstructor: Prof. Donatella Sciuto
HPPS @ PdM – March 2007HPPS @ PdM – March 2007
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2
OutlineOutline
DReAMSAlessandro PanellaMatteo Murgida
CITiESAlessio MontoneAlessandro MeroniSimone Corbetta
Operating SystemIvan Beretta
Design FlowAntonio Piazzi
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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3
What’s nextWhat’s next
DReAMSAlessandro PanellaMatteo Murgida
CITiESAlessio MontoneAlessandro MeroniSimone Corbetta
Operating SystemIvan Beretta
Design FlowAntonio Piazzi
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
DDynamicynamic Re Reconfigurabilityconfigurability AAppliedpplied toto M Multi-FPGAulti-FPGA
SSystemsystems
DReAMS
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DReAMSDReAMS
Dynamic ReconfigurabilityApplied to Multi-
FPGA SystemsBranch of DRESD projectInherits architectures and tools
Automatic workflow from VHDL system description to FPGA implementation
VHDL parsing and system simulationSystem creation over a specific architectureBitstream creation and download onto FPGAs
DReAMS
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Project OrganizationProject Organization
First Phase (15 Mar- 15 Apr)Goals
State of the art analysisProposed approach: basic idea
Second Phase (15 Apr – 15 May)Goal
Partitioning algorithm: development and implementation
Third Phase (15 May – 15 June)Goal
Algorithm experimental evaluationPhysical evaluation using the Kmera (DIP) architecture
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First Phase: resultsFirst Phase: results
Analysis of several partitioning approaches“Classic” methods (KL, FM)Iterative methods (Genetic, Tabu Search, Simulated Annealing)Multilevel methods (METIS, hMETIS)“Structural” methods
Our approach (some hints)Structural methodExploit already existing tools to create the structural treePartitioning
Exploit the hyerarchyGraph-covering approachFocus on cutsize minimization
ProsModular fashionLess communication problemsNo need of “extremely” efficient algorithm
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What’s next…What’s next…
Second Phase
Existing tools exloration (XST, EDK, Synplify Pro)How to retrieve information?How to build a structural tree?How to use it?
Proposed algorithmDefinitionImplementationBenchmark indentification
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10
What’s nextWhat’s next
DReAMSAlessandro PanellaMatteo Murgida
CITiESSimone CorbettaAlessandro MeroniAlessio Montone
Operating SystemIvan Beretta
Design FlowAntonio Piazzi
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
ChimeraChimeraMulti-FPGAs Architecture DefinitionMulti-FPGAs Architecture Definition
Matteo [email protected]
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Project OrganizationProject Organization
1st PhaseGoals:Digilent Spartan3- Starter Board studyBoards connection
2nd PhaseGoals: Distributed architecture description Communication protocol definition and implementation
3rd PhaseGoal: Design a simple distribuited application to verify the correctness of the proposed approach
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First Phase: resultsFirst Phase: results
Choice of the A2 Expansion Connector to allow communication between two boardsLeds (located on one or two boards) control implemented both manually and via MicroblazeConfiguration of the connector pins to support the future communication protocol
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What’s next…What’s next…
Second phase organization…
Communication protocol design
Design the IP-Cores needed by the communication protocolDistributed core design methodology - first definitionReconstruction of the original data in the receiverImplementation of the Call/Ack mechanism
Microblazes (one per board) data exchange
Application design and development to validate the proposed approach
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15
What’s nextWhat’s next
DReAMSAlessandro PanellaMatteo Murgida
CITiESAlessio MontoneAlessandro MeroniSimone Corbetta
Operating SystemIvan Beretta
Design FlowAntonio Piazzi
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
CITiESCITiES
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CITiESCITiES
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POLITECNICO DI MILANO
PProcessingrocessing E Elementslements REREconfigurationconfiguration I Inn
RReconfigurableeconfigurable A Architecturesrchitectures
Alessio [email protected]
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Project OrganizationProject Organization
First PhaseTime window: 15/March – 15/AprilGoal:
bitstream structure analysismemory mapping equations formalization
Second PhaseTime window: 15/April – 15/MayGoal: Implement mapping algorithm and equations
Third PhaseTime window: 15/May – 15/JuneGoal: Harware Validation
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First Phase: resultsFirst Phase: results
Understanding of:Bitstream StructureArchitectural Memory Mapping File (BMM)Compiled source code (ELF)
Formalization of:Code Splitting (on BRAM Blocks) AlgorithmBRAM Content Mapping Equations
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What’s next…What’s next…
Second phase in detailsCreate a software that
Takes in input .bmm (BRAM used) and .elf (code) fileOutputs: memory configuration bitstreamIs device parametricIs tailored for Xilinx Virtex II Pro Family FPGAs
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22
What’s nextWhat’s next
DReAMSAlessandro PanellaMatteo Murgida
CITiESAlessio MontoneAlessandro MeroniSimone Corbetta
Operating SystemIvan Beretta
Design FlowAntonio Piazzi
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
RReconfigurationeconfiguration O Orientedriented MeMetricstrics
Alessandro [email protected]
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Project OrganizationProject Organization
First PhaseTime Window: 15/March - 15/AprilGoal: Analysis of a well-known set of metrics
Second PhaseTime Window: 15/April - 15/MayGoal: Metrics definition and implementation
Third PhaseTime Window: 15/May - 15/JuneGoal: Creation of a metrics Simulator
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First Phase: ResultsFirst Phase: Results
Communication Achitectures analyzedPoint-to-pointBusNetwork-on-Chip
Performance Parameters evaluatedLatency, Bandwidth, ThroughputTopology
Cost Factors evaluatedArea usagePower Consumption
Final Report that summerizes the results
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What’s next…What’s next…
Second PhaseMetrics implementation and rules definition:
To improve the system performancesTailored for the dynamic reconfiguration of the communication infrastructure, e.g.:
The creation of a new Processing ElementThe change of the routing protocol exploited
Study and analysis of different simulatorsNS2…
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27
What’s nextWhat’s next
DReAMSAlessandro PanellaMatteo Murgida
CITiESAlessandro MeroniAlessio MontoneSimone Corbetta
Operating SystemIvan Beretta
Design FlowAntonio Piazzi
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
REREconfigurableconfigurable CCommunicationommunication
IInfrastructurenfrastructure F Foror EEmbedded-systemsmbedded-systems
Simone [email protected]
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Project OrganizationProject Organization
Goal: design a communication infrastructure tailored for reconfigurable FPGA-based embedded system
Organization: three phasesPHASE 1 (due to 12th April):
literature analysis on communication infrastructure paradigms and design choicesSurvey
PHASE 2 (due to 17th May)De Micheli architecture exploration
PHASE 3 (due to 17th June)Communication infrastructure model definition
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First Phase: resultsFirst Phase: results
Literature analysis - Topics:Communication infrastructure definitionCI design choices and trades-offUnderstanding different CI paradigms
AdvantagesPitfallsImprovements
Existing applications and solutions (both academic and commercial)
Survey: conveys study and analysis of different approaches.
The base for future work
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Next PhaseNext Phase
Networks-on-Chip De Micheli state-of-the-artVHDL descriptionStudy, analysis Improvements (if any...)Tailoring for dynamically reconfigurable systems
SurveyExtension to specific De Micheli's NoC architectureCommunication infrastructure design methodology used in ReCIFE
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32
What’s nextWhat’s next
DReAMSAlessandro PanellaMatteo Murgida
CITiESAlessio MontoneAlessandro MeroniSimone Corbetta
Operating SystemIvan Beretta
Design FlowAntonio Piazzi
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
Development of an OS Development of an OS architecture-independent architecture-independent
layer for dynamic layer for dynamic reconfigurationreconfiguration
Ivan [email protected]
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Project OrganizationProject Organization
First PhaseGoal: State of the art and Boot process analysis
Second PhaseGoal: Implementation and comparison of the existing solutions
Third PhaseGoal: Definition of the new architecture-independent layer and testing
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First Phase: resultsFirst Phase: results
Analysis of the Caronte solutionReconfiguration controller driverIP-Core manager
Analysis of the DRESD-SW solutionReconfiguration controller, MAC, LOL ,Reconfiguration LibraryROTFL Architecture
Caronte implementation studyBoot process
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What’s next…What’s next…
Second phase:
Implementation of the DRESD operating system solution, based on ISE and EDK 9.1 version, on Xilinx Virtex II Pro VP7 and VP20
Previous solution comparisonDynamic reconfiguration OS support abstraction layer: basic idea
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37
What’s nextWhat’s next
DReAMSAlessandro PanellaMatteo Murgida
CITiESAlessio MontoneAlessandro MeroniSimone Corbetta
Operating SystemIvan Beretta
Design FlowAntonio Piazzi
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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Project organizationProject organization
1 st phaseTime window: 15 March – 15 AprilGoal: Understand the execution of each previous tool (archgen, yara’s console script and inca)
2 nd phaseTime window: 15 April – 15 MayGoal: Create an algorithm to merge each tool and a directory structure skeleton for each project type
3 rd phaseTime window: 15 May – 15 JuneGoal: Create and test the new tool with almost four architecture (2 YARA based and 2 InCA based) on Spartan and Virtex FPGA family
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First phase’s resultsFirst phase’s results
Study phase:Archgen
Which are inputs and outputs and how this tool work
YaRALearn the directory structure and the console script which automates the work flow
InCAUnderstand the early access reconfiguration flow proposed by Xilinx and how this tool complete its function
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The future is looking for usThe future is looking for us
Now: for each work flow and for each architecture we have to execute a file.
Tomorrow: Unique file to create an architecture and rebuild her workflow.
Tool phases
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Before After
Planning
VHDL gen.
UCF and Com. Inf. Gen.
Bitstream gen.
Merging phase
Planning
VHDL gen.
UCF and Com. Inf. Gen.
Bitstream gen.
Merging phase
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4242
What’s nextWhat’s next
DReAMSAlessandro PanellaMatteo Murgida
CITiESAlessio MontoneAlessandro MeroniSimone Corbetta
Operating SystemIvan Beretta
Design FlowAntonio Piazzi
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
PolarisPolaris
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POLITECNICO DI MILANO
Effects of 2D Reconfiguration Effects of 2D Reconfiguration in a Reconfigurable Systemin a Reconfigurable System
Massimo [email protected]
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Project OrganizationProject Organization
First Phase:General analysis of 2D reconfigurationDetailed description of the new problems
Second Phase:Analysis of possible solutions to those problemsEvaluation of alternatives
Third Phase:Propose a new combined solution to effectively handle problems of 2D reconfiguration
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First Phase: resultsFirst Phase: results
Definition of the settingAnalysis of the advantages of 2D Reconfiguration
In area usage and performance
Definition and Analysis of:
the 2D-fragmentation problem
Bi-dimensional placement
Communication infrastructure creation in 2D vs 1D
Bitstream generation phase complexity increase
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What’s next…What’s next…
Second phase:
Analysis of literature for proposed solutions to the problems defined in current phase
Selection of those that can be exploited in self partial dynamical run-time reconfiguration
Evaluation of different solutions to choose what is best suited to our problem
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What’s nextWhat’s next
DReAMSAlessandro PanellaMatteo Murgida
CITiESAlessio MontoneAlessandro MeroniSimone Corbetta
Operating SystemIvan Beretta
Design FlowAntonio Piazzi
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
Relocation for 2D Relocation for 2D Reconfigurable SystemsReconfigurable Systems
Marco [email protected]
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Project OrganizationProject Organization
First Phase:Examine Xilinx documentation of Virtex-4 and Virtex-5Analyze the new bitstream structure
Second Phase:Implement the new version of BiRF
Third Phase:Test of BiRF²Validate the results
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First Phase: resultsFirst Phase: results
Study of the new Virtex-4 and Virtex-5 FPGA:Analysis of the new architecture:
New frame addressingPossibility of addressing rows and columns
Generation and analysis of Virtex-4 and Virtex-5 bitstreams
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What’s next…What’s next…
Implementation of BiRF²:
Define the functionality:Determine fomulae for:
– FAR calculation– CRC calculation
Create the new bitstream parser
Design the structure BiRF²
HW implementation
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5353
What’s nextWhat’s next
DReAMSAlessandro PanellaMatteo Murgida
CITiESAlessio MontoneAlessandro MeroniSimone Corbetta
Operating SystemIvan Beretta
Design FlowAntonio Piazzi
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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Project OrganizationProject Organization
First PhaseTime window: 1st monthGoal: Clustering
Second PhaseTime window: 2nd monthGoal:Coloring
Third PhaseTime window: 3rd monthGoal:Scheduling
ClusteredGraph Metric
CircuitRepresentation
Reconfigurable
ClusteredGraph
AreaLatency
Rec. TimePower
Isomorphic
Target Architecture
Database
Gcc Frontend PartitioningAlgorithmPandA
SchedulingAlgorithm
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First Phase: resultsFirst Phase: results
Theoretical WorkRedefinition of HLR workflow
Interfaces between various phasesFlexible clustering and scheduling algorithms Suitable for future researches
Implementation of the Clustering phaseDFG Graph production
Used Panda --> 0.3 and 0.4Clustering Algorithm
Used Isomorphic reconfigurable partitioning
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What’s next…What’s next…
Second phase in detailsAdd to clustered graph reconfigurable info
Latency timeReconfiguration timeCluster areaEtc…
Definition of reconfigurable clustered graph structure
Implement a simple evaluation metric for latency times
Connect the flow with clustering phase