Resolving interrupt conflicts

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Resolving interrupt conflicts. An introduction to reprogramming of the 8259A Interrupt Controllers. Intel’s “reserved” interrupts. Intel had reserved interrupt-numbers 0-31 for the processor’s various exceptions But only interrupts 0-4 were used by 8086 - PowerPoint PPT Presentation

Transcript of Resolving interrupt conflicts

  • Resolving interrupt conflictsAn introduction to reprogramming of the 8259A Interrupt Controllers

  • Intels reserved interruptsIntel had reserved interrupt-numbers 0-31 for the processors various exceptionsBut only interrupts 0-4 were used by 8086Designers of the early IBM-PC ROM-BIOS disregarded the Intel reserved warningSo interrupts 5-31 got used by ROM-BIOS code for its own various purposesThis created interrupt-conflicts for 80286+

  • Exceptions in Protected-ModeThe interrupt-conflicts seldom arise while the processor is executing in Real-ModePC BIOS uses interrupts 8-15 for devices (such as timer, keyboard, printers, serial communication ports, and diskette drives)CPU uses this range of interrupt-numbers for various processor exceptions (such as page-faults, stack-faults, protection-faults)

  • Handling these conflictsThere are two ways we can resolve these interrupt-conflicts when we write handlers for device-interrupts in the overlap rangeWe can design each ISR to query the system in some way, to determine the cause for the interrupt-condition (i.e., a device or the CPU?) We can reprogram the Interrupt Controllers to use non-conflicting interrupt-numbers when the peripheral devices trigger their interrupts

  • Learning to program the 8259AEither solution will require us to study how the systems two Programmable Interrupt Controllers are programmedOf the two potential solutions, it is evident that greater system efficiency will result if we avoid complicating our interrupt service routines with any extra overhead (i.e., to see which component wished to interrupt)

  • Three internal registersIRRIMRISR8259AIRR = Interrupt Request RegisterIMR = Interrupt Mask RegisterISR = In-Service Registeroutput-signal input-signals

  • PC System Design8259APIC(slave)8259APIC(master)CPUINTR Programming is viaI/O-ports 0xA0-0xA1 Programming is viaI/O-ports 0x20-0x21

  • How to program the 8259AThe 8259A has two modes:Initialization ModeOperational ModeOperational Mode Programming:Write a (9-bit) command to the PICMaybe read a return-byte from the PICInitialization Mode Programming:Write a complete initialization sequence

  • How to access the IMRIf in operational mode, the Interrupt Mask Register (IMR) can be read or written at any time (by doing in/out with A0-line=1)Read the master IMR:in $0x21, %alWrite the master IMR:out %al, $0x21Read the slave IMR: in $0xA1, %alWrite the slave IMR: out %al, $0xA1

  • How to read the master IRRIssue the read register command-byte, with RR=1 and RIS=0; read return-byte:mov $0x0B, %alout %al, $0x20in $0x20, %al

  • How to read the master ISRIssue the read register command-byte, with RR=1 and RIS=1; read return-byte:mov $0x0A, %alout %al, $0x20in $0x20, %al

  • End-of-InterruptIn operational mode (unless AEOI was programmed), the interrupt service routine must issue an EOI-command to the PICThis clears an appropriate bit in the ISR and allows other unmasked interrupts of equal or lower priority to be issuedThe non-specific EOI-command clears the In-Service Registers highest-priority bit

  • Some EOI examplesSend non-specific EOI to the master PIC:mov $0x20, %alout %al, $0x20

    Send non-specific EOI to both the PICs:mov $0x20, %alout $%al, 0xA0out %al, $0x20

  • Initializing the 8259AA series of 9-bit values is sent to the PIC Once its begun, it must be completedEach 9-bit values is called an Initialization Command Word (abbreviated ICW)The least significant 8 bits are sent on the PCs data-bus, while the 9th bit is sent as bit 0 on the PCs address-bus

  • Official ReferenceThe official Intel programming reference manual for the 8259A is available online (see Resources on our course website)This document is 24 pages in .pdf formatMany pages are irrelevant to programmers (e.g., they are concerned with electrical specifications, physical dimensions, pin configurations, and heating restrictions)

  • ICW1 and ICW20A7A6A51LTIMADISNGLIC41A15/ T7A14/ T6A13/ T5A12/ T4A11/ T3A10A9A8ICW1ICW2LTIM (1 = Level-Triggered Interrupt Mode, 0 = Edge-Triggered Interupt Mode)ADI is length of Address-Interval for call-instruction (1 = 4-bytes, 0 = 8-bytes) SNGL (1 = single controller system, 0 = multiple controllers in cascade mode)IC4 means Initialization Command-Word 4 is needed (1 = yes, 0 = no)

  • ICW31S7S6S5100000ID2ID1ID0(master)(slave)S4S3S2S1S0S Interrupt-Request Input is from a slave controller (1=yes, 0=no)ID number of slave controllers input-pin to master controller (0-7)

  • ICW41000SFNMBUFM / SAEOIPM microprocessor mode 1=8086/8088 0=8080Automatic EOI mode 1 = yes, 0 = noSpecial Fully-Nested Mode (1 = yes, 0 = no) NON-BUFFERED mode (00 or 01)BUFFERED-MODE (10 = slave, 11 = master)

  • Initializing the master PICWrite a sequence of four command-bytes(Each command is comprised of 9-bits)0000100011100000100100000001A0D7D6D5D4D3D2D1D0ICW1=0x11ICW2=baseIDICW3=0x04ICW4=0x01

  • Initializing the slave PICWrite a sequence of four command-bytes(Each command is comprised of 9-bits)0000100011100000010100000001A0D7D6D5D4D3D2D1D0ICW1=0x11ICW2=baseIDICW3=0x02ICW4=0x01

  • Unused real-mode ID-rangeWe can use our showivt.s demo to see the unused real-mode interrupt-vectorsOne range of sixteen consecutive unused interrupt-vectors is 0x90-0x9FWe created a demo-program (reporter.s) to reprogram the 8259s to use this rangeThis could be done in protected-mode, tooIt would resolve the interrupt-conflict issue

  • Other ideas in the demoIt uses an assembly language macro to create sixteen different ISR entry-points:.macroisridpushfpushw$\idcallaction.endm All the instances of this macro call to a common interrupt-handling procedure (named action)

  • The Macros expansionIf the macro-definition is invoked, with an argument equal to, say, 0x08, like this:isr0x08then the as assembler will expand that macro-invocation, replacing it with:pushfpushw $0x08callaction

  • How action worksUpon entering the action procedure, the system stack has six words:

    The two topmost words (at bottom of picture) will get replaced by the interrupt-vector corresponding to int-IDFLAGSCSIPFLAGSInterrupt-IDreturn-from-actionSS:SP

  • The stack statesFLAGSFLAGSFLAGSFLAGSCSIPCSCSCSIPIPIPFLAGSInt-IDaction-returnFLAGSvector-HIvector-LOStage 1Stage 2Stage 3Stage 4Upon entering isr Upon entering action Before exiting action After exiting action(and entering ROM-BIOS interrupt- handler)

  • The on-screen status-lineWe call ROM-BIOS services to setup the video display-mode for 28-rows of textWe use lines 0 through 24 for the standard 80-column by 25-rows of text outputLine 25 is kept blank (as visual separator)Lines 26 and 27 are used to show sixteen labeled interrupt-counters (IRQ0-IRQ15)Any device-interrupt increments a counter

  • In-class exerciseThe main new idea was reprogramming of the 8259A Interrupt Controllers, in order to avoid overloading of any Intel reserved interrupt-numbers: 0x00 - 0x1FModify our tickdemo.s program so that a timer-tick interrupt in protected-mode will get routed through Interrupt Gate 0x20 (instead of through reserved Gate 0x08)