Ming Liu

Institute of Microelectronics, CAS

Feb.7, 2014

EDS Mini Colloquim WIMNACT 39, Tokyo

Resistive Switching Memory

in Integration

Outline

Motivation

RRAM Integration

Self-Rectifying RRAM

1D1R Integration

1k HfO2 based RRAM Test Chip

Summary

3

Concepts proposed by D.

Kahng and S. M. Sze, Bell Lab,

1967

Kahng and S. M. Sze, Bell Systems

Technical Journal 46 (1967) 1288.

Flash Memory

•Uses Fowler-Nordheim tunneling to erase

the memory

•Uses CHE or FN to program the memory

Total Semiconductor market : 300 B US$ in 2011; Memory occupied 23.9%

semiconductor market.

Flash - E2PROM (NOR Type) NAND - E2PROM

Control Gate

Floating Gate

Drain Source

WL1

WL2

WL3

WL16

1 Transistor / 1 Bit

Bit Line Basic unit

18 Transistor / 32 Bit

Bit Line Basic unit

WL1

WL2

WL3

WL4

WL14

WL15

WL16

SG (D)

SG (D)

Drain Source

Control Gate

WL1 WL2 WL3 WL14 WL15 WL16Select Gate

SG (D)

Select Gate

SG (S)

NOR Type Flash: High Speed，Random Access per bit, Code Storage

NAND Type Flash : High Density，Block Access , Data Storage

Flash Integration

Challenges of Flash scaling down

Crosstalk effect Low No. of electron Leakage current

Physical limitations exist!

–– leakage current

–– High voltage operations

–– Charge storage requirements of the dielectrics and reliability issues

–– Slow writing speed

3D Flash Architecture

Vertical structure

1st Mass Production of 3D VNAND

Integration Trend of Memory

3D integration is the mainstream to enhance the storage density of memory.

3D RRAM is one of the most promising candidates of Flash memory.

Outline

Motivation

RRAM Integration

Self-Rectifying RRAM

1D1R Integration

1k HfO2 based RRAM Test Chip

Summary

MIM: resistive switching

under electric fieldBipolar switching

Advantages of RRAM:

Simple device structure（MIM）

Good compatibility with CMOS process

Easy scaling down to 8 nm

Large on/off ratio (103~106)

Fast operating speed（~ns）

Good endurance (>106)

Good retention (>10years)

Unipolar switching

What is RRAM?

Opportunities for RRAM

Working memory

Embedded NVM

Stand-alone NVM

Working memory

Embedded NVMStand-alone NVM

RRAM

Required memory specs

Expected RRAM specs

RRAM is not suitable for working memory, but quite competitive

for embedded and stand-alone NVM application.

RRAM Integration: Active or Passive Array

Active

6~8F2

Ref. A. Chen, et al., IEDM 2005, pp. 765-768.

Passive

4F2

Ref. ITRS 2010.

Passive crossbar array structure is the best choice for high

storage density application！

3D RRAM Integration

Ref. ITRS 2010.

Passive crossbar array structure is the good choice for high

storage density application！

2D RRAM crossbar — 4F2

3D RRAM crossbar — 4F2/n

HRS HRS

HRS HRS

Vread Open

V=0

Open

HRS LRS

LRS LRS

Vread Open

V=0

Open

When reading a HRS cell, if the

surrounded cells are all in HRS,

the reading is correct.

If some surrounded cells is in LRS

and form a sneak current path, the

HRS cell will be misread as LRS.

×

Sneaking Current in RRAM Integration

Ref. I. G. Baek, et al., IEDM 2005; B. Cho, et al.,Adv. Mater. 2009

solution

-3 -2 -1 0 1 21E-9

1E-7

1E-5

1E-3

Cu

rre

nt

(A)

Voltage (V)

20x200x

bit ‘0’

bit ‘1’

(1). 1D1R

(2). 1S1R

(3). Self-

Rectifying

How to Suppress Sneaking Current

How to Suppress Sneaking Current

1R: RRAM with self-rectifying effect

1 Selector + 1 RRAM

Requirements of Selector:

High current density (Jselector>Jreset,RRAM)

High rectifying ratio or nonlinear factor

Compatible with CMOS

Low fabrication temperature (<400℃ set by the copper BEOL)

Solutions

Schematic of the crosstalk effect

Asymmetric I-V curve

Outline

Motivation

RRAM Integration

Self-Rectifying RRAM

1D1R Integration

1k HfO2 based RRAM Test Chip

Summary

Typical I-V characteristics of the Au/ZrO2 :nc-Au/n+ Si device, it

showed low switch voltage and producible set and reset process.

RRAM with (Au/ZrO2:Au/n+-Si)

-4 -2 0 2 410

-11

10-9

10-7

10-5

10-3

Curr

ent (A

)

Voltage (V)

C

ResetSet

1

23

4

Q Zuo, et al., J. Appl. Phys. , 106, 073724 (2009).

n+-Si

Au NC

Au

ZrO2

Device structure

TEM image of the device

RRAM with (Au/ZrO2:Au/n+-Si)

0 25 50 75 100

10-10

10-8

10-6

10-4

Cu

rre

nt

(A)

Cycle (#)

LRS @0.5 V

HRS @0.5 V

100

101

102

103

103

105

107

109

Re

sis

tance

(

)

Time (s)

LRS @0.5 V

HRS @0.5 V

The Au/ZrO2:Au/n+-Si device demonstrated very good cycling and

retention characteristics.

Q Zuo, et al., J. Appl. Phys. , 106, 073724 (2009).

-1.0 -0.5 0.0 0.5 1.0

10-9

10-7

10-5

10-3

Curr

ent (A

)

Voltage (V)

700

Self-rectifying Characteristics

0 50 100

10-9

10-8

10-7

10-6

10-5

10-4

Cu

rre

nt (A

)

Switching number

@ 0.5 V

@ -0.5 V

The Au/ZrO2:Au/n+ Si has a very good rectifying characteristics at

LRS. Ion/Ioff ratio is 700.

After 100 cycling, its rectifying characteristics is still keeping very

well.

Q Zuo, et al., J. Appl. Phys. , 106, 073724 (2009).

0 2 4 6 8

101

102

103

104

Re

sis

tan

ce

()

X Axis Title

Ron in sigle cell ��

Roff in sigle cell

Ron without rectifying

Roff without rectifying

Ron with rectifying

Roff with rectifying

AA B C

Comparison in 2×2 Array

Group A: HRS and LRS of Single device;

Group B: HRS and LRS of 2×2 array without rectifying;

Group C: HRS and LRS of 2×2 array with rectifying

Self-Rectifying RRAM for WORM Application

10-10

10-8

10-6

10-4

10-2

0

20

40

60

80

100

Cum

ula

tive P

robabili

ty (

%)

Current (A)

After PRG

Before PRG

Area 200x200m2

Read @ 1V

x106

100

101

102

103

104

10510

1

103

105

107

109

1011

After PRG

Before PRG

Resis

tance (

)

Time (s)

Read @ 1 V • Large rectifying ratio (>104)

• RHRS/RLRS >106

• High uniformity

• Long retention time

Data retention

Uniformity of the states before and after program

IEEE Electron Device Letters, 2010, 29, 43

US Patent 2012/0140543 Al

Self-Rectifying Mechanism

Adv. Mater. 24, 1844, 2012

Ag CF

n+-Si

HfO2

Ag

Ag

Based on the TEM results, we demonstrated that the CF composition in the oxide-

electrolyte-based RRAM mainly consists of the electrode materials when using Cu, Ag

or Ni as electrode.

By using semiconductor as another electrode, RRAM with self-rectifying effect can be

obtained, and the rectifying characteristics is controlled by metal and semiconductor

electrodes.

The Role of Silicon for Self-Rectifying RRAM

n+-Si/a-Si/Ag n+-Si/ZrOx/Pt NiSi/HfOx/TiN

APL 2009 JAP 2009 VLSI 2011

Metallic property of conductive filaments → Ohmic contact with metal electrode → No rectifying characteristics.

Highly doped Si is generally needed to guarantee a Schottky contact of CF with c-Si.

Crystal Si is not expected for 3D integration.

A-Si to achieve Self-rectifying RRAM

Si(100)

SiO2

Cu

WO3

Pt

TE

BE

4200-SCS DC bias/control

a-Si

Cu

a-Si

WO3

Pt

100 nmSi(100)

SiO2

Cu

WO3

Pt

TE

BE

4200-SCS DC bias/control

a-Si

Cu

a-Si

WO3

Pt

100 nm

Why a-Si?

Requirements of low fabrication temperature (<400℃ set by the copper BEOL)

for 3D integration.

√.CMOS compatible;√. Low temperature fabricate;√. Cheap;√. well controlled

process;

Memory Characteristics

The device exhibits bipolar switch behavior, there is 20 times window

between HRS and LRS;

Very excellent stability, even after 103 and 106 switch pulses, there is

still no obvious shift.

-2 -1 0 1 2 3

10-9

10-8

10-7

10-6

10-5

10-4

RESET

1st cycle

after 10 pulses

after 10 pulses

Cu

rre

nt (A

)

Voltage (V)

3

6

@ 25 oC

SET

-2 -1 0 1 2 3

10-9

10-8

10-7

10-6

10-5

10-4

RESET

1st cycle

after 10 pulses

after 10 pulses

Cu

rre

nt (A

)

Voltage (V)

3

6

@ 25 oC

SET

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10-4

-3

-2

-1

0

1

2

3

4

Vo

lta

ge

(V

)

SET Voltage

RESET Voltage

C1 C2 C3 C4 C5 C6 C7 C8 C9 C1010

4

105

106

107

Re

sis

tan

ce

(

)

10x window

HRS

LRS

Uniformity of DTD and CTC

Excellent switching uniformity in cycle-to-cycle and device-to-device.

(data were collected from 100 switching cycles in random selected 10

cells)IEEE Electron Device Letters, 2013, 34, 229

International Memory Workshop, 2013

Patent NO. 201210311109.8

Programming Speed and Cycling

1E-8 1E-7 1E-6 1E-5

106

107

108

Re

sis

tan

ce

(

)

P/E pulse width (sec)

HRS(bit’0’)

LRS(bit’1’)

Temp=25 ℃

1E-8 1E-7 1E-6 1E-5

106

107

108

Re

sis

tan

ce

(

)

P/E pulse width (sec)

HRS(bit’0’)

LRS(bit’1’)

Temp=25 ℃

100

102

104

106

108

1010

1012

106

107

108

Re

sis

tan

ce

(

)P/E cycles (#)

HRS(bit’0’)

LRS(bit’1’)

Temp=25 ℃

100

102

104

106

108

1010

1012

106

107

108

Re

sis

tan

ce

(

)P/E cycles (#)

HRS(bit’0’)

LRS(bit’1’)

Temp=25 ℃

Very fast switching speed, 30 ns both for write and erase;

Endurance is more than 109 switching cycles.IEEE Electron Device Letters, 2013, 34, 229

International Memory Workshop, 2013

Patent NO. 201210311109.8

Self-Rectifying Characteristics

Obvious rectifying characteristics for both HRS and LRS after forming,

rectify ratio is 200;

Excellent reliability and reproducibility.IEEE Electron Device Letters, 2013, 34, 229

International Memory Workshop, 2013

Patent NO. 201210311109.8

Origin of Self-Rectifying Behavior

Both of Cu/WO3/Pt and Cu/a-Si/Pt control sample show symmetrical I-V.

Rini of Cu/WO3 /Pt is three orders higher than that of Cu/a-Si/Pt, same with

Pt/WO3/a-Si/Cu device,

The WO3 layer is switched into LRS after forming, while the a-Si layer still

keeps in HRS.

The rectifying property of Cu/a-Si/WO3/Pt device is from the Schottky

contact of CF in WOx with a-Si.

-3 -2 -1 0 1 2 3 410

-12

10-10

10-8

10-6

10-4

10-2

100

Curr

ent

(A)

Voltage (V)

Rini~109Ω@0.5V

RLRS~105Ω@0.5V

Vf~3.2 VIf~10-4A

VPt

WO3W

PtWO3

Cu

-3 -2 -1 0 1 2 3 410

-12

10-10

10-8

10-6

10-4

10-2

100

Curr

ent

(A)

Voltage (V)

Rini~109Ω@0.5V

RLRS~105Ω@0.5V

Vf~3.2 VIf~10-4A

VPt

WO3W

PtWO3

Cu

-2 -1 0 1 2 3 4 5 6 7 810

-9

10-7

10-5

10-3

10-1

Cu

rre

nt

(A)

Voltage (V)

Rini<106Ω@0.5V

RLRS<102Ω@0.5V

Vf~7 VIf>10-3A

VPt

a-SiCu

Pta-SiCu

-2 -1 0 1 2 3 4 5 6 7 810

-9

10-7

10-5

10-3

10-1

Cu

rre

nt

(A)

Voltage (V)

Rini<106Ω@0.5V

RLRS<102Ω@0.5V

Vf~7 VIf>10-3A

VPt

a-SiCu

Pta-SiCu

-4 -2 0 2 4 6 810

-12

10-10

10-8

10-6

10-4

10-2

100

Curr

ent

(A)

Voltage (V)

Rini~109Ω @0.5V

RLRS~105Ω@0.5V

Vf~6.5 VIf~10-4A

VPt

WO3a-SiCu

VPt

WO3a-SiCu

PtWO3a-SiCu

-4 -2 0 2 4 6 810

-12

10-10

10-8

10-6

10-4

10-2

100

Curr

ent

(A)

Voltage (V)

Rini~109Ω @0.5V

RLRS~105Ω@0.5V

Vf~6.5 VIf~10-4A

VPt

WO3a-SiCu

VPt

WO3a-SiCu

PtWO3a-SiCu

Mechanism of Resistive Switching

The process of O2- ions trapping

andde-trapping on the vacancy site is

attributed to the switching behavior.

Filament composed of oxygen

vacancy is formed in SET process.

The recombination of O2- ions with

vacancy corresponds to the RESET

process.

Comparison of Various Technologies

The self-rectifying RRAM is a promising candidate for high density

application.

Outline

Motivation

RRAM Integration

Self-Rectifying RRAM

1D1R Integration

1k HfO2 based RRAM Test Chip

Summary

Comparison of Endurance and Reset

Current in unipolar and bipolar RRAM

0.0 0.1 0.210

4

106

108

1010

1012

0.2 0.4 0.6 0.8 1.0

Bipolar RRAM devices:

High endurance

Low reset current

Ref [5]: Ta2O5/TaOx

Ref [6]: TiOx/HfOx

Ref [5]: ZrOx/Ta2O5/AlO

En

du

ran

ce

cyc

les

Reset current (mA)

Ref [7]: Ta2O5/TiO2

Ref [8]: HfOx

Ref [8]: HfOx/AlOy

Unipolar RRAM devices:

Low endurance

High reset current

[7] Y. Sakotsubo, et al., VLSI, p. 87, 2010. [8] X.A. Tran, et al., VLSI, p. 44, 2011.

Most 1D-1R integration only suitable for Unipolar

RRAM .

Y. T. Li, et al., Nanoscale, 5, 4785 (2013).

Bipolar 1D-1R Integration

Diode: Ni/TiOx/Ti

RRAM: Pt/HfO2/Cu

(a) Typical I-V characteristics of Ti/TiOx/Ti and Ni/TiOx/Ti devices.

(b) Bipolar resistive switching characteristic of the Pt/HfO2/Cu RRAM cell.

Diode and bipolar RRAM characteristics

Y. T. Li, et al., Nanoscale, 5, 4785 (2013).

The 1D-1R device exhibits bipolar switching characteristic, a self-

compliance behavior can be achieved during the set process;

After 100 DC cycling, its bipolar switching characteristics is still

keeping very well.

Y. T. Li, et al., Nanoscale, 5, 4785 (2013).

Bipolar Resistive Switching of 1D1R Integration

Uniformity and Retention

Bipolar 1D-1R demonstrated very good uniformity

and retention characteristics.

Programming Speed

Fast switching speed, 100 ns both for write and erase.

0 1 2 3 4 5 6 7

-3

-2

-1

0

1

2

3

4

Transition from

LRS to HRS again

Transition from

HRS to LRSHRS

Read Read Read

Reset pulse

100ns/+3V

Vo

lta

ge

(V

)

Time (s)

V1

V2

Set pulse

100ns/-2.5V

V2OSCV1

RRAM Diode

Rs

Multi-level storage and low power consumption

Obvious Multi-level storage can be realized by controlling different voltage

during the SET process (Vset) ;

Ireset is found to reduce with the decrease of Vset.

-2 -1 0 1 2 310

-9

10-7

10-5

10-3

10-1

Vreset, Ireset@-1.5V

Vreset, Ireset@-2V

Cu

rre

nt

(A)

Voltage (V)

Vset=-1.5V

Vset=-2V

Vset=-2.5V

Vreset, Ireset@-2.5V

0

2

4

6

8

10

AVR=9.22mA

STD=0.98mA

AVR=3.17mA

STD=1.39mA

Vset=-2.5VVset=-2VVset=-1.5V

R

eset

cu

rren

t (m

A)

AVR=0.55mA

STD=0.21mA

AVR: average value

STD: standard deviation

Scalability of Ni/TiOx/Ti Selecting Diode

The forward current density is over 104 A/cm2 at 1V for 2×2 μm2 active area;

An even higher forward current density over 106 A/cm2 is expected from a

smaller area of 100×100 nm2 .

Y. T. Li, et al., Nanoscale, 5, 4785 (2013).

References RRAMRRAM

TypeDiode Diode Type Compliance current

This work Cu/HfO2 /Pt Bipolar W/TiOx/Ni Schottky Self-compliance

[1] Pt/NiO/Pt Unipolar Pt/CuO/IZO/Pt p-n junction External current limiter

[2] Pt/NiO/Pt Unipolar Pt/CuO/IZO/Pt p-n junction GIZO transistor

[3] Pt/TiOx/Pt Unipolar Pt/TiOx/Pt Schottky External current limiter

[4] Pt/ZnO/Pt Unipolar Pt/NiO/ZnO/Pt p-n junction External current limiter

[4] Pt/ZnO/Pt Unipolar Pt/WO3/ZnO/Pt Tunnel barrier External current limiter

1D1R structure generally can only use unipolar RRAM device, but the bipolar

RRAM has superior performance than unipolar RRAM. This work is a first

demonstration of a 1D1R structure using bipolar RRAM and Schottky diode.

Comparison

Outline

Motivation

RRAM Integration

Self-Rectifying RRAM

1D1R Integration

1k HfO2 based RRAM Test Chip

Summary

1kb RRAM Test Chip Demo

Integration solution

RRAM cell

1kb RRAM test chip

Control unit

clk

trigger

operationwritedata

readdata

Write_finish

Latch_addr

Write_trigger

P/E

read

LatchAddress[9:0]

ARRAY

WD

SA

data

Cell_fail

Latch

trigger

P/E

read

readout

finish

read

P/E

addr

Write_fail

ready

DMA DMA

DMA_port1

DMA_port2

SA

SASA_ref

SA_ref

WD

WD

WD_ref

WD_ref

DMA_wlv

端口信号线

内部控制信号线

数据线

模拟信号rst

read

Rre

adre

f1

Rre

adre

f2

Rpro

gra

mre

f1

Rpro

gra

mre

f2

Rera

sere

f1

Rera

sere

f2

Periphery circuit design

Forming

SET

RESET

Operation VBL VSL VWL

GND

GND

+++

GND

++++

Table. 1

-2 -1 0 1 2 3

-600.0u

-400.0u

-200.0u

0.0

200.0u

400.0u

Cu

rre

nt

(A)

Voltage (V)

SET

RESET

Icc

WL

SL

BL

RRAM

(c)

Device Structure and Bipolar Switching

CT

M1

V4

M5

M4

V3

M3

V2

M2

V1

GD S500 nm

Cu

HfO2

TE

4 nm

5 nm

Layout outlook Data writing

1kb RRAM Test Chip Demo

Summary

RRAM with crossbar architecture attracts significant interests due to its

excellent scalability and 3D integration for high-density application.

The big challenge of this structure is how to eliminate crosstalk issue.

Self-rectifying RRAM and RRAM integration with 1D1R architecture

can suppress crosstalk leakage greatly.

RRAM with excellent memory performance and good reproducibility

are demonstrated with a self-rectifying characteristics, which can

suppress crosstalk leakage greatly.

Bipolar 1D-1R devices also exhibits good features in uniform switching,

satisfactory data retention, fast speed, as well as excellent scalability.

HfO2 based 1k test chip was demonstrated.

Thanks for your attention!