Requirements, Constraints, and Verification Activities · Requirements, Constraints, and...

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© 2014 Carnegie Mellon University Requirements, Constraints, and Verification Activities Peter Feiler Feb, 2014

Transcript of Requirements, Constraints, and Verification Activities · Requirements, Constraints, and...

Page 1: Requirements, Constraints, and Verification Activities · Requirements, Constraints, and Verification Activities Peter Feiler Feb, 2014 . 2 ... Reqs , Constraints, and VAs Feiler,

© 2014 Carnegie Mellon University

Requirements, Constraints,

and Verification Activities

Peter Feiler Feb, 2014

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© 2014 Carnegie Mellon University

Copyright 2014 Carnegie Mellon University This material is based upon work funded and supported by the Department of Defense under Contract No. FA8721-05-C-0003 with Carnegie Mellon University for the operation of the Software Engineering Institute, a federally funded research and development center. Any opinions, findings and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the United States Department of Defense. NO WARRANTY. THIS CARNEGIE MELLON UNIVERSITY AND SOFTWARE ENGINEERING INSTITUTE MATERIAL IS FURNISHED ON AN “AS-IS” BASIS. CARNEGIE MELLON UNIVERSITY MAKES NO WARRANTIES OF ANY KIND, EITHER EXPRESSED OR IMPLIED, AS TO ANY MATTER INCLUDING, BUT NOT LIMITED TO, WARRANTY OF FITNESS FOR PURPOSE OR MERCHANTABILITY, EXCLUSIVITY, OR RESULTS OBTAINED FROM USE OF THE MATERIAL. CARNEGIE MELLON UNIVERSITY DOES NOT MAKE ANY WARRANTY OF ANY KIND WITH RESPECT TO FREEDOM FROM PATENT, TRADEMARK, OR COPYRIGHT INFRINGEMENT. This material has been approved for public release and unlimited distribution. This material may be reproduced in its entirety, without modification, and freely distributed in written or electronic form without requesting formal permission. Permission is required for any other use. Requests for permission should be directed to the Software Engineering Institute at [email protected]. DM-0000965

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Outline

Architecture Centric Requirements

Requirements and Safety Hazards

Verification Activities and Assurance Cases

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Requirement

System Requirement

Requirement

Refined to

Goal

RDAL Requirement Object Stakeholder

Stakeholder

Requirements

System/Technical

Requirements

Requirement

DOORS

Bridge to traditional requirements representations

Stand-alone requirement specification (?)

Traceability into system architecture specification

Nested folders to reflect requirement doc hierarchy? Or

we assume architecture hierarchy implies requirements

report structure.

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Stakeholder Needs and Requirement Categories

Leveson System Theoretic Framework

System, operational environment,

development and V&V process

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Requirements

Guarantees

Assumptions

Behavior

Performance

Mission

Requirements

Function

Safety

Security

Dependability

Requirements

Reliability

Implementation constraints

Precondition

Postcondition

Invariant

Exceptional condition

Environmental Assumption

about external component

System Specification and Different Categories of System Requirements

Quality attribute utility tree

Assurability

Modifiability

Developmental

Requirements

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Requirements and Architecture Model Elements

A requirements object can apply to multiple model elements individually

• System type implies each (implementation and) instance

• Manually selected model elements

A requirement applies to a collection of model elements?

• The collection together has to satisfy a constraint? E.g., implementation constraint

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Requirement as Conditional Constraint

Role of what: expression (constraint)

• expresses requirement condition independent of architecture model

• Ensures that requirement is correctly specified in architecture model

• Pointer to the specification in the architecture model?

Role of when

• When does it apply: e.g., which operational or failure mode

• When assumptions for expression evaluation are met (has a property value then value is < x)

• When in the development process does it have to be satisfied by the implementation? (VA)

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Requirement

System Spec Formal spec

Requirement

Requirement

Refined to

Requirement Specification Consistency

System/Technical

Requirements

RDAL Goal,

assumption,

Requirement Object Description

Textual spec of constraint

Formal spec of constraint

System model

RDAL Req Spec

Spec of requirement

independent of AADL model

actualLatency < MaxLatency of

20ms from input x to output y

Verification Activity (VA): use

of constraint to ensure the

spec is correctly reflected in

AADL (should be separate from

formal spec of requirement)

Latency Property value of System

S returns the maximum expected

latency. The analyzer (method

used in VA) evaluates actual

latency against this max latency.

Or there is a property constant

MaxLatency and MaxLatency is

used as value for the Latency

property on the system type.

Spec of requirement in context of AADL model

a pointer into the AADL model to the spec there, or in terms of

properties in AADL model.

Actual_Latency < Latency with actual latency defined as

computed value with method point to the analysis formula.

Different Vas are interpreting the

requirement in different forms: AADL Spec

or RDAL expression .

Or in other form embedded in a theorem or

Simulink script, etc.) that would need to be

validated.

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System Spec Formal spec

On Quality of Requirements

RDAL Req

System model RDAL Req Spec

Verification of requirement artifact:

Quality of requirements

Coverage: with respect to system spec

Complete: All states have transitions.

Input/output value, timing, rate, sequence

Consistent: overlapping /conflicting x>5 and x<4

RDAL Req

RDAL Req

Coverage of

system spec

Verifying the quality of collection of requirements

Verification Activity (VA) of AADL model:

Syntax, semantic, consistency rules for

component types (implementations constraints,

interaction contracts)

Verification method (VM): theorem

Verification activity(VA): application of VM to a model to

assess whether some constraint is met.

Verification of development process

requirements: VA on a req spec (set of

requirements) or that two representations

are consistent (req/AADL spec)

We could explicitly specify such development

requirements that apply to any system development.

We can write theorems that check for it.

Stakeholder

Stakeholder

Requirements

Goal

Traceability coverage as DOORS

supports. Some listed in RDAL

under analysis (e.g., all goals/reqs

have stakeholders or are derived.

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Integrated Model of Safety Hazards and Requirements

Original system

requirements

Safety hazard as exceptional condition that must

be addressed through derived requirements or

evidence of absence

Traceable to error source specification in AADL model

Safety hazard as exceptional condition that must

be addressed through derived requirements or

evidence of absence

Traceable to error source specification in AADL model

Derived safety requirements

linked to original requirement

specification

Fault Ontology as part

of EMV2 Standard

I used special sub-category of

requirement to represent exceptional

condition/obstacle/hazard. Leveson

STAMP/STPA

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Requirement

System

System Realization

System System

Requirement

Requirement

Requirement

Requirement Requirement

Decomposed to

Refined to

Requirement Decomposition

Rationale

System Spec

Formal Tech Spec

(pre/post/ass/guar)

T/S T/S

RDAL Req Spec

Impl Constraints

On specific or all implementations

Constraint that talks about the parts and their

interactions (connectivity, partial ordering)

Example one controller at a time controls system

Two (redundant) instances of sensor

Interaction contracts along connections

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Compositional Verification of Requirements

Theorems represent a system requirement, its

presence in the AADL model, or verification method

of implementation against requirement

Establish validity of sub-

requirement/assumption and

implementation verification activity.

Argumentation implicit in and of proof

list. In some examples it was embedded

in top-level expression of proof logic.

Req/Verification activity instance: the prove is evaluated

for each instance of the system implementation .

Application of proofs results in an instance of an

assurance case record

Using Resolute from Rockwell Collins SMACM project

Resolute statements currently not integrated with RDAL, but the

theorem corresponds to a library of Lute functions and the prove

the RDAL Req expression invoking a single Lute lib function.

In an annex library: Some are generic,

some only work for specific system

types or implementations.

Mixture of system and

process requirement

verification.

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Requirement

System

System Realization

System System

Requirement

Requirement

Requirement

Requirement Requirement

Decomposed to

Refined to

Compositional Verification

Rationale

System Spec

Formal Tech Spec

(pre/post/ass/guar)

T/S T/S

RDAL Req Spec

Impl Constraint

VA guarantee-assumptions: output to input types (SAVI functional integration)

Assumption/guarantee, pre/post: Resolute/BLESS

Verified by AADL compiler, functional integration checker, Lute equivalent,

BLESS, etc.

VA compositional formula: may use subcomponent

properties, i.e., requirements that it assumes are met.

Example: latency calculation based in latency specs of

subcomponents.

Input-output transformation substitution (model checking)

VA impl constraints: may assume

subcomponent requirements are met.

Verification within the space of

architectural design/decomposition

Example requirement: ActualLatency < MaxLatency of 250ms

In AADL spec: value(Latency) = 250 ms

Latency analysis (verification method) interprets Latency property as MaxLatency

Need to verify that the assumptions

made by the VA hold.

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Combining AADL and Simulink Based Verification

Simulink to AADL

bridge

Architecture compliance

Consistency checking between Simulink architecture

structure and AADL-based architecture spec.

Basis for Simulink based simulation as verification against

an AADL specification, and

basis for AADL based Resolute/Agree verification of

Simulink StateFlow behavior.

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Combining Requirement Validation & Compositional Verification

RDAL Verification Activity: Simulink or

SCADE based verification. Result to be

reflected in requirement satisfaction status.

Safety hazards have

safety requirements

that address them

when satisfied

Linkage to Resolute proofs

as verification activities.

Evidence records below claims that

requirements have been met

Combining Resolute, RDAL, Lute, Agree, others

Requirement quality

(coverage, consistency) and

assumption evidence

Process requirements as verification activities.

Req object expression used as verification activity.

What should go in a Req object vs. a VA object?

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Requirement

System

System Realization

Subsystem Subsystem

Requirement

Requirement

Requirement

Requirement Requirement

Decomposed to

Refined to

Assurance Case Record

Rationale

Formal Tech Spec

(pre/post/ass/guar)

T/S T/S

Impl Constraint

Compositional

verification evidence

Verification against quality requirements

Compositional

verification evidence

System architecture

System and SW Requirements

Requirement quality

verification evidence

Requirement quality

verification evidence

Implementation

verification/test

evidence

Design/Source code

Assurance case Confidence map

GSM, CAE, Eurocontrol safety case, Confidence map

OMG Structured Assurance Case Metamodel (SACM)

Claim: Req instance

Evidence: VA instance

Argumentation: implicit or

explicit And/Or/Implies

logic & rationale

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Claim and VA Status

System

Powertrain

System

ETC

Model Variant

Continuous

Model Variant

Continuous

Input dataset verification method

Verification Activity

Simulated environment test

Status

Test parameter

Claim

Status

Actual

Parameters

Result dataset

SVM Objects

VA Status

Claim

Status

Claim

Status

Claim

Status

VA Status

VA Status

Pass, Fail, quant, TBD

SVM

TBD, InProgress, Pass, Fail, Unknown

Argumentation logic

Which combinations of VA

VA Instance: Evidence object with state invoking VA spec

Verified: pass/fail

Satisfied: quantitative 0..1

VA spec: Verification method

(VM), applied to model, with

input/param to produce

expected output/meet

specified constraint.

May include a script invoking

VM multiple times with

different parameters/data sets

Some Vas may be long-running

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Traceability to requirement.

Verification that requirement is

correctly reflected in respective

parameters.

When should a VA be performed and

expected to be satisfied (based on

development phases)?

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Verification (&Valid) Artifacts and Ontology

Need a place where the result records are stored for post-mortem

examination (counter examples, simulation traces, etc.)

Can be a person “executing” a checklist

Correct version of tool with correct switches set

We have different categories (types) of verification activities.

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OMG SACM Meta Model

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OMG SACM Meta Model

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Implications on RDAL

Additional Requirement and verification activity categories

• Clarification of condition/expression role in Req (claim)

• Multi-valued state, persistence vs. dynamic evaluation

• State determined by argument logic vs. cond/expression

Explicit representation of argument (logic to determine satisfaction)

• Currently alternative OR and decomposition AND

Elaboration of verification activity

• Multi-valued state - persistence

• Verification activity assumptions

• Long running verification activities

Library of verification methods

• Notations supported by extension

• External methods invoked by script

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Contact Information

Peter H. Feiler

Principal Researcher

RTSS

Telephone: +1 412-268-7790

Email: [email protected]

U.S. Mail

Software Engineering Institute

Customer Relations

4500 Fifth Avenue

Pittsburgh, PA 15213-2612

USA

Web

Wiki.sei.cmu.edu/aadl

www.aadl.info

Customer Relations

Email: [email protected]

SEI Phone: +1 412-268-5800

SEI Fax: +1 412-268-6257