Request for Proposal For Design and Fabrication of GNSS ......MBIST insertion & testing to be done...

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RFP for Design and Fabrication of GDB ASIC

Request for Proposal

For

Design and Fabrication of

GNSS Digital Baseband (GDB) ASIC

Jan 2021

Space Applications Centre (SAC)

Indian Space Research Organization (ISRO)

Ahmedabad- 380015

INDIA

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This document contains proprietary information of SAC/ISRO, Ahmedabad and is protected by

copyright laws and international treaties. Unauthorized copy or reproduction of this document in

whole or in part without the prior written consent of SAC/ISRO is strictly forbidden and constitutes

a copyright infringement.

SAC/ISRO reserves the right to alter this information at any time without notice.

© Copyright 2021, by SAC/ISRO, Ahmedabad.

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Contents

1 General Background ............................................................................................................... 5

2 Scope of Work ........................................................................................................................ 6 3 ASIC development flowchart ................................................................................................. 9 4 Definitions & Abbreviations ................................................................................................. 10

4.1 Definitions ...................................................................................................................... 10 4.2 Abbreviations ................................................................................................................. 10

5 Specifications of GDB ASIC ................................................................................................ 11

5.1 Technical Specifications ................................................................................................ 11

6 Higher level functional block diagram of GDB ASIC.......................................................... 12 6.1 Digital Modules: ............................................................................................................. 12

6.1.1 GNSS Correlator Module: ...................................................................................... 12 6.1.2 Data Interface Module: ........................................................................................... 12

6.1.3 Processor Module: .................................................................................................. 12 6.2 Analog Modules: ............................................................................................................ 13

6.2.1 Clock Management Unit: ........................................................................................ 13 6.3 Memories:....................................................................................................................... 14

6.3.1 SRAM: .................................................................................................................... 14

7 Interface details of GDB ASIC ............................................................................................ 14

8 CAD Tools and Formats ....................................................................................................... 15 9 Testing................................................................................................................................... 16

9.1 Internal Scan Chain Tests ............................................................................................... 16

9.2 Boundary Scan Chain DC Tests ..................................................................................... 16 9.3 MBIST Tests .................................................................................................................. 16

9.4 Functional Tests ............................................................................................................. 16 9.5 Temperature Tests .......................................................................................................... 16

10 Design Reviews .................................................................................................................... 17

11 Deliverable Items .................................................................................................................. 18 11.1 Inputs from SAC ......................................................................................................... 18

11.2 Vendor deliverables .................................................................................................... 18

12 Tendering Procedure ............................................................................................................. 20 13 Criteria for Vendor Selection ................................................................................................ 24 14 Other Terms and Conditions / Important Guidelines ............................................................ 26

ANNEXURE-1 ............................................................................................................................. 29 ANNEXURE-2 ............................................................................................................................. 34

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List of Figures

Figure 1: ASIC design flow ............................................................................................................ 9 Figure 2: GNSS Digital Baseband ASIC Block Diagram ............................................................ 12 Figure 3: GDB ASIC Interface block diagram ............................................................................. 14

List of Tables

Table 1: SAC & Vendor Responsibilities ....................................................................................... 8 Table 2: Technical Specifications of GDB ASIC ......................................................................... 11 Table 3: Processor Clock Frequency Selection ............................................................................ 13

Table 4: Specifications of CMU (PLL IP) .................................................................................... 13 Table 5: Front End tools used by SAC ......................................................................................... 15

Table 6: Preferred Tools for Back-End Design ............................................................................ 15 Table 7: Technical Details ............................................................................................................ 20

Table 8: Vendor Details ................................................................................................................ 21 Table 9: Delivery Schedule ........................................................................................................... 22 Table 10: Cost Break-up & Total cost .......................................................................................... 23

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1 General Background Space Applications Centre (SAC/ISRO) is currently engaged in the development of variety of

GNSS navigation receivers for various applications. In order to reduce size and power

requirements for GNSS Receiver, it is being proposed to develop a GNSS Digital Baseband (GDB)

ASIC at 28 nm node.

The development of GDB ASIC is proposed to be carried out in the following manner:

ASIC Front End design will be carried out by Space Applications Centre (SAC/ISRO) using

vendor provided PDK of the target foundry. Vendor will be responsible for complete back-end

design of the ASIC. After the back-end design completion, vendor will be responsible for Proto

ASIC development through MPW run of targeted foundry, which includes mask preparation, wafer

fabrication, device packaging, testing and delivery of proto ASICs.

This document contains specifications and technical details for GDB ASIC. The scope of this

document is to establish the basic requirements and provide assessment for the development and

procurements of some IPs, back-end design & development work of ASIC, quality assurance

requirements, prototype manufacture, testing and validations which are to be applied by the vendor

for manufacturing ASICs with specific reliability (industrial grade) and quality requirements

required for ground use with budgetary quotes. It is to be understood that the resulting design,

including GDS-II file will be a deliverable and subsequently the intellectual property of SAC.

This RFP provides the scope of work including assignment of responsibilities, GDB ASIC

specifications, higher-level functional block diagram, interface details, development flowchart,

CAD tools & formats, testing, design reviews, deliverables, tendering procedure, criteria for

vendor selection and other applicable terms & conditions.

Space Applications Centre invites your Company to submit a detailed proposal for the Back-end

design, Fabrication, packaging and testing of this ASIC.

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2 Scope of Work

Responsibility:

S : SAC V : Vendor

Sr.

No. Activity

Respons

ibility

Inputs from SAC to

Vendor

Outputs from Vendor

to SAC

1. Placement of Purchase Order

(T0) S - Purchase Order ---

2. Explaining requirements &

specification S

- Final requirements

and specifications as

mentioned in P.O.

---

3.

Generation of Source Control

Drawing (SCD) and Project

Plan Document

V - Requirements &

Specifications

- SCD & Project Plan

Document

4. Review and Approval of SCD

and Project Plan Document S --- ---

5. Proposal of 28nm technology

node process variant & Foundry V ---

- 28nm technology node

process variant &

Foundry details

6. Approval of technology node

process variant & foundry S --- ---

7. NDA signing S,V NDA (Annexure-1) ---

8. Preliminary Design Review

(PDR) S,V --- -PDR reports, document

9.

Provide PDK of the approved

technology node & foundry

along with SPRAM & True

DPRAM memory cuts required

in the design to SAC for Front-

end design and simulation.

V ---

- PDK & Memory cuts

of the approved

technology node &

Foundry

10.

Procurement of Clock

Management Unit (CMU) PLL

IP core having design heritage at

targeted node & process.

V ---

- CMU (PLL) IP core

Datasheet & design

heritage details

11. CMU (PLL) IP tuning V --- -PLL IP tuning results &

reports

12. RTL Design, Synthesis with

Power Intent, DFT Scan chain

insertion

S --- ---

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13. STA, Power analysis, Formal &

Functional Verification of Front

End gate level netlist

S - Reports & logs ---

14. Signoff of the Front End design

to the vendor (T1) S

- scan-inserted

netlist, UPF file

- scripts, reports, logs

---

15. Interim Design Review (IDR) V,S --- -IDR reports, documents

16. CMU (PLL) IP integration V --- -Behavioral model for

simulation.

17. MBIST & Boundary scan

insertion at netlist level & its

simulation

V ---

- MBIST & Boundary

scan inserted gate level

netlist & simulation

results

18. Power-aware physical

implementation and verification

(both static & functional)

V ---

- Power-aware physical

implementation and

verification (both static

& functional) reports

19. Floor Planning, Clock Tree

synthesis & Pin Assignment V

- Preferred Pin-

assignment - Pin Assignment details

20. Place and Route V ---

- Post layout netlist in

VHDL and Verilog

formats

- scripts & constraint

files

21. Formal Equivalence check V --- -Formal Equivalence

check Reports

22. Static & Dynamic IR Drop

Analysis V ---

- IR Drop Analysis

Reports

23. Physical Verification (LVS &

DRC) V --- - LVS and DRC reports

24. SI Analysis & Static Timing

Analysis (STA) V --- - SI & STA reports

25. Parasitic Extraction/

Back Annotation V ---

- Spice netlist with

extracted parasitics

- Back-annotated delays

in SDF and SPEF

format.

26. ATPG Test vector Generation

& Fault Simulation V ---

- Test vectors for all

fault models in

VCD/VHDL formats

- Fault analysis report.

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27. MBIST & Boundary scan Test

vector generation and fault

simulation

V ---

- Test vectors for all

fault models in

VCD/VHDL formats

- Fault analysis report.

28. Full chip FAST-SPICE

simulation with PLL IP (Post-

layout)

V -Functional test

vectors/testbench -Simulation log, reports

29. Critical Design Review (CDR) V,S --- - CDR reports,

documents

30. GDSII & Mask data Preparation V --- - Complete GDSII &

Mask dataset

31. Foundry Signoff Review (FSR) V,S --- - FSR Report

32. Tape out (Fabrication through

MPW Run) V --- ---

33. Proto device packaging V ---

- Package & pin details,

package simulation &

wire bonding diagram

34. Packaged device testing V Functional test

vectors (EVCD files)

- All test results with

reports and logs.

- Acceptance &

Validation Test

document.

35. ASIC Test Results Review

(ATR) V,S - ATR Report

36. Proto device delivery & other

deliverables V ---

- Packaged & Tested

Proto Devices.

- Zero Insertion Force

(ZIF) socket, carrier and

test board

- Dummy packages

Table 1: SAC & Vendor Responsibilities

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3 ASIC development flowchart

Figure 1: ASIC design flow

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4 Definitions & Abbreviations

4.1 Definitions

Vendor: Vendor is defined as the entity responsible for back-end design processing from layout,

place and route, mask generation, wafer fabrication, prototype ASIC manufacture using the front-

end design files and qualification & testing requirements provided by SAC. Vendor will interface

directly with SAC during the design, fabrication, packaging and testing phases.

GDB ASIC: GDB ASIC is defined as a chip, which implements all the requirement functionalities

of GNSS Digital Baseband Processing as enumerated within and forming the subject matter of this

RFP.

4.2 Abbreviations

ASIC Application Specific Integrated Circuit

ATPG Automatic Test Pattern Generation

CAD Computer Aided Design

CMOS Complementary Metal Oxide Semiconductor

CMU Clock Management Unit

DPRAM Dual Port Random Access Memory

DRC Design Rule Check

GNSS Global Navigation Satellite System

LVS Layout-vs-Schematic

MBIST Memory Built-in Self Test

PLL Phase Locked Loop

SDF Standard Delay Format

SRAM Static Random Access Memory

SPRAM Single Port Random Access Memory

UART Universal Asynchronous Receiver/Transmitter

VHDL VHSIC Hardware Descriptive Language

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5 Specifications of GDB ASIC

5.1 Technical Specifications

S.No. Parameter Specifications

1. ASIC type and

technology node

Digital ASIC (with on-chip PLL), 28 nm

2. ASIC gates ~50 Million NAND2 Equivalent ASIC gates

(excluding memory)

~5 MB SRAM memory

3. External Input Clocks = 56 MHz correlator clock;

= 10MHz reference clock for CMU (PLL IP)

4. Derived Clocks from

on-chip PLL

= 540 MHz (max.) processor clock;

= 12 MHz Data Interface Module clock

5. Clock Management

Unit (CMU)

PLL IP having design heritage at targeted node

& foundry and as per our requirements

mentioned in section 5.2.1

6. Major Digital Blocks

Correlator core Multi-channel GNSS correlator core

Processor core 32 bit Processor core with FPU

Data Interface Module Data Interface IP core

7. On chip Memory

(in MB= Megabytes)

SPRAM & True DPRAM of various cuts

(Total = ~5 MB)

Major Memory Block is ~4 MB SPRAM for

processor. Remaining 1MB is for various

SPRAM & DPRAM cuts of different sizes.

8. No. of Functional I/O

Pins & type

~100, 1.8V CMOS

9. Testing ATPG, MBIST, Boundary scan & Functional

tests (Scan & ATPG with logic Fault Coverage

of > 95 %)

10. IO Voltage 1.8V

11. Core Voltage As per the targeted process & foundry @ 28nm

12. Power Dissipation

(targeted)

<0.7W (Peak)

<0.3W (Typical)

13. Package QFP/BGA/CGA

14. Package Size <20 mm X 20 mm

15. Operating Temperature -40C to +105C

16. Storage Temperature - 60C to +125C

17. ESD sensitivity level ≥ 2KV HBM

Table 2: Technical Specifications of GDB ASIC

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6 Higher level functional block diagram of GDB ASIC

Higher level functional blocks of the GNSS Digital Baseband ASIC are shown in Figure-2.

Figure 2: GNSS Digital Baseband ASIC Block Diagram

The major functional blocks/modules of the baseband ASIC are as follows:

1. GNSS Correlator Module

2. Data Interface Module

3. Processor Module

6.1 Digital Modules:

6.1.1 GNSS Correlator Module:

It consists of signal processing blocks such as acquisition, tracking channels etc.

6.1.2 Data Interface Module:

This module implements Data Interface logic for interfacing to an external device.

6.1.3 Processor Module:

Processor Module consists of 32-bit processor module with Floating point Unit (FPU)

required for various functionalities.

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6.2 Analog Modules:

6.2.1 Clock Management Unit:

Clock Management Unit (CMU) is required for generating Processor & Data Interface

module clocks from external reference 10 MHz TCXO. Standard characterized off-the-

shelf PLL IP having design heritage including layout at targeted node & process and as

per the requirements mentioned below to be supplied / procured by vendor and included

in the design. PLL reference voltage to be generated inside PLL IP, which can be derived

from either IO or core voltage. PLL lock status to be provided. Vendor has to provide

trimming interface for tuning of PLL output clock freq. to address the process variations.

Provision should be provided for Processor clock frequency selection using external 2

bit IO input as per below Table-3.

S.No. Freq. selection control bits Processor Clock Freq. Output

1. 00 540 MHz

2. 01 420 MHz

3. 10 300 MHz

4. 11 180 MHz

Table 3: Processor Clock Frequency Selection

Clock

Input

Clock Outputs Frequency

Tolerance

Remarks

10 MHz

(Reference

clock)

Processor clock

(540/420/300/180

MHz)

0.1% User selectable Processor clock

frequency to be generated using

PLL IP as per details provided in

Table-3

12 MHz

(Data Interface

module clock)

0.1% 12 MHz clock to be generated by

dividing user selectable

processor clock which is integer

multiple of 12.

This 12 MHz clock should be

output from chip, which will be

looped back externally through

another IO pin for Data interface

module clock.

Table 4: Specifications of CMU (PLL IP)

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6.3 Memories:

6.3.1 SRAM:

SPRAM & True DPRAM cuts of various sizes are required in the design. Major Memory Block is

~4 MB SPRAM for processor. Remaining 1MB is for various SPRAM & True DPRAM cuts of

different sizes. The preliminary indicative list of memory cuts is provided here. The exact

configurations and sizes will be provided in the P.O.

S.No. Memory Type Memory size [depth x width]

1. DPRAM [16x8]

2. SPRAM [64x4]

3. SPRAM [64x32]

4. SPRAM [256x8]

5. SPRAM, DPRAM [256x32]

6. SPRAM [8192x8]

7. DPRAM [2048x8]

8. DPRAM [2048x36]

7 Interface details of GDB ASIC

Figure 3: GDB ASIC Interface block diagram

The interface details of the GDB ASIC are shown above. GDB ASIC interfaces to different devices

such as Signal conditioning & filtering chip, SPI Flash, Transceiver IC & peripherals such as SPI,

UART, I2C & GPIO with I/O type and level as LVCMOS 1.8V.

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8 CAD Tools and Formats

All the technology independent CAD tools to be employed during the development shall be mature

and suited for their purpose. It is encouraged to use the latest version of the CAD tools as far as

possible. Preference shall be given to the use of established international standards in all data

exchange. Timing parameters should use names compliant with the VITAL Specification

standardized by the IEEE, which could allow back-annotation on the board-level to be performed

using the Standard Delay File (SDF) format.

S. No. Purpose Front End tools (S/W) used by SAC

1. Simulation VCS (Synopsys)

2. Synthesis Design Compiler (Synopsys)

3. DFT DFT Compiler (Synopsys)

4. STA Prime-Time (Synopsys)

5. Formal

Equivalence

check

Formality (Synopsys)

Table 5: Front End tools used by SAC

The following tools are preferred for the back-end design of the ASIC for seamless flow of data

between Front End & Back End Design and to avoid any compatibility issues.

S. No. Purpose Preferred tools (S/W) for Back-End Design

1. Back-end design IC Compiler (Synopsys)

2. STA Prime-Time (Synopsys)

3. Formal

Equivalence

check

Formality (Synopsys)

4. IR-drop analysis Prime Rail (Synopsys)

5. Sign-off Caliber (Mentor Graphics)

Table 6: Preferred Tools for Back-End Design

The vendor should clearly provide the details of their tools to be used for development stages along

with their offer. The tools to be used for the back-end design and sign-off should be documented

and approved by the SAC before use. If vendor wants to use other EDA tools than mentioned

above, it is vendor’s responsibility to ensure compatibility and seamless flow of data-exchange

between front-end and back-end design tools under suitable intimation to ISRO. General IT

security guidelines to be followed by vendor for storage and handling of the design files. Public

cloud and storage servers mandatorily must not be used during the development.

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9 Testing

9.1 Internal Scan Chain Tests

All of the storage elements (flip-flops, latches etc.) used in the design would have the scan

capability with >95% coverage implemented using a multiplexer at input to accept either system

data or scan data.

ATPG test vectors to be generated & scan chain tests to be performed by vendor on tester

(Preferably on Teradyne ultraflex) to detect manufacturing defects with various fault models like

Stuck-at Fault, Transition Delay fault (TDF), Path-delay fault (PDF), Small Delay Defects (SDD),

IDDQ test etc.

9.2 Boundary Scan Chain DC Tests

Boundary scan chain to be inserted by vendor at all digital I/Os & DC parametric tests to be

performed such as VIL/VIH, VOL/VOH , IIL/IIH , IOL/IOH etc. The boundary scan chain should be

implemented as per IEEE 1149.1 JTAG standard. Following pins should be implemented for JTAG

TAP interface

TDI : Test Data Input

TDO: Test Data Output

TMS: Test Mode Select

TCK: Test Clock

TRST : Reset (optional)

9.3 MBIST Tests

MBIST insertion & testing to be done by vendor for testing different SRAM memories in the

design with various fault models such as Coupling fault, Neighborhood pattern sensitive fault

(NPSF), Address decoder faults, Stuck-at Fault, Transition fault etc.

9.4 Functional Tests

Functional test vectors (EVCD format) will be provided by SAC. Vendor is required to carry out

functional tests on ATE at speed.

9.5 Temperature Tests

Proto Devices must be tested at three temperatures (i.e. min = -40C, typical= 25C, max = 105C)

at different PVT corners.

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10 Design Reviews

The Vendor shall provide a Development Plan along with his proposal, which as a minimum

should incorporate the following reviews:

Preliminary Design Review (PDR)

Interim Design Review (IDR)

Critical Design Review (CDR)

Foundry Signoff Review (FSR)

ASIC Test-Results Review (ATR)

The Vendor shall be responsible for the scheduling and performance of design reviews and

preparation of detailed documentation. The Vendor may also highlight the outline contents of the

respective review documents with his technical offer. SAC will be regularly carrying out progress

reviews against each activity milestone of the proposed development plan to monitor the same and

ensure timely completion and the Vendor shall participate in all these reviews.

Vendor has to submit results and reports of each design step involved in the development (to a

minimum as specified in Section 2) along with the achieved performance.

The vendor must include all the tests details in Acceptance & Validation Test document for the

verification of all the parameters as specified in this document. The vendor shall prepare the

Design Review related documents for the review and submit the same in advance.

SAC PARTICIPATION:

SAC reserves the right to participate at different back-end development stages, as and when

felt necessary. Vendor shall intimate schedule of above events well in advance to enable SAC to

communicate such decision of participating in person/online in any of these events. The cost of

travel and admissible allowances, if any, for ISRO personnel for the above participation shall be

borne by ISRO and need not be factored into the budgetary quote.

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11 Deliverable Items

11.1 Inputs from SAC

Overall requirements & specifications

Scan-inserted post synthesis VHDL/Verilog netlist

Constraints, EDA tool scripts used during synthesis with reports & logs

UPF File for power intent

Preferred pin-assignments

Functional test-vectors/testbench for full chip simulation by vendor

Functional test vectors (EVCD format) for proto device testing on ATE

It is to be noted that SAC designers will be continually interacting with the Vendor’s teams during

the total development phase to ensure proper implementation. The Vendor should be prepared to

send his technical team for these meetings/conduct online meetings whenever required. The cost

of travel and other allowances for Vendor’s personnel for this purpose shall be borne by the

Vendor.

11.2 Vendor deliverables

1. Source Control Drawing (SCD)

2. Project Plan Document

3. Design Review (PDR, IDR, CDR, FSR, ATR) documents, Acceptance & Validation

Test document.

4. Foundry design library toolkit, design manual, design checklists

5. Required SRAM (SPRAM/DPRAM) memory cuts

6. Libraries/PDK required for simulation/characterization in various process corners

7. CMU (PLL) IP along with its datasheet containing block diagram, I/O details,

timing diagram, detailed description of operation, design heritage etc. Behavioral

model of PLL IP after its tuning for simulation. SPICE netlist of PLL module.

8. Verification and test plan document for CMU (PLL) IP module.

9. Post layout timing simulation results & Full chip FAST-SPICE simulation results

with PLL IP at different process corners.

10. Final post-layout ASIC design database in netlist format

11. Back-annotated SDF files

12. EDA tool Scripts & Constraints files used during whole process.

13. Reports/logs of all EDA process

14. Complete layout in GDS-II format & Mask Data Preparation (MDP) files.

15. ATPG, MBIST & Boundary scan chain test vectors with reports

16. Color photograph of manufactured die

17. Process Control Monitor (PCM) Data

18. Pin-out files and bonding diagram of packaged device

19. Package assembly, proto device characterization (As per specified performance

with iterations if require) and testing along with test results and read record data.

20. Packaged & tested proto ASIC devices

21. Dummy packages

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22. Zero Insertion Force (ZIF) socket, carrier along with test board (with all ASIC

package pins routed to berg strips) for packaged devices testing

23. Anything not mentioned above but required to reproduce ASIC in future.

Heritage & failure rate estimation:

Complete details of the process technology used for the fabrication of the die, and the process

capability shall be provided. Details of other devices fabricated with this process technology,

including their life test results shall be provided. Failure rate data for the process, estimated

failure rate for the device and details of failure mechanisms shall be supplied.

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12 Tendering Procedure

This is a two part tender. Vendor should submit separate technical bid and commercial bid.

It is emphasized that the commercial bid must not be submitted (even if inadvertently) along

with the technical bid. Doing so would render the bidder disqualified from further participation

in the procurement process even if their proposal is technically sound.

The bids are to be submitted in two-parts. (A) Techno-Commercial Bid (B) Price Bid

A. Techno-Commercial Bid

This part should contain all the technical details and Commercial Terms and Conditions

including a list of deliverables as indicated in the RFP, without indicating any prices. It

may be noted that in case any incomplete techno-commercial information is provided or if

price details in any manner are disclosed in this part of the bid, the bid will not be

considered for further evaluation as being invalid. Following details should be included in

the techno-commercial bid:

1. Point by point compliance to all specifications/requirements & responsibilities described

in this RFP with supporting documents.

2. Additionally, Bidder has to provide following details with necessary supporting

documents:

S/No. Description Details Supporting

Document Ref.

1. Targeted foundry & its process variant at 28nm

technology node

2. Estimated die size

3. Datasheet & Implementation methodology of

Clock Management Unit (PLL) IP core having

design heritage at targeted foundry node

4. Back-end design flow

5. Packaging information

6. Testing information

7. Overall methodology for entire scope of work

8. Any other additional information, if any

Table 7: Technical Details

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Table 8: Vendor Details

Sr. No DESCRIPTION DETAILS Supporting

Document Ref.

1. Year of Establishment

2. Vendor’s Area of Core Competence / Activities

3. Infrastructure Details (Area, Facilities Etc.)

4. Annual Turnover in the last three financial years

5. Value of major orders for similar work executed in

last 5 years along with client’s name, Address, etc.

6. Number of Technical Manpower with breakup of

Engineers, Technicians, Tradesman with relevant

experience.

7. Number of Technical Manpower with title can be

spared for this project if order is placed.

8. List of in house facilities (including EDA Tools with

license details).

9. Any tie-ups with relevant / specialized companies

proposed for this activity and list of their facilities

with qualification Status. Work Distribution and any

concern from those companies.

10. Quality certification (ISO-9000 Etc.) and Internal

QC procedures followed in all development phases

like design, fabrication, assembly and testing.

11. Details of Customer Base In India

12. Details of similar ASIC designs executed at 28nm

and lower technology nodes.

13. Digital/Mixed Signal ASIC design experience

14. Details of VLSI test facility planned to be used.

15. Estimated timeline for completion/achievement of

various likely milestones involved in the project.

The vendor may define their individual milestones

with brief explanation.

16. Export license requirements, if any.

17. Willingness to provide Non-Disclosure Agreement

(NDA),Confidentiality Agreement & Intellectual

Property Rights (IPR)

18. Service support office in India with manpower

19. Earlier experience in interaction with fab houses or

its authorized aggregator during last 5 years.

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Sample reports of total complexity of designs handled, hands on work experience in this field, or

work done for other customers to be submitted along with customer’s name and project name in

order for SAC/ISRO to judge the vendor’s capability. Complete literature/leaflets/catalogues or

brochures as relevant are also to be enclosed.

The Techno-commercial bid should also contain full details regarding development plan,

payment terms, delivery schedule, warranty, guarantee, security deposit, performance bank

guarantee, training / familiarization for SAC design engineers with the design flow (if

required, at vendor’s premises) etc. under separate heads.

Delivery schedule:

The vendor is also required to provide the detailed breakup of the Activity Schedule with all the

milestones at least with the following main activities/reviews. The front-end gate level netlist

signoff (IDR) is expected to be completed within 6 months from PO (T1= T0 + 6 months). Vendor

has to complete all the activities & delivery within 15 months after IDR (T1+15 months).

S.No. Activity Milestone Expected Timeline Vendor’s

Proposed

Timeline

1. Placement of P.O. T0

2. Preliminary Design Review (PDR) T0 + 1 month

3. PDK & Memory cuts availability to SAC T0 + 2 months

4. Interim Design Review (IDR) T1 = ~ T0 + 6 month

5. Critical Design Review (CDR) T1 + 7 months

6. Foundry Signoff Review (FSR) T1 + 8 months

7. ASIC Fabrication through MPW run T1 + 11 months

8. Packaging, Testing & ASIC Test Results

Review (ATR)

T1 + 14 months

9.

Delivery of packaged & tested proto

devices along with dummy packages, ZIF

sockets, carriers, test cards as per quantity

mentioned in Table-10 & design files,

documents & reports etc. mentioned in

Section 11.2 (Vendor Deliverables)

T1 + 15 months

Table 9: Delivery Schedule

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Please note that the price should NOT be indicated in the Technical Offer. However, it should

include a Sample format of the actual pricing quote, including all line items but with blank or no

entries against the pricing column.

Initially only the technical bids would be opened for technical evaluation of the vendors. Only

those vendors who are short-listed after evaluation of their technical bids would have their price

bids opened.

B. Price Bid

The price bid required must be in Indian Rupees. The bidders are required to submit quotations

with following break-up of cost as a minimum as per the below format in the price bid. Extra cost

of any item (if applicable) should be well indicated in bid other than mentioned in following

format. The final comparison will be made on total cost and it will be decisive. All other Break

ups are for reference.

Table 10: Cost Break-up & Total cost

S.No. Item Cost ( in INR)

1. GDB ASIC Design & Development (NRE) Cost

2. Cost of packaged & tested proto ASIC (Qty-300)

3. Test Board, Sockets & Dummy devices: -

ASIC test board with mounted ZIF socket & carrier

(Qty-2)

Additional ZIF socket & carrier (Qty-5 each)

Dummy packages (Qty-5)

Total cost

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13 Criteria for Vendor Selection The prospective vendors will be judged based on the following criteria:

1. Vendor should be a reputed Indian engineering company in existence for a minimum of 3

years, with necessary technical facilities and experience. Vendor should have design center

in India.

2. Demonstrable proof of competence (eg. Execution of similar designs, customer certifications

etc.) in undertaking this kind of ASIC Design, Fabrication, Packaging and Testing work.

Vendor should have executed successfully at least one such project(s) at 28nm or lower node

in the last five financial years.

3. Compliance to technology, design, package & testing requirements.

4. The vendor should have working experience on EDA tools proposed to be used for this work

contract & should be able to demonstrate the same, if required.

5. Availability of suitable technical manpower (atleast 2 engineers having around 8 years of

VLSI industry experience and exposure to 28nm design flow). Vendor shall have no

objection in providing (if required) the list of team members proposed for this task along

with their qualifications and involvements in similar assignment. The percentage of loading

proposed for each employee identified for this development may be indicated.

6. Earlier experience in interaction with fab houses or their authorized aggregator during last 5

years.

7. In-house Facilities and Infrastructure including that of sub-contractor and partners, if any.

8. Willingness to execute binding undertaking regarding Non-Disclosure Agreement (NDA),

Confidentiality Agreement, Intellectual Property Rights (IPR).

9. Vendor should have a minimum average annual Turnover of more than INR 1 crore in last

three consecutive financial years.

10. Acceptance of SAC/ISRO regular commercial terms and conditions.

11. The provisions of order No. P-45021/2/2017-PP (BE-II) dated 16.9.2020 issued by

Government of India, Ministry of Commerce and Industry (DPIIT - PPS) shall be applicable

to this tender. Bidders seeking benefit of the provisions of the a.m. order shall necessarily

include the documentary evidence as required. A copy of the said order is enclosed for ready

reference (Annexure-2).

12. Compliance with requirements defined in S.No. 1 to 11 above shall be determined in the light

of the details provided in Section 12 of this RFP.

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Inspection of Vendor’s Facilities by SAC Team

The vendor should allow inspection of their facilities by a SAC team, if found necessary, for an

on the spot assessment of their capabilities, prior to placement of order or at any later date during

execution of the contract. The vendor should be in a position to present and explain in detail sample

designs performed earlier at his site to ascertain their capabilities.

Manpower Deployment for this Contract

The vendor is expected to assign the development work related to this design contract only to those

employees who have at least three years’ experience and are fully familiar with usage of relevant

CAD packages and infield of ASIC development. A middle level project lead (with minimum

experience of 8 years) should be identified as the FOCAL POINT, through whom all technical

interaction with the SAC team should take place. The vendor should have different team of

persons to undertake the main design work and the development of test benches. The vendor

should undertake not to change the personnel to the extent possible involved in this design contract

during the course of execution of this contract.

Following Undertaking regarding Confidentiality and IPR should also be provided.

Contractor shall not divulge the information relating to the design, processes, fabrication

procedures, product, quality control methods etc., that are exclusively provided by SAC for its

(SAC’s) own requirements; to any third party. Contractor shall not, without prior written consent

from SAC, use such information for any purpose other than for fulfilling obligations under the

Contract to be placed. Contractor shall maintain absolute secrecy and security to the circuit

schematics, drawings, process methods / documentation etc., provided by SAC for the purpose of

design, fabrication and testing and Contractor shall return the original and copies of the same to

SAC after completion of the work. Contractor undertakes to restrict the access of non-Contractor

personnel and other customers/ visitors to their plant, to any of the details of the job being

performed under this Contract.

The Intellectual property rights relating to the ASIC design, test bench, processes, and other

fabrication details given to the Contractor selected shall remain the exclusive property of SAC.

Settlement of Disputes

The work to be assigned and taken up under this contract is, based on confidentiality, mutual trust

and confidence. Differences of opinion, if any, which arise during the execution of this work

contract will be settled amicably through mutual consultation and dialog between SAC Designer’s

and the vendor’s Techno-Management team. Dispute resolution will be as per arbitration clause in

the General terms and conditions.

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14 Other Terms and Conditions / Important Guidelines 1. The quotation must be in Indian rupees only.

2. The vendor has to comply with the specified attached delivery schedule in PO. This is a time

bound activity and delivery of the end product should not exceed time given in PO in any

case. Vendors are requested to make a note of it. A penalty clause will be applicable beyond

delivery dates, if violated without valid reasons. Delivery schedule and dependency should

form a part of proposal.

3. The vendor is required to clearly state all the assumptions made in his proposal.

4. The vendor should provide cost (to be attached with price bid only) and schedule break-up in

as much detail as possible.

5. The vendor is required to submit undertaking regarding Confidentiality / Non-Disclosure

Agreement (NDA) and Intellectual Property Rights (IPR).

6. SAC will provide the preliminary requirements with the Purchase Order (P.O). Any

modifications, if required, have to be mutually worked out by the vendor and SAC design

team. The vendor shall understand that this is a development activity and minor changes in

functionalities are expected. The vendor shall accommodate such changes during

development or acceptance or activities at no extra cost.

7. The vendor has to furnish all reports at all steps and get the same cleared by SAC.

8. The vendor must include all the tests details in Acceptance & Validation Test document for

the verification of all the parameters as specified in this document at vendor’s site before

shipment and at SAC after delivery.

9. The supplier is also required to supply the hard as well as soft copies of the required

documentation like design & review reports, datasheet etc., at no extra cost.

10. Other Commercial terms and conditions will be as per SAC/ISRO’s standard guidelines for

work order of this nature.

11. It is anticipated that a face-to-face discussion may be required to be held with the vendor after

scrutiny of the technical bid. The vendor should be ready for such a meeting at short notice

and shall send competent technical personnel for the same.

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12. Any deviations in any specification in any of the item must be clearly mentioned along with

the offer.

13. The Techno-Commercial and price offer shall have validity for minimum 6 months.

14. For any query on this tender, please contact the Purchase and Stores Officer by e-mail to:

[email protected].

15. Provisions of Government of India order on preference to Make in India vide reference No.

P-45021/2/2017-PP (BE-II) dated 16th September 2020 issued by Ministry of Commerce and

Industry, Department for Promotion of Industry and Internal Trade (DPIIT) shall be

applicable to this tender. Bidders seeking benefit of the provisions of the a.m. order shall

necessarily include the documentary evidence as required. A copy of the said order is

enclosed for ready reference (Annexure-2).

16. In accordance with the policy notified by Government of India, this tender is open for

participation only by Indian bidders. The bidders will have to declare the proportion of

indigenous content in the techno-commercial bid, suitably certified in accordance with

provisions of the MII order referred to in (15) above. A copy of Bill of material in line with

the price bid / unpriced copy of the price bid shall be attached with the techno-commercial

bid for evaluation. Bids submitted without such details will not be eligible to claim benefits

under Make in India guidelines.

17. Any other guidelines as may be notified and have a bearing on the evaluation criteria of the

tender shall also be applicable even if not explicitly mentioned herein.

18. In case a bidder is submitting their offer as a consortium/Joint Venture(JV) of multiple

vendors by combining their capabilities to execute the complete scope of work described

herein:

a. The consortium/JV partners shall submit a joint undertaking of formation of such a

consortium in the techno-commercial bid clearly giving the details of the consortium

partners and declaring name of the Principal Consortium Partner.

b. Copy of the consortium/JV agreement must be submitted with the techno-commercial

bid. Role of each of the consortium partners shall be clearly described in the bid. In

absence of the same (as well as ‘a’ above) the bid will not be considered for evaluation.

c. In case the tender is awarded against such a bid, order/contract for entire scope of the RFP

will be awarded on the Principal Partner only. Multiple purchase orders covering parts of

the total scope of work defined in this RFP WILL NOT BE ACCEPTED.

d. Multi-currency bids will not be entertained and will be rejected even though they may be

otherwise technically acceptable.

e. All payments shall be released only to the Principal partner in whose name the

Order/contract will be awarded.

mailto:[email protected]

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f. The Principal Partner shall be entirely responsible and accountable to the Purchaser for

the execution of the Order/Contract, if awarded. The joint undertaking as per (a) above

and Consortium/JV agreement shall clearly specify the same. However, the other

consortium/JV partners shall not be absolved of their responsibilities as a result of such

an undertaking and shall stand individually responsible if so determined along with the

Principal Partner.

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ANNEXURE-1

Legal Agreement of the contract & Non-Disclosure Agreement (NDA) A proposed draft of NDA is provided below which shall be executed by the selected bidder on

awarding contract, with minor modifications if deemed necessary by Purchaser (SAC).

Agreement No:

Indian Space Research Organization

Space Applications Centre,

Ahmedabad 380 015

(Entity/Group): ‘X’: (Sl. No.): (Year)

NON DISCLOSURE AGREEMENT

This Agreement made on this -------- day of ---------, 20__ (the ‘Effective Date’) BETWEEN: (1) Space Applications Centre (SAC), Indian Space Research Organization (ISRO), Department of Space,

Government of India, Jodhpur Tekra, Satellite Road, Ahmedabad 380 015, India (hereinafter called

SAC)

(2) ‘X’ whose registered office is at ------------------------------ and works at --------- (hereinafter called the

‘Other Party’ Herein after referred to, individually, as the ‘Party’ and collectively, as the ‘Parties’)

Background:

The Parties are, or will be, evaluating, discussing and negotiating a potential contractual relationship

concerning the participation in ISRO programs for the realization of Design and Fabrication of GNSS

Digital Baseband (GDB) ASIC

i) The parties may in these evaluations, discussions and negotiations disclose to each other

information that is technically and /or commercially confidential.

ii) The Parties have agreed that disclosure and use of such technical and/or commercial confidential

information shall be made on the terms and conditions of this Agreement.

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Now it is agreed as follows: 1.0 DEFINITIONS :

In this Agreement, the following terms shall, unless the context otherwise requires, have the following meanings:

1.1 ‘Disclosing Party’ means the Party disclosing Confidential Information to the other party under this Agreement.

1.2 ‘Receiving Party’ means the Party receiving Confidential Information from the other Party under this Agreement.

1.3 ‘Confidential Information’ means any information, which shall include but is not limited to, design, fabrication & assembly

drawings, know-how, processes, product specifications, raw materials, trade secrets, market opportunities, or business or

financial affairs of the Parties or their customers, product samples, inventions, concepts and any other technical and / or

commercial information, disclosed directly or indirectly and in any form whatsoever (including, but not limited to,

disclosure made in writing, oral or in the form of samples, models, computer programs, drawings or other instruments)

furnished by the Disclosing Party to the Receiving Party under this Agreement.

1.3.1 Such Confidential Information shall also include but shall not be limited to:

1.3.1.1 Information disclosed by the Disclosing Party in writing marked as confidential at the time of

disclosure;

1.3.1.2 Information disclosed by the Disclosing Party orally which is slated to be confidential at the time

of disclosure;

1.3.1.3 Information disclosed in any other manner is designated in writing as Confidential Information at

the time of disclosure; or

1.3.1.4 Notwithstanding sub-clauses 1.3.1.1, 1.3.1.2 and 1.3.1.3 of this definition, any information whose

nature makes it obvious that it is confidential.

1.3.2 Such Confidential Information shall not include any information which:

1.3.2.1 is, at the time of disclosure, publicly known; or

1.3.2.2 becomes at a later date, publicly available otherwise than a wrongful act or negligence or breach

of this Agreement of or by the Receiving Party; or

1.3.2.3 the Receiving Party can demonstrate by its written records was in its possession, or known to the

Receiving Party, before receipt under this Agreement, and which was not previously acquired

under an obligation of confidentiality; or

1.3.2.4 is legitimately obtained at any time by the Receiving Party from a third party without restrictions

in respect of disclosure or use; or

1.3.2.5 the Receiving Party can demonstrate to the satisfaction of the Disclosing Party, has been

developed independently of its obligations under this Agreement and without access to the

Confidential Information.

1.4 ‘Purpose’ means the evaluations, discussions, negotiations and execution regarding a contractual relationship between the

Parties in respect of the Project defined in paragraph (i) of the Background section.

1.5 ‘Affiliate’ means any legal entity, which, at the time of disclosure to it on any Confidential Information, is directly or

indirectly controlling, controlled by or under common control with any of the Parties.

1.6 ‘Contemplated Agreement’ means any future legally binding Agreement between the parties in respect of the fabrication

work envisaged under this Agreement.

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2.0 Non-Disclosure of Confidential Information:

2.1 In consideration of the disclosure of Confidential Information by the Disclosing Party to the Receiving Party solely for the Purpose, the Receiving Party undertakes whether by itself, its successors and heirs, not to disclose Confidential Information to any third party, unless in accordance with Clause 4.

2.2 In addition to the undertaking in Clause 2.1, the Receiving Party shall be liable for:

2.2.1 Any loss, theft or other inadvertent disclosure of Confidential Information, and

2.2.2 any unauthorized disclosure of Confidential Information by persons (including, but not limited to, present and former employees) or entities to whom the Receiving Party under this Agreement has the right to disclose Confidential Information, except where, the Receiving Party has used the same degree of care in safeguarding such Confidential Information as it uses for its own Confidential Information of like importance and in no event less than a reasonable degree of care; and upon becoming aware of such inadvertent or unauthorized disclosure the Receiving Party has promptly notified the Disclosing Party thereof and taken all reasonable measures to mitigate the effects of such disclosure and to prevent further disclosure.

2.3 The Receiving Party understands and agrees that:

2.3.1 Any information known only to a few people to whom it might be of commercial interest and not generally known to the public is not public knowledge;

2.3.2 A combination of two or more parts of the Confidential Information is not public knowledge merely because each part is separately available to the public.

2.4 The Receiving Party acknowledges the technical, commercial and strategic value of the Confidential Information to the Disclosing Party and understands that unauthorized disclosure of such Confidential Information will be injurious to the Disclosing Party.

3.0 Use of Confidential Information:

The Receiving Party is entitled to use the Confidential Information but only for the intended Purpose.

4.0 Permitted Disclosure of Confidential Information:

4.1 The Receiving Party may disclose in confidence Confidential Information to any of its Affiliates and employees, in which event the Affiliate and employee shall be entitled to use the Confidential Information but only to the same extent the Receiving Party is permitted to do so under this Agreement. The Receiving Party agrees that such Affiliates or employees are subject to confidentiality obligations no less restrictive than those of this Agreement.

4.2 The Receiving Party shall limit the dissemination of Confidential Information of its Affiliates and employees having a need

to receive such information to carry out the Purpose.

4.3 The Receiving Party may disclose Confidential Information to its consultants, contractors, subcontractors, agents or similar

persons and entities having a need to receive such information to carry out the Purpose on the prior written consent of the

Disclosing Party. In the event that the Disclosing Party gives such consents, the Receiving Party agrees that such individuals

are subject to confidentiality obligations no less restrictive than those of this Agreement.

4.4 Notwithstanding Clause 2.1, the Receiving Party shall not be prevented from disclosing Confidential Information where (I)

such disclosure is in response to a valid order of a court or any other governmental body having jurisdiction over this

Agreement or (ii) such disclosure is otherwise required by law, provided that the Receiving Party, to the extent possible,

has first given prior written notice to the Disclosing Party and made reasonable effort to protect the Confidential

Information in connection with such disclosure.

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5.0 Copying and Return of Furnished Instruments:

5.1 The Receiving Party shall not be entitled to copy samples, models, computer programs, drawings, documents or other instruments furnished by the Disclosing Party hereunder and containing Confidential Information, unless and to the extent it is necessary for the Purpose.

5.2 All samples, models, computer programs, drawings, documents and other instruments furnished hereunder and containing Confidential Information shall remain the Disclosing Party’s property.

5.3 At any time upon request from the Disclosing Party or upon the conclusion of the Purpose or expiry of this Agreement, the Receiving Party will, at its own cost, return or procure the return, promptly and in any event within 14 days of receipt of such request, of each and every copy of Confidential Information given by the Disclosing Party, and satisfy the Disclosing Party that it no longer holds any further Confidential Information.

6.0 Non-Disclosure of Negotiations:

Except as provided in Clause 4, each Party agrees that it will not, without the other Party’s prior written approval, disclose to any third party the fact that the Parties are discussing the Project. The Parties acknowledge that the provisions of this Agreement shall apply in respect of the content of any such discussions. The undertaking set forth in this Clause 7 shall survive the termination of this Agreement.

7.0 Term and Termination:

7.1 This Agreement shall become effective on the Effective Date. The provisions of this Agreement shall however apply

retroactively to any Confidential Information, which may have been disclosed in connection with discussions and

negotiations regarding the Project prior to the Effective Date.

7.2 This Agreement shall remain in force for five years from the Effective Date, except to the extent this Agreement is

superseded by stipulations of the Contemplated Agreement.

7.3 The rights and obligations of each Party with respect to all Confidential Information of the other Party that is received under

this Agreement shall remain in effect for a period of 5 years from the date of disclosure of Confidential Information.

8.0 Intellectual Property Rights:

All Confidential Information disclosed herein shall remain the sole property of the Disclosing Party and the Receiving Party shall obtain no right thereto of any kind by reason of this Agreement.

9.0 Future Agreements:

Nothing in this Agreement shall obligate either party to enter into any further Agreements.

10.0 Amendments:

Any amendment to this Agreement shall be agreed in writing by both Parties and shall refer to this Agreement.

11.0 Severance:

If any term or provision in this Agreement is held to be either illegal or unenforceable, in whole or in part, under any enactment or rule of law, such term or provision or part shall to that extent be deemed not to form part of this Agreement, but the validity and enforceability of the remainder of this Agreement shall not be affected.

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12.0 Governing Law:

This Agreement shall be governed by and construed in accordance with the laws of India and the Parties hereby submit to the exclusive jurisdiction of the Courts situated at Ahmedabad, India.

IN WITNESS whereof this Agreement was duly executed on behalf of the parties on the day and year first above written.

For and on behalf of For and on behalf of

(Space Applications Centre-SAC) (X)

Authorized Representative of SAC Director / Chief Executive - ‘X’

Name:

Designation:

(Rubber Stamp or Common Seal of the Company)

WITNESS: WITNESS:

1) 1)

2) 2)

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ANNEXURE-2

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Request for Proposal For Design and Fabrication of GNSS ......MBIST insertion & testing to be done...

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Transcript of Request for Proposal For Design and Fabrication of GNSS ......MBIST insertion & testing to be done...