Release 14.2 - xst P.28xd (nt64)Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to xst/projnav.tmpTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.13 secs --> Parameter xsthdpdir set to xstTotal REAL time to Xst completion: 0.00 secsTotal CPU time to Xst completion: 0.14 secs --> Reading design: CSA.prjTABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report9.1) Device utilization summary9.2) Partition Resource Summary9.3) TIMING REPORT=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "CSA.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "CSA"Output Format : NGCTarget Device : xc3s100e-4-cp132---- Source OptionsTop Module Name : CSAAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoSafe Implementation : NoFSM Style : LUTRAM Extraction : YesRAM Style : AutoROM Extraction : YesMux Style : AutoDecoder Extraction : YESPriority Encoder Extraction : YesShift Register Extraction : YESLogical Shifter Extraction : YESXOR Collapsing : YESROM Style : AutoMux Extraction : YesResource Sharing : YESAsynchronous To Synchronous : NOMultiplier Style : AutoAutomatic Register Balancing : No---- Target OptionsAdd IO Buffers : YESGlobal Maximum Fanout : 500Add Generic Clock Buffer(BUFG) : 24Register Duplication : YESSlice Packing : YESOptimize Instantiated Primitives : NOUse Clock Enable : YesUse Synchronous Set : YesUse Synchronous Reset : YesPack IO Registers into IOBs : AutoEquivalent register Removal : YES---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Keep Hierarchy : NoNetlist Hierarchy : As_OptimizedRTL Output : YesGlobal Optimization : AllClockNetsRead Cores : YESWrite Timing Constraints : NOCross Clock Analysis : NOHierarchy Separator : /Bus Delimiter : Case Specifier : MaintainSlice Utilization Ratio : 100BRAM Utilization Ratio : 100Verilog 2001 : YESAuto BRAM Packing : NOSlice Utilization Ratio Delta : 5==================================================================================================================================================* HDL Compilation *=========================================================================Compiling verilog file "HA.vf" in library workCompiling verilog file "FA_V1.vf" in library workModule compiledCompiling verilog file "RCA_8_bits.vf" in library workModule compiledModule compiledModule compiledCompiling verilog file "Add1_Buff.vf" in library workModule compiledCompiling verilog file "CSA.vf" in library workModule compiledModule compiledModule compiledModule compiledModule compiledModule compiledNo errors in compilationAnalysis of file succeeded. =========================================================================* Design Hierarchy Analysis *=========================================================================Analyzing hierarchy for module in library .Analyzing hierarchy for module in library .Analyzing hierarchy for module in library .Analyzing hierarchy for module in library .Analyzing hierarchy for module in library .=========================================================================* HDL Analysis *=========================================================================Analyzing top module .Module is correct for synthesis. Analyzing module in library .Module is correct for synthesis. Analyzing module in library .Module is correct for synthesis. Analyzing module in library .Module is correct for synthesis. Analyzing module in library .Module is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Performing bidirectional port resolution...Synthesizing Unit . Related source file is "CSA.vf".Unit synthesized.Synthesizing Unit . Related source file is "CSA.vf".Unit synthesized.Synthesizing Unit . Related source file is "CSA.vf".Unit synthesized.Synthesizing Unit . Related source file is "CSA.vf".Unit synthesized.Synthesizing Unit . Related source file is "CSA.vf".Unit synthesized.=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Advanced HDL Synthesis *==================================================================================================================================================Advanced HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit ...Optimizing unit ...Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block CSA, actual ratio is 0.Final Macro Processing ...=========================================================================Final Register ReportFound no macro==================================================================================================================================================* Partition Report *=========================================================================Partition Implementation Status------------------------------- No Partitions were found in this design.-------------------------------=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : CSA.ngrTop Level Output File Name : CSAOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NoDesign Statistics# IOs : 14Cell Usage :# BELS : 26# AND2 : 11# OR2 : 4# XOR2 : 11# IO Buffers : 14# IBUF : 9# OBUF : 5=========================================================================Device utilization summary:---------------------------Selected Device : 3s100ecp132-4 Number of Slices: 0 out of 960 0% Number of IOs: 14 Number of bonded IOBs: 14 out of 83 16% ---------------------------Partition Resource Summary:--------------------------- No Partitions were found in this design.---------------------------=========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE.Clock Information:------------------No clock signals found in this designAsynchronous Control Signals Information:----------------------------------------No asynchronous control signals found in this designTiming Summary:---------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 14.037nsTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default path analysis Total number of paths / destination ports: 93 / 5-------------------------------------------------------------------------Delay: 14.037ns (Levels of Logic = 10) Source: B (PAD) Destination: Cout (PAD) Data Path: B to Cout Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 2 1.218 0.447 B_1_IBUF (B_1_IBUF) XOR2:I0->O 2 0.704 0.447 XLXI_1/XLXI_1/XLXI_6 (XLXI_1/XLXI_1/XLXN_25) AND2:I0->O 1 0.704 0.420 XLXI_1/XLXI_1/XLXI_11 (XLXI_1/XLXI_1/XLXN_24) OR2:I0->O 2 0.704 0.447 XLXI_1/XLXI_1/XLXI_7 (XLXI_1/XLXN_2) AND2:I1->O 1 0.704 0.420 XLXI_1/XLXI_2/XLXI_11 (XLXI_1/XLXI_2/XLXN_24) OR2:I0->O 2 0.704 0.447 XLXI_1/XLXI_2/XLXI_7 (XLXI_1/XLXN_3) XOR2:I0->O 2 0.704 0.447 XLXI_1/XLXI_3/XLXI_5 (XLXN_1) AND2:I1->O 1 0.704 0.420 XLXI_2/XLXI_14 (XLXN_4) OR2:I1->O 1 0.704 0.420 XLXI_3 (Cout_OBUF) OBUF:I->O 3.272 Cout_OBUF (Cout) ---------------------------------------- Total 14.037ns (10.122ns logic, 3.915ns route) (72.1% logic, 27.9% route)=========================================================================Total REAL time to Xst completion: 8.00 secsTotal CPU time to Xst completion: 7.83 secs --> Total memory usage is 252812 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)